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[109.243.67.101]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4834d5ebd1bsm303288185e9.6.2026.02.13.08.29.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Feb 2026 08:29:10 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 21281e8b-08f9-11f1-b163-2bf370ae4941 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1771000151; x=1771604951; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9TfHO4ZBv8S5+fXcFeskWF2fV7HooHkCu0wCOijIOOI=; b=khab3WmcHIur70PgAG9nspbF2BN/xlbprsqw5Bvku9SUsdEOZaay6IsfAItfatKG2R puSTaKbGfBCS6LKWdRM54qCZ6MOB2/tLhC+SKYciooVaGdHHsplbaOfY2hOPBQZlxqlv aOczY6DdBH/R04T7LUr4fvTGQWfQg/IakqHbqn6OP+tt2smLLWFNDNwU7nMhRWJNsMt4 gDxODKZu9a15HEzlzI34lzNJZTZ0n7VrULrlv/yehCKlMcajVFhjYLDgBhqNxfzHz9OD VPQ6C/icdxx9JPIZ7T91LMMqvzlRSWagKG12PJmWA6KuqQlWDK0PAs3v2/bA1U7mu497 sRRQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1771000151; x=1771604951; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=9TfHO4ZBv8S5+fXcFeskWF2fV7HooHkCu0wCOijIOOI=; b=seFfG6FZ49QE6vSmDPl07cQubwFlNdLquRKFBBZQp9WS7RHrS236dnjhb+y48MeDaK HMWx+kDJkuXzC0SC5jOqsfSbCiwxj703bZb2sW1E79XK0qWahXiFDWwvWOUd3DvQwZWd UUkE30sJtsxYUYe5kP1UwnB/O8/jKn3qxxPXuxy9T3KhWKREyOLtZtgb0Oq+Lul0bUb8 DAf4i5KdGg5bnb0RYXr7GgTLY7bZwOh5utGjUtODsAoVQqEB8GZ4vYsbVyeiZAHyQ5P3 oyMWeSE4N6wmdYR93dTAJ+dQJvOXhIgMdacAWx9MMJ3SiXa7bFzfYrPNVLzyO0hkZBd/ ySZQ== X-Gm-Message-State: AOJu0Yz4lovp5Wry9rXV8soz7LyFUJPr/RubBfYJuQCyk4/hi1k/4Rkj XHRXl7o8z1aEtjXAFKAZ4JRIya6yy/XCpgzFyNK7c96qugaIL4GJ3ZCrrQKXbtAc X-Gm-Gg: AZuq6aJA9ZYH/QsOoaNHls5HdNacumC72hk9r5t8+iczqZv+jKTHO+cOSggHTKS7RKc Tma/itnBOm7EAEsidfM0gerldXrjqwLuXGYaGkAX6Rhokev+fiLVnlMk3Ni4EN68BbH/Q10ih1w 3G011rITR9pj/YKVwe9/JVqbW7mLD+WMJ2INIABKSurCnh4E3nfLtrXj+ibSLQe7QwM4oBgtQxm Ib4NXk+Jt9tDtbU/xXRUPWMSd6CUA1u5SQcL5RPgi9XzMQLmZg7hcnOtw6rQzTwcH2B4iiZhxrF 3+UGnfge/WNRqF1ifQ9WTcNhF6pyDDhULAlqaa0HVrq5T627o8G46KKy2ksw67FOrmi4yRQpz3N SUboOVJMf4oGwWswl6mbhsxUBPHsk/gOH85tsHSbnpwn8YWspTNR9rvfkX9Cd/EkDbKygSwO/y4 gWscVWSahxZccoq3u9Q2r0Q0o36yZYK6ky1tKWhU1WYIYLJ6XOhFfovnO/eAbP3PlDhdTZauO+C PYT X-Received: by 2002:a05:600c:34c6:b0:483:6ff1:18b with SMTP id 5b1f17b1804b1-483737bde90mr36700935e9.0.1771000151157; Fri, 13 Feb 2026 08:29:11 -0800 (PST) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Romain Caritey , Oleksii Kurochko , Alistair Francis , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH v4 01/16] xen/riscv: implement arch_vcpu_{create,destroy}() Date: Fri, 13 Feb 2026 17:28:47 +0100 Message-ID: <42534cb6aabf25cf551a13ae1288045e1ac08f9e.1770999383.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1771000183493154100 Introduce architecture-specific functions to create and destroy VCPUs. Note that arch_vcpu_create() currently returns -EOPNOTSUPP, as the virtual timer and interrupt controller are not yet implemented. Add calle-saved registers to struct arch_vcpu which are used to preserve Xen=E2=80=99s own execution context when switching between vCPU stacks. It is going to be used in the following way (pseudocode): context_switch(prev_vcpu, next_vcpu): ... /* Switch from previous stack to the next stack. */ __context_switch(prev_vcpu, next_vcpu); ... schedule_tail(prev_vcpu): Save and restore vCPU's CSRs. The Xen-saved context allows __context_switch() to switch execution from the previous vCPU=E2=80=99s stack to the next vCPU=E2=80=99s stack and= later resume execution on the original stack when switching back. During vCPU creation, the Xen-saved context is going to be initialized with: - SP pointing to the newly allocated vCPU stack. - RA pointing to a helper that performs final vCPU setup before transferring control to the guest. As part of this change, add continue_new_vcpu(), which will be used after the first context_switch() of a new vCPU. Since this functionality is not yet implemented, continue_new_vcpu() is currently provided as a stub. The prev argument is going to be set by RISC-V ABI (prev will be stored in a0) when __context_swtich() will be introduced and called from context_switch(). Update the STACK_SIZE definition and introduce STACK_ORDER (to align with other architectures) for allocating the vCPU stack. Introduce struct cpu_info to store per-vCPU state that lives at the top of the vCPU's stack. Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich --- Changes in v4: - Update the code of arch_vcpu_destroy() by shortening passed vfree()'s argument. - Update the commit message. --- Changes in v3: - Move declaration of xen_saved_context structure and cpu_info structure here as they are going to be used in this patch. - Drop separate zero-ing of arch.cpu_info as a memory for it is allocated by vzalloc(). - Correct calculation of stack pointer in arch_vcpu_destroy() function. --- Changes in v2: - Drop BUILD_BUG_ON() in arch_vcpu_create() as a check isn't very useful. - Use vzalloc() instead of alloc_xenheap_page() to use the larger domheap = to allocate vCPU's stack. - Drop printk() inside arch_vcpu_create() to not have potential big noise in console as it could be that an amount of vCPUs is pretty big. - Use XVFREE() instead of free_xenheap_pages() as vCPU's stack allocation happens with a usage of vzalloc() now. - Drop stack field as it is enough to have only cpu_info as stack pointer could be calculated based on cpu_info. - Drop cast when v.arch.cpu_info is inialized as it is not necessary to have it. - Drop memset() for arch.cpu_info() as it is enough to have vzalloc(). --- xen/arch/riscv/Makefile | 1 + xen/arch/riscv/domain.c | 58 ++++++++++++++++++++++++++++ xen/arch/riscv/include/asm/config.h | 3 +- xen/arch/riscv/include/asm/current.h | 6 +++ xen/arch/riscv/include/asm/domain.h | 24 ++++++++++++ xen/arch/riscv/stubs.c | 10 ----- 6 files changed, 91 insertions(+), 11 deletions(-) create mode 100644 xen/arch/riscv/domain.c diff --git a/xen/arch/riscv/Makefile b/xen/arch/riscv/Makefile index 1eb9ab090b48..caa1aac5b2f6 100644 --- a/xen/arch/riscv/Makefile +++ b/xen/arch/riscv/Makefile @@ -1,5 +1,6 @@ obj-y +=3D aplic.o obj-y +=3D cpufeature.o +obj-y +=3D domain.o obj-$(CONFIG_EARLY_PRINTK) +=3D early_printk.o obj-y +=3D entry.o obj-y +=3D imsic.o diff --git a/xen/arch/riscv/domain.c b/xen/arch/riscv/domain.c new file mode 100644 index 000000000000..f5c624ac92c7 --- /dev/null +++ b/xen/arch/riscv/domain.c @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +static void continue_new_vcpu(struct vcpu *prev) +{ + BUG_ON("unimplemented\n"); +} + +static void __init __maybe_unused build_assertions(void) +{ + /* + * Enforce the requirement documented in struct cpu_info that + * guest_cpu_user_regs must be the first field. + */ + BUILD_BUG_ON(offsetof(struct cpu_info, guest_cpu_user_regs) !=3D 0); +} + +int arch_vcpu_create(struct vcpu *v) +{ + int rc =3D 0; + void *stack =3D vzalloc(STACK_SIZE); + + if ( !stack ) + return -ENOMEM; + + v->arch.cpu_info =3D stack + STACK_SIZE - sizeof(struct cpu_info); + + v->arch.xen_saved_context.sp =3D (register_t)v->arch.cpu_info; + v->arch.xen_saved_context.ra =3D (register_t)continue_new_vcpu; + + /* Idle VCPUs don't need the rest of this setup */ + if ( is_idle_vcpu(v) ) + return rc; + + /* + * As the vtimer and interrupt controller (IC) are not yet implemented, + * return an error. + * + * TODO: Drop this once the vtimer and IC are implemented. + */ + rc =3D -EOPNOTSUPP; + goto fail; + + return rc; + + fail: + arch_vcpu_destroy(v); + return rc; +} + +void arch_vcpu_destroy(struct vcpu *v) +{ + vfree((void *)&v->arch.cpu_info[1] - STACK_SIZE); +} diff --git a/xen/arch/riscv/include/asm/config.h b/xen/arch/riscv/include/a= sm/config.h index 1e08d3bf78be..86a95df018b5 100644 --- a/xen/arch/riscv/include/asm/config.h +++ b/xen/arch/riscv/include/asm/config.h @@ -143,7 +143,8 @@ =20 #define SMP_CACHE_BYTES (1 << 6) =20 -#define STACK_SIZE PAGE_SIZE +#define STACK_ORDER 3 +#define STACK_SIZE (PAGE_SIZE << STACK_ORDER) =20 #define IDENT_AREA_SIZE 64 =20 diff --git a/xen/arch/riscv/include/asm/current.h b/xen/arch/riscv/include/= asm/current.h index 0c3ea70c2ec8..58c9f1506b7c 100644 --- a/xen/arch/riscv/include/asm/current.h +++ b/xen/arch/riscv/include/asm/current.h @@ -21,6 +21,12 @@ struct pcpu_info { /* tp points to one of these */ extern struct pcpu_info pcpu_info[NR_CPUS]; =20 +/* Per-VCPU state that lives at the top of the stack */ +struct cpu_info { + /* This should be the first member. */ + struct cpu_user_regs guest_cpu_user_regs; +}; + #define set_processor_id(id) do { \ tp->processor_id =3D (id); \ } while (0) diff --git a/xen/arch/riscv/include/asm/domain.h b/xen/arch/riscv/include/a= sm/domain.h index 316e7c6c8448..f78f145258d6 100644 --- a/xen/arch/riscv/include/asm/domain.h +++ b/xen/arch/riscv/include/asm/domain.h @@ -24,6 +24,30 @@ struct arch_vcpu_io { =20 struct arch_vcpu { struct vcpu_vmid vmid; + + /* + * Callee saved registers for Xen's state used to switch from + * prev's stack to the next's stack during context switch. + */ + struct + { + register_t s0; + register_t s1; + register_t s2; + register_t s3; + register_t s4; + register_t s5; + register_t s6; + register_t s7; + register_t s8; + register_t s9; + register_t s10; + register_t s11; + register_t sp; + register_t ra; + } xen_saved_context; + + struct cpu_info *cpu_info; }; =20 struct paging_domain { diff --git a/xen/arch/riscv/stubs.c b/xen/arch/riscv/stubs.c index acbfde79b5a7..c5784a436574 100644 --- a/xen/arch/riscv/stubs.c +++ b/xen/arch/riscv/stubs.c @@ -116,16 +116,6 @@ void dump_pageframe_info(struct domain *d) BUG_ON("unimplemented"); } =20 -int arch_vcpu_create(struct vcpu *v) -{ - BUG_ON("unimplemented"); -} - -void arch_vcpu_destroy(struct vcpu *v) -{ - BUG_ON("unimplemented"); -} - void vcpu_switch_to_aarch64_mode(struct vcpu *v) { BUG_ON("unimplemented"); --=20 2.52.0 From nobody Mon Apr 13 03:40:41 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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Writing unsupported bits can either be ignored or raise an exception depending on the platform. Detect the set of writable bits for selected hypervisor CSRs at boot and store the resulting masks for later use. This allows safely programming these CSRs during vCPU context switching and avoids relying on hardcoded architectural assumptions. Note that csr_set() is used instead of csr_write() to write all ones to the mask, as the CSRRS instruction, according to the RISC-V specification, sets only those bits that are writable (note that the quote consider only non-read-only CSRs as writing to read-only CSRs according to the spec. will raise an exception): Any bit that is high in rs1 will cause the corresponding bit to be set in the CSR, if that CSR bit is writable. In contrast, the CSRRW instruction does not take CSR bit writability into account, which could lead to unintended side effects when writing all ones to a CSR. Masks are calculated at the moment only for hedeleg, henvcfg, hideleg, hstateen0 registers as only them are going to be used in the follow up patch. If the Smstateen extension is not implemented, hstateen0 cannot be read because the register is considered non-existent. Instructions that attempt to access a CSR that is not implemented or not visible in the current mode are reserved and will raise an illegal-instruction exception. Signed-off-by: Oleksii Kurochko --- Changes in V4: - Move csr_masks defintion to domain.c. Make it static as at the moment it is going to be used only in domain.c. - Rename and refactor X macros inside init_csr_masks(). --- Changes in V3: - New patch. --- xen/arch/riscv/domain.c | 5 +++++ xen/arch/riscv/include/asm/setup.h | 9 +++++++++ xen/arch/riscv/setup.c | 21 +++++++++++++++++++++ 3 files changed, 35 insertions(+) diff --git a/xen/arch/riscv/domain.c b/xen/arch/riscv/domain.c index f5c624ac92c7..5572e10bfaa9 100644 --- a/xen/arch/riscv/domain.c +++ b/xen/arch/riscv/domain.c @@ -2,9 +2,14 @@ =20 #include #include +#include #include #include =20 +#include + +struct csr_masks __ro_after_init csr_masks; + static void continue_new_vcpu(struct vcpu *prev) { BUG_ON("unimplemented\n"); diff --git a/xen/arch/riscv/include/asm/setup.h b/xen/arch/riscv/include/as= m/setup.h index c9d69cdf5166..d54f6a2d1d29 100644 --- a/xen/arch/riscv/include/asm/setup.h +++ b/xen/arch/riscv/include/asm/setup.h @@ -5,6 +5,15 @@ =20 #include =20 +struct csr_masks { + register_t hedeleg; + register_t henvcfg; + register_t hideleg; + register_t hstateen0; +}; + +extern struct csr_masks csr_masks; + #define max_init_domid (0) =20 void setup_mm(void); diff --git a/xen/arch/riscv/setup.c b/xen/arch/riscv/setup.c index 9b4835960d20..dc469b49623f 100644 --- a/xen/arch/riscv/setup.c +++ b/xen/arch/riscv/setup.c @@ -70,6 +70,25 @@ static void * __init relocate_fdt(paddr_t dtb_paddr, siz= e_t dtb_size) return fdt; } =20 +void __init init_csr_masks(void) +{ + register_t old; + +#define INIT_CSR_MASK(csr, field) do { \ + old =3D csr_read(CSR_##csr); \ + csr_set(CSR_##csr, ULONG_MAX); \ + csr_masks.field =3D csr_read(CSR_##csr); \ + csr_write(CSR_##csr, old); \ +} while (0) + + INIT_CSR_MASK(HEDELEG, hedeleg); + INIT_CSR_MASK(HENVCFG, henvcfg); + INIT_CSR_MASK(HIDELEG, hideleg); + + if ( riscv_isa_extension_available(NULL, RISCV_ISA_EXT_smstateen) ) + INIT_CSR_MASK(HSTATEEN0, hstateen0); +} + void __init noreturn start_xen(unsigned long bootcpu_id, paddr_t dtb_addr) { @@ -137,6 +156,8 @@ void __init noreturn start_xen(unsigned long bootcpu_id, =20 riscv_fill_hwcap(); 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Suggested-by: Jan Beulich Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich --- Changes in V4: - New patch. --- xen/arch/riscv/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/xen/arch/riscv/Makefile b/xen/arch/riscv/Makefile index caa1aac5b2f6..bc47e83b26d7 100644 --- a/xen/arch/riscv/Makefile +++ b/xen/arch/riscv/Makefile @@ -12,7 +12,7 @@ obj-y +=3D paging.o obj-y +=3D pt.o obj-$(CONFIG_RISCV_64) +=3D riscv64/ obj-y +=3D sbi.o -obj-y +=3D setup.o +obj-y +=3D setup.init.o obj-y +=3D shutdown.o obj-y +=3D smp.o obj-y +=3D smpboot.o --=20 2.52.0 From nobody Mon Apr 13 03:40:41 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1771000175; cv=none; d=zohomail.com; s=zohoarc; b=Q2PjJVckFr+s3xii6GQDFpcoL7xW9kPb3S8sIo6tO6x2ft2o97AyuF6WtEtso2712aZm/P2/NLlehgWo2PWP/vRL2o03y+OfOhH+n9+rbt1n1+oAG/xQbXMy2ODP+tMibUWR9hcFPtkMdLdG6VHNyG8efiNO0ta51SQuK8hfqCA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1771000175; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=sFTZR6VEK+iEcNLXUgansIu4xb+JbI0KY9wblj0cuZ4=; b=lFABXUar5DbP4WSs585wXTovVHajmJ+Wzb2VoaGF3WQ5SZOIzBApNL8CTZYueXqHxH74DzQwzmGsqmu9pNnTaopFJ88LepxpwgQOiUbD37w1isu177kxGRPeK/ieWVpKF2no11fo1ZWJOSEAqSoP3KSn4XcXAcRO6z6qgxEDyVA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1771000175825492.67112747641636; Fri, 13 Feb 2026 08:29:35 -0800 (PST) Received: from list by lists.xenproject.org with outflank-mailman.1231313.1536521 (Exim 4.92) (envelope-from ) id 1vqw2g-0006LC-19; Fri, 13 Feb 2026 16:29:18 +0000 Received: by outflank-mailman (output) from mailman id 1231313.1536521; Fri, 13 Feb 2026 16:29:17 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vqw2f-0006KU-R4; Fri, 13 Feb 2026 16:29:17 +0000 Received: by outflank-mailman (input) for mailman id 1231313; Fri, 13 Feb 2026 16:29:16 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vqw2e-0005Ws-Dp for xen-devel@lists.xenproject.org; Fri, 13 Feb 2026 16:29:16 +0000 Received: from mail-wm1-x334.google.com (mail-wm1-x334.google.com [2a00:1450:4864:20::334]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 23096eea-08f9-11f1-b163-2bf370ae4941; Fri, 13 Feb 2026 17:29:15 +0100 (CET) Received: by mail-wm1-x334.google.com with SMTP id 5b1f17b1804b1-482f2599980so12670085e9.0 for ; Fri, 13 Feb 2026 08:29:15 -0800 (PST) Received: from fedora (user-109-243-67-101.play-internet.pl. [109.243.67.101]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4834d5ebd1bsm303288185e9.6.2026.02.13.08.29.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Feb 2026 08:29:14 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 23096eea-08f9-11f1-b163-2bf370ae4941 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1771000155; x=1771604955; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=sFTZR6VEK+iEcNLXUgansIu4xb+JbI0KY9wblj0cuZ4=; b=CvbgeaSEAskkQJVXJ3FKdQgvdAbIZMtcK5SpxxMAW6SE5XO/vffLqCzrcMFM/bHC9M 7XGGCqSJsDRp8/jtXfg1QHk8gqUI8ubP7KZhE7AExm+2rFZqmDDb1MFeua8owHO893zS SdAjcEhSmqhe8G77cxuUzh7n3Wb/RYA6mnjXE5yJbT7c90g2Kpe+rgqe6+3YLNAYX2E5 QtJwWjahpfapMDlp+Zbho7YqqGzW0skaqbUvXf75AelloFD7unKdWZZ+z10HAvAPV1w8 jAuRIA0zZihf0QqDS2KRXXYeluzp6UHzngCUEomJ+RcfL+HpC3TVp7r/+40z9erHidtY j2wg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1771000155; x=1771604955; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=sFTZR6VEK+iEcNLXUgansIu4xb+JbI0KY9wblj0cuZ4=; b=d8OLzJleWUrJBp28ZD1cyBdytMQsWnAe5DlKBeQZVUE2gCGel4XohXkHTW7xIddUga fbwLhqWiyw8YwMl+JzFo2A5xQo8MbFJxtXpDxYSkwNxFutbk14cS1RHe75l4E6wYbQos prAHKRzR1vWrgHyjmzqPKmPkPcaScLORNSFyZZGw56DWP0y4RaEIdv+nFEy/0LhGLfIx HOFx5xkvcuQNeyqs/uk1Mt+l9wgkv2nTIc99xwxH7kHyry2UarOcVIQXBI1Y7wHJhwKj NrLkwzlw1YN9yGPDVI5iEjkSdxSu/BxcyYDnmvkcI3+7DW0ZtONmPp3i4tasOkn4k9bn DUAg== X-Gm-Message-State: AOJu0YwTkhbasxl0lyesiJpXgpTGwYCx1hcKrcaB/jAF8/yM4QiAYV+c 91BlnpELlf8PvPhAImAl5stdhaSwwpFawA8vWUghWZRscJB7gh0hfI8ruoWvn2nT X-Gm-Gg: AZuq6aL8J+5PPnxbe6ZOJqNSN0f0WcJOBhlHxVCNBCdwE9p1+KcSOrDcd+f0X9AM7NS MBywZcAbJqfWaMFVmcicpvvNyIpRGuZlQGNfiOSmgceqcwRtHYrBijCn/4cUnQT5NK7orLpDRya SQF8cGc6vsvW3JKEpWgdBSbGN+c4rVKizDKxr/J8eVrF8l8Q2+TN4sCoHw4y4dT+6qieI+4Dl08 e8LY3cP6pBRkxKEPjhQtZziUpowPL/+HugR0DerYFIQngTuKJV4BVNdVkwCysdNUbjDtNs2/LZ5 GkHg3teNdKut5oRwo2X54BSabdg7Li4uqzACnnK3DzSJNaYV0AMp/Y4Sl8muQ4HDmbYPoQboN61 j7wq5i0UepkYp5/bhRQYLy0e9oU+Kt0aP5DyfmUI77+u/mEJ4YHKHR3sFxELH1vJMGCKbMTN9qp nFze5mtsSli9eIiY5v7LduL4vQdP9CW6f0WFA7LhwWgw25KJ3aLogsMTpW2z1bnjvJDg== X-Received: by 2002:a05:600c:34d4:b0:465:a51d:d4 with SMTP id 5b1f17b1804b1-48373a1611fmr43468945e9.6.1771000154460; Fri, 13 Feb 2026 08:29:14 -0800 (PST) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Romain Caritey , Oleksii Kurochko , Alistair Francis , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH v4 04/16] xen/riscv: implement vcpu_csr_init() Date: Fri, 13 Feb 2026 17:28:50 +0100 Message-ID: <7c58dfbac99694811e4276858b48baa211331229.1770999383.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1771000177580154100 Content-Type: text/plain; charset="utf-8" Introduce vcpu_csr_init() to initialise hypervisor CSRs that control vCPU execution and virtualization behaviour before the vCPU is first scheduled. The function configures trap and interrupt delegation to VS-mode by setting the appropriate bits in the hedeleg and hideleg registers, initializes hstatus so that execution enters VS-mode when control is passed to the guest, and restricts guest access to hardware performance counters by initializing hcounteren, as unrestricted access would require additional handling in Xen. When the Smstateen and SSAIA extensions are available, access to AIA CSRs and IMSIC guest interrupt files is enabled by setting the corresponding bits in hstateen0, avoiding unnecessary traps into Xen (note that SVSLCT(Supervisor Virtual Select) name is used intead of CSRIND as OpenSBI uses such name and riscv_encoding.h is mostly based on it). If the Svpbmt extension is supported, the PBMTE bit is set in henvcfg to allow its use for VS-stage address translation. Guest access to the ENVCFG CSR is also enabled by setting ENVCFG bit in hstateen0, as a guest may need to control certain characteristics of the U-mode (VU-mode when V=3D1) execution environment. For CSRs that may contain read-only bits (e.g. hedeleg, hideleg, hstateen0), to the written value a correspondent mask is applied to avoid divergence between the software state and the actual CSR contents. As hstatus is not part of struct arch_vcpu (it already resides in struct cpu_user_regs), introduce vcpu_guest_cpu_user_regs() to provide a uniform way to access hstatus and other guest CPU user registers. This establishes a consistent and well-defined initial CSR state for vCPUs prior to their first context switch. Signed-off-by: Oleksii Kurochko --- Changes in v4: - Move local variable hstateen0 into narrower scope. - Code style fixes. - Move the call of vcpu_csr_init(v) after if ( is_idle_vcpu() ) check in arcg_vcpu_create(). --- Changes in v3: - Add hypervisor register used to initalize vCPU state. - Apply masks introduced before instead of csr_write()/csr_read() pattern. --- Changes in v2: - As hstatus isn't a part of arch_vcpu structure (as it is already a part = of cpu_user_regs) introduce vcpu_guest_cpu_user_regs() to be able to access hstatus and other CPU user regs. - Sort hideleg bit setting by value. Drop a stray blank. - Drop | when the first initialization of hcounteren and hennvcfg happen. - Introduce HEDELEG_DEFAULT. Sort set bits by value and use BIT() macros instead of open-coding it. - Apply pattern csr_write() -> csr_read() for hedeleg and hideleg instead of direct bit setting in v->arch.h{i,e}deleg as it could be that for some reason some bits of hedeleg and hideleg are r/o. The similar patter is used for hstateen0 as some of the bits could be r/= o. - Add check that SSAIA is avaialable before setting of SMSTATEEN0_AIA | SMSTATEEN0_IMSIC | SMSTATEEN0_SVSLCT bits. - Drop local variables hstatus, hideleg and hedeleg as they aren't used anymore. --- xen/arch/riscv/domain.c | 66 +++++++++++++++++++++ xen/arch/riscv/include/asm/current.h | 2 + xen/arch/riscv/include/asm/domain.h | 6 ++ xen/arch/riscv/include/asm/riscv_encoding.h | 2 + 4 files changed, 76 insertions(+) diff --git a/xen/arch/riscv/domain.c b/xen/arch/riscv/domain.c index 5572e10bfaa9..6c8a6269d791 100644 --- a/xen/arch/riscv/domain.c +++ b/xen/arch/riscv/domain.c @@ -6,10 +6,74 @@ #include #include =20 +#include +#include +#include #include =20 struct csr_masks __ro_after_init csr_masks; =20 +#define HEDELEG_DEFAULT (BIT(CAUSE_MISALIGNED_FETCH, U) | \ + BIT(CAUSE_FETCH_ACCESS, U) | \ + BIT(CAUSE_ILLEGAL_INSTRUCTION, U) | \ + BIT(CAUSE_BREAKPOINT, U) | \ + BIT(CAUSE_MISALIGNED_LOAD, U) | \ + BIT(CAUSE_LOAD_ACCESS, U) | \ + BIT(CAUSE_MISALIGNED_STORE, U) | \ + BIT(CAUSE_STORE_ACCESS, U) | \ + BIT(CAUSE_USER_ECALL, U) | \ + BIT(CAUSE_FETCH_PAGE_FAULT, U) | \ + BIT(CAUSE_LOAD_PAGE_FAULT, U) | \ + BIT(CAUSE_STORE_PAGE_FAULT, U)) + +#define HIDELEG_DEFAULT (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP) + +static void vcpu_csr_init(struct vcpu *v) +{ + v->arch.hedeleg =3D HEDELEG_DEFAULT & csr_masks.hedeleg; + + vcpu_guest_cpu_user_regs(v)->hstatus =3D HSTATUS_SPV | HSTATUS_SPVP; + + v->arch.hideleg =3D HIDELEG_DEFAULT & csr_masks.hideleg; + + /* + * VS should access only the time counter directly. + * Everything else should trap. + */ + v->arch.hcounteren =3D HCOUNTEREN_TM; + + if ( riscv_isa_extension_available(NULL, RISCV_ISA_EXT_svpbmt) ) + v->arch.henvcfg =3D ENVCFG_PBMTE & csr_masks.henvcfg; + + if ( riscv_isa_extension_available(NULL, RISCV_ISA_EXT_smstateen) ) + { + register_t hstateen0 =3D 0; + + if ( riscv_isa_extension_available(NULL, RISCV_ISA_EXT_ssaia) ) + /* + * If the hypervisor extension is implemented, the same three + * bits are defined also in hypervisor CSR hstateen0 but conce= rn + * only the state potentially accessible to a virtual machine + * executing in privilege modes VS and VU: + * bit 60 CSRs siselect and sireg (really vsiselect and + * vsireg) + * bit 59 CSRs siph and sieh (RV32 only) and stopi (really + * vsiph, vsieh, and vstopi) + * bit 58 all state of IMSIC guest interrupt files, inclu= ding + * CSR stopei (really vstopei) + * If one of these bits is zero in hstateen0, and the same bit= is + * one in mstateen0, then an attempt to access the correspondi= ng + * state from VS or VU-mode raises a virtual instruction excep= tion. + */ + hstateen0 =3D SMSTATEEN0_AIA | SMSTATEEN0_IMSIC | SMSTATEEN0_S= VSLCT; + + /* Allow guest to access CSR_ENVCFG */ + hstateen0 |=3D SMSTATEEN0_HSENVCFG; + + v->arch.hstateen0 =3D hstateen0 & csr_masks.hstateen0; + } +} + static void continue_new_vcpu(struct vcpu *prev) { BUG_ON("unimplemented\n"); @@ -41,6 +105,8 @@ int arch_vcpu_create(struct vcpu *v) if ( is_idle_vcpu(v) ) return rc; =20 + vcpu_csr_init(v); + /* * As the vtimer and interrupt controller (IC) are not yet implemented, * return an error. diff --git a/xen/arch/riscv/include/asm/current.h b/xen/arch/riscv/include/= asm/current.h index 58c9f1506b7c..5fbee8182caa 100644 --- a/xen/arch/riscv/include/asm/current.h +++ b/xen/arch/riscv/include/asm/current.h @@ -48,6 +48,8 @@ DECLARE_PER_CPU(struct vcpu *, curr_vcpu); #define get_cpu_current(cpu) per_cpu(curr_vcpu, cpu) =20 #define guest_cpu_user_regs() ({ BUG_ON("unimplemented"); NULL; }) +#define vcpu_guest_cpu_user_regs(vcpu) \ + (&(vcpu)->arch.cpu_info->guest_cpu_user_regs) =20 #define switch_stack_and_jump(stack, fn) do { \ asm volatile ( \ diff --git a/xen/arch/riscv/include/asm/domain.h b/xen/arch/riscv/include/a= sm/domain.h index f78f145258d6..6bb06a50c6ab 100644 --- a/xen/arch/riscv/include/asm/domain.h +++ b/xen/arch/riscv/include/asm/domain.h @@ -48,6 +48,12 @@ struct arch_vcpu { } xen_saved_context; =20 struct cpu_info *cpu_info; + + register_t hcounteren; + register_t hedeleg; + register_t henvcfg; + register_t hideleg; + register_t hstateen0; }; =20 struct paging_domain { diff --git a/xen/arch/riscv/include/asm/riscv_encoding.h b/xen/arch/riscv/i= nclude/asm/riscv_encoding.h index 1f7e612366f8..dd15731a86fa 100644 --- a/xen/arch/riscv/include/asm/riscv_encoding.h +++ b/xen/arch/riscv/include/asm/riscv_encoding.h @@ -228,6 +228,8 @@ #define ENVCFG_CBIE_INV _UL(0x3) #define ENVCFG_FIOM _UL(0x1) =20 +#define HCOUNTEREN_TM BIT(1, U) + /* =3D=3D=3D=3D=3D User-level CSRs =3D=3D=3D=3D=3D */ =20 /* User Trap Setup (N-extension) */ --=20 2.52.0 From nobody Mon Apr 13 03:40:41 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; 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Note that smp_wmb() is used instead of smp_mb__before_atomic() as what we want to guarantee that if a bit in irqs_pending_mask is obversable that the correspondent bit in irqs_pending is observable too. Add lockless tracking of pending vCPU interrupts using atomic bitops. Two bitmaps are introduced: - irqs_pending =E2=80=94 interrupts currently pending for the vCPU - irqs_pending_mask =E2=80=94 bits that have changed in irqs_pending The design follows a multi-producer, single-consumer model, where the consumer is the vCPU itself. Producers may set bits in irqs_pending_mask without a lock. Clearing bits in irqs_pending_mask is performed only by the consumer via xchg(). The consumer must not write to irqs_pending and must not act on bits that are not set in the mask. Otherwise, extra synchronization should be provided. On RISC-V interrupts are not injected via guest registers, so pending interrupts must be recorded in irqs_pending (using the new vcpu_{un}set_interrupt() helpers) and flushed to the guest by updating HVIP before returning control to the guest. The consumer side is implemented in a follow-up patch. A barrier between updating irqs_pending and setting the corresponding mask bit in vcpu_set_interrupt()/vcpu_unset_interrupt() guarantees that if the consumer observes a mask bit set, the corresponding pending bit is also visible. This prevents missed interrupts during the flush. It is possible that a guest could have pending bit in the hardware register without being marked pending in irq_pending bitmap as: According to the RISC-V ISA specification: Bits hip.VSSIP and hie.VSSIE are the interrupt-pending and interrupt-enable bits for VS-level software interrupts. VSSIP in hip is an alias (writable) of the same bit in hvip. Additionally: When bit 2 of hideleg is zero, vsip.SSIP and vsie.SSIE are read-only zeros. Else, vsip.SSIP and vsie.SSIE are aliases of hip.VSSIP and hie.VSSIE. This means the guest may modify vsip.SSIP, which implicitly updates hip.VSSIP and the bit being written with 1 would also trigger an interrupt as according to the RISC-V spec: These conditions for an interrupt trap to occur must be evaluated in a bounded amount of time from when an interrupt becomes, or ceases to be, pending in sip, and must also be evaluated immediately following the execution of an SRET instruction or an explicit write to a CSR on which these interrupt trap conditions expressly depend (including sip, sie and sstatus). What means that IRQ_VS_SOFT must be synchronized separately, what is done in vcpu_sync_interrupts(). Note, also, that IRQ_PMU_OVF would want to be synced for the similar reason as IRQ_VS_SOFT, but isn't sync-ed now as PMU isn't supported now. For the remaining VS-level interrupt types (IRQ_VS_TIMER and IRQ_VS_EXT), the specification states they cannot be modified by the guest and are read-only because of: Bits hip.VSEIP and hie.VSEIE are the interrupt-pending and interrupt-enab= le bits for VS-level external interrupts. VSEIP is read-only in hip, and is the logical-OR of these interrupt sources: =E2=80=A2 bit VSEIP of hvip; =E2=80=A2 the bit of hgeip selected by hstatus.VGEIN; and =E2=80=A2 any other platform-specific external interrupt signal directe= d to VS-level. Bits hip.VSTIP and hie.VSTIE are the interrupt-pending and interrupt-enab= le bits for VS-level timer interrupts. VSTIP is read-only in hip, and is the logical-OR of hvip.VSTIP and any other platform-specific timer interrupt signal directed to VS-level. and When bit 10 of hideleg is zero, vsip.SEIP and vsie.SEIE are read-only zer= os. Else, vsip.SEIP and vsie.SEIE are aliases of hip.VSEIP and hie.VSEIE. When bit 6 of hideleg is zero, vsip.STIP and vsie.STIE are read-only zero= s. Else, vsip.STIP and vsie.STIE are aliases of hip.VSTIP and hie.VSTIE. and also, Bits sip.SEIP and sie.SEIE are the interrupt-pending and interrupt-enable bits for supervisor-level external interrupts. If implemented, SEIP is read-only in sip, and is set and cleared by the execution environment, typically through a platform-specific interrupt controller. Bits sip.STIP and sie.STIE are the interrupt-pending and interrupt-enable bits for supervisor-level timer interrupts. If implemented, STIP is read-only in sip, and is set and cleared by the execution environment Thus, for these interrupt types, it is sufficient to use vcpu_set_interrupt= () and vcpu_unset_interrupt(), and flush them during the call of vcpu_flush_interrupts() (which is introduced in follow up patch). vcpu_sync_interrupts(), which is called just before entering the VM, slightly bends the rule that the irqs_pending bit must be written first, followed by updating the corresponding bit in irqs_pending_mask. However, it still respects the core guarantee that the producer never clears the mask and only writes to irqs_pending if it is the one that flipped the corresponding mask bit from 0 to 1. Moreover, since the consumer won't run concurrently because vcpu_sync_interrupts() and the consumer path are going to be invoked equentially immediately before VM entry, it is safe to slightly relax this ordering rule in vcpu_sync_interrupts(). Signed-off-by: Oleksii Kurochko --- Changes in v4: - Update the commit message. - Update the comments in vcpu_(un)set_interrupt() and add the the comment above smp_wmb() barrier. - call vcpu_kick() only if the pending_mask bit going from 0 to 1. - Code style fixes. - Update defintion of RISCV_VCPU_NR_IRQS to cover potential RV128 case and the case if AIA isn't used. - latch current into a local variable in check_for_pcpu_work(). --- Changes in v3: - Use smp_wb() instead of smp_mb__before_atomic(). - Add explanation of the change above in the commit message. - Move vcpu_sync_interrupts() here to producers side. - Introduce check_for_pcpu_work() to be clear from where vcpu_sync_interru= pts() is called. --- Changes in V2: - Move the patch before an introduction of vtimer. - Drop bitmap_zero() of irqs_pending and irqs_pending_mask bitmaps as vcpu structure starts out all zeros. - Drop const for irq argument of vcpu_{un}set_interrupt(). - Drop check "irq < IRQ_LOCAL_MAX" in vcpu_{un}set_interrupt() as it could lead to overrun of irqs_pending and irqs_pending_mask bitmaps. - Drop IRQ_LOCAL_MAX as there is no usage for it now. --- xen/arch/riscv/domain.c | 71 +++++++++++++++++++++++++++++ xen/arch/riscv/include/asm/domain.h | 24 ++++++++++ xen/arch/riscv/traps.c | 10 ++++ 3 files changed, 105 insertions(+) diff --git a/xen/arch/riscv/domain.c b/xen/arch/riscv/domain.c index 6c8a6269d791..edbac39a0b18 100644 --- a/xen/arch/riscv/domain.c +++ b/xen/arch/riscv/domain.c @@ -6,6 +6,7 @@ #include #include =20 +#include #include #include #include @@ -127,3 +128,73 @@ void arch_vcpu_destroy(struct vcpu *v) { vfree((void *)&v->arch.cpu_info[1] - STACK_SIZE); } + +int vcpu_set_interrupt(struct vcpu *v, unsigned int irq) +{ + /* We only allow VS-mode software, timer, and external interrupts */ + if ( irq !=3D IRQ_VS_SOFT && + irq !=3D IRQ_VS_TIMER && + irq !=3D IRQ_VS_EXT ) + return -EINVAL; + + set_bit(irq, v->arch.irqs_pending); + /* + * The counterpart of this barrier is the one encoded implicitly in xc= hg() + * which is used in consumer part (vcpu_flush_interrupts()). + */ + smp_wmb(); + set_bit(irq, v->arch.irqs_pending_mask); + + if ( !test_and_set_bit(irq, v->arch.irqs_pending_mask) ) + vcpu_kick(v); + + return 0; +} + +int vcpu_unset_interrupt(struct vcpu *v, unsigned int irq) +{ + /* We only allow VS-mode software, timer, external interrupts */ + if ( irq !=3D IRQ_VS_SOFT && + irq !=3D IRQ_VS_TIMER && + irq !=3D IRQ_VS_EXT ) + return -EINVAL; + + clear_bit(irq, v->arch.irqs_pending); + /* + * The counterpart of this barrier is the one encoded implicitly in xc= hg() + * which is used in consumer part (vcpu_flush_interrupts()). + */ + smp_wmb(); + set_bit(irq, v->arch.irqs_pending_mask); + + return 0; +} + +void vcpu_sync_interrupts(struct vcpu *v) +{ + unsigned long hvip; + + /* Read current HVIP and VSIE CSRs */ + v->arch.vsie =3D csr_read(CSR_VSIE); + + /* Sync-up HVIP.VSSIP bit changes done by Guest */ + hvip =3D csr_read(CSR_HVIP); + if ( ((v->arch.hvip ^ hvip) & BIT(IRQ_VS_SOFT, UL)) && + !test_and_set_bit(IRQ_VS_SOFT, &v->arch.irqs_pending_mask) ) + { + if ( hvip & BIT(IRQ_VS_SOFT, UL) ) + set_bit(IRQ_VS_SOFT, &v->arch.irqs_pending); + else + clear_bit(IRQ_VS_SOFT, &v->arch.irqs_pending); + } + + /* + * Sync-up AIA high interrupts. + * + * It is necessary to do only for CONFIG_RISCV_32 which isn't supported + * now. + */ +#ifdef CONFIG_RISCV_32 +# error "Update v->arch.vsieh" +#endif +} diff --git a/xen/arch/riscv/include/asm/domain.h b/xen/arch/riscv/include/a= sm/domain.h index 6bb06a50c6ab..2793f694d36f 100644 --- a/xen/arch/riscv/include/asm/domain.h +++ b/xen/arch/riscv/include/asm/domain.h @@ -54,6 +54,25 @@ struct arch_vcpu { register_t henvcfg; register_t hideleg; register_t hstateen0; + register_t hvip; + + register_t vsie; + + /* + * VCPU interrupts + * + * We have a lockless approach for tracking pending VCPU interrupts + * implemented using atomic bitops. The irqs_pending bitmap represent + * pending interrupts whereas irqs_pending_mask represent bits changed + * in irqs_pending. Our approach is modeled around multiple producer + * and single consumer problem where the consumer is the VCPU itself. + * + * DECLARE_BITMAP() is needed here to support 64 vCPU local interrupts + * on RV32 host. + */ +#define RISCV_VCPU_NR_IRQS MAX(BITS_PER_LONG, 64) + DECLARE_BITMAP(irqs_pending, RISCV_VCPU_NR_IRQS); + DECLARE_BITMAP(irqs_pending_mask, RISCV_VCPU_NR_IRQS); }; =20 struct paging_domain { @@ -92,6 +111,11 @@ static inline void update_guest_memory_policy(struct vc= pu *v, =20 static inline void arch_vcpu_block(struct vcpu *v) {} =20 +int vcpu_set_interrupt(struct vcpu *v, unsigned int irq); +int vcpu_unset_interrupt(struct vcpu *v, unsigned int irq); + +void vcpu_sync_interrupts(struct vcpu *v); + #endif /* ASM__RISCV__DOMAIN_H */ =20 /* diff --git a/xen/arch/riscv/traps.c b/xen/arch/riscv/traps.c index c81a4f79a0d2..366c3ff23e76 100644 --- a/xen/arch/riscv/traps.c +++ b/xen/arch/riscv/traps.c @@ -169,6 +169,13 @@ static void do_unexpected_trap(const struct cpu_user_r= egs *regs) die(); } =20 +static void check_for_pcpu_work(void) +{ + struct vcpu *c =3D current; + + vcpu_sync_interrupts(c); +} + void do_trap(struct cpu_user_regs *cpu_regs) { register_t pc =3D cpu_regs->sepc; @@ -222,6 +229,9 @@ void do_trap(struct cpu_user_regs *cpu_regs) do_unexpected_trap(cpu_regs); break; } + + if ( cpu_regs->hstatus & HSTATUS_SPV ) + check_for_pcpu_work(); } =20 void vcpu_show_execution_state(struct vcpu *v) --=20 2.52.0 From nobody Mon Apr 13 03:40:41 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1771000185; cv=none; d=zohomail.com; s=zohoarc; b=Fny3cRgILYgPVBbUP/9XIR5VTYiRDwBCGUIzo3OanuMLcFr4BfrDSJpLh1mRiXeLx+VeHsvevyM3cKCRfMAh6FFwHhPSU6DbDLsnRZHHTTvhWVkrbPg6HyBGGktRCgdyS9g/Ia9XJfuathQAttWpxxKD2D3thEl4ZHbuXnLOQAc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1771000185; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=g8aUJGUOJbQQ949TKJQepHTgKcmZAnEVr+LIZcPPPBc=; b=DAm98zlfL388EGjXF93WYTMM5C5WaYm7cun36IXr4A4thvrwW1rpl9T6xdp6Rm1k1tw7wjWGGvzcWt7MjAfWiWaktjJjhuA+DXGGsWr5CxkVjyXNogkeKwNhXl5Fuav7s7PgS5LKSp27hTznm31XSlFOMxxQvJMQuL4LAayKOVc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1771000185410480.77628319073824; Fri, 13 Feb 2026 08:29:45 -0800 (PST) Received: from list by lists.xenproject.org with outflank-mailman.1231315.1536535 (Exim 4.92) (envelope-from ) id 1vqw2i-0006li-Er; Fri, 13 Feb 2026 16:29:20 +0000 Received: by outflank-mailman (output) from mailman id 1231315.1536535; Fri, 13 Feb 2026 16:29:20 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vqw2i-0006ks-Ai; Fri, 13 Feb 2026 16:29:20 +0000 Received: by outflank-mailman (input) for mailman id 1231315; Fri, 13 Feb 2026 16:29:18 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vqw2g-0005Ws-9f for xen-devel@lists.xenproject.org; Fri, 13 Feb 2026 16:29:18 +0000 Received: from mail-wm1-x333.google.com (mail-wm1-x333.google.com [2a00:1450:4864:20::333]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 244823da-08f9-11f1-b163-2bf370ae4941; Fri, 13 Feb 2026 17:29:17 +0100 (CET) Received: by mail-wm1-x333.google.com with SMTP id 5b1f17b1804b1-483487335c2so10283795e9.2 for ; Fri, 13 Feb 2026 08:29:17 -0800 (PST) Received: from fedora (user-109-243-67-101.play-internet.pl. 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Add the consumer side (vcpu_flush_interrupts()) of the lockless pending interrupt tracking introduced in part 1 (for producers). According, to the design only one consumer is possible, and it is vCPU itself. vcpu_flush_interrupts() is expected to be ran (as guests aren't ran now due to the lack of functionality) before the hypervisor returns control to the guest. Producers may set bits in irqs_pending_mask without a lock. Clearing bits in irqs_pending_mask is performed only by the consumer via xchg() (with aquire semantics). The consumer must not write to irqs_pending and must not act on bits that are not set in the mask. Otherwise, extra synchronization should be provided. The worst thing which could happen with such approach is that a new pending bit will be set to irqs_pending bitmap during update of hvip variable in vcpu_flush_interrupt() but it isn't problem as the new pending bit won't be lost and just be proceded during the next flush. As AIA specs introduced hviph register which would want to be updated when guest related AIA code vcpu_update_hvip() is introduced instead of just open-code it in vcpu_flush_interrupts(). Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich --- Changes in v4: - Move defintion of hvip local variable to narrower space in vcpu_flush_interrupts(). - Use initializers for mask and val variables. - Use local variable c as an argument of vcpu_flush_interrupts() in check_for_pcpu_work(). --- Changes in v3: - Update the error message in case of RV32 from "hviph" to v->arch.hviph. - Make const argument of vcpu_update_hvip. - Move local variables mask and val inside if() in vcpu_flush_interrupts(). - Call vcpu_flush_interrupts() in check_pcpu_work(). - Move vcpu_update_hvip() inside if() in vcpu_flush_interrupts(). --- Changes in v2: - New patch. --- xen/arch/riscv/domain.c | 31 +++++++++++++++++++++++++++++ xen/arch/riscv/include/asm/domain.h | 1 + xen/arch/riscv/traps.c | 2 ++ 3 files changed, 34 insertions(+) diff --git a/xen/arch/riscv/domain.c b/xen/arch/riscv/domain.c index edbac39a0b18..35d8d5db02d0 100644 --- a/xen/arch/riscv/domain.c +++ b/xen/arch/riscv/domain.c @@ -198,3 +198,34 @@ void vcpu_sync_interrupts(struct vcpu *v) # error "Update v->arch.vsieh" #endif } + +static void vcpu_update_hvip(const struct vcpu *v) +{ + csr_write(CSR_HVIP, v->arch.hvip); +} + +void vcpu_flush_interrupts(struct vcpu *v) +{ + if ( ACCESS_ONCE(v->arch.irqs_pending_mask[0]) ) + { + register_t *hvip =3D &v->arch.hvip; + + unsigned long mask =3D xchg(&v->arch.irqs_pending_mask[0], 0UL); + unsigned long val =3D ACCESS_ONCE(v->arch.irqs_pending[0]) & mask; + + *hvip &=3D ~mask; + *hvip |=3D val; + + vcpu_update_hvip(v); + } + +/* + * Flush AIA high interrupts. + * + * It is necessary to do only for CONFIG_RISCV_32 which isn't + * supported now. + */ +#ifdef CONFIG_RISCV_32 +# error "Update v->arch.hviph" +#endif +} diff --git a/xen/arch/riscv/include/asm/domain.h b/xen/arch/riscv/include/a= sm/domain.h index 2793f694d36f..5d25a884eea6 100644 --- a/xen/arch/riscv/include/asm/domain.h +++ b/xen/arch/riscv/include/asm/domain.h @@ -115,6 +115,7 @@ int vcpu_set_interrupt(struct vcpu *v, unsigned int irq= ); int vcpu_unset_interrupt(struct vcpu *v, unsigned int irq); =20 void vcpu_sync_interrupts(struct vcpu *v); +void vcpu_flush_interrupts(struct vcpu *v); =20 #endif /* ASM__RISCV__DOMAIN_H */ =20 diff --git a/xen/arch/riscv/traps.c b/xen/arch/riscv/traps.c index 366c3ff23e76..77738a01c8b5 100644 --- a/xen/arch/riscv/traps.c +++ b/xen/arch/riscv/traps.c @@ -174,6 +174,8 @@ static void check_for_pcpu_work(void) struct vcpu *c =3D current; =20 vcpu_sync_interrupts(c); + + vcpu_flush_interrupts(c); } =20 void do_trap(struct cpu_user_regs *cpu_regs) --=20 2.52.0 From nobody Mon Apr 13 03:40:41 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1771000181; cv=none; d=zohomail.com; s=zohoarc; b=aj0QLvwNUJWKg1wE2pbKJ2kI6pez4spUrsn52ZCXi5Q5hiXKHHUZLVE3AawkOjAmbQJHtkMEWhvBdbWU7ercZHkBVT9Mcyxov2E8Xhqj9tuVprtxFSm9VF7AwCX4guh1WIiI5iaB5+M6nt3c4ddix05EaVTNs0xETCmnJT7WahM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; 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[109.243.67.101]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4834d5ebd1bsm303288185e9.6.2026.02.13.08.29.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Feb 2026 08:29:17 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 250672fc-08f9-11f1-b163-2bf370ae4941 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1771000158; x=1771604958; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=GtYixxVFRGricJNR3QGHatVLbdL2gCHohkRG/oMMero=; b=a9hrPUnYVSTpnjsjLOdKvuRFZD9HXiXb2CCe0xQaeZa4r7ZmNX1xF2TDtV0G7l02a8 hPxzBcDf0OeZfbXXtgApM9i5EQ1XzYXJQBaX3Xs94x1FDKGkVvx3DZiOqIVmB9VzvgyC i18Nnb8STNMDv+PsWF0u1xVn6AYMbTdrL1Dt5p1HgHiQqPpVb8NUujhEVAH+uNLCUx+m 0+OEsEBvFfRk3dLVSmxEZWosFeJy0Wd8vwOhb03B40LSDbRKRBelcmf74mpVXVhbFttI LNCP3vupLGsiM9R9UuHjcSNq/FOoVQ0m8zyGWZyMj7RSPRU1OqwsbcueQEdUbs2vHkZU Nkgg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1771000158; x=1771604958; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=GtYixxVFRGricJNR3QGHatVLbdL2gCHohkRG/oMMero=; b=BWlBfC7d6Aqr2+4QyRdCNzjzeMH/4Bm1jxMnTEwdgAnbh2QcF+GIzFR53YfhHwMBUA 9VP8BTouq8oP8ZBcEf7+YbEX3XmiX7HkKY0+H0gjguoZ+lTHibQfu0vgLyYNTPwaCtIm wJJLRWmgQzPbUIBqCJbX2GIgJyzjKiq3LMWVw+FIMnOGi/2Wzx7DMkZ2yKNV0Tb09shB IqcVnjdNicxSDYw+MyuiNh6x0P7AQAJJoDnzz2AMAkia5w2eWinYn0gfbW8gFDbpBRQP BtfP2Jyri/OGvkjVN6qgj7x5gEead/DbZA+qszuIRAyzdxWsp7SuTdLsvh/QdrPUGMJG qGRA== X-Gm-Message-State: AOJu0YxLeWJOH5ABvPRdXiCbpWh59uNVNl34qdPbHIlnWYzJnhdP/4Cz 6xNt67WBH0mtsJc6YGJM/GRjmnz/LetlPNhjoYfNcJR5qgAVytfr1YO4P27ywQia X-Gm-Gg: AZuq6aLiZOiIQE2kKeIoCeWed3lRwosKKGFq3bwLtLymUF/+x3dtsRcIeftW2I1U/6Y nWybUpmMrlliKlFk+PuOgbkJG8LxHA0Ipi0mnUIISjivXvsnLsY6gwRq25ApsGSPZz3fAh1Odc2 MX0c7zg4HD/mO2IbJGrDaoTSF1HygV44KMoJxgr6qwtQm0zMqglS2C3m7eACOTMdYo3ca/xef9L 94jbjVFIvta5c4U6boXX7bKtGhKkPzs/Uun0pHqdFuZhUFqX/JJx22zmk+FNNQ4yK3I7ej4AINX ROxlbLpPnJ1LVVhkYigz/XuAactimFn6ni7lZCOBTTvMg5qF482S2Jgtngu10uiBySucv9Xq1g0 px5SUBUAYDmK19wLot0eWYF70F67u8HIGdHAIXgBFxF6+Xfy0aIl18p4YhAGj/B++xDiLciN6C0 +Qdp6OjapA4Q7wJAu+knOspWwms4WX5oVnMw07lf2/5Z+2z+CpPecuiJW1zPN3zfowFowtPvKg7 rTv/dF3 X-Received: by 2002:a05:600c:1907:b0:477:73e9:dc17 with SMTP id 5b1f17b1804b1-48373a79afbmr42485465e9.35.1771000157888; Fri, 13 Feb 2026 08:29:17 -0800 (PST) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Romain Caritey , Oleksii Kurochko , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk , Andrew Cooper , Anthony PERARD , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Alistair Francis , Connor Davis Subject: [PATCH v4 07/16] xen/time: move ticks<->ns helpers to common code Date: Fri, 13 Feb 2026 17:28:53 +0100 Message-ID: <360aa61f2a0d1a95268e431909d1f210733d7dc9.1770999383.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1771000183468154100 Content-Type: text/plain; charset="utf-8" ticks_to_ns() and ns_to_ticks() are not architecture-specific, so provide a common implementation that is more resilient to overflow than the historical Arm version. This is not a practical issue for Arm, as the latest ARM ARM that timer frequency should be fixed at 1 GHz and older platforms used much lower rates, which is shy of 32-bit overflow. As the helpers are declared as static inline, they should not affect x86, which does not use them. On Arm, these helpers were historically implemented as out-of-line functions because the counter frequency was originally defined as static and unavaila= ble to headers [1]. Later changes [2] removed this restriction, but the helpers remained unchanged. Now they can be implemented as static inline without any issues. Centralising the helpers avoids duplication and removes subtle differences between architectures while keeping the implementation simple. Drop redundant includes where already pulls it in. No functional change is intended. [1] ddee56dc2994 arm: driver for the generic timer for ARMv7 [2] 096578b4e489 xen: move XEN_SYSCTL_physinfo, XEN_SYSCTL_numainfo and XEN_SYSCTL_topologyinfo to common code Suggested-by: Jan Beulich Signed-off-by: Oleksii Kurochko Reviewed-by: Jan Beulich --- Changes in v4: - Nothing changed. Only rebase. --- Changes in v3: - Add Reviewed-by: Jan Beulich . --- Changes in v2: - Move ns_to_ticks() and ticks_to_ns() to common code. --- xen/arch/arm/include/asm/time.h | 3 --- xen/arch/arm/time.c | 11 ----------- xen/arch/arm/vtimer.c | 2 +- xen/arch/riscv/include/asm/time.h | 5 ----- xen/arch/riscv/time.c | 1 + xen/include/xen/time.h | 11 +++++++++++ 6 files changed, 13 insertions(+), 20 deletions(-) diff --git a/xen/arch/arm/include/asm/time.h b/xen/arch/arm/include/asm/tim= e.h index 49ad8c1a6d47..c194dbb9f52d 100644 --- a/xen/arch/arm/include/asm/time.h +++ b/xen/arch/arm/include/asm/time.h @@ -101,9 +101,6 @@ extern void init_timer_interrupt(void); /* Counter value at boot time */ extern uint64_t boot_count; =20 -extern s_time_t ticks_to_ns(uint64_t ticks); -extern uint64_t ns_to_ticks(s_time_t ns); - void preinit_xen_time(void); =20 void force_update_vcpu_system_time(struct vcpu *v); diff --git a/xen/arch/arm/time.c b/xen/arch/arm/time.c index cc3fcf47b66a..a12912a106a0 100644 --- a/xen/arch/arm/time.c +++ b/xen/arch/arm/time.c @@ -27,7 +27,6 @@ #include #include #include -#include #include =20 uint64_t __read_mostly boot_count; @@ -47,16 +46,6 @@ unsigned int timer_get_irq(enum timer_ppi ppi) return timer_irq[ppi]; } =20 -/*static inline*/ s_time_t ticks_to_ns(uint64_t ticks) -{ - return muldiv64(ticks, SECONDS(1), 1000 * cpu_khz); -} - -/*static inline*/ uint64_t ns_to_ticks(s_time_t ns) -{ - return muldiv64(ns, 1000 * cpu_khz, SECONDS(1)); -} - static __initdata struct dt_device_node *timer; =20 #ifdef CONFIG_ACPI diff --git a/xen/arch/arm/vtimer.c b/xen/arch/arm/vtimer.c index d2124b175521..2e85ff2b6e62 100644 --- a/xen/arch/arm/vtimer.c +++ b/xen/arch/arm/vtimer.c @@ -12,13 +12,13 @@ #include #include #include +#include #include =20 #include #include #include #include -#include #include #include #include diff --git a/xen/arch/riscv/include/asm/time.h b/xen/arch/riscv/include/asm= /time.h index 1e7801e2ea0e..be3875b9984e 100644 --- a/xen/arch/riscv/include/asm/time.h +++ b/xen/arch/riscv/include/asm/time.h @@ -24,11 +24,6 @@ static inline cycles_t get_cycles(void) return csr_read(CSR_TIME); } =20 -static inline s_time_t ticks_to_ns(uint64_t ticks) -{ - return muldiv64(ticks, MILLISECS(1), cpu_khz); -} - void preinit_xen_time(void); =20 #endif /* ASM__RISCV__TIME_H */ diff --git a/xen/arch/riscv/time.c b/xen/arch/riscv/time.c index e962f8518d78..2c7af0a5d63b 100644 --- a/xen/arch/riscv/time.c +++ b/xen/arch/riscv/time.c @@ -4,6 +4,7 @@ #include #include #include +#include #include =20 unsigned long __ro_after_init cpu_khz; /* CPU clock frequency in kHz. */ diff --git a/xen/include/xen/time.h b/xen/include/xen/time.h index fe0d7a578a99..2185dd26a439 100644 --- a/xen/include/xen/time.h +++ b/xen/include/xen/time.h @@ -8,6 +8,7 @@ #ifndef __XEN_TIME_H__ #define __XEN_TIME_H__ =20 +#include #include #include =20 @@ -75,6 +76,16 @@ extern void send_timer_event(struct vcpu *v); =20 void domain_set_time_offset(struct domain *d, int64_t time_offset_seconds); =20 +static inline s_time_t ticks_to_ns(uint64_t ticks) +{ + return muldiv64(ticks, MILLISECS(1), cpu_khz); +} + +static inline uint64_t ns_to_ticks(s_time_t ns) +{ + return muldiv64(ns, cpu_khz, MILLISECS(1)); +} + #include =20 #endif /* __XEN_TIME_H__ */ --=20 2.52.0 From nobody Mon Apr 13 03:40:41 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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[109.243.67.101]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4834d5ebd1bsm303288185e9.6.2026.02.13.08.29.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Feb 2026 08:29:18 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 25e5c8fd-08f9-11f1-9ccf-f158ae23cfc8 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1771000159; x=1771604959; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=U12wg7j2L+OzyyqYL/Nhiy8muuFfmghvCXhWj5eSfXY=; b=HNzZqAzJCc5molMLJ+UjmCnCZMeS5Q0NGdGy6uVA2NuPfj3K2+GOLQV9kG9+J6R2Ue LWLfyvlLD39VYBoqFLlMhfbQQ9e70FcQuGWQ3GPNj9LWDFqeyuT6OM34731tpTImifLb Iu1MVS6YrBlKUH8B8I5ZtNkK/+LqNpmWbEBxNMjCZDDeEPSLrEbMKwJZe63Wj0YVWbho SZtzbIxlBG4QHbdMbqj1569je3l2J95R4NeVlwvpVtLxMYKmpJ//p9RNCogG8oK9KNtl dKR5jpFrhRlzX7RQdAdmeEfB25eyCuSm9ZTEhlx5+xEIn9PeYgXS38NqyE+KQ2BJ+NBs jUHA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1771000159; x=1771604959; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=U12wg7j2L+OzyyqYL/Nhiy8muuFfmghvCXhWj5eSfXY=; b=HsyyMfYopeonN2VQbx+MmRK9BbVFS+6KDgOLy/gZfKMKebhNxeHVcOugEiFS4stRPW vt06E+5jbM93d16oWoNCO7YIW6aBaRNXDofrFDiEVAfvzZ9BcguT0l9Il24Q2vdDY+Z4 bpRmU2XvvrMvTuKwAiV9SApkMHyUUsdviu8ze1n4y2IIvDEc4/KHIOyYrA0spB+pzln1 /iT9vlPsmOTn9sq5KW9zWArBcts5ce0Jfj2F3FcP7H2pZe8DnEo6kDixjKw4Fms3koWd fJ6ExGXpLpG6vEDHr34P5e1GZuFd/xJc4EvWaQpz94C+pRHjoCtoP8xwQBwo9/CYAC0J FRtw== X-Gm-Message-State: AOJu0YyQ+SRxNxVBN43DIAHKNRLR7rJ+8vlNffmgZjNohdM4JHKHzmbn NFRIC7WbfY5kiG86gpmv4kYfwrez1aHhhqJbNsUVl8DcXbj+YniVgTkvU3RCDTkk X-Gm-Gg: AZuq6aL5tOANSs5otA4dii4d3eoWJr2RPT0ciPQ5F2aC0z1qmU6HEmduiK5/BcOAH3f zoLVoEmbuUFD9WQ2rEfyig6OnEeHJplmpWZjNCgfe8hgMcmTmLriroAW6OHJrzpmcS4SX/U6XRJ VuQuqcI/eTuxkY1TusqHi7HjjsqQP9a3KQh7KLneYFoSZmnNqPM+US9xPqQW1oeFw4+NmP7CXYL vA4jxbZIxqu/qaHyi8tWb0V1Xq4yd1+ogUN8Yb/ix0pWnBzXS/2SEWB3k0ouTcMjgthxMkgSTcw bPSXS+bjRyrUJtRnDkBnohfIvUkegzj8DGNi/UyenTvga/pgOeTNgo6fgl/obWIzCJTcpwOXEt4 /kSEVo2C7luaf+5bgJoVlCvcenmnuiulASiKSqqiro+O5IHPbcLp9dcF63kiB1iEGWxGBxWJ+AY aFRrnIlbGtomWJw8MP4IFBohsYRgmHO5VnXlwndRCVdtcWspUKwbJ/QAoaX1NzKlp1GZU2vQ== X-Received: by 2002:a05:600c:4745:b0:483:6bb1:117 with SMTP id 5b1f17b1804b1-48373a7591amr33578375e9.32.1771000159094; Fri, 13 Feb 2026 08:29:19 -0800 (PST) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Romain Caritey , Oleksii Kurochko , Alistair Francis , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH v4 08/16] xen/riscv: introduce basic vtimer infrastructure for guests Date: Fri, 13 Feb 2026 17:28:54 +0100 Message-ID: <7426e2d974bfe67786c67709d487c7f64c22ae58.1770999383.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1771000186620158500 Lay the groundwork for guest timer support by introducing a per-vCPU virtual timer backed by Xen=E2=80=99s common timer infrastructure. The virtual timer is programmed in response to the guest SBI sbi_set_timer() call and injects a virtual supervisor timer interrupt into the vCPU when it expires. While a dedicated struct vtimer is not strictly required at present, it is expected to become necessary once SSTC support is introduced. In particular, it will need to carry additional state such as whether SSTC is enabled, the next compare value (e.g. for the VSTIMECMP CSR) to be saved and restored across context switches, and time delta state (e.g. HTIMEDELTA) required for use cases such as migration. Introducing struct vtimer now avoids a later refactoring. Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich --- Changes in v4: - Add vcpu_timer_destroy() to void arch_vcpu_destroy(). --- Changes in v3: - use one container_of() to get vcpu instead of two container_of()s. --- Changes in v2: - Drop domain_vtimer_init() as it does nothing. - Drop "struct vcpu *v;" from struct vtimer as it could be taken from arch_vcpu using container_of(). - Drop vtimer_initialized, use t->status =3D=3D TIMER_STATUS_invalid instead to understand if timer was or wasn't initialized. - Drop inclusion of xen/domain.h as xen/sched.h already includes it. - s/ xen/time.h/ xen.timer.h in vtimer.c. - Drop ULL in if-conidtion in vtimer_set_timer() as with the cast it isn't necessary to have suffix ULL. - Add migrate timer to vtimer_set_timer() to be sure that vtimer will occur on pCPU it was ran, so the signalling to that vCPU will (commonly) be cheaper. - Check if the timeout has already expired and just inject the event in vtimer_vtimer_set_timer(). - Drop const for ticks argument of vtimer_set_timer(). - Merge two patches to one: - xen/riscv: introduce vtimer - xen/riscv: introduce vtimer_set_timer() and vtimer_expired() --- xen/arch/riscv/Makefile | 1 + xen/arch/riscv/domain.c | 10 +++- xen/arch/riscv/include/asm/domain.h | 3 ++ xen/arch/riscv/include/asm/vtimer.h | 20 ++++++++ xen/arch/riscv/vtimer.c | 71 +++++++++++++++++++++++++++++ 5 files changed, 103 insertions(+), 2 deletions(-) create mode 100644 xen/arch/riscv/include/asm/vtimer.h create mode 100644 xen/arch/riscv/vtimer.c diff --git a/xen/arch/riscv/Makefile b/xen/arch/riscv/Makefile index bc47e83b26d7..ffbd7062e214 100644 --- a/xen/arch/riscv/Makefile +++ b/xen/arch/riscv/Makefile @@ -22,6 +22,7 @@ obj-y +=3D traps.o obj-y +=3D vmid.o obj-y +=3D vm_event.o obj-y +=3D vsbi/ +obj-y +=3D vtimer.o =20 $(TARGET): $(TARGET)-syms $(OBJCOPY) -O binary -S $< $@ diff --git a/xen/arch/riscv/domain.c b/xen/arch/riscv/domain.c index 35d8d5db02d0..45a7f0d1da7e 100644 --- a/xen/arch/riscv/domain.c +++ b/xen/arch/riscv/domain.c @@ -11,6 +11,7 @@ #include #include #include +#include =20 struct csr_masks __ro_after_init csr_masks; =20 @@ -108,11 +109,14 @@ int arch_vcpu_create(struct vcpu *v) =20 vcpu_csr_init(v); =20 + if ( (rc =3D vcpu_vtimer_init(v)) ) + goto fail; + /* - * As the vtimer and interrupt controller (IC) are not yet implemented, + * As interrupt controller (IC) is not yet implemented, * return an error. * - * TODO: Drop this once the vtimer and IC are implemented. + * TODO: Drop this once IC is implemented. */ rc =3D -EOPNOTSUPP; goto fail; @@ -126,6 +130,8 @@ int arch_vcpu_create(struct vcpu *v) =20 void arch_vcpu_destroy(struct vcpu *v) { + vcpu_timer_destroy(v); + vfree((void *)&v->arch.cpu_info[1] - STACK_SIZE); } =20 diff --git a/xen/arch/riscv/include/asm/domain.h b/xen/arch/riscv/include/a= sm/domain.h index 5d25a884eea6..3da2387cb197 100644 --- a/xen/arch/riscv/include/asm/domain.h +++ b/xen/arch/riscv/include/asm/domain.h @@ -8,6 +8,7 @@ #include =20 #include +#include =20 struct vcpu_vmid { uint64_t generation; @@ -49,6 +50,8 @@ struct arch_vcpu { =20 struct cpu_info *cpu_info; =20 + struct vtimer vtimer; + register_t hcounteren; register_t hedeleg; register_t henvcfg; diff --git a/xen/arch/riscv/include/asm/vtimer.h b/xen/arch/riscv/include/a= sm/vtimer.h new file mode 100644 index 000000000000..0d1555511755 --- /dev/null +++ b/xen/arch/riscv/include/asm/vtimer.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * (c) 2023-2024 Vates + */ + +#ifndef ASM__RISCV__VTIMER_H +#define ASM__RISCV__VTIMER_H + +#include + +struct vtimer { + struct timer timer; +}; + +int vcpu_vtimer_init(struct vcpu *v); +void vcpu_timer_destroy(struct vcpu *v); + +void vtimer_set_timer(struct vtimer *t, uint64_t ticks); + +#endif /* ASM__RISCV__VTIMER_H */ diff --git a/xen/arch/riscv/vtimer.c b/xen/arch/riscv/vtimer.c new file mode 100644 index 000000000000..32d142bcdfcd --- /dev/null +++ b/xen/arch/riscv/vtimer.c @@ -0,0 +1,71 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +#include + +static void vtimer_expired(void *data) +{ + struct vtimer *t =3D data; + struct vcpu *v =3D container_of(t, struct vcpu, arch.vtimer); + + vcpu_set_interrupt(v, IRQ_VS_TIMER); +} + +int vcpu_vtimer_init(struct vcpu *v) +{ + struct vtimer *t =3D &v->arch.vtimer; + + init_timer(&t->timer, vtimer_expired, t, v->processor); + + return 0; +} + +void vcpu_timer_destroy(struct vcpu *v) +{ + struct vtimer *t =3D &v->arch.vtimer; + + if ( t->timer.status =3D=3D TIMER_STATUS_invalid ) + return; + + kill_timer(&v->arch.vtimer.timer); +} + +void vtimer_set_timer(struct vtimer *t, const uint64_t ticks) +{ + struct vcpu *v =3D container_of(t, struct vcpu, arch.vtimer); + s_time_t expires =3D ticks_to_ns(ticks - boot_clock_cycles); + + vcpu_unset_interrupt(v, IRQ_VS_TIMER); + + /* + * According to the RISC-V sbi spec: + * If the supervisor wishes to clear the timer interrupt without + * scheduling the next timer event, it can either request a timer + * interrupt infinitely far into the future (i.e., (uint64_t)-1), + * or it can instead mask the timer interrupt by clearing sie.STIE C= SR + * bit. + */ + if ( ticks =3D=3D ((uint64_t)~0) ) + { + stop_timer(&t->timer); + + return; + } + + if ( expires < NOW() ) + { + /* + * Simplify the logic if the timeout has already expired and just + * inject the event. + */ + stop_timer(&t->timer); + vcpu_set_interrupt(v, IRQ_VS_TIMER); + + return; + } + + migrate_timer(&t->timer, smp_processor_id()); + set_timer(&t->timer, expires); +} --=20 2.52.0 From nobody Mon Apr 13 03:40:41 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1771000190; cv=none; d=zohomail.com; s=zohoarc; b=EfVbT3UlrdsNZXdv7nRVS5RMMxToD6AHvnDbYOxJ3HwyUhl3Gd7hRUdlyCEo66ufa+eEil7FRPgTB0YT/00eC7iu5QguMGY5a48+O3tKFN45Zb0AcTs1NjVNl2rz1xLFXoLlDgFan5ybqAVzDZmntFQSZZkw/U7mYut9RFs1AP0= ARC-Message-Signature: i=1; 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This mirrors the behavior of Arm and enables proper vCPU wakeup handling on RISC-V. Remove the stub implementation from stubs.c, as it is now provided by arch/riscv/domain.c. Since vcpu_kick() calls perfc_incr(vcpu_kick), add perfcounter for vcpu_kick to handle the case when CONFIG_PERF_COUNTERS=3Dy. Although CONFIG_PERF_COUNTERS is not enabled by default, it can be enabled, for example, by randconfig what will lead to CI build issues. Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich --- Changes in v4: - Nothing changed. Only rebase. --- Changes in v3: - Add asm/perfc_defn.h to provide vcpu_kick perfcoounter to cover the case when CONFIG_PERF_COUNTERS=3Dy. --- Changes in v2: - Add Acked-by: Jan Beulich . --- xen/arch/riscv/domain.c | 14 ++++++++++++++ xen/arch/riscv/include/asm/Makefile | 1 - xen/arch/riscv/include/asm/perfc_defn.h | 3 +++ xen/arch/riscv/stubs.c | 5 ----- 4 files changed, 17 insertions(+), 6 deletions(-) create mode 100644 xen/arch/riscv/include/asm/perfc_defn.h diff --git a/xen/arch/riscv/domain.c b/xen/arch/riscv/domain.c index 45a7f0d1da7e..307da467c72e 100644 --- a/xen/arch/riscv/domain.c +++ b/xen/arch/riscv/domain.c @@ -1,9 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ =20 +#include #include #include #include #include +#include #include =20 #include @@ -235,3 +237,15 @@ void vcpu_flush_interrupts(struct vcpu *v) # error "Update v->arch.hviph" #endif } + +void vcpu_kick(struct vcpu *v) +{ + bool running =3D v->is_running; + + vcpu_unblock(v); + if ( running && v !=3D current ) + { + perfc_incr(vcpu_kick); + smp_send_event_check_mask(cpumask_of(v->processor)); + } +} diff --git a/xen/arch/riscv/include/asm/Makefile b/xen/arch/riscv/include/a= sm/Makefile index 3824f31c395c..86c56251d5d7 100644 --- a/xen/arch/riscv/include/asm/Makefile +++ b/xen/arch/riscv/include/asm/Makefile @@ -7,7 +7,6 @@ generic-y +=3D hypercall.h generic-y +=3D iocap.h generic-y +=3D irq-dt.h generic-y +=3D percpu.h -generic-y +=3D perfc_defn.h generic-y +=3D random.h generic-y +=3D softirq.h generic-y +=3D vm_event.h diff --git a/xen/arch/riscv/include/asm/perfc_defn.h b/xen/arch/riscv/inclu= de/asm/perfc_defn.h new file mode 100644 index 000000000000..8a4b945df662 --- /dev/null +++ b/xen/arch/riscv/include/asm/perfc_defn.h @@ -0,0 +1,3 @@ +/* This file is intended to be included multiple times. */ + +PERFCOUNTER(vcpu_kick, "vcpu: notify other vcpu") diff --git a/xen/arch/riscv/stubs.c b/xen/arch/riscv/stubs.c index c5784a436574..1f0add97b361 100644 --- a/xen/arch/riscv/stubs.c +++ b/xen/arch/riscv/stubs.c @@ -208,11 +208,6 @@ void vcpu_block_unless_event_pending(struct vcpu *v) BUG_ON("unimplemented"); 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[109.243.67.101]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4834d5ebd1bsm303288185e9.6.2026.02.13.08.29.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Feb 2026 08:29:21 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 2732d33a-08f9-11f1-9ccf-f158ae23cfc8 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1771000161; x=1771604961; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=5hWO4jWrfrLp9yyPELp3VQAn+IIJ4GM5hz6O0oK25QU=; b=CCIadwNVQE/aeo301zLTi9O2azuT9S4rQGI3SHrWi8m+kDwUCPazBIQhNlXEMxdDaQ RfXXMe/BSyiRAhdXThU0XWsnulvi+yQIEVhyDqNfT4qlJwAeFc0LDPnR8LsClAukGfi5 ka0kVDK0hmKiJVpkB6oc4K3yraQdwW1an5MdyFxiuPAo1IcLJgjmGfsp4p2tlrejTZtk QfmEilm9FYL0JlueRBNJZS0B+QCj3VdMtsgRXarCpSKjg8IN5RoC00IJswQofgoSEQVD 7OVKIreoSYZ4aLUofrQhIVws+JdYYNh87YKYpZ8xD8TOQzygvfCuwYNOlLq2PbWIr2ov wpSA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1771000161; x=1771604961; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=5hWO4jWrfrLp9yyPELp3VQAn+IIJ4GM5hz6O0oK25QU=; b=jj2DDOxv2IIwjKPnjBKOyujGdQak2jOmU513aIjMMIx5j5uNdKNPTp9xtaZ78HgMVu VaYwbZ/In/nY4vXHvYDCGY5d8Y8+Il4NEwlUdroWe29VAi3BJPvTQ4sEK6tVMGcZp6t/ TiJpJAhOcDtgoHMVWzsVv/2wifXcPHJVkxrV5mmv48KdS3s/FcrT0zDXbFJh9xigDpyS F7+uTZ6dwDDnRUNZfbGRhxlmW48uGtY1DJIu6b/ydaqEzaG/IWDXfn5nXXFNbFqAt6kJ 0fmK7F95hUxMJygt79lSw16wSsG6MGXGSleoa6lMPVQutcHi6S322VXF8q3Zn0TX/85Q NdqQ== X-Gm-Message-State: AOJu0Yw6o3aVVKT8eF7VyM6vFBIchn5dgU8dcmJ6oeHa5KowngsM2n3s w4gl60ZVlo3OUiQIyk6CgtasU72qTYYBXeOoMkS34RkRv/ef3ftBTQjlOJOHMM38 X-Gm-Gg: AZuq6aJL1ZN6zEeASpi67PvEPIgKoc/J/IxkH8xApJR1GE0Qrk+jnpcJBfB1UQcwQ/H HBXzl/q7WVDOgQURO0sOAWkDmFhJ6nGiUcQR+QoHvrbR/llz4G1qAaUrYmijnOKNB7jX2SEDufV XOOUnPLzZPeeobRDvuDo8yyFQXnoIi6HBXCL2lQu2BjOQPjvVbJp/mQy2ojnTvLzff8UcxClIqP 6xG2lFwJyEvdMxu18JCYFpPVOfAaS8tjN//OXMrmTIcZJJAUmDY3wTFkjynS6kjOtMqDQssX7E5 pFM62mJ5uSjtpWm6QNxJY3x9oYzB0NwkAiH9J1y/nnUhbVeZX0HEcu5hhmvuSK5SNcbzG4TXVld /y0Zk7Yqem0Y2+R3mMYhDsxYy1GeXDdWCbhUpm5xfyHPtn5ImURcWl8hDpI9RMrnl8ImqNdSLSs Fty4yKbNt2nS4rukbvXurHdo16gC0L9mXQd5wIVtJKotZf7uUZwy1iyEBLHOPYxXXEfJWw1/wpq +fu X-Received: by 2002:a05:600c:c8d:b0:480:699c:abe9 with SMTP id 5b1f17b1804b1-48373a7b3f1mr37905615e9.37.1771000161294; Fri, 13 Feb 2026 08:29:21 -0800 (PST) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Romain Caritey , Oleksii Kurochko , Alistair Francis , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH v4 10/16] xen/riscv: add vtimer context switch helpers Date: Fri, 13 Feb 2026 17:28:56 +0100 Message-ID: X-Mailer: git-send-email 2.52.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1771000194372158500 Content-Type: text/plain; charset="utf-8" Introduce vtimer_ctxt_switch_from() and vtimer_ctxt_switch_to() to handle virtual timer state across vCPU context switches. At present, vtimer_ctxt_switch_from() is a no-op because the RISC-V SSTC extension, which provides a virtualization-aware timer, is not yet supported. Xen therefore relies the virtual (SBI-based) timer. The virtual timer uses Xen's internal timer infrastructure and must be associated with the pCPU on which the vCPU is currently running so that timer events can be delivered efficiently. As a result, vtimer_ctxt_switch_= to() migrates the timer to the target pCPU when a vCPU is scheduled in. Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich --- Changes in v4: - Nothing changed. Only rebase. --- Changes in v3: - s/vtimer_ctx_switch_to/vtimer_ctxt_switch_to - s/vtimer_ctx_switch_from/vtimer_ctxt_switch_from - Add Acked-by: Jan Beulich . --- Changes in v2: - Align the parameters names for vtimer_ctx_switch_from() and vtimer_ctx_= switch_to() in declarations to match the ones in the defintions to make Misra happy. - s/vtimer_save/vtimer_ctx_switch_from. - s/vtimer_restore/vtimer_ctx_switch_to. - Update the commit message. --- xen/arch/riscv/include/asm/vtimer.h | 3 +++ xen/arch/riscv/vtimer.c | 15 +++++++++++++++ 2 files changed, 18 insertions(+) diff --git a/xen/arch/riscv/include/asm/vtimer.h b/xen/arch/riscv/include/a= sm/vtimer.h index 0d1555511755..c70b0226515e 100644 --- a/xen/arch/riscv/include/asm/vtimer.h +++ b/xen/arch/riscv/include/asm/vtimer.h @@ -17,4 +17,7 @@ void vcpu_timer_destroy(struct vcpu *v); =20 void vtimer_set_timer(struct vtimer *t, uint64_t ticks); =20 +void vtimer_ctxt_switch_from(struct vcpu *p); +void vtimer_ctxt_switch_to(struct vcpu *n); + #endif /* ASM__RISCV__VTIMER_H */ diff --git a/xen/arch/riscv/vtimer.c b/xen/arch/riscv/vtimer.c index 32d142bcdfcd..afd8a53a7387 100644 --- a/xen/arch/riscv/vtimer.c +++ b/xen/arch/riscv/vtimer.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ =20 +#include #include #include =20 @@ -69,3 +70,17 @@ void vtimer_set_timer(struct vtimer *t, const uint64_t t= icks) migrate_timer(&t->timer, smp_processor_id()); set_timer(&t->timer, expires); } + +void vtimer_ctxt_switch_from(struct vcpu *p) +{ + ASSERT(!is_idle_vcpu(p)); + + /* Nothing to do at the moment as SSTC isn't supported now. */ +} + +void vtimer_ctxt_switch_to(struct vcpu *n) +{ + ASSERT(!is_idle_vcpu(n)); + + migrate_timer(&n->arch.vtimer.timer, n->processor); +} --=20 2.52.0 From nobody Mon Apr 13 03:40:41 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1771000185; cv=none; d=zohomail.com; s=zohoarc; b=O5f3b/bIy/8+qALPMoe3K9RSx1D1BqqSZ8QluuxIwarvXKJvC6++bBgj8ZzlZXQ/5WedUrWRK0Y0lLhANB+f3l/cow9B3StL+BqJkg0cP22lrz4EzJSmwy9YcdoO93qhEQfdIt3Ooq5wRjqFZkBKEXY8JikRh27PHriCWm30gs4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1771000185; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=kV1At2uKXk7mbgmcEWB93vzkp5laONizknlqDWczQMQ=; b=juhMD7Msd6lODC6/3cnL4ilXiLTdSl0+ThFeCab4wd2V1EvXDyYyT8wW5KI8/lWdfn+azMrhPCm2XuwDWVPgaW/bxQm4euRoBGmtk9pF3AoG0K/0M6OzWSQOBgsWAYoXgHRdZWlEyoP4c4hPO7FabbVnoR2/PAq/eoiGc5AQ85E= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1771000185187811.8549212296653; Fri, 13 Feb 2026 08:29:45 -0800 (PST) Received: from list by lists.xenproject.org with outflank-mailman.1231323.1536587 (Exim 4.92) (envelope-from ) id 1vqw2p-00088w-4Z; Fri, 13 Feb 2026 16:29:27 +0000 Received: by outflank-mailman (output) from mailman id 1231323.1536587; Fri, 13 Feb 2026 16:29:27 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vqw2o-00087X-Mt; Fri, 13 Feb 2026 16:29:26 +0000 Received: by outflank-mailman (input) for mailman id 1231323; Fri, 13 Feb 2026 16:29:25 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vqw2n-0005Wn-5p for xen-devel@lists.xenproject.org; Fri, 13 Feb 2026 16:29:25 +0000 Received: from mail-wm1-x334.google.com (mail-wm1-x334.google.com [2a00:1450:4864:20::334]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 27cab0c3-08f9-11f1-9ccf-f158ae23cfc8; Fri, 13 Feb 2026 17:29:23 +0100 (CET) Received: by mail-wm1-x334.google.com with SMTP id 5b1f17b1804b1-4836e3288cdso6974395e9.0 for ; Fri, 13 Feb 2026 08:29:23 -0800 (PST) Received: from fedora (user-109-243-67-101.play-internet.pl. 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The handler now programs the vCPU=E2=80=99s virtual timer via vtimer_set_timer() and returns SBI_SUCCESS. This enables guests using the legacy SBI timer interface to schedule timer events correctly. Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich --- Changes in v3 - v4: - Nothing changed. Only rebase. --- Changes in v2: - Add Acked-by: Jan Beulich . --- xen/arch/riscv/vsbi/legacy-extension.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/xen/arch/riscv/vsbi/legacy-extension.c b/xen/arch/riscv/vsbi/l= egacy-extension.c index 2e8df191c295..090c23440cea 100644 --- a/xen/arch/riscv/vsbi/legacy-extension.c +++ b/xen/arch/riscv/vsbi/legacy-extension.c @@ -7,6 +7,7 @@ =20 #include #include +#include =20 static void vsbi_print_char(char c) { @@ -44,6 +45,11 @@ static int vsbi_legacy_ecall_handler(unsigned long eid, = unsigned long fid, ret =3D SBI_ERR_NOT_SUPPORTED; break; =20 + case SBI_EXT_0_1_SET_TIMER: + vtimer_set_timer(¤t->arch.vtimer, regs->a0); + regs->a0 =3D SBI_SUCCESS; + break; + default: /* * TODO: domain_crash() is acceptable here while things are still = under --=20 2.52.0 From nobody Mon Apr 13 03:40:41 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1771000190; cv=none; d=zohomail.com; s=zohoarc; b=gcJ/vXyjJI9Nd2Oa5Hedib0dZ++RbgMrBgFJAZBhlVcM6aSqqLlPd9nVyWlY6D+hSnTnEHHXgGZz3FrBC3m4YGRvd9YZ+4Sew4Qtd/kgJyNmuWQMDVAvfbvjKsKO2vw6T5rhBLVU4fopI/M9yDHYZobHvoDLbmhDRVJX08/ni3E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1771000190; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=CLlglP14ExjU++WXhAZWVrIW/WEgsqaINRWzZuIchKM=; b=bT1YGDEKbph4CqTnGTv8QPhQooF8lOepIZiR5prIYvQhkJlCvbH27qptbVXrKt3+aqcJjWQrIYwXKf++LDGldsEYSniraRoKgD2TRtShQVZ5VnQw+UD3NW+vceNtkFl3LHXdGJd8srQqhczlb1poqZgh88mNJG8X4NDG0F5cZ2U= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1771000190555343.37387035927634; Fri, 13 Feb 2026 08:29:50 -0800 (PST) Received: from list by lists.xenproject.org with outflank-mailman.1231324.1536590 (Exim 4.92) (envelope-from ) id 1vqw2p-0008E2-F3; Fri, 13 Feb 2026 16:29:27 +0000 Received: by outflank-mailman (output) from mailman id 1231324.1536590; Fri, 13 Feb 2026 16:29:27 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vqw2p-0008Cb-6R; Fri, 13 Feb 2026 16:29:27 +0000 Received: by outflank-mailman (input) for mailman id 1231324; Fri, 13 Feb 2026 16:29:26 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vqw2o-0005Wn-6I for xen-devel@lists.xenproject.org; Fri, 13 Feb 2026 16:29:26 +0000 Received: from mail-wm1-x335.google.com (mail-wm1-x335.google.com [2a00:1450:4864:20::335]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 287a6297-08f9-11f1-9ccf-f158ae23cfc8; Fri, 13 Feb 2026 17:29:24 +0100 (CET) Received: by mail-wm1-x335.google.com with SMTP id 5b1f17b1804b1-48371119eacso10399525e9.2 for ; Fri, 13 Feb 2026 08:29:24 -0800 (PST) Received: from fedora (user-109-243-67-101.play-internet.pl. [109.243.67.101]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4834d5ebd1bsm303288185e9.6.2026.02.13.08.29.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Feb 2026 08:29:23 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 287a6297-08f9-11f1-9ccf-f158ae23cfc8 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1771000164; x=1771604964; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=CLlglP14ExjU++WXhAZWVrIW/WEgsqaINRWzZuIchKM=; b=f4UH0M0NJRe//6Ej9tGfxpwZE7+bLCyFq9bE0Ixu3hL4vo6QKnJOc5Fn2I+TQA8vGr fPUPYGXmrDmIfWyVq5oL/qn8b4weln1NuXd0m+SLyLCx7yygOF9CFDW/d/s0by1z7SES laWM72zPAZdDgXJVLEtzdLBZBYnein7U0ugfe4sQ/4S2d7wBC1hChEXqa08qYIUMoaY0 qCYwKP9/ZSiYMUi8yKf/GHDVWPnmiI6OdBf6hqvPGdKMwD18N80n98GdUMtzG41uYOzZ nfed05URt2oalyTVnkTzvzJ4lIDZtsVZk/KSD3tkWlrM/PBZXPBsNNuZ3V37EpdY1O2k /srQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1771000164; x=1771604964; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=CLlglP14ExjU++WXhAZWVrIW/WEgsqaINRWzZuIchKM=; b=pqoJCtplbDEliVCf36MJDZM+OygJNoshQAey5n1bpZRzKHil4gOA3hxBRhG3lPX2Gf jZQs6Xop7/3upd+AnpYfgwsQLMvgYn/73zCYqc/rQ8fZkYjNFKM31DiGM3zLalK9cBIZ qEKL/6pP+0oCe8lcOaPloARW+v6KNe6f1oCm3y1AkP4OEgHQ5qrh9j4UtVjQDsYSCKNF /Ywu/y7j4xIEUhCtZFel0UTZ9owSyV93lyif/3J1IipNlEpmp29JhwOykJepDExZqC+i ULjS3uo9N9jFcE90f1jP+ICQQ4w7v3cmxSyYvdEft6y4vllmMeCqVeaZj5L7navkLva+ SBjw== X-Gm-Message-State: AOJu0Yx7McEE3Mpqf9FmXtKqdXaLtyLU4okLxdkqt3uASZPTSniNEqkd Zh7djugT+ImU+DLZdtaevCvu39EjPeUVl5IJAuClBAfLs0AUIoTv0dVusox8v1+d X-Gm-Gg: AZuq6aIAm3KBCFxmBEHUY3qGzh2Cigvf2nsYHI9zmiS1JmPYOzC4CLhtFx5JVg91ci+ aAtsb5uOpV6jSzIrkRWnFjpIZYChsThMrHiqoaQaLspGua0ViCi94BR2AuUo2Sx0Aby+nJf8aME KPK2ZiBIEkGTMIcVF6qr/3F4Vh3vhNgqKxWIEY1D5sjp5OCXkwcM7IAPEfAtD5l1XLIE+yBAbdI QEi45a7BgnhOstpdWPnMLLDDTyq83PCvMJqjioviTN/j+fmdaBbI0MCdHBnHhyf/fFcDO7jCVZF gh+LWD5pdP46o1p1hWMr3f/RJNRPSjn10wZPbKXVh4RSJklfZTOE7tpJ1gzmns+ZiwM46KB1UCi mMr6EBzPaWyKxMFfiJbNTl365akc9OK8l4IearHiLDz2SgPODirNY2n870d1RaewCHTiYCF4K6B RdMIQsoDuDPJSrhDC9PI8UatM1SQQx7DCRatz0NfuESIHceMLkX941175sCatU7SiKc9sHUA== X-Received: by 2002:a05:600c:4e49:b0:477:54cd:200e with SMTP id 5b1f17b1804b1-48373a08300mr40938015e9.1.1771000163535; Fri, 13 Feb 2026 08:29:23 -0800 (PST) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Romain Caritey , Oleksii Kurochko , Alistair Francis , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH v4 12/16] xen/riscv: introduce sbi_set_timer() Date: Fri, 13 Feb 2026 17:28:58 +0100 Message-ID: <6d811ceefa3bfc4e6bd5d11b0a4d4eef886bc693.1770999383.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1771000191612154100 Introduce a function pointer for sbi_set_timer(), since different OpenSBI versions may implement the TIME extension with different extension IDs and/or function IDs. If the TIME extension is not available, fall back to the legacy timer mechanism. This is useful when Xen runs as a guest under another Xen, because the TIME extension is not currently virtualised and therefore will not appear as available. Despite of the fact that sbi_set_timer_v01 is introduced and used as fall back, SBI v0.1 still isn't fully supported (with the current SBI calls usage, sbi_rfence_v01 should be introduced too), so panic() in sbi_init() isn't removed. The sbi_set_timer() pointer will be used by reprogram_timer() to program Xen=E2=80=99s physical timer as without SSTC extension there is no any other option except SBI call to do that as only M-timer is available for us. Use dprintk() for all the cases to print that a speicifc SBI extension is available as it isn't really necessary in case of release builds. Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich --- Changes in v4: - Add "stime_value is in absolute time" to the comment above declaration of sbi_set_timer() function pointer. - Add Acked-by: Jan Beulich . --- Changes in v3: - Init sbi_set_timer with sbi_set_timer_v01 as fallback value. - Sort SBI IDs in the same way as SBI EXT IDs are declared. - Add __ro_after_init for sbi_set_timer variable. - use dprintk instead of printk to print information if SBI ext is availab= le. --- Changes in v2: - Move up defintion of SBI_EXT_TIME_SET_TIMER and use the same padding as defintions around it. - Add an extra comment about stime_value granuality above declaration of sbi_set_timer function pointer. - Refactor implemetation of sbi_set_timer_v02(). - Provide fallback for sbi_set_timer_v01(). - Update the commit message. --- xen/arch/riscv/include/asm/sbi.h | 21 +++++++++++++++++ xen/arch/riscv/sbi.c | 40 +++++++++++++++++++++++++++++++- 2 files changed, 60 insertions(+), 1 deletion(-) diff --git a/xen/arch/riscv/include/asm/sbi.h b/xen/arch/riscv/include/asm/= sbi.h index 79f7ff5c5501..e612f49e425b 100644 --- a/xen/arch/riscv/include/asm/sbi.h +++ b/xen/arch/riscv/include/asm/sbi.h @@ -29,6 +29,7 @@ =20 #define SBI_EXT_BASE 0x10 #define SBI_EXT_RFENCE 0x52464E43 +#define SBI_EXT_TIME 0x54494D45 =20 /* SBI function IDs for BASE extension */ #define SBI_EXT_BASE_GET_SPEC_VERSION 0x0 @@ -48,6 +49,9 @@ #define SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA 0x5 #define SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID 0x6 =20 +/* SBI function IDs for TIME extension */ +#define SBI_EXT_TIME_SET_TIMER 0x0 + #define SBI_SPEC_VERSION_MAJOR_MASK 0x7f000000 #define SBI_SPEC_VERSION_MINOR_MASK 0x00ffffff =20 @@ -134,6 +138,23 @@ int sbi_remote_hfence_gvma(const cpumask_t *cpu_mask, = vaddr_t start, int sbi_remote_hfence_gvma_vmid(const cpumask_t *cpu_mask, vaddr_t start, size_t size, unsigned long vmid); =20 +/* + * Programs the clock for next event after stime_value time. stime_value i= s in + * absolute time. This function must clear the pending timer interrupt bit= as + * well. + * + * If the supervisor wishes to clear the timer interrupt without schedulin= g the + * next timer event, it can either request a timer interrupt infinitely far + * into the future (i.e., (uint64_t)-1), or it can instead mask the timer + * interrupt by clearing sie.STIE CSR bit. + * + * The stime_value parameter represents absolute time measured in ticks. + * + * This SBI call returns 0 upon success or an implementation specific nega= tive + * error code. + */ +extern int (* __ro_after_init sbi_set_timer)(uint64_t stime_value); + /* * Initialize SBI library * diff --git a/xen/arch/riscv/sbi.c b/xen/arch/riscv/sbi.c index 425dce44c679..b4a7ae6940c1 100644 --- a/xen/arch/riscv/sbi.c +++ b/xen/arch/riscv/sbi.c @@ -249,6 +249,38 @@ static int (* __ro_after_init sbi_rfence)(unsigned lon= g fid, unsigned long arg4, unsigned long arg5); =20 +static int cf_check sbi_set_timer_v02(uint64_t stime_value) +{ + struct sbiret ret; + + ret =3D sbi_ecall(SBI_EXT_TIME, SBI_EXT_TIME_SET_TIMER, stime_value, +#ifdef CONFIG_RISCV_32 + stime_value >> 32, +#else + 0, +#endif + 0, 0, 0, 0); + + return sbi_err_map_xen_errno(ret.error); +} + +static int cf_check sbi_set_timer_v01(uint64_t stime_value) +{ + struct sbiret ret; + + ret =3D sbi_ecall(SBI_EXT_0_1_SET_TIMER, 0, stime_value, +#ifdef CONFIG_RISCV_32 + stime_value >> 32, +#else + 0, +#endif + 0, 0, 0, 0); + + return sbi_err_map_xen_errno(ret.error); +} + +int (* __ro_after_init sbi_set_timer)(uint64_t stime_value) =3D sbi_set_ti= mer_v01; + int sbi_remote_sfence_vma(const cpumask_t *cpu_mask, vaddr_t start, size_t size) { @@ -324,7 +356,13 @@ int __init sbi_init(void) if ( sbi_probe_extension(SBI_EXT_RFENCE) > 0 ) { sbi_rfence =3D sbi_rfence_v02; - printk("SBI v0.2 RFENCE extension detected\n"); + dprintk(XENLOG_INFO, "SBI v0.2 RFENCE extension detected\n"); + } + + if ( sbi_probe_extension(SBI_EXT_TIME) > 0 ) + { + sbi_set_timer =3D sbi_set_timer_v02; + dprintk(XENLOG_INFO, "SBI v0.2 TIME extension detected\n"); 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[109.243.67.101]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4834d5ebd1bsm303288185e9.6.2026.02.13.08.29.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Feb 2026 08:29:24 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 291e1003-08f9-11f1-9ccf-f158ae23cfc8 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1771000165; x=1771604965; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=5shaKaLaj3PbsgiRISlWhSdddD1d/VOeFOR/4Kyrmqo=; b=WVwJyaSl4liyWVAePxTkCH+8vgRE8k0PDKiXxQtQwuWMFjX3lwgrEkLiVrsRE2Zdlm hWHKTHzfOg9dE5/NvetjIjtlT4Ca76RdIq/vAdvxgCFuYlfxiAZ4CytK+zDMGNBl1Z4x Uhhr5TuTBYSV5kA0H5Ek1DBGe7GGvZFIISf9ioPDG4slDSujJl2OubkeOdFMW7iCTKuf 2zdMK/clNe8Dc9YnvP4wNaJg/U6gxujxkUifg40z9KSrzcsrt0VE4jTOHaWNdqSsob8g Y7/z9pAhUyM717uOOjBeL32j4XP04MkJ7PwoSDK2/RHnfTixy9O+Txngfajr14LMriv+ UprQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1771000165; x=1771604965; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=5shaKaLaj3PbsgiRISlWhSdddD1d/VOeFOR/4Kyrmqo=; b=fHtH4cY6ZiybNktv50po9S/3MGhd3ms6jqFK6xgSoBZJ5c2FMvPprn1SZiXpaNjGMr +R8P2y1fojGchuyJDJWqASxQJbG2Zkni5/baQdOeaRUCBPyE3LXalLxlqMh+aM1La/8o SPHIu6qfnJ52iSQjZw0qDhL9Q3gx4FPdFxHBJyfqTFjayhwuq/ut5E6suLoJauQZb0Hx SsEXOhrDhgRlUYyUIvo4GqLX7EAUUT02Fug9xxrkUwRlC8lz45JaJG16R3FRYB1b7NsB MFm51ZQEoqxGhPUrm1f/M4+ZKJIH69bsbzXLQovT6kWc5cVrhAiox36zwuIZ+JSD6i/k ZRCQ== X-Gm-Message-State: AOJu0Yyd97Kvid5siagVfMkJje9dvIMUo1j2VCg5BwWpcIHrju2nLcF4 R41Dt9vIArmoAUdQEYllLFc63xT0PtNbZZ7ed4jodhFSPK7Ge7hQ5Ib0YhcLPY5W X-Gm-Gg: AZuq6aIH+EsK8c88nup36dsYr5/C2xok9eb7JvMxHNP9xEng10gqjMBadJv8fn7jBOr 8ROmk4pDT4s7A6KHf33VA/pc+puoAZJXqIvncCrYHl21FCoKBAvn6VtFykMr7nsJZB4Vg1hgdkB YjgNmTvpHULiBqgZMNXpUY5c5C03sMIpHJubAKw+A6LgiyTZyvBeWM1p99TjMo1Phr00wWn+Zu+ cVSLVw2p8QTMy+D6CkziGkpe3R7ZC/8mOvuMYa+BRMeU6idipwzlW8qcDNIyEQo0PgXYUEXnbmH IRGBM9C+fetwxgMalgtqaFnpJNQmedRJlVPTGzib50i197jAHVz+No/N06NYAmvQ+X3Cof1yeLH QJv+s7Behoiwjddh7D0L35SVmzJwcWFCgbTHJvD7HGszrpMX/G3gmUAJIeCiuxKmWm88qdUWZFd k3gZw38DeyqDrb9xOWYctKtBj7eyn1HOYNkShaVHlVxQF4RIwt4rzPRKOWedzIdXlnT1PYvA== X-Received: by 2002:a05:600c:64c6:b0:46e:4e6d:79f4 with SMTP id 5b1f17b1804b1-48373a2626dmr39747575e9.15.1771000164568; Fri, 13 Feb 2026 08:29:24 -0800 (PST) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Romain Caritey , Oleksii Kurochko , Alistair Francis , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH v4 13/16] xen/riscv: implement reprogram_timer() via SBI Date: Fri, 13 Feb 2026 17:28:59 +0100 Message-ID: X-Mailer: git-send-email 2.52.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1771000190533158501 Content-Type: text/plain; charset="utf-8" Implement reprogram_timer() on RISC-V using the standard SBI timer call. The privileged architecture only defines machine-mode timer interrupts (using mtime/mtimecmp). Therefore, timer services for S/HS/VS mode must be provided by M-mode via SBI calls. SSTC (Supervisor-mode Timer Control) is optional and is not supported on the boards available to me, so the only viable approach today is to program the timer through SBI. reprogram_timer() enables/disables the supervisor timer interrupt and programs the next timer deadline using sbi_set_timer(). If the SBI call fails, the code panics, because sbi_set_timer() is expected to return either 0 or -ENOSUPP (this has been stable from early OpenSBI versions to the latest ones). The SBI spec does not define a standard negative error code for this call, and without SSTC there is no alternative method to program the timer, so the SBI timer call must be available. reprogram_timer() currently returns int for compatibility with the existing prototype. While it might be cleaner to return bool, keeping the existing signature avoids premature changes in case sbi_set_timer() ever needs to return other values (based on which we could try to avoid panic-ing) in the future. Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich --- Changes in v4: - Add Acked-by: Jan Beulich . --- Changes in v3: - Correct the comments in reprogram_timer(). - Move enablement of timer interrupt after sbi_set_timer() to avoid potentially receiving a timer interrupt between these 2 operations. --- Changes in v2: - Add TODO comment above sbi_set_timer() call. - Update the commit message. --- xen/arch/riscv/stubs.c | 5 ----- xen/arch/riscv/time.c | 43 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 43 insertions(+), 5 deletions(-) diff --git a/xen/arch/riscv/stubs.c b/xen/arch/riscv/stubs.c index 1f0add97b361..cb7546558b8e 100644 --- a/xen/arch/riscv/stubs.c +++ b/xen/arch/riscv/stubs.c @@ -21,11 +21,6 @@ nodemask_t __read_mostly node_online_map =3D { { [0] =3D= 1UL } }; =20 /* time.c */ =20 -int reprogram_timer(s_time_t timeout) -{ - BUG_ON("unimplemented"); -} - void send_timer_event(struct vcpu *v) { BUG_ON("unimplemented"); diff --git a/xen/arch/riscv/time.c b/xen/arch/riscv/time.c index 2c7af0a5d63b..7efa76fdbcb1 100644 --- a/xen/arch/riscv/time.c +++ b/xen/arch/riscv/time.c @@ -7,6 +7,9 @@ #include #include =20 +#include +#include + unsigned long __ro_after_init cpu_khz; /* CPU clock frequency in kHz. */ uint64_t __ro_after_init boot_clock_cycles; =20 @@ -40,6 +43,46 @@ static void __init preinit_dt_xen_time(void) cpu_khz =3D rate / 1000; } =20 +int reprogram_timer(s_time_t timeout) +{ + uint64_t deadline, now; + int rc; + + if ( timeout =3D=3D 0 ) + { + /* Disable timer interrupt */ + csr_clear(CSR_SIE, BIT(IRQ_S_TIMER, UL)); + + return 1; + } + + deadline =3D ns_to_ticks(timeout) + boot_clock_cycles; + now =3D get_cycles(); + if ( deadline <=3D now ) + return 0; + + /* + * TODO: When the SSTC extension is supported, it would be preferable = to + * use the supervisor timer registers directly here for better + * performance, since an SBI call and mode switch would no longer + * be required. + * + * This would also reduce reliance on a specific SBI implementat= ion. + * For example, it is not ideal to panic() if sbi_set_timer() re= turns + * a non-zero value. Currently it can return 0 or -ENOSUPP, and + * without SSTC we still need an implementation because only the + * M-mode timer is available, and it can only be programmed in + * M-mode. + */ + if ( (rc =3D sbi_set_timer(deadline)) ) + panic("%s: timer wasn't set because: %d\n", __func__, rc); + + /* Enable timer interrupt */ + csr_set(CSR_SIE, BIT(IRQ_S_TIMER, UL)); + + return 1; +} + void __init preinit_xen_time(void) { if ( acpi_disabled ) --=20 2.52.0 From nobody Mon Apr 13 03:40:41 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1771000196; cv=none; d=zohomail.com; s=zohoarc; b=KC01M+S8jlpMIAH8csTNgyw4ndNPKTt2F8MWa7+t7YIYg91eS40nyxfNYrZXc1OflzZDlizWzJY9o45p0fcuhiIV+A4ez/ULhwwEogEdN59yYz+WeZcOH5WpVes4YtDLG/gs2beB86lXW6ZGSW4zLyosfexMAJGleIxHCJlWAwE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1771000196; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=W1EYQt5A3i5QUF1c7sbvdjSw7GZbau53/KdhZnxOwj0=; b=hr7Rz4lH+qlDJizL8wz+eFZkMFH6wvT7GeyFOKWuL4OYbaslpsMtl9vT3aPHaLzo+t6d0vYHA5zWLW6mBaa+5u5Rzcnvb5KeheCcWP/VTBUTBKPhmOIb1EBKdcyOWUIx/pKpVMrs3mtA0HmQKznViXN1izFUaKQe6vffWb/SGvA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1771000196078789.8227472372573; Fri, 13 Feb 2026 08:29:56 -0800 (PST) Received: from list by lists.xenproject.org with outflank-mailman.1231327.1536619 (Exim 4.92) (envelope-from ) id 1vqw2t-0000fI-Sd; Fri, 13 Feb 2026 16:29:31 +0000 Received: by outflank-mailman (output) from mailman id 1231327.1536619; Fri, 13 Feb 2026 16:29:31 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vqw2t-0000cR-0f; Fri, 13 Feb 2026 16:29:31 +0000 Received: by outflank-mailman (input) for mailman id 1231327; Fri, 13 Feb 2026 16:29:28 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vqw2q-0005Wn-Ij for xen-devel@lists.xenproject.org; Fri, 13 Feb 2026 16:29:28 +0000 Received: from mail-wm1-x32f.google.com (mail-wm1-x32f.google.com [2a00:1450:4864:20::32f]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 29e3e8cd-08f9-11f1-9ccf-f158ae23cfc8; Fri, 13 Feb 2026 17:29:27 +0100 (CET) Received: by mail-wm1-x32f.google.com with SMTP id 5b1f17b1804b1-480706554beso10850105e9.1 for ; Fri, 13 Feb 2026 08:29:26 -0800 (PST) Received: from fedora (user-109-243-67-101.play-internet.pl. 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The handler disables further timer interrupts by clearing SIE.STIE and raises TIMER_SOFTIRQ so the generic timer subsystem can perform its processing. Update do_trap() to dispatch IRQ_S_TIMER to this new handler. Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich --- Changes in v4: - Nothing changed. Only rebase. --- Changes in v3: - add Acked-by: Jan Beulich . --- Changes in v2: - Drop cause argument of timer_interrupt() as it isn't used inside the function and anyway it is pretty clear what is the cause inside timer_interrupt(). --- xen/arch/riscv/traps.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/xen/arch/riscv/traps.c b/xen/arch/riscv/traps.c index 77738a01c8b5..ce8d346a14d2 100644 --- a/xen/arch/riscv/traps.c +++ b/xen/arch/riscv/traps.c @@ -10,6 +10,7 @@ #include #include #include +#include =20 #include #include @@ -178,6 +179,15 @@ static void check_for_pcpu_work(void) vcpu_flush_interrupts(c); } =20 +static void timer_interrupt(void) +{ + /* Disable the timer to avoid more interrupts */ + csr_clear(CSR_SIE, BIT(IRQ_S_TIMER, UL)); + + /* Signal the generic timer code to do its work */ + raise_softirq(TIMER_SOFTIRQ); +} + void do_trap(struct cpu_user_regs *cpu_regs) { register_t pc =3D cpu_regs->sepc; @@ -219,6 +229,10 @@ void do_trap(struct cpu_user_regs *cpu_regs) intc_handle_external_irqs(cpu_regs); break; =20 + case IRQ_S_TIMER: + timer_interrupt(); + break; + default: intr_handled =3D false; break; --=20 2.52.0 From nobody Mon Apr 13 03:40:41 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1771000700; cv=none; d=zohomail.com; s=zohoarc; b=Z3Hek0DuoeAmZRzub0n4hh6aAkYX2+F47392DsKi+nQActFM4AYu76FSBQ93xSE1Qcx1mo+TD2BUosOFbG1H4RxFBNYetl3hCnnzsp0lwczKHVrotbEIdzyy1V1sURTELzWuLrpbrUhwxMW0dyhFIr4t1jxJMWhbPB0Gwxx+A74= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1771000700; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=4f8nWiqSAdQ3ihvLKp54Tg1Gj2dyPRa9lPHwnTHLKUI=; b=NkAmSCjOsE13eDuKZ1du0u8ZgXrkvHwDQlccAXPdtBMO1makKJtgpITg3doWP2hn5pMqYhUso7A2AF2msQ1c/K/M4gW0H9Pu7rWvKwPIgQjHD4MLbzqIEofryp2C9G2Cxnap1AGj08NMN1jNU5c7Dq5yF/j8UVV2H6E8HjcraMY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1771000700608349.4312111137899; Fri, 13 Feb 2026 08:38:20 -0800 (PST) Received: from list by lists.xenproject.org with outflank-mailman.1231445.1536651 (Exim 4.92) (envelope-from ) id 1vqwAz-0006pO-Fd; Fri, 13 Feb 2026 16:37:53 +0000 Received: by outflank-mailman (output) from mailman id 1231445.1536651; Fri, 13 Feb 2026 16:37:53 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vqwAz-0006pH-CO; Fri, 13 Feb 2026 16:37:53 +0000 Received: by outflank-mailman (input) for mailman id 1231445; Fri, 13 Feb 2026 16:37:52 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vqw2s-0005Wn-B7 for xen-devel@lists.xenproject.org; Fri, 13 Feb 2026 16:29:30 +0000 Received: from mail-wm1-x32b.google.com (mail-wm1-x32b.google.com [2a00:1450:4864:20::32b]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 2a88587e-08f9-11f1-9ccf-f158ae23cfc8; Fri, 13 Feb 2026 17:29:28 +0100 (CET) Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-48069a48629so10260255e9.0 for ; Fri, 13 Feb 2026 08:29:27 -0800 (PST) Received: from fedora (user-109-243-67-101.play-internet.pl. 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Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich --- Changes in v4: - Nothing changed. Only rebase. --- Changes in v3: - add Acked-by: Jan Beulich . --- Changes in v2: - Update the commit message. - Move implementation of sync_vcpu_execstate() to separate commit as it doesn't connect to tasklet subsystem. --- xen/arch/riscv/setup.c | 3 +++ xen/arch/riscv/stubs.c | 10 ---------- 2 files changed, 3 insertions(+), 10 deletions(-) diff --git a/xen/arch/riscv/setup.c b/xen/arch/riscv/setup.c index dc469b49623f..5843609350aa 100644 --- a/xen/arch/riscv/setup.c +++ b/xen/arch/riscv/setup.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -152,6 +153,8 @@ void __init noreturn start_xen(unsigned long bootcpu_id, panic("Booting using ACPI isn't supported\n"); } =20 + tasklet_subsys_init(); + init_IRQ(); =20 riscv_fill_hwcap(); diff --git a/xen/arch/riscv/stubs.c b/xen/arch/riscv/stubs.c index cb7546558b8e..26434166acc6 100644 --- a/xen/arch/riscv/stubs.c +++ b/xen/arch/riscv/stubs.c @@ -91,16 +91,6 @@ void continue_running(struct vcpu *same) BUG_ON("unimplemented"); } =20 -void sync_local_execstate(void) -{ - BUG_ON("unimplemented"); -} - -void sync_vcpu_execstate(struct vcpu *v) -{ - BUG_ON("unimplemented"); -} - void startup_cpu_idle_loop(void) { BUG_ON("unimplemented"); --=20 2.52.0 From nobody Mon Apr 13 03:40:41 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1771000721; cv=none; d=zohomail.com; s=zohoarc; b=D2/mlsr94vl9d0NC85u8GsUdWMnpYCD6uk16ojDFDebci32t569bCH9RgtzVH/4qNFQoZDj0p/CGZggxkgXj2Jiko898JDvZ0u0zdaVzw2oKGAOkX6gagPTmfiGzzdtVkeWANHd//fJX/mCsYK3mUoqsPlz8giwdfN/0h6+0Q7A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1771000721; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=aS1nE3ehxrhnhvUQVu6uQ+BpfKhXXAT1M63On5oqAkY=; b=eBf/JAFv73ftWV54B4m/Gy2Z/cp9+2aQSwGZI/GvYuw66kkZ769uGHX4uOllmHu9nirp/s/seAn+3NsTLEHVYr180IJc6BflmTyPZ9dFV+gNh4VCEbgIEzusCGdGFXCW6ontyqvcPZrqFMV5A35CLEdTqFJc6pmhq3X7AGdS390= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1771000721545666.5299608227741; Fri, 13 Feb 2026 08:38:41 -0800 (PST) Received: from list by lists.xenproject.org with outflank-mailman.1231469.1536661 (Exim 4.92) (envelope-from ) id 1vqwBS-0007i5-TN; Fri, 13 Feb 2026 16:38:22 +0000 Received: by outflank-mailman (output) from mailman id 1231469.1536661; Fri, 13 Feb 2026 16:38:22 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vqwBS-0007hy-Qg; Fri, 13 Feb 2026 16:38:22 +0000 Received: by outflank-mailman (input) for mailman id 1231469; Fri, 13 Feb 2026 16:38:20 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vqw2r-0005Ws-ED for xen-devel@lists.xenproject.org; Fri, 13 Feb 2026 16:29:29 +0000 Received: from mail-wm1-x334.google.com (mail-wm1-x334.google.com [2a00:1450:4864:20::334]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 2b0d0c2d-08f9-11f1-b163-2bf370ae4941; Fri, 13 Feb 2026 17:29:28 +0100 (CET) Received: by mail-wm1-x334.google.com with SMTP id 5b1f17b1804b1-48329eb96a7so6943105e9.3 for ; Fri, 13 Feb 2026 08:29:28 -0800 (PST) Received: from fedora (user-109-243-67-101.play-internet.pl. [109.243.67.101]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4834d5ebd1bsm303288185e9.6.2026.02.13.08.29.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Feb 2026 08:29:27 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 2b0d0c2d-08f9-11f1-b163-2bf370ae4941 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1771000168; x=1771604968; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=aS1nE3ehxrhnhvUQVu6uQ+BpfKhXXAT1M63On5oqAkY=; b=QquHo+ZOLXR7e6DaAfPCjwENioUnmhLDXbPCUCRaGERV+KCA2lyFfHGaykWsKpTm2r 9pyXH1lfiOZG6GRENrkVdY1dJYUK/BCTV2rWFHeIzyNAO9mMCWqr/tHt1liQ8vH2kHjt JtkcNaWWP6+rsUKvONffV1WJZzVpDAnuofrRvzzmeHcZ4ITYOAdDSHr5wL0fwInYAIux ICwywbePxlQO8ypjgYSox1/ivDThJKoMTGmhBAaGj3rioZJXl+Cq0viPEe+NOAJ9DPn2 1q6N/LuhFhcdzrnvJ20KmkB5CuEGOdSYFjcvaQ076ZU0s8/S+bn9IyXA6WYgze5+NLOA nehw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1771000168; x=1771604968; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=aS1nE3ehxrhnhvUQVu6uQ+BpfKhXXAT1M63On5oqAkY=; b=JtHKsf+1YrqABRiozdKk7bFHtIx8kbQRz1SCGAyTPzTo30Zq/PPJbh8tyv8raIkajB 8VrNRWobXuAZF7lfuQezZdLgzpWCw4EHItsTMy8O+/mXQFS5wKIoLXMYqsBqbXJ/6Sfc C0BbPPWrswwe4n7ggzw3RG8QlkKDKy6P6i0nKv7waLQTViqRgxaj9j64BePFOZ6B1isH xbtRckgI2niAFRjItHWCy+EwZ2LiCNNAJOfoh1xdv8ynVP96nUX/SnFtP8zATHt6q4V5 wWmNGGkHvfLu7AtAuku/+CzTF47fG9eeUyeUMpCona/Hrmo11HW7sHXJWnWRcKauvFMR 9aHw== X-Gm-Message-State: AOJu0YxvwGlgpI1c/7Cs25lQe+GsVb6+PwPjnbBgjbKPUW1NZJcOtXMB em0ulHltVZQpDEF8Cc7cFxexLAGej18S/YIa0BTScIW/tzpM4h6xiq4HV3lWu8N9 X-Gm-Gg: AZuq6aJM3TKxhtIBj2Iw8QUWwXozPR8s9EhUDYoFdRLrlGtN0kgRpW6yEEtJ4ci2ndm hXvXvIVW+/Xhcita3N4aXkQq+Kfv0nLjDY1+6mOkKEd/hwEBeIsS7rBidiABx5d2Wa88+g2B5R0 5NNKaYeJtiYF0Nw4Da/pHQeZxXGsj1//1EDJ423PYqpEJrIF2y4wh6luRiqoV5VYDYvDU0HSq67 eH531lvpxn5dwM9Li41jOply1AoYrCNO1rmkH+lpvM+JTPNmCf3v8A67WqjCRSgYwH90sr7nnM0 HhEuoTYsinJ7yJIxlPa8DVNUlGgmCNpvDiny3SITt7OU8VJo6d/xccrXsKIeEflAj1AN0tfv1Le CODTuiF2SkEDzrMxC1ppgx3ZND8L/EPLcwpsLwayLForYHHBUbKIcofdKr7G3b/UhIo4Nc9cchd dAci/T2fK4MOaUlbRVCgtrXGX0HaSQ2tPQEue7JfX7KXyjpYozHTK9WREp4W06cOuqyg== X-Received: by 2002:a05:600c:474d:b0:47e:e72b:1fce with SMTP id 5b1f17b1804b1-48373a59a59mr42787315e9.37.1771000168120; Fri, 13 Feb 2026 08:29:28 -0800 (PST) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Romain Caritey , Oleksii Kurochko , Alistair Francis , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH v4 16/16] xen/riscv: implement sync_vcpu_execstate() Date: Fri, 13 Feb 2026 17:29:02 +0100 Message-ID: X-Mailer: git-send-email 2.52.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1771000723095158500 Content-Type: text/plain; charset="utf-8" The scheduler may call this function to force synchronization of given vCPU's state. RISC-V does not support lazy context switching, so nothing is done in sync_vcpu_execstate() and sync_local_execstate(). Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich --- Changes in v4: - Drop footer as [PATCH] sched: move vCPU exec state barriers is merged to upstream/staging. - Add Acked-by: Jan Beulich . --- Changes in v3: - Align sync_vcpu_execstate() with patch: [PATCH] sched: move vCPU exec state barriers --- Changes in v2: - New patch. --- xen/arch/riscv/domain.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/xen/arch/riscv/domain.c b/xen/arch/riscv/domain.c index 307da467c72e..6d3d7277bf8f 100644 --- a/xen/arch/riscv/domain.c +++ b/xen/arch/riscv/domain.c @@ -249,3 +249,13 @@ void vcpu_kick(struct vcpu *v) smp_send_event_check_mask(cpumask_of(v->processor)); } } + +void sync_local_execstate(void) +{ + /* Nothing to do -- no lazy switching */ +} + +void sync_vcpu_execstate(struct vcpu *v) +{ + /* Nothing to do -- no lazy switching */ +} --=20 2.52.0