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[109.243.67.101]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b8edacf1564sm415776866b.52.2026.02.09.08.52.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Feb 2026 08:52:38 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: be6d4348-05d7-11f1-9ccf-f158ae23cfc8 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1770655959; x=1771260759; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=JMEwFKcyHIZZ4fXEejJ25YZMQb9FLhdSrVKjYgj/ce8=; b=d5CC6t6dB2t2c2BaoE5K0s8L6UrVhG/Kwx5yteQo7PJ+FPh0QdmppARh4W9A8GkCb9 ZvFOm1CFK4aQNOEJEtWGavTdhgMNAOViCI64+hD7CNBnB1o22hIr9XWcmKZ/hBK8Oxa7 WU5zK4rkp5KxKDMBL8gcxKBSeF55ZG2MPAh9vV1R24NbOcqsWonn8g5lwtQE7Wh82Wdw w3wxz0YA/3N1TloZMi4yWrk0KftlY+Qi5JEzJWejtaBeK7TPn/xJjiqLk/tZIrmM/QOO xGiyBglq/D4FVxdEsQsk+wbAbPgcJJoCDRtTZRsS4ePiXX6KxPKzCcb3au1LER45Vd0I dFog== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1770655959; x=1771260759; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=JMEwFKcyHIZZ4fXEejJ25YZMQb9FLhdSrVKjYgj/ce8=; b=sJdyJWRY0BxuA3LjCb7afPVeQkBdUXV4aTFCCpbZncniKRRo4I4g8iumq5s4JiBu6q XNo2Yam/aTrGW/nSidC2TmNoa6WOTTIo2Zh/gJECIrcltqBJBTeZ8ct2NWNf/JdbMEJe Irn1nvIo/+9bxklKyAgNpf25HQKiQKPVV4XHOC4JBsfsq21KIzR0KFAZy46ySyD3hhJG YNJ5UQMxSlht/fHq5q89eR3E3BuPJEsP6kZmfeXFuWozGeu3coF0kYlQOFPS4U7xD/HS HdKEyAXQTazRv6M+tCNovqi0TAZaocE7cxFnPfzYcwEJfsOIoXYHW8r0C0e78+Vqtxjc 0dYw== X-Gm-Message-State: AOJu0YwUdPPwX6KPx49NsiI5aZRJahLA2ynWwOSNAfg2CiQuqlZUvMFu PCC58Bst11vlCjV9OtBLL2o5vH91eSmBJ4MqsSgiuGnbY4/eUZCdT/BxSpUHWmq8 X-Gm-Gg: AZuq6aK6FVDU6F+HIzVNKNzARq+AL0J4AybsX+2N5MZnou0/cz6Zvp7txUehbQa8mQw 1JFGamfp7onKW7zQoY3HaF2Kt+eVXNdf3qZ0SwHijN0HhfSkn5REk67XdUTeV7pOTDoqv1o/DRA U2OYWdrcgXBEX9YPpADZoAhVyW/63Rd5+2g+vfs3t+f9e7fSpxNLLLprnv8SIht0rmo+brujN5j mBoWzXv4+8rKbwLKioD0/9WAvYy8LA0ihEZ676fYnpdziG9zMWcD1j1fAl89Ix546VtQfiolwut 5xkArmKLPhs/t0Dh+//CA4oFrHQlDUuMv+gF0BIY1bfm0GanM9sLIzQ+LqgCyQRwL5boO3D4rUs esxdkrqMpSeFqM2ZN3qEFDnmTizdKnMsBxaDO/UGGpyNrX0UZTq9Zd+j/2DayYfg7RgCti2P1nO oxb4PfifQEevnoXhjTljVNILA8RtQvJxITU/Q48l0YCturmZYeRluY8A== X-Received: by 2002:a17:907:a44:b0:b8e:d0ec:c9e2 with SMTP id a640c23a62f3a-b8edf37ec3emr628174066b.53.1770655958667; Mon, 09 Feb 2026 08:52:38 -0800 (PST) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Romain Caritey , Oleksii Kurochko , Alistair Francis , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH v3 01/16] xen/riscv: implement arch_vcpu_{create,destroy}() Date: Mon, 9 Feb 2026 17:52:14 +0100 Message-ID: X-Mailer: git-send-email 2.52.0 In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1770655995019154100 Introduce architecture-specific functions to create and destroy VCPUs. Note that arch_vcpu_create() currently returns -EOPNOTSUPP, as the virtual timer and interrupt controller are not yet implemented. Add calle-saved registers used to preserve Xen=E2=80=99s own execution cont= ext when switching between vCPU stacks. It is going to be used in the following way (pseudocode): context_switch(prev_vcpu, next_vcpu): ... /* Switch from previous stack to the next stack. */ __context_switch(prev_vcpu, next_vcpu); ... schedule_tail(prev_vcpu): Save and restore vCPU's CSRs. The Xen-saved context allows __context_switch() to switch execution from the previous vCPU=E2=80=99s stack to the next vCPU=E2=80=99s stack and= later resume execution on the original stack when switching back. During vCPU creation, the Xen-saved context is going to be initialized with: - SP pointing to the newly allocated vCPU stack - RA pointing to a helper that performs final vCPU setup before transferring control to the guest After the first execution of __context_switch(), RA naturally points to the instruction following the call site, and the remaining callee-saved registers contain the Xen register state at the time of the switch. As part of this change, add continue_new_vcpu(), which will be used after the first context_switch() of a new vCPU. Since this functionality is not yet implemented, continue_new_vcpu() is currently provided as a stub. The prev argument is going to be set by RISC-V ABI (prev will be stored in a0) when __context_swtich() will be introduced and called from context_switch(). Update the STACK_SIZE definition and introduce STACK_ORDER (to align with other architectures) for allocating the vCPU stack. Introduce struct cpu_info to store per-vCPU state that lives at the top of the vCPU's stack. Signed-off-by: Oleksii Kurochko --- Changes in v3: - Move declaration of xen_saved_context structure and cpu_info structure here as they are going to be used in this patch. - Drop separate zero-ing of arch.cpu_info as a memory for it is allocated by vzalloc(). - Correct calculation of stack pointer in arch_vcpu_destroy() function. --- Changes in v2: - Drop BUILD_BUG_ON() in arch_vcpu_create() as a check isn't very useful. - Use vzalloc() instead of alloc_xenheap_page() to use the larger domheap = to allocate vCPU's stack. - Drop printk() inside arch_vcpu_create() to not have potential big noise in console as it could be that an amount of vCPUs is pretty big. - Use XVFREE() instead of free_xenheap_pages() as vCPU's stack allocation happens with a usage of vzalloc() now. - Drop stack field as it is enough to have only cpu_info as stack pointer could be calculated based on cpu_info. - Drop cast when v.arch.cpu_info is inialized as it is not necessary to have it. - Drop memset() for arch.cpu_info() as it is enough to have vzalloc(). --- xen/arch/riscv/Makefile | 1 + xen/arch/riscv/domain.c | 58 ++++++++++++++++++++++++++++ xen/arch/riscv/include/asm/config.h | 3 +- xen/arch/riscv/include/asm/current.h | 6 +++ xen/arch/riscv/include/asm/domain.h | 24 ++++++++++++ xen/arch/riscv/stubs.c | 10 ----- 6 files changed, 91 insertions(+), 11 deletions(-) create mode 100644 xen/arch/riscv/domain.c diff --git a/xen/arch/riscv/Makefile b/xen/arch/riscv/Makefile index 0df139b27423..868514c25006 100644 --- a/xen/arch/riscv/Makefile +++ b/xen/arch/riscv/Makefile @@ -1,5 +1,6 @@ obj-y +=3D aplic.o obj-y +=3D cpufeature.o +obj-y +=3D domain.o obj-$(CONFIG_EARLY_PRINTK) +=3D early_printk.o obj-y +=3D entry.o obj-y +=3D imsic.o diff --git a/xen/arch/riscv/domain.c b/xen/arch/riscv/domain.c new file mode 100644 index 000000000000..d035b105c2cc --- /dev/null +++ b/xen/arch/riscv/domain.c @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +static void continue_new_vcpu(struct vcpu *prev) +{ + BUG_ON("unimplemented\n"); +} + +static void __init __maybe_unused build_assertions(void) +{ + /* + * Enforce the requirement documented in struct cpu_info that + * guest_cpu_user_regs must be the first field. + */ + BUILD_BUG_ON(offsetof(struct cpu_info, guest_cpu_user_regs) !=3D 0); +} + +int arch_vcpu_create(struct vcpu *v) +{ + int rc =3D 0; + void *stack =3D vzalloc(STACK_SIZE); + + if ( !stack ) + return -ENOMEM; + + v->arch.cpu_info =3D stack + STACK_SIZE - sizeof(struct cpu_info); + + v->arch.xen_saved_context.sp =3D (register_t)v->arch.cpu_info; + v->arch.xen_saved_context.ra =3D (register_t)continue_new_vcpu; + + /* Idle VCPUs don't need the rest of this setup */ + if ( is_idle_vcpu(v) ) + return rc; + + /* + * As the vtimer and interrupt controller (IC) are not yet implemented, + * return an error. + * + * TODO: Drop this once the vtimer and IC are implemented. + */ + rc =3D -EOPNOTSUPP; + goto fail; + + return rc; + + fail: + arch_vcpu_destroy(v); + return rc; +} + +void arch_vcpu_destroy(struct vcpu *v) +{ + vfree((char *)v->arch.cpu_info + sizeof(struct cpu_info) - STACK_SIZE); +} diff --git a/xen/arch/riscv/include/asm/config.h b/xen/arch/riscv/include/a= sm/config.h index 1e08d3bf78be..86a95df018b5 100644 --- a/xen/arch/riscv/include/asm/config.h +++ b/xen/arch/riscv/include/asm/config.h @@ -143,7 +143,8 @@ =20 #define SMP_CACHE_BYTES (1 << 6) =20 -#define STACK_SIZE PAGE_SIZE +#define STACK_ORDER 3 +#define STACK_SIZE (PAGE_SIZE << STACK_ORDER) =20 #define IDENT_AREA_SIZE 64 =20 diff --git a/xen/arch/riscv/include/asm/current.h b/xen/arch/riscv/include/= asm/current.h index 0c3ea70c2ec8..58c9f1506b7c 100644 --- a/xen/arch/riscv/include/asm/current.h +++ b/xen/arch/riscv/include/asm/current.h @@ -21,6 +21,12 @@ struct pcpu_info { /* tp points to one of these */ extern struct pcpu_info pcpu_info[NR_CPUS]; =20 +/* Per-VCPU state that lives at the top of the stack */ +struct cpu_info { + /* This should be the first member. */ + struct cpu_user_regs guest_cpu_user_regs; +}; + #define set_processor_id(id) do { \ tp->processor_id =3D (id); \ } while (0) diff --git a/xen/arch/riscv/include/asm/domain.h b/xen/arch/riscv/include/a= sm/domain.h index 316e7c6c8448..f78f145258d6 100644 --- a/xen/arch/riscv/include/asm/domain.h +++ b/xen/arch/riscv/include/asm/domain.h @@ -24,6 +24,30 @@ struct arch_vcpu_io { =20 struct arch_vcpu { struct vcpu_vmid vmid; + + /* + * Callee saved registers for Xen's state used to switch from + * prev's stack to the next's stack during context switch. + */ + struct + { + register_t s0; + register_t s1; + register_t s2; + register_t s3; + register_t s4; + register_t s5; + register_t s6; + register_t s7; + register_t s8; + register_t s9; + register_t s10; + register_t s11; + register_t sp; + register_t ra; + } xen_saved_context; + + struct cpu_info *cpu_info; }; =20 struct paging_domain { diff --git a/xen/arch/riscv/stubs.c b/xen/arch/riscv/stubs.c index acbfde79b5a7..c5784a436574 100644 --- a/xen/arch/riscv/stubs.c +++ b/xen/arch/riscv/stubs.c @@ -116,16 +116,6 @@ void dump_pageframe_info(struct domain *d) BUG_ON("unimplemented"); } =20 -int arch_vcpu_create(struct vcpu *v) -{ - BUG_ON("unimplemented"); -} - -void arch_vcpu_destroy(struct vcpu *v) -{ - BUG_ON("unimplemented"); -} - void vcpu_switch_to_aarch64_mode(struct vcpu *v) { BUG_ON("unimplemented"); --=20 2.52.0 From nobody Tue Feb 10 23:53:55 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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[109.243.67.101]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b8edacf1564sm415776866b.52.2026.02.09.08.52.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Feb 2026 08:52:39 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: bf2bce51-05d7-11f1-b162-2bf370ae4941 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1770655960; x=1771260760; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Q13SfGkfAmGOcNIHPBnLiB5Lf3crQ10q+6piREbgcus=; b=JJQcTvpghBmg+G46LfvQrwDma7uWBK3+q4Pxq/lcG3gVNxaqczJ3VfP6Z8mwWtw37U jlAzBJvmk0N6xIFy/qgRO76HtF+xiFpetH49DVA6X6//uxnHVtHA7PmNM5n3j5a7PxoS Jx15Ciighbk9yqoibGxJzt74KLqvI2UUtELXIC2vwAMMD71mBOy2Ph3WYEeZZFbC1Jcs mZ0skXEeEJi5MZZ7mnwNMHBe8jpU59VGB7yidMtDFh2Fg9FHgJcGw90R9StDPN5acbHv BhIxxtUSRCLMYNftWfGc9UcynKPGATb5iZwDU25utib48sLBpkAVHeqLnxQXAzLwRHp2 fN6Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1770655960; x=1771260760; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=Q13SfGkfAmGOcNIHPBnLiB5Lf3crQ10q+6piREbgcus=; b=YCcfCG/2+ml9LKMTfrz1Rl0D53bETmpojrweadFBdx6iUKoxvy/JXruB9+ETzQUMFF t0XjuyrTUVez5I3eSKrUIqomIAp4kRmQzZbuxx3PU967UsonzQtHfpR+6tNttoTtfsRd hccal0RZWd4c5uZdms6B7mnVJQvIUC7TCOj2bFYR0DRrMz/d7OtJ0lupGqIbZY0ZXZJB fxXoRdEx/FZYlaNqg3nhuwhvc7LhJEO5EUuW4z8Zn0YC6rsvev37VwFg90GFbPfQgBlO 7waksulpb/ybD4rN4tst6jWmmCSs4Z+1ihnAFOGxFxXPrKGhZXMbrxvTvaEdMDII//h5 JQ6A== X-Gm-Message-State: AOJu0YyELK+Fho2EmVEZYDUkcIkJ6DP1u7s9LZ+B8G7xgFpHsPy/poUk jWeKJNz7TeN7tqpdrXR6//r3LgNWmYIUsWZeGmB2An7djD7FUp8RaCElx7GrjBEp X-Gm-Gg: AZuq6aKYlC1lZJrp5V2Hlku8T1nOAciE6C9IasOHenLy9DXVIgyWicEMFJqiDftmWd6 DROh+AnYrDXb374Yt8e7a8c3qo28CorM4RqGJ0Pu9m3NapytWhMWZ/pt5wMcHIDDSDzCekfq46v UpKLis1ujJAHvsKNAjQEYGr/Lpd7g2wwawWnYvd9nLooP7enzpqXx60l5/sMNm03XpPLkIPvKEX +hO62a4ZZVnweqwLiVf+S/FAv2GcUHh+QkqqEQGnQalivScLMcnmZVtD7pxq+0cRhDwS0bIuTvx F+xeKYUDgistdydUBymZlf2NZRAIu5Qm9zR69hVr5BVMW6a+sVnOoYYpJC8kameILHnrzHdE7XK lBW5RB/W+cUm3ze4PyYZ9R8aJNnPoUv9vKMu1lXtvyEBUS6YaHX17XP1h4V0Ywd4bUxkm0fNvlj Co8HdPaj68toljlbrdSYzN4ZvHUl5FxCDW1PQU0WZE6ZCLKpArYBL6Ug== X-Received: by 2002:a17:907:3d0c:b0:b8e:a1ae:8054 with SMTP id a640c23a62f3a-b8edf178627mr705971366b.2.1770655959738; Mon, 09 Feb 2026 08:52:39 -0800 (PST) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Romain Caritey , Oleksii Kurochko , Alistair Francis , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH v3 02/16] xen/riscv: avoid reading hstateen0 when Smstateen is not implemented Date: Mon, 9 Feb 2026 17:52:15 +0100 Message-ID: X-Mailer: git-send-email 2.52.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1770656002842158500 Content-Type: text/plain; charset="utf-8" If the Smstateen extension is not implemented, the hstateen0 CSR is considered non-existent. Any attempt to access it will raise an illegal-instruction exception. Guard the hstateen0 dump with a runtime check for Smstateen support to avoid triggering traps when dumping CSRs on systems that do not implement this extension. Fixes: 3babc8d2e546 ("xen/riscv: dump GPRs and CSRs on unexpected traps") Signed-off-by: Oleksii Kurochko --- Changes in V3: - New patch --- xen/arch/riscv/cpufeature.c | 1 + xen/arch/riscv/include/asm/cpufeature.h | 1 + xen/arch/riscv/traps.c | 8 +++++++- 3 files changed, 9 insertions(+), 1 deletion(-) diff --git a/xen/arch/riscv/cpufeature.c b/xen/arch/riscv/cpufeature.c index 02b68aeaa49f..03e27b037be0 100644 --- a/xen/arch/riscv/cpufeature.c +++ b/xen/arch/riscv/cpufeature.c @@ -137,6 +137,7 @@ const struct riscv_isa_ext_data __initconst riscv_isa_e= xt[] =3D { RISCV_ISA_EXT_DATA(zbb), RISCV_ISA_EXT_DATA(zbs), RISCV_ISA_EXT_DATA(smaia), + RISCV_ISA_EXT_DATA(smstateen), RISCV_ISA_EXT_DATA(ssaia), RISCV_ISA_EXT_DATA(svade), RISCV_ISA_EXT_DATA(svpbmt), diff --git a/xen/arch/riscv/include/asm/cpufeature.h b/xen/arch/riscv/inclu= de/asm/cpufeature.h index b69616038888..ef02a3e26d2c 100644 --- a/xen/arch/riscv/include/asm/cpufeature.h +++ b/xen/arch/riscv/include/asm/cpufeature.h @@ -36,6 +36,7 @@ enum riscv_isa_ext_id { RISCV_ISA_EXT_zbb, RISCV_ISA_EXT_zbs, RISCV_ISA_EXT_smaia, + RISCV_ISA_EXT_smstateen, RISCV_ISA_EXT_ssaia, RISCV_ISA_EXT_svade, RISCV_ISA_EXT_svpbmt, diff --git a/xen/arch/riscv/traps.c b/xen/arch/riscv/traps.c index 34920f4e5693..c81a4f79a0d2 100644 --- a/xen/arch/riscv/traps.c +++ b/xen/arch/riscv/traps.c @@ -11,6 +11,7 @@ #include #include =20 +#include #include #include #include @@ -144,7 +145,12 @@ static void dump_csrs(const char *ctx) (v & HSTATUS_SPV) ? " SPV" : "", (v & HSTATUS_GVA) ? " GVA" : ""); X(hgatp, CSR_HGATP, "\n"); - X(hstateen0, CSR_HSTATEEN0, "\n"); + + if ( riscv_isa_extension_available(NULL, RISCV_ISA_EXT_smstateen) ) + { + X(hstateen0, CSR_HSTATEEN0, "\n"); + } + X(stvec, CSR_STVEC, " "); X(vstvec, CSR_VSTVEC, "\n"); X(sepc, CSR_SEPC, " "); X(vsepc, CSR_VSEPC, "\n"); X(stval, CSR_STVAL, " "); X(vstval, CSR_VSTVAL, "\n"); --=20 2.52.0 From nobody Tue Feb 10 23:53:55 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1770655988; cv=none; d=zohomail.com; s=zohoarc; b=BqDifwk9CKg9vRrIdrYieZFzZXzLFWL5RS9+eCQm+TDgIdkL9md3x0EUikEcUU5bRCM7bLKjwigJaH0FnQ7jTL1dr3n6MX5qAQBfnjtxJyA0GablX0lLr+noytVuAMkzwcBWSu73w2NBl/D5yCVh2TqVsSGCvGpo+j5qVplMxC4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1770655988; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=u33CKgrUFdgsGpUw8x9D4VJJRV1mttKFRSeG1+lahcw=; b=AbcrgA8qIbU1ZQO0qXprhuzn2KFHgwMZqAsGIYXUV+jF1H7IeSqJ1W9fwyH6rjBivbYusZ2T87Wz10XJCXGl1xc44+sTQIJ+XrFrMBFQ9LYqwasSQqoN9be8JtaHsn7pXK4gkfxAQlHICoWYqk2hKWBkUfeVZDTM6c8sk7vfCAI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1770655988309964.2782630782478; Mon, 9 Feb 2026 08:53:08 -0800 (PST) Received: from list by lists.xenproject.org with outflank-mailman.1225787.1532380 (Exim 4.92) (envelope-from ) id 1vpUVA-0007yt-7o; Mon, 09 Feb 2026 16:52:44 +0000 Received: by outflank-mailman (output) from mailman id 1225787.1532380; Mon, 09 Feb 2026 16:52:44 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vpUVA-0007yY-0A; Mon, 09 Feb 2026 16:52:44 +0000 Received: by outflank-mailman (input) for mailman id 1225787; Mon, 09 Feb 2026 16:52:42 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vpUV8-0007Zo-Sv for xen-devel@lists.xenproject.org; Mon, 09 Feb 2026 16:52:42 +0000 Received: from mail-ej1-x635.google.com (mail-ej1-x635.google.com [2a00:1450:4864:20::635]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id bfbf3b32-05d7-11f1-b162-2bf370ae4941; Mon, 09 Feb 2026 17:52:42 +0100 (CET) Received: by mail-ej1-x635.google.com with SMTP id a640c23a62f3a-b885e8c6727so487877666b.1 for ; Mon, 09 Feb 2026 08:52:41 -0800 (PST) Received: from fedora (user-109-243-67-101.play-internet.pl. [109.243.67.101]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b8edacf1564sm415776866b.52.2026.02.09.08.52.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Feb 2026 08:52:40 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: bfbf3b32-05d7-11f1-b162-2bf370ae4941 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1770655961; x=1771260761; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=u33CKgrUFdgsGpUw8x9D4VJJRV1mttKFRSeG1+lahcw=; b=b8Nd+ojWbI8XN2n5eAKILcx6uqvdDJKfbggqnaTqo7ApKHvcDbPfx2MyFigUqmmyrz klTR7uMuoEO1VAEuiElllK/5ni1ezrnrhcwHsAnrqJSZZDVMFR2U+ZcM3Kwydhval5f9 jH39wyueqqPpL+Hcypj4BXKsvIv2xOAsf7X2DqHw266UvUgNgHeI467n8cxpFeXPg6V0 ieW1N46VeQGeq85Pn/AnW25N9w+bz3VvmfIt8kla9JvDvWPWxPCg5vuZ6SUJa1Kf7XHw ZYKhSZP04T1RNNWssE7e9YkkDzRbsZz1BDp6wn/dDNdZd71ZpVLNKFcSyveYaTkYpk9J tzrw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1770655961; x=1771260761; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=u33CKgrUFdgsGpUw8x9D4VJJRV1mttKFRSeG1+lahcw=; b=AL6bGU+kKig8Mp7A/f0MUlhCiACxa4D4nxRUoltnbeE88LMFCD07f9+n7QNr6zQvlK EFRNY67ji+ELWndFN9zjybm+7CDFS8Y9BtWbBvp6zXKWAoCJj5OmKdU/Z4IqKX4iOhUV b61UODt3LtBGhefi7f7O9RZ02lows/Vz24+0CPp44+e+Ru2UTaYNrSi40SPkU0BSASFC g104SLKqEDuH7UMOz0B9u1FZIjXWGeZ/Y+dokY7GZ4r1AL2/YiQqmNu+vYPBAwgpUXMv 6FUEELhHKBC7DAJDHTixREZRHt3UtxRmXFgbTnz5DvYX0ymxjVqrw+PE6cQBcwiFP0CP ERVA== X-Gm-Message-State: AOJu0Yxd7ZzaX8x62qo4qEieZiOHrd2s+BmwDRW0A2C9fREeZcq0i4Vi C5wuPBM9W+KLPskwCMVzsxTaBfb5wq3S2d7VqPh9TOpfHUPhdbIUOLe+j2UoUos+ X-Gm-Gg: AZuq6aIaRyiaxM+dYFVfmw3aWvSxJW59v7a+BMAslgI27eaB1/D0KqVwzGDc8cunb/W vt5n7mWlNvY6/HmALj7rzRjZobHpJsImfQjew1PLUzBLVlZgzZjzsUB1e7bDmO9fSVbnA+AybA3 BPQIbpN8g82dX1lvceuswHTs67en2a/vKPYr64pf4N5x3IbdVcYTj1d0qxW2OnJj9+Mwpz8Fq2I +o7JPwqUhEF0oJMka6FpxWsG58Evaq3Wo1dUJ+sZCHAEQLLCCCscIdysLUMc0tLbnDECcwkIFRP rwFALI+5v0gm8zDvkZ9KFqRcxNltC5QgxHugZGyRDwcHSGwy6SERhr3yLwxTCDxyWk1zHJd83wj frslqnH2beXk9QsyQ7oVathygRMPVbzdPzTGVdye5+JRNqe/uOswO/gtN3E5ROfmQW+UUdc0Amv tjoy9WuUr1SWWMkPHoXyrrduYJc4gGt3/VbkqDPsGjzFhGmC9K9fFIww== X-Received: by 2002:a17:907:9409:b0:b88:5a61:5461 with SMTP id a640c23a62f3a-b8f4d34f084mr6259266b.2.1770655960777; Mon, 09 Feb 2026 08:52:40 -0800 (PST) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Romain Caritey , Oleksii Kurochko , Alistair Francis , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH v3 03/16] xen/riscv: detect and store supported hypervisor CSR bits at boot Date: Mon, 9 Feb 2026 17:52:16 +0100 Message-ID: X-Mailer: git-send-email 2.52.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1770655988836158500 Content-Type: text/plain; charset="utf-8" Some hypervisor CSRs expose optional functionality and may not implement all architectural bits. Writing unsupported bits can either be ignored or raise an exception depending on the platform. Detect the set of writable bits for selected hypervisor CSRs at boot and store the resulting masks for later use. This allows safely programming these CSRs during vCPU context switching and avoids relying on hardcoded architectural assumptions. Note that csr_set() is used instead of csr_write() to write all ones to the mask, as the CSRRS instruction, according to the RISC-V specification, sets only those bits that are writable: Any bit that is high in rs1 will cause the corresponding bit to be set in the CSR, if that CSR bit is writable. In contrast, the CSRRW instruction does not take CSR bit writability into account, which could lead to unintended side effects when writing all ones to a CSR. Masks are calculated at the moment only for hdeleg, henvcfg, hideleg, hstateen0 registers as only them are going to be used in the follow up patch. If the Smstateen extension is not implemented, hstateen0 cannot be read because the register is considered non-existent. Instructions that attempt to access a CSR that is not implemented or not visible in the current mode are reserved and will raise an illegal-instruction exception. Signed-off-by: Oleksii Kurochko --- Changes in V3: - New patch. --- xen/arch/riscv/include/asm/setup.h | 9 +++++++++ xen/arch/riscv/setup.c | 26 ++++++++++++++++++++++++++ 2 files changed, 35 insertions(+) diff --git a/xen/arch/riscv/include/asm/setup.h b/xen/arch/riscv/include/as= m/setup.h index c9d69cdf5166..d54f6a2d1d29 100644 --- a/xen/arch/riscv/include/asm/setup.h +++ b/xen/arch/riscv/include/asm/setup.h @@ -5,6 +5,15 @@ =20 #include =20 +struct csr_masks { + register_t hedeleg; + register_t henvcfg; + register_t hideleg; + register_t hstateen0; +}; + +extern struct csr_masks csr_masks; + #define max_init_domid (0) =20 void setup_mm(void); diff --git a/xen/arch/riscv/setup.c b/xen/arch/riscv/setup.c index 9b4835960d20..010489f0b713 100644 --- a/xen/arch/riscv/setup.c +++ b/xen/arch/riscv/setup.c @@ -32,6 +32,8 @@ unsigned char __initdata cpu0_boot_stack[STACK_SIZE] __aligned(STACK_SIZE); =20 +struct csr_masks __ro_after_init csr_masks; + /** * copy_from_paddr - copy data from a physical address * @dst: destination virtual address @@ -70,6 +72,28 @@ static void * __init relocate_fdt(paddr_t dtb_paddr, siz= e_t dtb_size) return fdt; } =20 +void __init init_csr_masks(void) +{ + register_t old; + +#define X(csr, field) \ + old =3D csr_read(CSR_##csr); \ + csr_set(CSR_##csr, ULONG_MAX); \ + csr_masks.field =3D csr_read(CSR_##csr); \ + csr_write(CSR_##csr, old) + + X(HEDELEG, hedeleg); + X(HENVCFG, henvcfg); + X(HIDELEG, hideleg); + + if ( riscv_isa_extension_available(NULL, RISCV_ISA_EXT_smstateen) ) + { + X(HSTATEEN0, hstateen0); + } + +#undef X +} + void __init noreturn start_xen(unsigned long bootcpu_id, paddr_t dtb_addr) { @@ -137,6 +161,8 @@ void __init noreturn start_xen(unsigned long bootcpu_id, =20 riscv_fill_hwcap(); =20 + init_csr_masks(); + preinit_xen_time(); =20 intc_preinit(); --=20 2.52.0 From nobody Tue Feb 10 23:53:55 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1770656000; cv=none; d=zohomail.com; s=zohoarc; b=BV2612z4/aptYJBE/RgHDdINtlxtS/iUuHDd81mlwAUi3UDxlsmT9psPotTquFuQkCf9hxFXgmuMU08DQhcOPD7AxUvS1rmTMcw8OIBehw+BriTl+wySbHzjxNmIup6PQ2rYPy7nvEwePNnIG4XkAqcEHvZQVh+S6ecvbe6lWhQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1770656000; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=EKSs5oLs7wKY5onKUxL0luWYu7wbrnabRL4F2MZ4aOo=; b=joyDg9h5NfefiPf7plCuFbRA+PBQbgD/CaQj4SoMPU8L5KRsCwF7eAPSXMlejOtAMHd+alVB+ow1iB9SPxzwqaENjq7W1opHwzPhcdikikZEQJRDBGjdvJpBTGj0PFC4Az6lDz5XZCUQwvdGdLpnFAHVjHwFrewq0mGo/AxQ+i0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1770656000670305.3904407494624; Mon, 9 Feb 2026 08:53:20 -0800 (PST) Received: from list by lists.xenproject.org with outflank-mailman.1225788.1532396 (Exim 4.92) (envelope-from ) id 1vpUVC-0008Th-9g; Mon, 09 Feb 2026 16:52:46 +0000 Received: by outflank-mailman (output) from mailman id 1225788.1532396; Mon, 09 Feb 2026 16:52:46 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vpUVC-0008TX-6P; Mon, 09 Feb 2026 16:52:46 +0000 Received: by outflank-mailman (input) for mailman id 1225788; Mon, 09 Feb 2026 16:52:44 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vpUVA-0007Zd-Hm for xen-devel@lists.xenproject.org; Mon, 09 Feb 2026 16:52:44 +0000 Received: from mail-ej1-x632.google.com (mail-ej1-x632.google.com [2a00:1450:4864:20::632]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id c03d163d-05d7-11f1-9ccf-f158ae23cfc8; Mon, 09 Feb 2026 17:52:42 +0100 (CET) Received: by mail-ej1-x632.google.com with SMTP id a640c23a62f3a-b884a84e655so678536366b.0 for ; Mon, 09 Feb 2026 08:52:42 -0800 (PST) Received: from fedora (user-109-243-67-101.play-internet.pl. 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The function configures trap and interrupt delegation to VS-mode by setting the appropriate bits in the hedeleg and hideleg registers, initializes hstatus so that execution enters VS-mode when control is passed to the guest, and restricts guest access to hardware performance counters by initializing hcounteren, as unrestricted access would require additional handling in Xen. When the Smstateen and SSAIA extensions are available, access to AIA CSRs and IMSIC guest interrupt files is enabled by setting the corresponding bits in hstateen0, avoiding unnecessary traps into Xen (note that SVSLCT(Supervisor Virtual Select) name is used intead of CSRIND as OpenSBI uses such name and riscv_encoding.h is mostly based on it). If the Svpbmt extension is supported, the PBMTE bit is set in henvcfg to allow its use for VS-stage address translation. Guest access to the ENVCFG CSR is also enabled by setting ENVCFG bit in hstateen0, as a guest may need to control certain characteristics of the U-mode (VU-mode when V=3D1) execution environment. For CSRs that may contain read-only bits (e.g. hedeleg, hideleg, hstateen0), to the written value a correspondent mask is applied to avoid divergence between the software state and the actual CSR contents. As hstatus is not part of struct arch_vcpu (it already resides in struct cpu_user_regs), introduce vcpu_guest_cpu_user_regs() to provide a uniform way to access hstatus and other guest CPU user registers. This establishes a consistent and well-defined initial CSR state for vCPUs prior to their first context switch. Signed-off-by: Oleksii Kurochko --- Changes in v3: - Add hypervisor register used to initalize vCPU state. - Apply masks introduced before instead of csr_write()/csr_read() pattern. --- Changes in v2: - As hstatus isn't a part of arch_vcpu structure (as it is already a part = of cpu_user_regs) introduce vcpu_guest_cpu_user_regs() to be able to access hstatus and other CPU user regs. - Sort hideleg bit setting by value. Drop a stray blank. - Drop | when the first initialization of hcounteren and hennvcfg happen. - Introduce HEDELEG_DEFAULT. Sort set bits by value and use BIT() macros instead of open-coding it. - Apply pattern csr_write() -> csr_read() for hedeleg and hideleg instead of direct bit setting in v->arch.h{i,e}deleg as it could be that for some reason some bits of hedeleg and hideleg are r/o. The similar patter is used for hstateen0 as some of the bits could be r/= o. - Add check that SSAIA is avaialable before setting of SMSTATEEN0_AIA | SMSTATEEN0_IMSIC | SMSTATEEN0_SVSLCT bits. - Drop local variables hstatus, hideleg and hedeleg as they aren't used anymore. --- xen/arch/riscv/domain.c | 68 +++++++++++++++++++++ xen/arch/riscv/include/asm/current.h | 2 + xen/arch/riscv/include/asm/domain.h | 6 ++ xen/arch/riscv/include/asm/riscv_encoding.h | 2 + 4 files changed, 78 insertions(+) diff --git a/xen/arch/riscv/domain.c b/xen/arch/riscv/domain.c index d035b105c2cc..af9586a4eb0d 100644 --- a/xen/arch/riscv/domain.c +++ b/xen/arch/riscv/domain.c @@ -5,6 +5,72 @@ #include #include =20 +#include +#include +#include +#include + +#define HEDELEG_DEFAULT (BIT(CAUSE_MISALIGNED_FETCH, U) | \ + BIT(CAUSE_FETCH_ACCESS, U) | \ + BIT(CAUSE_ILLEGAL_INSTRUCTION, U) | \ + BIT(CAUSE_BREAKPOINT, U) | \ + BIT(CAUSE_MISALIGNED_LOAD, U) | \ + BIT(CAUSE_LOAD_ACCESS, U) | \ + BIT(CAUSE_MISALIGNED_STORE, U) | \ + BIT(CAUSE_STORE_ACCESS, U) | \ + BIT(CAUSE_USER_ECALL, U) | \ + BIT(CAUSE_FETCH_PAGE_FAULT, U) | \ + BIT(CAUSE_LOAD_PAGE_FAULT, U) | \ + BIT(CAUSE_STORE_PAGE_FAULT, U)) + +#define HIDELEG_DEFAULT (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP) + +static void vcpu_csr_init(struct vcpu *v) +{ + register_t hstateen0; + + v->arch.hedeleg =3D HEDELEG_DEFAULT & csr_masks.hedeleg; + + vcpu_guest_cpu_user_regs(v)->hstatus =3D HSTATUS_SPV | HSTATUS_SPVP; + + v->arch.hideleg =3D HIDELEG_DEFAULT & csr_masks.hideleg; + + /* + * VS should access only the time counter directly. + * Everything else should trap. + */ + v->arch.hcounteren =3D HCOUNTEREN_TM; + + if ( riscv_isa_extension_available(NULL, RISCV_ISA_EXT_svpbmt) ) + v->arch.henvcfg =3D ENVCFG_PBMTE & csr_masks.henvcfg; + + if ( riscv_isa_extension_available(NULL, RISCV_ISA_EXT_smstateen) ) + { + if (riscv_isa_extension_available(NULL, RISCV_ISA_EXT_ssaia)) + /* + * If the hypervisor extension is implemented, the same three + * bitsare defined also in hypervisor CSR hstateen0 but concern + * only the state potentially accessible to a virtual machine + * executing in privilege modes VS and VU: + * bit 60 CSRs siselect and sireg (really vsiselect and + * vsireg) + * bit 59 CSRs siph and sieh (RV32 only) and stopi (really + * vsiph, vsieh, and vstopi) + * bit 58 all state of IMSIC guest interrupt files, inclu= ding + * CSR stopei (really vstopei) + * If one of these bits is zero in hstateen0, and the same bit= is + * one in mstateen0, then an attempt to access the correspondi= ng + * state from VS or VU-mode raises a virtual instruction excep= tion. + */ + hstateen0 =3D SMSTATEEN0_AIA | SMSTATEEN0_IMSIC | SMSTATEEN0_S= VSLCT; + + /* Allow guest to access CSR_ENVCFG */ + hstateen0 |=3D SMSTATEEN0_HSENVCFG; + + v->arch.hstateen0 =3D hstateen0 & csr_masks.hstateen0; + } +} + static void continue_new_vcpu(struct vcpu *prev) { BUG_ON("unimplemented\n"); @@ -32,6 +98,8 @@ int arch_vcpu_create(struct vcpu *v) v->arch.xen_saved_context.sp =3D (register_t)v->arch.cpu_info; v->arch.xen_saved_context.ra =3D (register_t)continue_new_vcpu; =20 + vcpu_csr_init(v); + /* Idle VCPUs don't need the rest of this setup */ if ( is_idle_vcpu(v) ) return rc; diff --git a/xen/arch/riscv/include/asm/current.h b/xen/arch/riscv/include/= asm/current.h index 58c9f1506b7c..5fbee8182caa 100644 --- a/xen/arch/riscv/include/asm/current.h +++ b/xen/arch/riscv/include/asm/current.h @@ -48,6 +48,8 @@ DECLARE_PER_CPU(struct vcpu *, curr_vcpu); #define get_cpu_current(cpu) per_cpu(curr_vcpu, cpu) =20 #define guest_cpu_user_regs() ({ BUG_ON("unimplemented"); NULL; }) +#define vcpu_guest_cpu_user_regs(vcpu) \ + (&(vcpu)->arch.cpu_info->guest_cpu_user_regs) =20 #define switch_stack_and_jump(stack, fn) do { \ asm volatile ( \ diff --git a/xen/arch/riscv/include/asm/domain.h b/xen/arch/riscv/include/a= sm/domain.h index f78f145258d6..6bb06a50c6ab 100644 --- a/xen/arch/riscv/include/asm/domain.h +++ b/xen/arch/riscv/include/asm/domain.h @@ -48,6 +48,12 @@ struct arch_vcpu { } xen_saved_context; =20 struct cpu_info *cpu_info; + + register_t hcounteren; + register_t hedeleg; + register_t henvcfg; + register_t hideleg; + register_t hstateen0; }; =20 struct paging_domain { diff --git a/xen/arch/riscv/include/asm/riscv_encoding.h b/xen/arch/riscv/i= nclude/asm/riscv_encoding.h index 1f7e612366f8..dd15731a86fa 100644 --- a/xen/arch/riscv/include/asm/riscv_encoding.h +++ b/xen/arch/riscv/include/asm/riscv_encoding.h @@ -228,6 +228,8 @@ #define ENVCFG_CBIE_INV _UL(0x3) #define ENVCFG_FIOM _UL(0x1) =20 +#define HCOUNTEREN_TM BIT(1, U) + /* =3D=3D=3D=3D=3D User-level CSRs =3D=3D=3D=3D=3D */ =20 /* User Trap Setup (N-extension) */ --=20 2.52.0 From nobody Tue Feb 10 23:53:55 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; 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Note that smp_wmb() is used instead of smp_mb__before_atomic() as what we want to guarantee that if a bit in irqs_pending_mask is obversable that the correspondent bit in irqs_pending is observable too. Add lockless tracking of pending vCPU interrupts using atomic bitops. Two bitmaps are introduced: - irqs_pending =E2=80=94 interrupts currently pending for the vCPU - irqs_pending_mask =E2=80=94 bits that have changed in irqs_pending The design follows a multi-producer, single-consumer model, where the consumer is the vCPU itself. Producers may set bits in irqs_pending_mask without a lock. Clearing bits in irqs_pending_mask is performed only by the consumer via xchg_acquire(). The consumer must not write to irqs_pending and must not act on bits that are not set in the mask. Otherwise, extra synchronization should be provided. On RISC-V interrupts are not injected via guest registers, so pending interrupts must be recorded in irqs_pending (using the new vcpu_{un}set_interrupt() helpers) and flushed to the guest by updating HVIP before returning control to the guest. The consumer side is implemented in a follow-up patch. A barrier between updating irqs_pending and setting the corresponding mask bit in vcpu_set_interrupt()/vcpu_unset_interrupt() guarantees that if the consumer observes a mask bit set, the corresponding pending bit is also visible. This prevents missed interrupts during the flush. It is possible a guest could have pending bit not result in the hardware register without to be marked pending in irq_pending bitmap as: According to the RISC-V ISA specification: Bits hip.VSSIP and hie.VSSIE are the interrupt-pending and interrupt-enable bits for VS-level software interrupts. VSSIP in hip is an alias (writable) of the same bit in hvip. Additionally: When bit 2 of hideleg is zero, vsip.SSIP and vsie.SSIE are read-only zeros. Else, vsip.SSIP and vsie.SSIE are aliases of hip.VSSIP and hie.VSSIE. This means the guest may modify vsip.SSIP, which implicitly updates hip.VSSIP and the bit being writable with 1 would also trigger an interrupt as according to the RISC-V spec: These conditions for an interrupt trap to occur must be evaluated in a bounded amount of time from when an interrupt becomes, or ceases to be, pending in sip, and must also be evaluated immediately following the execution of an SRET instruction or an explicit write to a CSR on which these interrupt trap conditions expressly depend (including sip, sie and sstatus). What means that IRQ_VS_SOFT must be synchronized separately, what is done in vcpu_sync_interrupts(). Note, also, that IRQ_PMU_OVF would want to be synced for the similar reason as IRQ_VS_SOFT, but isn't sync-ed now as PMU isn't supported now. For the remaining VS-level interrupt types (IRQ_VS_TIMER and IRQ_VS_EXT), the specification states they cannot be modified by the guest and are read-only: Bits hip.VSEIP and hie.VSEIE are the interrupt-pending and interrupt-enab= le bits for VS-level external interrupts. VSEIP is read-only in hip, and is the logical-OR of these interrupt sources: =E2=80=A2 bit VSEIP of hvip; =E2=80=A2 the bit of hgeip selected by hstatus.VGEIN; and =E2=80=A2 any other platform-specific external interrupt signal directe= d to VS-level. Bits hip.VSTIP and hie.VSTIE are the interrupt-pending and interrupt-enab= le bits for VS-level timer interrupts. VSTIP is read-only in hip, and is the logical-OR of hvip.VSTIP and any other platform-specific timer interrupt signal directed to VS-level. Thus, for these interrupt types, it is sufficient to use vcpu_set_interrupt= () and vcpu_unset_interrupt(), and flush them during the call of vcpu_flush_interrupts() (which is introduced in follow up patch). vcpu_sync_interrupts(), which is called just before entering the VM, slightly bends the rule that the irqs_pending bit must be written first, followed by updating the corresponding bit in irqs_pending_mask. However, it still respects the core guarantee that the producer never clears the mask and only writes to irqs_pending if it is the one that flipped the corresponding mask bit from 0 to 1. Moreover, since the consumer won't run concurrently because vcpu_sync_interrupts() and the consumer path are going to be invoked equentially immediately before VM entry, it is safe to slightly relax this ordering rule in vcpu_sync_interrupts(). Signed-off-by: Oleksii Kurochko --- Changes in v3: - Use smp_wb() instead of smp_mb__before_atomic(). - Add explanation of the change above in the commit message. - Move vcpu_sync_interrupts() here to producers side. - Introduce check_for_pcpu_work() to be clear from where vcpu_sync_interru= pts() is called. --- Changes in V2: - Move the patch before an introduction of vtimer. - Drop bitmap_zero() of irqs_pending and irqs_pending_mask bitmaps as vcpu structure starts out all zeros. - Drop const for irq argument of vcpu_{un}set_interrupt(). - Drop check "irq < IRQ_LOCAL_MAX" in vcpu_{un}set_interrupt() as it could lead to overrun of irqs_pending and irqs_pending_mask bitmaps. - Drop IRQ_LOCAL_MAX as there is no usage for it now. --- xen/arch/riscv/domain.c | 70 +++++++++++++++++++++++++++++ xen/arch/riscv/include/asm/domain.h | 24 ++++++++++ xen/arch/riscv/traps.c | 8 ++++ 3 files changed, 102 insertions(+) diff --git a/xen/arch/riscv/domain.c b/xen/arch/riscv/domain.c index af9586a4eb0d..4513f778cdc4 100644 --- a/xen/arch/riscv/domain.c +++ b/xen/arch/riscv/domain.c @@ -5,6 +5,7 @@ #include #include =20 +#include #include #include #include @@ -124,3 +125,72 @@ void arch_vcpu_destroy(struct vcpu *v) { vfree((char *)v->arch.cpu_info + sizeof(struct cpu_info) - STACK_SIZE); } + +int vcpu_set_interrupt(struct vcpu *v, unsigned int irq) +{ + /* + * We only allow VS-mode software, timer, and external + * interrupts when irq is one of the local interrupts + * defined by RISC-V privilege specification. + */ + if ( irq !=3D IRQ_VS_SOFT && + irq !=3D IRQ_VS_TIMER && + irq !=3D IRQ_VS_EXT ) + return -EINVAL; + + set_bit(irq, v->arch.irqs_pending); + smp_wmb(); + set_bit(irq, v->arch.irqs_pending_mask); + + vcpu_kick(v); + + return 0; +} + +int vcpu_unset_interrupt(struct vcpu *v, unsigned int irq) +{ + /* + * We only allow VS-mode software, timer, external + * interrupts when irq is one of the local interrupts + * defined by RISC-V privilege specification. + */ + if ( irq !=3D IRQ_VS_SOFT && + irq !=3D IRQ_VS_TIMER && + irq !=3D IRQ_VS_EXT ) + return -EINVAL; + + clear_bit(irq, v->arch.irqs_pending); + smp_wmb(); + set_bit(irq, v->arch.irqs_pending_mask); + + return 0; +} + +void vcpu_sync_interrupts(struct vcpu *v) +{ + unsigned long hvip; + + /* Read current HVIP and VSIE CSRs */ + v->arch.vsie =3D csr_read(CSR_VSIE); + + /* Sync-up HVIP.VSSIP bit changes done by Guest */ + hvip =3D csr_read(CSR_HVIP); + if ( (v->arch.hvip ^ hvip) & BIT(IRQ_VS_SOFT, UL) && + !test_and_set_bit(IRQ_VS_SOFT, &v->arch.irqs_pending_mask) ) + { + if ( hvip & BIT(IRQ_VS_SOFT, UL) ) + set_bit(IRQ_VS_SOFT, &v->arch.irqs_pending); + else + clear_bit(IRQ_VS_SOFT, &v->arch.irqs_pending); + } + + /* + * Sync-up AIA high interrupts. + * + * It is necessary to do only for CONFIG_RISCV_32 which isn't supported + * now. + */ +#ifdef CONFIG_RISCV_32 +# error "Update v->arch.vsieh" +#endif +} diff --git a/xen/arch/riscv/include/asm/domain.h b/xen/arch/riscv/include/a= sm/domain.h index 6bb06a50c6ab..8d9432ec5a8b 100644 --- a/xen/arch/riscv/include/asm/domain.h +++ b/xen/arch/riscv/include/asm/domain.h @@ -54,6 +54,25 @@ struct arch_vcpu { register_t henvcfg; register_t hideleg; register_t hstateen0; + register_t hvip; + + register_t vsie; + + /* + * VCPU interrupts + * + * We have a lockless approach for tracking pending VCPU interrupts + * implemented using atomic bitops. The irqs_pending bitmap represent + * pending interrupts whereas irqs_pending_mask represent bits changed + * in irqs_pending. Our approach is modeled around multiple producer + * and single consumer problem where the consumer is the VCPU itself. + * + * DECLARE_BITMAP() is needed here to support 64 vCPU local interrupts + * on RV32 host. + */ +#define RISCV_VCPU_NR_IRQS 64 + DECLARE_BITMAP(irqs_pending, RISCV_VCPU_NR_IRQS); + DECLARE_BITMAP(irqs_pending_mask, RISCV_VCPU_NR_IRQS); }; =20 struct paging_domain { @@ -92,6 +111,11 @@ static inline void update_guest_memory_policy(struct vc= pu *v, =20 static inline void arch_vcpu_block(struct vcpu *v) {} =20 +int vcpu_set_interrupt(struct vcpu *v, unsigned int irq); +int vcpu_unset_interrupt(struct vcpu *v, unsigned int irq); + +void vcpu_sync_interrupts(struct vcpu *v); + #endif /* ASM__RISCV__DOMAIN_H */ =20 /* diff --git a/xen/arch/riscv/traps.c b/xen/arch/riscv/traps.c index c81a4f79a0d2..82e1dc59cdea 100644 --- a/xen/arch/riscv/traps.c +++ b/xen/arch/riscv/traps.c @@ -169,6 +169,11 @@ static void do_unexpected_trap(const struct cpu_user_r= egs *regs) die(); } =20 +static void check_for_pcpu_work(void) +{ + vcpu_sync_interrupts(current); +} + void do_trap(struct cpu_user_regs *cpu_regs) { register_t pc =3D cpu_regs->sepc; @@ -222,6 +227,9 @@ void do_trap(struct cpu_user_regs *cpu_regs) do_unexpected_trap(cpu_regs); break; } + + if ( cpu_regs->hstatus & HSTATUS_SPV ) + check_for_pcpu_work(); } =20 void vcpu_show_execution_state(struct vcpu *v) --=20 2.52.0 From nobody Tue Feb 10 23:53:55 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1770655995; cv=none; d=zohomail.com; s=zohoarc; b=KQAZmVMAsLixSVvN1cNUiN3SnTNbwwKjk/im/Za0Q75yDX5sCofT+tv60DEN4fEjPdVEeDPcZI1xeyB5zTjTPJQ192ZwvihkcysxCaEmJgSAhC9yzxf+MyXm8XLCG+Z074jTry+YR/kI++9KcHwyT3REZKWLN0Zy9q66+Wj6Dn8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1770655995; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=Y3eDIzczLgQjn9FFXjHOFuYc8YqhLVGUUTFDMX/MKvY=; b=AnbrVNaEoP5HwCd9Jh+yifCUzqX5TV0j0iuOAIh4W2OkMSDQIfAKF/Dlr8FxEd4sfWKJDWcCyDBvwlKWv2RGMdmHEDu1DmRa59C/vgB7jYE+tLeJztOR01+mbwNoJ/mc8AsivZ130uNX/nu5jG3M4oXwbxCLnAe3UtQ/uJhOpwQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1770655995426980.5450827297473; Mon, 9 Feb 2026 08:53:15 -0800 (PST) Received: from list by lists.xenproject.org with outflank-mailman.1225789.1532406 (Exim 4.92) (envelope-from ) id 1vpUVD-0000IQ-Jd; Mon, 09 Feb 2026 16:52:47 +0000 Received: by outflank-mailman (output) from mailman id 1225789.1532406; Mon, 09 Feb 2026 16:52:47 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vpUVD-0000IA-Et; Mon, 09 Feb 2026 16:52:47 +0000 Received: by outflank-mailman (input) for mailman id 1225789; Mon, 09 Feb 2026 16:52:45 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vpUVB-0007Zo-RU for xen-devel@lists.xenproject.org; Mon, 09 Feb 2026 16:52:45 +0000 Received: from mail-ej1-x62c.google.com (mail-ej1-x62c.google.com [2a00:1450:4864:20::62c]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id c1bcfd39-05d7-11f1-b162-2bf370ae4941; Mon, 09 Feb 2026 17:52:45 +0100 (CET) Received: by mail-ej1-x62c.google.com with SMTP id a640c23a62f3a-b8871718b05so750097466b.2 for ; Mon, 09 Feb 2026 08:52:45 -0800 (PST) Received: from fedora (user-109-243-67-101.play-internet.pl. [109.243.67.101]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b8edacf1564sm415776866b.52.2026.02.09.08.52.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Feb 2026 08:52:43 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: c1bcfd39-05d7-11f1-b162-2bf370ae4941 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1770655964; x=1771260764; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Y3eDIzczLgQjn9FFXjHOFuYc8YqhLVGUUTFDMX/MKvY=; b=F73EzOUl3QVOu6ZynsmuNdlkdZCBZ5WDsmxfdMhr/PMW++kfraRBFEfNaDN33N20tJ sD2xgLA2pRnyz6x1PaRmb4aBo/YilpbLFkQo5fdhkZqgmMyjw9NWupP2cckch8LaLRGV 8aOUOUjR6Uk3D/yNsBNuL/ljUwRCZmJB63qlHxPJe6vRRiAUvp+16TmkZXByYQvI8UFr HHYX/EO7ePtBRCwCT5BLsQTCaQc0IljUDOFCEtq8zCIe6FZ0rdqinqe7d159V48NpSNl J3Bra+JzIMMUSAL4zlIaiFBJu2fdGVBq0BA8XOZd7OrK4WWWtEbfAc8cY6gkYtilKI+d e1cQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1770655964; x=1771260764; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=Y3eDIzczLgQjn9FFXjHOFuYc8YqhLVGUUTFDMX/MKvY=; b=ON2ZK2z/VvEE1/z6FM3hMMvJ6dO807Ja1Xn4CRY4ics1ZOPkQwYsB+zWg/EGhb8HzE WiJujV/pAjfJQJc9SNEr9LRRwwuJ125kJ8+bQ4CPWSLiL7F/eo4UrfErd3sFZNAKVol9 etNBDjgStP68wVrx5Co0tksIfx5np+YDp/TYsr8hBod566W9YGXGpsFsEZ201qebH6LO z6IxWjqUslawdakK988NmKXhz1IZbt5bEbzrmCiWem1SigxDBUFyTj/Ak4jafYso4bja 5EW8M89MqWGltqPsW3gUJroKmINviC39UsrXxxq4VDbg83H6eaNi1xTPy4kwcRmTIakL cRug== X-Gm-Message-State: AOJu0YxszFQ04loNBQit7bPERO1XV+hhKKT0beCTFC/avtfX5q68WxAz BWsRf7D/Led18G9D50AqOg5NBG834K2fLs09ArEkIq+nuT49WshJ7pNO8J1SBPmg X-Gm-Gg: AZuq6aJlwpxdmqfA+LZHNEHfoyAUe3ERkzZgzpsZuQ+zojHfiw7aB+LsWDBkFoNOm6I wcB0U4q63NRvYKK3QPPTTnlAS8ngPidfMg4FVSxSIOCoCQvwr6JiDFawftI+3eU2SlsNlzc6JQH CEVaeSV+L1PEcsgf2pBw4K7FtBNOuh3qgg1jc2TuVR8+6a133O9bwxyUWX3vdwX3UT082O3ot2T M6DZQLGKLj8UjDYro8FOCV3GzNEvqMGG2vM1gSpqK4NN1ZxzZR/kX/o6DXagZF8mB1MmvSj/s/W NlAGpUvTpEQ9k0uf/g5mRL1PkUEg8rUo1TDxnZIrJc+AKb7+hgtWZvpSVc6kPEIIymKHT5qswp4 I7YagQ/2y07Euvn7DEfAIpCzMZmF8xm/SleTNGkBemgZZp+hVqPCoaYQGUkQBV80KKf8DDAE9bi VQcGfAX3UmAkK34gksFsd7tcgaPr1PcX0vnfhg8h+a5iQY8mW4NuDmpA== X-Received: by 2002:a17:907:1c9e:b0:b87:bb45:bd5c with SMTP id a640c23a62f3a-b8edf42c682mr810413966b.58.1770655964157; Mon, 09 Feb 2026 08:52:44 -0800 (PST) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Romain Caritey , Oleksii Kurochko , Alistair Francis , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH v3 06/16] xen/riscv: introduce tracking of pending vCPU interrupts, part 2 Date: Mon, 9 Feb 2026 17:52:19 +0100 Message-ID: X-Mailer: git-send-email 2.52.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1770655997068154100 Content-Type: text/plain; charset="utf-8" This patch is based on Linux kernel 6.16.0. Add the consumer side (vcpu_flush_interrupts()) of the lockless pending interrupt tracking introduced in part 1 (for producers). According, to the design only one consumer is possible, and it is vCPU itself. vcpu_flush_interrupts() is expected to be ran (as guests aren't ran now due to the lack of functionality) before the hypervisor returns control to the guest. Producers may set bits in irqs_pending_mask without a lock. Clearing bits in irqs_pending_mask is performed only by the consumer via xchg() (with aquire= & release semantics). The consumer must not write to irqs_pending and must not act on bits that are not set in the mask. Otherwise, extra synchronization should be provided. The worst thing which could happen with such approach is that a new pending bit will be set to irqs_pending bitmap during update of hvip variable in vcpu_flush_interrupt() but it isn't problem as the new pending bit won't be lost and just be proceded during the next flush. As AIA specs introduced hviph register which would want to be updated when guest related AIA code vcpu_update_hvip() is introduced instead of just open-code it in vcpu_flush_interrupts(). Signed-off-by: Oleksii Kurochko --- Changes in v3: - Update the error message in case of RV32 from "hviph" to v->arch.hviph. - Make const argument of vcpu_update_hvip. - Move local variables mask and val inside if() in vcpu_flush_interrupts(). - Call vcpu_flush_interrupts() in check_pcpu_work(). - Move vcpu_update_hvip() inside if() in vcpu_flush_interrupts(). --- Changes in v2: - New patch. --- xen/arch/riscv/domain.c | 33 +++++++++++++++++++++++++++++ xen/arch/riscv/include/asm/domain.h | 1 + xen/arch/riscv/traps.c | 2 ++ 3 files changed, 36 insertions(+) diff --git a/xen/arch/riscv/domain.c b/xen/arch/riscv/domain.c index 4513f778cdc4..67437912605a 100644 --- a/xen/arch/riscv/domain.c +++ b/xen/arch/riscv/domain.c @@ -194,3 +194,36 @@ void vcpu_sync_interrupts(struct vcpu *v) # error "Update v->arch.vsieh" #endif } + +static void vcpu_update_hvip(const struct vcpu *v) +{ + csr_write(CSR_HVIP, v->arch.hvip); +} + +void vcpu_flush_interrupts(struct vcpu *v) +{ + register_t *hvip =3D &v->arch.hvip; + + if ( ACCESS_ONCE(v->arch.irqs_pending_mask[0]) ) + { + unsigned long mask, val; + + mask =3D xchg(&v->arch.irqs_pending_mask[0], 0UL); + val =3D ACCESS_ONCE(v->arch.irqs_pending[0]) & mask; + + *hvip &=3D ~mask; + *hvip |=3D val; + + /* + * Flush AIA high interrupts. + * + * It is necessary to do only for CONFIG_RISCV_32 which isn't + * supported now. + */ +#ifdef CONFIG_RISCV_32 + # error "Update v->arch.hviph" +#endif + + vcpu_update_hvip(v); + } +} diff --git a/xen/arch/riscv/include/asm/domain.h b/xen/arch/riscv/include/a= sm/domain.h index 8d9432ec5a8b..de5aecb862b5 100644 --- a/xen/arch/riscv/include/asm/domain.h +++ b/xen/arch/riscv/include/asm/domain.h @@ -115,6 +115,7 @@ int vcpu_set_interrupt(struct vcpu *v, unsigned int irq= ); int vcpu_unset_interrupt(struct vcpu *v, unsigned int irq); =20 void vcpu_sync_interrupts(struct vcpu *v); +void vcpu_flush_interrupts(struct vcpu *v); =20 #endif /* ASM__RISCV__DOMAIN_H */ =20 diff --git a/xen/arch/riscv/traps.c b/xen/arch/riscv/traps.c index 82e1dc59cdea..676a2da55811 100644 --- a/xen/arch/riscv/traps.c +++ b/xen/arch/riscv/traps.c @@ -172,6 +172,8 @@ static void do_unexpected_trap(const struct cpu_user_re= gs *regs) static void check_for_pcpu_work(void) { vcpu_sync_interrupts(current); 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[109.243.67.101]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b8edacf1564sm415776866b.52.2026.02.09.08.52.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Feb 2026 08:52:45 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: c2443fb1-05d7-11f1-9ccf-f158ae23cfc8 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1770655965; x=1771260765; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=rogtIGkdjsiYuHIg+cB4eDpb8GAwkYYPz5C7nze5IWY=; b=Z/MCfMErKNZxhDZA1lKjhPNZsFYniq/YhHahD0zI5qnH/nwVER4+/pJm/XN8Mo1UGd ixA3Vx7JJPQXymj2aUTzEYJr+sH23RzIeJXRkHM5//27kLf6z6IA4VSz3EwiWRlZfBFY Zpoe372MGc8NVnjre9RemZ4Hw3NPqQT2cj+vnT+o2tZ3WxaL6v5/sB+mJAqVqvbDDuij coiiqZigAGbD3T5uXQuJAiLm2BdzIsErMdPXTir2te+mrRRYMn0re0/HGzp0BhoqfP4T P6IJwbfVcWXSqbDf0z40r+oNZCHtDr1t9rBTtlZxA7zhff3ObKP3kie2pV3T0KdiqDDj 4sHA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1770655965; x=1771260765; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=rogtIGkdjsiYuHIg+cB4eDpb8GAwkYYPz5C7nze5IWY=; b=cU7QNVXpcC6caKbTsCHYWupMJyR8mzm3LYLYB7KtmQu/5AXE0m+7B4z7MkjdxnggpW /ttpweImYOq/2Whv+2BA6V5ji/nV0DlOxdL5r8gqDl3d7AxnjRIXY63A7/TkPv8r3p1N 1P17wcF52pdwoAMtORrEbm/FJbmMXWwZgusg64LBNfFS73KS5VLXEssljjJwoflEc3CP twgz+lA/k9clG5SqcxssoE4cIk6QyjscQ8HMcLnQ36HAWZlcIcnzK5/xBBdrkPpW7/Ij wLiFkn4FgdN/14EypmQ4sPw+ysCwoXSMVeKT8n1/GDANbYXdd/gvEkVwoj+6eLdELQfG Aeyg== X-Gm-Message-State: AOJu0Yz0zP8n9RrjSfXhVy4et2ZXTCAEOYY4EPt6ZGSURmgIf9FoWJBT N+qn1MN5wQ2G16vcCZFWIk+vnyFiBt4o9QK6o0936Deyy8kp8Cl/JMBQqBPK+Hmq X-Gm-Gg: AZuq6aJB9N9XtBpdK1zm9Y9dwx00tACIqvmyaHBYkuxl3M9GiIPE/nS65qiHhDWhKVM EOzA9L20D1eA2ue/iZW5XeLMjai1f5fy2RbyBNAvi0lo3njsp7GDncIWvFo7P8nDQ/DxxDypjpw rq4QE5FnE0uuOJwMS7yRyhzvMa0h+p9PS4cgxJTVKv1WBI8/XPmFBfRwpk0iRRmymGKpTz27qx0 uRvsyzfsa4Ky5rXgdDctvdLnxUs2r9JVHL0cCKNps0K7JWMbhhxEEPR3RtXqfYzs9jZr7CI4R3J d0z74a9GQ0nnLkbpcuNR0BFVlaW3pMmb7ZjeXIHxXeyNtsTRYy066YRAw7XgV9Q8QqJ2XDT5cgs 0+YeopvF2F4WCqcyT3gBusMgfI7FwHUE1/l6j8WiC7DEMmeMOVz9Uexco1DTdJ7bg/UJyszAiF9 OuBPd+kqyRKmRKJm/36EDmAqS7Y2U7aPJrK0/JqHo4fbabme1OLn/lYOIIk86KwPK3 X-Received: by 2002:a17:907:849:b0:b87:720c:f182 with SMTP id a640c23a62f3a-b8edf173b94mr602939866b.9.1770655965308; Mon, 09 Feb 2026 08:52:45 -0800 (PST) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Romain Caritey , Oleksii Kurochko , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk , Andrew Cooper , Anthony PERARD , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Alistair Francis , Connor Davis Subject: [PATCH v3 07/16] xen/time: move ticks<->ns helpers to common code Date: Mon, 9 Feb 2026 17:52:20 +0100 Message-ID: <5c9644065978daa7d227713b2e2f83ee39b18a64.1770650552.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1770655995145158500 Content-Type: text/plain; charset="utf-8" ticks_to_ns() and ns_to_ticks() are not architecture-specific, so provide a common implementation that is more resilient to overflow than the historical Arm version. This is not a practical issue for Arm, as the latest ARM ARM that timer frequency should be fixed at 1 GHz and older platforms used much lower rates, which is shy of 32-bit overflow. As the helpers are declared as static inline, they should not affect x86, which does not use them. On Arm, these helpers were historically implemented as out-of-line functions because the counter frequency was originally defined as static and unavaila= ble to headers [1]. Later changes [2] removed this restriction, but the helpers remained unchanged. Now they can be implemented as static inline without any issues. Centralising the helpers avoids duplication and removes subtle differences between architectures while keeping the implementation simple. Drop redundant includes where already pulls it in. No functional change is intended. [1] ddee56dc2994 arm: driver for the generic timer for ARMv7 [2] 096578b4e489 xen: move XEN_SYSCTL_physinfo, XEN_SYSCTL_numainfo and XEN_SYSCTL_topologyinfo to common code Suggested-by: Jan Beulich Signed-off-by: Oleksii Kurochko Reviewed-by: Jan Beulich --- Changes in v3: - Add Reviewed-by: Jan Beulich . --- Changes in v2: - Move ns_to_ticks() and ticks_to_ns() to common code. --- xen/arch/arm/include/asm/time.h | 3 --- xen/arch/arm/time.c | 11 ----------- xen/arch/arm/vtimer.c | 2 +- xen/arch/riscv/include/asm/time.h | 5 ----- xen/arch/riscv/time.c | 1 + xen/include/xen/time.h | 11 +++++++++++ 6 files changed, 13 insertions(+), 20 deletions(-) diff --git a/xen/arch/arm/include/asm/time.h b/xen/arch/arm/include/asm/tim= e.h index 49ad8c1a6d47..c194dbb9f52d 100644 --- a/xen/arch/arm/include/asm/time.h +++ b/xen/arch/arm/include/asm/time.h @@ -101,9 +101,6 @@ extern void init_timer_interrupt(void); /* Counter value at boot time */ extern uint64_t boot_count; =20 -extern s_time_t ticks_to_ns(uint64_t ticks); -extern uint64_t ns_to_ticks(s_time_t ns); - void preinit_xen_time(void); =20 void force_update_vcpu_system_time(struct vcpu *v); diff --git a/xen/arch/arm/time.c b/xen/arch/arm/time.c index cc3fcf47b66a..a12912a106a0 100644 --- a/xen/arch/arm/time.c +++ b/xen/arch/arm/time.c @@ -27,7 +27,6 @@ #include #include #include -#include #include =20 uint64_t __read_mostly boot_count; @@ -47,16 +46,6 @@ unsigned int timer_get_irq(enum timer_ppi ppi) return timer_irq[ppi]; } =20 -/*static inline*/ s_time_t ticks_to_ns(uint64_t ticks) -{ - return muldiv64(ticks, SECONDS(1), 1000 * cpu_khz); -} - -/*static inline*/ uint64_t ns_to_ticks(s_time_t ns) -{ - return muldiv64(ns, 1000 * cpu_khz, SECONDS(1)); -} - static __initdata struct dt_device_node *timer; =20 #ifdef CONFIG_ACPI diff --git a/xen/arch/arm/vtimer.c b/xen/arch/arm/vtimer.c index d2124b175521..2e85ff2b6e62 100644 --- a/xen/arch/arm/vtimer.c +++ b/xen/arch/arm/vtimer.c @@ -12,13 +12,13 @@ #include #include #include +#include #include =20 #include #include #include #include -#include #include #include #include diff --git a/xen/arch/riscv/include/asm/time.h b/xen/arch/riscv/include/asm= /time.h index 1e7801e2ea0e..be3875b9984e 100644 --- a/xen/arch/riscv/include/asm/time.h +++ b/xen/arch/riscv/include/asm/time.h @@ -24,11 +24,6 @@ static inline cycles_t get_cycles(void) return csr_read(CSR_TIME); } =20 -static inline s_time_t ticks_to_ns(uint64_t ticks) -{ - return muldiv64(ticks, MILLISECS(1), cpu_khz); -} - void preinit_xen_time(void); =20 #endif /* ASM__RISCV__TIME_H */ diff --git a/xen/arch/riscv/time.c b/xen/arch/riscv/time.c index e962f8518d78..2c7af0a5d63b 100644 --- a/xen/arch/riscv/time.c +++ b/xen/arch/riscv/time.c @@ -4,6 +4,7 @@ #include #include #include +#include #include =20 unsigned long __ro_after_init cpu_khz; /* CPU clock frequency in kHz. */ diff --git a/xen/include/xen/time.h b/xen/include/xen/time.h index fe0d7a578a99..2185dd26a439 100644 --- a/xen/include/xen/time.h +++ b/xen/include/xen/time.h @@ -8,6 +8,7 @@ #ifndef __XEN_TIME_H__ #define __XEN_TIME_H__ =20 +#include #include #include =20 @@ -75,6 +76,16 @@ extern void send_timer_event(struct vcpu *v); =20 void domain_set_time_offset(struct domain *d, int64_t time_offset_seconds); =20 +static inline s_time_t ticks_to_ns(uint64_t ticks) +{ + return muldiv64(ticks, MILLISECS(1), cpu_khz); +} + +static inline uint64_t ns_to_ticks(s_time_t ns) +{ + return muldiv64(ns, cpu_khz, MILLISECS(1)); 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[109.243.67.101]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b8edacf1564sm415776866b.52.2026.02.09.08.52.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Feb 2026 08:52:46 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: c311b7df-05d7-11f1-b162-2bf370ae4941 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1770655966; x=1771260766; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ftXQlefZdbz0dncAwMVaBMfjTGZihapLiGK/88smptw=; b=B0Fl9Oikdm84wh+lWNu8SEQwSI3fs3ich86nX53CWPZZV6m4bOBw9QBOCHM/9I+6hm znXl9GJxzvFAkMlE+RceJeJtvozQUvMkYV/N640MbLk+NYn3zm3Dzo2xigdH45dCFhF2 fLfl3xS8UNxeJrrHFBtxHSI0braQkUjUZciCBuV1POntaMrRi/wKHWydfTTZ/EQLMrRF 4wvCove5+oyfM6RFr9pgrGzWzS34OVXq8elrtivle3c0G+AEacfmADXkmpdrOC0W4UUz gRB8nGk18BGWNq+8Rhfr6fum26WgNtrjIeGhXt8PJDr14JLGzE7Ie2geK/tauItqk7me g3Cw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1770655966; x=1771260766; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=ftXQlefZdbz0dncAwMVaBMfjTGZihapLiGK/88smptw=; b=Sk44xEyp8B90E6TraQOo2FUfvHfgOjt+t/0OeJancWyoiTJvCWGrXcOVDoEX0jccnS +YxI8c83BJGZ7/38HG76X498SDNY0/C59hDNSVO0FPIBRAm1x7dONqpX/oCOmTTSeamN JiVRqh/2NUuT2Lt/crx9jepQtz9IHQ4jhanGpdC1jJsgFTL74ChyARgPGH5olSxUUZKL iwukE/3VJtX4Qcu/lBxcaPuheSQCqng42mJLGPM/0AxoVQge8ezg00Sr0L6IGJGSSZUw G7QaJxkaEnbwO2hQVSQ58vclosblZocyXod2mjavl59pUvOCDlaHr0su6+CGvcoTCp3G nb2w== X-Gm-Message-State: AOJu0Yxrqmcpd9ThMqG04GGEpysYeIUCeFTKuYbX5D05Cbfel72c40K2 TVhFXULs/4iW/Ggn2FqRj7zdFUTE7cLqnA+muzaQnJ+HJfyl8KeMNJYzgselqcyE X-Gm-Gg: AZuq6aLGheRZEpZk8n6RK+6UDWEeXXBIHooetrr15MzGL/ltH1AjWnb6rxxGGY3E7Wv mzB2HgelYDKPkmqT8Dofe/VuELBqSNVJgf6xKIwfqIZFITzVqjn80un27XzzrFyKpYelntwYMYs 1W4tFKpGumaioHD8k4cQHU5ArYvVRd9XHpzaTBTHx21fTJdTJ+gcQWY0bW8Pfak3BteYOs1wFKW LR78oG8jLIrnejaQ/9BhRifZZICczaBgGx7Omnp9dLNe+cRjPoH/PuyT7u15RmglHrtnjHw/KVG 0G8Mza1a6Idg5uG5XFEJdopdPw6sq/riJ1T5dGL1jW5s83hKLG0iUiJgIn5Bv+8yzkDFl5wsuzm ptWOtNuvrhspDmhQ75KoNbLMJjJ/DtHSXiuq97XnWj4UBH5ald7o093PFxJymya6CIRZMIPykOF 2TBxg29IWQUC60+/0utSURLp76tHggaZC6BA0q3TfXYY0NJmGZ2hD1Mg== X-Received: by 2002:a17:907:868f:b0:b87:fad:442b with SMTP id a640c23a62f3a-b8edf11f316mr720701766b.3.1770655966298; Mon, 09 Feb 2026 08:52:46 -0800 (PST) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Romain Caritey , Oleksii Kurochko , Alistair Francis , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH v3 08/16] xen/riscv: introduce basic vtimer infrastructure for guests Date: Mon, 9 Feb 2026 17:52:21 +0100 Message-ID: <792ea928d748e9ff7bd331b8e8b0262695a062e9.1770650552.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1770655990970154100 Lay the groundwork for guest timer support by introducing a per-vCPU virtual timer backed by Xen=E2=80=99s common timer infrastructure. The virtual timer is programmed in response to the guest SBI sbi_set_timer() call and injects a virtual supervisor timer interrupt into the vCPU when it expires. While a dedicated struct vtimer is not strictly required at present, it is expected to become necessary once SSTC support is introduced. In particular, it will need to carry additional state such as whether SSTC is enabled, the next compare value (e.g. for the VSTIMECMP CSR) to be saved and restored across context switches, and time delta state (e.g. HTIMEDELTA) required for use cases such as migration. Introducing struct vtimer now avoids a later refactoring. Signed-off-by: Oleksii Kurochko --- Changes in v3: - use one container_of() to get vcpu instead of two container_of()s. --- Changes in v2: - Drop domain_vtimer_init() as it does nothing. - Drop "struct vcpu *v;" from struct vtimer as it could be taken from arch_vcpu using container_of(). - Drop vtimer_initialized, use t->status =3D=3D TIMER_STATUS_invalid instead to understand if timer was or wasn't initialized. - Drop inclusion of xen/domain.h as xen/sched.h already includes it. - s/ xen/time.h/ xen.timer.h in vtimer.c. - Drop ULL in if-conidtion in vtimer_set_timer() as with the cast it isn't necessary to have suffix ULL. - Add migrate timer to vtimer_set_timer() to be sure that vtimer will occur on pCPU it was ran, so the signalling to that vCPU will (commonly) be cheaper. - Check if the timeout has already expired and just inject the event in vtimer_vtimer_set_timer(). - Drop const for ticks argument of vtimer_set_timer(). - Merge two patches to one: - xen/riscv: introduce vtimer - xen/riscv: introduce vtimer_set_timer() and vtimer_expired() --- xen/arch/riscv/Makefile | 1 + xen/arch/riscv/domain.c | 8 +++- xen/arch/riscv/include/asm/domain.h | 3 ++ xen/arch/riscv/include/asm/vtimer.h | 20 ++++++++ xen/arch/riscv/vtimer.c | 71 +++++++++++++++++++++++++++++ 5 files changed, 101 insertions(+), 2 deletions(-) create mode 100644 xen/arch/riscv/include/asm/vtimer.h create mode 100644 xen/arch/riscv/vtimer.c diff --git a/xen/arch/riscv/Makefile b/xen/arch/riscv/Makefile index 868514c25006..7439d029cc45 100644 --- a/xen/arch/riscv/Makefile +++ b/xen/arch/riscv/Makefile @@ -22,6 +22,7 @@ obj-y +=3D traps.o obj-y +=3D vmid.o obj-y +=3D vm_event.o obj-y +=3D vsbi/ +obj-y +=3D vtimer.o =20 $(TARGET): $(TARGET)-syms $(OBJCOPY) -O binary -S $< $@ diff --git a/xen/arch/riscv/domain.c b/xen/arch/riscv/domain.c index 67437912605a..3f4b062b6ce8 100644 --- a/xen/arch/riscv/domain.c +++ b/xen/arch/riscv/domain.c @@ -10,6 +10,7 @@ #include #include #include +#include =20 #define HEDELEG_DEFAULT (BIT(CAUSE_MISALIGNED_FETCH, U) | \ BIT(CAUSE_FETCH_ACCESS, U) | \ @@ -105,11 +106,14 @@ int arch_vcpu_create(struct vcpu *v) if ( is_idle_vcpu(v) ) return rc; =20 + if ( (rc =3D vcpu_vtimer_init(v)) ) + goto fail; + /* - * As the vtimer and interrupt controller (IC) are not yet implemented, + * As interrupt controller (IC) is not yet implemented, * return an error. * - * TODO: Drop this once the vtimer and IC are implemented. + * TODO: Drop this once IC is implemented. */ rc =3D -EOPNOTSUPP; goto fail; diff --git a/xen/arch/riscv/include/asm/domain.h b/xen/arch/riscv/include/a= sm/domain.h index de5aecb862b5..b5a8a9f711ac 100644 --- a/xen/arch/riscv/include/asm/domain.h +++ b/xen/arch/riscv/include/asm/domain.h @@ -8,6 +8,7 @@ #include =20 #include +#include =20 struct vcpu_vmid { uint64_t generation; @@ -49,6 +50,8 @@ struct arch_vcpu { =20 struct cpu_info *cpu_info; =20 + struct vtimer vtimer; + register_t hcounteren; register_t hedeleg; register_t henvcfg; diff --git a/xen/arch/riscv/include/asm/vtimer.h b/xen/arch/riscv/include/a= sm/vtimer.h new file mode 100644 index 000000000000..0d1555511755 --- /dev/null +++ b/xen/arch/riscv/include/asm/vtimer.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * (c) 2023-2024 Vates + */ + +#ifndef ASM__RISCV__VTIMER_H +#define ASM__RISCV__VTIMER_H + +#include + +struct vtimer { + struct timer timer; +}; + +int vcpu_vtimer_init(struct vcpu *v); +void vcpu_timer_destroy(struct vcpu *v); + +void vtimer_set_timer(struct vtimer *t, uint64_t ticks); + +#endif /* ASM__RISCV__VTIMER_H */ diff --git a/xen/arch/riscv/vtimer.c b/xen/arch/riscv/vtimer.c new file mode 100644 index 000000000000..32d142bcdfcd --- /dev/null +++ b/xen/arch/riscv/vtimer.c @@ -0,0 +1,71 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +#include + +static void vtimer_expired(void *data) +{ + struct vtimer *t =3D data; + struct vcpu *v =3D container_of(t, struct vcpu, arch.vtimer); + + vcpu_set_interrupt(v, IRQ_VS_TIMER); +} + +int vcpu_vtimer_init(struct vcpu *v) +{ + struct vtimer *t =3D &v->arch.vtimer; + + init_timer(&t->timer, vtimer_expired, t, v->processor); + + return 0; +} + +void vcpu_timer_destroy(struct vcpu *v) +{ + struct vtimer *t =3D &v->arch.vtimer; + + if ( t->timer.status =3D=3D TIMER_STATUS_invalid ) + return; + + kill_timer(&v->arch.vtimer.timer); +} + +void vtimer_set_timer(struct vtimer *t, const uint64_t ticks) +{ + struct vcpu *v =3D container_of(t, struct vcpu, arch.vtimer); + s_time_t expires =3D ticks_to_ns(ticks - boot_clock_cycles); + + vcpu_unset_interrupt(v, IRQ_VS_TIMER); + + /* + * According to the RISC-V sbi spec: + * If the supervisor wishes to clear the timer interrupt without + * scheduling the next timer event, it can either request a timer + * interrupt infinitely far into the future (i.e., (uint64_t)-1), + * or it can instead mask the timer interrupt by clearing sie.STIE C= SR + * bit. + */ + if ( ticks =3D=3D ((uint64_t)~0) ) + { + stop_timer(&t->timer); + + return; + } + + if ( expires < NOW() ) + { + /* + * Simplify the logic if the timeout has already expired and just + * inject the event. + */ + stop_timer(&t->timer); + vcpu_set_interrupt(v, IRQ_VS_TIMER); + + return; + } + + migrate_timer(&t->timer, smp_processor_id()); + set_timer(&t->timer, expires); +} --=20 2.52.0 From nobody Tue Feb 10 23:53:55 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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This mirrors the behavior of Arm and enables proper vCPU wakeup handling on RISC-V. Remove the stub implementation from stubs.c, as it is now provided by arch/riscv/domain.c. Since vcpu_kick() calls perfc_incr(vcpu_kick), add perfcounter for vcpu_kick to handle the case when CONFIG_PERF_COUNTERS=3Dy. Although CONFIG_PERF_COUNTERS is not enabled by default, it can be enabled, for example, by randconfig what will lead to CI build issues. Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich --- Changes in v3: - Add asm/perfc_defn.h to provide vcpu_kick perfcoounter to cover the case when CONFIG_PERF_COUNTERS=3Dy. --- Changes in v2: - Add Acked-by: Jan Beulich . --- xen/arch/riscv/domain.c | 14 ++++++++++++++ xen/arch/riscv/include/asm/Makefile | 1 - xen/arch/riscv/include/asm/perfc_defn.h | 3 +++ xen/arch/riscv/stubs.c | 5 ----- 4 files changed, 17 insertions(+), 6 deletions(-) create mode 100644 xen/arch/riscv/include/asm/perfc_defn.h diff --git a/xen/arch/riscv/domain.c b/xen/arch/riscv/domain.c index 3f4b062b6ce8..30a966f53c1d 100644 --- a/xen/arch/riscv/domain.c +++ b/xen/arch/riscv/domain.c @@ -1,8 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ =20 +#include #include #include #include +#include #include =20 #include @@ -231,3 +233,15 @@ void vcpu_flush_interrupts(struct vcpu *v) vcpu_update_hvip(v); } } + +void vcpu_kick(struct vcpu *v) +{ + bool running =3D v->is_running; + + vcpu_unblock(v); + if ( running && v !=3D current ) + { + perfc_incr(vcpu_kick); + smp_send_event_check_mask(cpumask_of(v->processor)); + } +} diff --git a/xen/arch/riscv/include/asm/Makefile b/xen/arch/riscv/include/a= sm/Makefile index 3824f31c395c..86c56251d5d7 100644 --- a/xen/arch/riscv/include/asm/Makefile +++ b/xen/arch/riscv/include/asm/Makefile @@ -7,7 +7,6 @@ generic-y +=3D hypercall.h generic-y +=3D iocap.h generic-y +=3D irq-dt.h generic-y +=3D percpu.h -generic-y +=3D perfc_defn.h generic-y +=3D random.h generic-y +=3D softirq.h generic-y +=3D vm_event.h diff --git a/xen/arch/riscv/include/asm/perfc_defn.h b/xen/arch/riscv/inclu= de/asm/perfc_defn.h new file mode 100644 index 000000000000..8a4b945df662 --- /dev/null +++ b/xen/arch/riscv/include/asm/perfc_defn.h @@ -0,0 +1,3 @@ +/* This file is intended to be included multiple times. */ + +PERFCOUNTER(vcpu_kick, "vcpu: notify other vcpu") diff --git a/xen/arch/riscv/stubs.c b/xen/arch/riscv/stubs.c index c5784a436574..1f0add97b361 100644 --- a/xen/arch/riscv/stubs.c +++ b/xen/arch/riscv/stubs.c @@ -208,11 +208,6 @@ void vcpu_block_unless_event_pending(struct vcpu *v) BUG_ON("unimplemented"); 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[109.243.67.101]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b8edacf1564sm415776866b.52.2026.02.09.08.52.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Feb 2026 08:52:48 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: c457e3b0-05d7-11f1-b162-2bf370ae4941 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1770655969; x=1771260769; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=NpYDvQ6BAB6GpfLP621I0RKvGO5xaivkih7Lty/queI=; b=C7bkHyb1IODOZWStUacFDH5SOhQZOA75zj0sO9c3b8Ql6ZaAMfU1M9LeEQTF/facLE 4N9Ym5tGJxFwA9v+xYGZMjfSebiHIEsOv4dzjC71mIRTivQcgSW1dSrFLJ2gy2X/w6tA ZteF+Lg9CRnlT40vzVwI7Ombp9vg5Ci3xMO+pX51ZVHrScZmtVo/4U42A26aaI+LaRlP ZiTEyuHyb1ht3HsvjC/L11WbMlinyhAVre9A5nRVpoj57Rp39xxCtIQcFWRABIidUnzf 4uVaJhSpEZUjAOTdGMWRVM3aKk0uK6yzloe+hOewSZEDGb8QlWn3UJUokN/o9NbEyK1J W9Qg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1770655969; x=1771260769; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=NpYDvQ6BAB6GpfLP621I0RKvGO5xaivkih7Lty/queI=; b=siJQYfeFpCPtV/60zdBFvyoHmjap9AjAzI/Kp+WwnuVcbrqgO56XgO17hII1CKKCUK AhuSpRatV5iTKhbAkLOwfp0eHU4qpKRuZGTYYyLLi6eh5IsbAx8xtlQNK191iSJ7bcGj cLH5UkO3TqBwrlz2CHamXdx1Jwu4Mu69JikYPgr2m88Be1LAQsg9vnU9AQQ6ldfWicY9 /QU6fPR6BijhgZ09zohvaP2AJD09vq2tvASGl+bdhhN9S4t+BBSd+9RNIDyNyTxFv6e4 W1633lE4oRKsQXdPVSsPxobXp2gyfjk+iafFaFkTvHqFuK7GcttpANkIv7/kR5vOSWB0 jxsQ== X-Gm-Message-State: AOJu0YxvVfT0pDEAIK5px4uooFAhZYxNLOEaQa8AumuZdAg4aQF/jWF4 9PljHou+ls+hKkPCQersUBKX9R+wrcm/ttsEFBKPEvxpeNQxJupm4J+o3hOXPRlo X-Gm-Gg: AZuq6aIym2gcC0RoaKw+Hzz1IhvhX1/wKUw45uZNYm7EVrQEeGFjUcI+YgtKQPbqE4t CmWgwCCh9vwrKwkXSm6Dhg4Lyt1VyWOwn0rcM8/H/cQDR5lpVp/VEr6dPZO8TZY6ROWHi0JyWia Yli3779BQl1nnYMrN2w5tYuGY2IlCQL6wmVKHONBsi4wH22TzKJxgwKSKexmUta9STW2yCOWu0C IwyCy/w7MfIDCpBTmIAS4SuPJv97wRL+VW2JNUMSsTkYnzvze4A7msyfX9X2KG+PxeGPXJxAnYw +k8a5rSoG2obhQGYDwfwGFSWp7+c9myuvg0RvRVF7DsM2x/S3MFEPjbPXRPaHN8hOeA5XPQP5Z9 bkDiTODWiDoe1JH8VPm8uueAqzkxqIOALyK231Culy+uDk1xtiAHSClkEn2UfEnKsG3Kr7JLEZO e/Kamycws/J8vnH0w9aF9Pb+Sec3V1fRhip1sdIP44l8kuPeWGvSBUrA== X-Received: by 2002:a17:907:9717:b0:b87:892:f440 with SMTP id a640c23a62f3a-b8edf2fa568mr606769466b.38.1770655968372; Mon, 09 Feb 2026 08:52:48 -0800 (PST) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Romain Caritey , Oleksii Kurochko , Alistair Francis , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH v3 10/16] xen/riscv: add vtimer context switch helpers Date: Mon, 9 Feb 2026 17:52:23 +0100 Message-ID: X-Mailer: git-send-email 2.52.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1770656002845158500 Content-Type: text/plain; charset="utf-8" Introduce vtimer_ctxt_switch_from() and vtimer_ctxt_switch_to() to handle virtual timer state across vCPU context switches. At present, vtimer_ctxt_switch_from() is a no-op because the RISC-V SSTC extension, which provides a virtualization-aware timer, is not yet supported. Xen therefore relies the virtual (SBI-based) timer. The virtual timer uses Xen's internal timer infrastructure and must be associated with the pCPU on which the vCPU is currently running so that timer events can be delivered efficiently. As a result, vtimer_ctxt_switch_= to() migrates the timer to the target pCPU when a vCPU is scheduled in. Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich --- Changes in v3: - s/vtimer_ctx_switch_to/vtimer_ctxt_switch_to - s/vtimer_ctx_switch_from/vtimer_ctxt_switch_from - Add Acked-by: Jan Beulich . --- Changes in v2: - Align the parameters names for vtimer_ctx_switch_from() and vtimer_ctx_= switch_to() in declarations to match the ones in the defintions to make Misra happy. - s/vtimer_save/vtimer_ctx_switch_from. - s/vtimer_restore/vtimer_ctx_switch_to. - Update the commit message. --- xen/arch/riscv/include/asm/vtimer.h | 3 +++ xen/arch/riscv/vtimer.c | 15 +++++++++++++++ 2 files changed, 18 insertions(+) diff --git a/xen/arch/riscv/include/asm/vtimer.h b/xen/arch/riscv/include/a= sm/vtimer.h index 0d1555511755..c70b0226515e 100644 --- a/xen/arch/riscv/include/asm/vtimer.h +++ b/xen/arch/riscv/include/asm/vtimer.h @@ -17,4 +17,7 @@ void vcpu_timer_destroy(struct vcpu *v); =20 void vtimer_set_timer(struct vtimer *t, uint64_t ticks); =20 +void vtimer_ctxt_switch_from(struct vcpu *p); +void vtimer_ctxt_switch_to(struct vcpu *n); + #endif /* ASM__RISCV__VTIMER_H */ diff --git a/xen/arch/riscv/vtimer.c b/xen/arch/riscv/vtimer.c index 32d142bcdfcd..afd8a53a7387 100644 --- a/xen/arch/riscv/vtimer.c +++ b/xen/arch/riscv/vtimer.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ =20 +#include #include #include =20 @@ -69,3 +70,17 @@ void vtimer_set_timer(struct vtimer *t, const uint64_t t= icks) migrate_timer(&t->timer, smp_processor_id()); set_timer(&t->timer, expires); } + +void vtimer_ctxt_switch_from(struct vcpu *p) +{ + ASSERT(!is_idle_vcpu(p)); + + /* Nothing to do at the moment as SSTC isn't supported now. */ +} + +void vtimer_ctxt_switch_to(struct vcpu *n) +{ + ASSERT(!is_idle_vcpu(n)); + + migrate_timer(&n->arch.vtimer.timer, n->processor); +} --=20 2.52.0 From nobody Tue Feb 10 23:53:55 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1770655997; cv=none; d=zohomail.com; s=zohoarc; b=B7Y9RbD2E1hgnwm4nIAlLbFTeP53mu3R8xWXfnNWw6INJNyPx0idNiuhGht8pUaZNhc3an3lRlBXIg01L7FWFuUBDVNXCPhtvvNl02OxJd/wSR/Peh1widM4pG0Pma2QOIdXbsqXiNi+kcPhmPBkup55KR1ebvJQ6I8bFaBL8cU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1770655997; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=Hi3FnDG07OCkFyCy7UaZFSaTKT/2LCRxd2Xxk35QB18=; b=h5tJ5VVCVxbkDhbxER/8iuOC6ofvhLIqx6+XuBO8HCktoC7sfSUJSsWzU5621e3D20QYipfNbVT1G+FErDD8V2fiJX0Dv5YrB565ngcuuhTu2YAkAem4F18r94gCWex6itfmns6sCqyTsAy1nL23tBhopFgI6rKhZmWcKmSaGhY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1770655997442948.1930536564479; Mon, 9 Feb 2026 08:53:17 -0800 (PST) Received: from list by lists.xenproject.org with outflank-mailman.1225796.1532463 (Exim 4.92) (envelope-from ) id 1vpUVJ-0001jY-UO; Mon, 09 Feb 2026 16:52:53 +0000 Received: by outflank-mailman (output) from mailman id 1225796.1532463; Mon, 09 Feb 2026 16:52:53 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vpUVJ-0001fl-A7; Mon, 09 Feb 2026 16:52:53 +0000 Received: by outflank-mailman (input) for mailman id 1225796; Mon, 09 Feb 2026 16:52:51 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vpUVH-0007Zo-8z for xen-devel@lists.xenproject.org; Mon, 09 Feb 2026 16:52:51 +0000 Received: from mail-ej1-x632.google.com (mail-ej1-x632.google.com [2a00:1450:4864:20::632]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id c4f42146-05d7-11f1-b162-2bf370ae4941; Mon, 09 Feb 2026 17:52:50 +0100 (CET) Received: by mail-ej1-x632.google.com with SMTP id a640c23a62f3a-b8eafb515aeso553657466b.1 for ; Mon, 09 Feb 2026 08:52:50 -0800 (PST) Received: from fedora (user-109-243-67-101.play-internet.pl. [109.243.67.101]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b8edacf1564sm415776866b.52.2026.02.09.08.52.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Feb 2026 08:52:49 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: c4f42146-05d7-11f1-b162-2bf370ae4941 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1770655970; x=1771260770; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Hi3FnDG07OCkFyCy7UaZFSaTKT/2LCRxd2Xxk35QB18=; b=ejBeEvtEc4jh0Bds66dLiLpiJdqRE5/x7IGihF/HJGV8iUywTmgk++56bVHX/gQfGH fLwscUFTN4+MzQsIUaRJJ4Uai8LRtmscglmEDe3jS7YniVW79DCaQkH5Ps//HYMwDTWG Anw1+V/5M/tZFdVdJJ+gUatuGzdlyqneDeyOCLAf2O/YhqaVvZ+Vjhpmab5PoNUDlJqA RR74AWzyZnngFeSU4A/zfGkrM0EFrVwxizYuuMy994Qa2gAIt4+DQeccNDNJ/+tdOivv FWawK7+BV3OgszfDjGlLqlwQr9kJgTEGZH9jJF+wkPkaLNOOLcTvI1D4wKWYwQgo7jNZ 8HbQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1770655970; x=1771260770; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=Hi3FnDG07OCkFyCy7UaZFSaTKT/2LCRxd2Xxk35QB18=; b=felipY+3AixRu/7wL+Wl4KLt6XpO5X1A+Hdv+pB4p02cnaOZb+0Salzbafom0GWzLh nSKn1AEFa8KJHtmNBDDLldGK8GSqEtpV4KPIhZxv+gLOGci/HJ+oXmjd8Rbh7i9w+cq8 Pwd12kQBMYHNPczriRnvz/q3pFlOgb+as/964ehKDTV+H7pmk7O26+rOMYozkQwfM+9h BpLGBYWcHmn7z8biHGDiczktBhpmd9cLyfu32eIUCl8xWE2rlSPG8l5s+ecWUmRFAh7d LhE/Wgyz6EQELmH/JwQzaJrSIXO7y51TPerqK7s7vH+qukNjBcBdikJXroptutX2v2qx A+FA== X-Gm-Message-State: AOJu0YzcLxbqd7PUqjvGmPZ7Duxs1g1iCod0zd4k0cbavy56ycugUDqR 2R63bvk87pIfgY2T2YzAWtu+611ciUxVA1MSwDzxZ7HbfWm/nMbDoCbeQHOvueWK X-Gm-Gg: AZuq6aKDTbertHkX+IKbd9Yy6cVLVfzMLJkjMUgOD43EGKiMA+N9+XDoMY9Zw4bjKDa UfcH0/7wFKE6/eRPGLsCIMwzPSizttvUuma4d4cabiY3te+JRZU2j4/0cOcW1hfWiQ7tqGcpbb0 Zpq9aBMEE0ETIl2VkWVLbfNu3Fob5JulPHX8Y3SaeoomHxLr1w0DyPQ1zviFffK8F4QQufpZM0M Rs3KkQPfsucqUjlwB+v5M/hteHIQI9gqU+DddNtLbN+8v+nUHFoUmYBrR7+4WdzKeiCj5TTf+M+ Ie4V1qJNuqHmSchXs4AsNABOEnjOv9nNSQRFi+VriykKXHQ4IH4U9Ou9+8V5pQaBtZ/Hhxr9oWG cs6xHuQydLUubsIJutZoHwUd6VWMstoxlQ+uDzanJMv1KSaItu4LpnkKD41hpRlQT1d96p3sYpn Ivx4HSz+OzzMZ3XRKFvR9UgUOWdC68KHDx4hYrd0DeKptVyq7RARSH0A== X-Received: by 2002:a17:907:9451:b0:b83:1327:920d with SMTP id a640c23a62f3a-b8eded474b9mr601057966b.0.1770655969502; Mon, 09 Feb 2026 08:52:49 -0800 (PST) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Romain Caritey , Oleksii Kurochko , Alistair Francis , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH v3 11/16] xen/riscv: implement SBI legacy SET_TIMER support for guests Date: Mon, 9 Feb 2026 17:52:24 +0100 Message-ID: <0bc0547fe8ba97f66c9847cfc334d62add25504d.1770650552.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1770655999038154100 Add handling of the SBI_EXT_0_1_SET_TIMER function ID to the legacy extension ecall handler. The handler now programs the vCPU=E2=80=99s virtual timer via vtimer_set_timer() and returns SBI_SUCCESS. This enables guests using the legacy SBI timer interface to schedule timer events correctly. Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich --- Changes in v3: - Nothing changed. Only rebase. --- Changes in v2: - Add Acked-by: Jan Beulich . --- xen/arch/riscv/vsbi/legacy-extension.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/xen/arch/riscv/vsbi/legacy-extension.c b/xen/arch/riscv/vsbi/l= egacy-extension.c index 2e8df191c295..090c23440cea 100644 --- a/xen/arch/riscv/vsbi/legacy-extension.c +++ b/xen/arch/riscv/vsbi/legacy-extension.c @@ -7,6 +7,7 @@ =20 #include #include +#include =20 static void vsbi_print_char(char c) { @@ -44,6 +45,11 @@ static int vsbi_legacy_ecall_handler(unsigned long eid, = unsigned long fid, ret =3D SBI_ERR_NOT_SUPPORTED; break; =20 + case SBI_EXT_0_1_SET_TIMER: + vtimer_set_timer(¤t->arch.vtimer, regs->a0); + regs->a0 =3D SBI_SUCCESS; + break; + default: /* * TODO: domain_crash() is acceptable here while things are still = under --=20 2.52.0 From nobody Tue Feb 10 23:53:55 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1770655995; cv=none; d=zohomail.com; s=zohoarc; b=dSSqiPN/TpWzXmdA9r5c7RJQhyIN7GqZTmv94F+jv9k+zpsvQcOn0Fibqweel0yu/Woh79ZujAmvE+aVw4P0pWcHmpM4RXiDvJoJ9O5/k+GebcfxCxS6e7EPINuHSEnBr8RiO7sKOlWQDdTdWfQf7Xsw55x4G6/BvQ4TwGQePO0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1770655995; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=rzoW6oI1pZTCczygZ2TeNSQR2mfIOIpFjPwj3JLnlaQ=; b=cZdKI7AXOe8dG2QhMDmYM8vqbFNUBXUowvn61SuDI/d4fHF55+hvasgY5Ujl2hjlaN5VUQlLT9gl++4wWmfJqMxbj7l2n4qjvoNnOlyGdZ1uhmFawpn0UfzwIldD6uJqvcRreMy99Boa1M0gNDnluXofxBp1E0DCvopKklTvGtA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 17706559954961.4510806991065692; Mon, 9 Feb 2026 08:53:15 -0800 (PST) Received: from list by lists.xenproject.org with outflank-mailman.1225799.1532478 (Exim 4.92) (envelope-from ) id 1vpUVL-00029y-RB; Mon, 09 Feb 2026 16:52:55 +0000 Received: by outflank-mailman (output) from mailman id 1225799.1532478; Mon, 09 Feb 2026 16:52:55 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vpUVL-00027E-Fa; Mon, 09 Feb 2026 16:52:55 +0000 Received: by outflank-mailman (input) for mailman id 1225799; Mon, 09 Feb 2026 16:52:53 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vpUVJ-0007Zd-9A for xen-devel@lists.xenproject.org; Mon, 09 Feb 2026 16:52:53 +0000 Received: from mail-ed1-x52b.google.com (mail-ed1-x52b.google.com [2a00:1450:4864:20::52b]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id c579a60a-05d7-11f1-9ccf-f158ae23cfc8; Mon, 09 Feb 2026 17:52:51 +0100 (CET) Received: by mail-ed1-x52b.google.com with SMTP id 4fb4d7f45d1cf-6505cac9879so6220421a12.1 for ; Mon, 09 Feb 2026 08:52:51 -0800 (PST) Received: from fedora (user-109-243-67-101.play-internet.pl. [109.243.67.101]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b8edacf1564sm415776866b.52.2026.02.09.08.52.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Feb 2026 08:52:50 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: c579a60a-05d7-11f1-9ccf-f158ae23cfc8 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1770655971; x=1771260771; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=rzoW6oI1pZTCczygZ2TeNSQR2mfIOIpFjPwj3JLnlaQ=; b=Hk+aZ0J3Jv4UOB6n36pTG71ju2agjyMRptihvIzxvER5KUv91tmXMRUM3htgcbHsGW Czjfin2/dxlM7/Px+IR4RRtX8On15tszrZZ2aBz4ll0b0w3SJxcjrRtyyD2srHiXrdqY iRVFbZbYnRWpJxgPoCfRoB28B1HCHcizGYn0j6l9xAOu8eXkO65/hum8eItjK+TADMYH 8EzCALWx3LaU1gK0S6TPiESpaO/BhpeYt1YsP2PhOqycojMURTtFzvSIJPLd7aQBQ6se /ckyVg28sX55OErJZFwMDl9yoSU92wZ/w33FK68TlkpoKGEF8js+6hEh2yirvZZasR+N Robg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1770655971; x=1771260771; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=rzoW6oI1pZTCczygZ2TeNSQR2mfIOIpFjPwj3JLnlaQ=; b=i26V5HqftEpkWMnjuJrIn+hXuf3nBZRkZyQnDO+lMDUWKVQ53A0F1aKACoT5P7fd/8 g8s/je7Oq24UO/MzVmvCbN0dVx1/J7nVSUb+eP1VVmar4MuMz5khKbrhAoEO1/61yBbA nnx8ukq/sJK3N8yQsjfFsC8cuT+wNDpdtH2T4BvGgl2M9TkrfkXqNt9iRPhkM6Fu0eOa SOj/jzRMX/qAjVbwt/xSmJaA/RCNJFGXvaqjNjYczcjx5oMaeWUuCexwdyf9y/nBYtOo iorPCENyBp6u5/0/sC64McnmwoeUdFRxeczvDmCiUTOPemuMctdUYsPjnHhSWbNaHRDs jKXw== X-Gm-Message-State: AOJu0Ywod3471JMLq/BUO3hDOJ+eQIuEi4DXVW1+UCco7m8aNDI4C650 DthJ9XqmwF75ziDlG6ZQOMOQuhXviyBI5dUw5ckVlOuv2EQU1wkOop6a9VSiQJCP X-Gm-Gg: AZuq6aJbOCDP5UfWDk1JjLcTfUP+G+lexZcVbPkFB71wA7GXrAx0OKF9GF4K20giPKD mEgBxB3s3PLZXMOEIFe2iePlJmy1nX03XvGLEVQeJ7phDAky+9OK4v+DY5uIA1bodPIXoSVWW89 5hWSDMzyNXCtvsi5LV1wAR1PZitHAwWnxwmDbEDnRtllv6Googg10KGSReTekbjUCcvtW3n67JM +vAj2ts5pXcGJ30XbiwseuTSdqcK5Yqm7BBqK+XgHQ8wXK1nVUTYhAUhdgkBJKl1CktqnNImX8a etmJj3t7vrALTLwGjyfQV/ncHGOL6ciYCM6eQ/AWVxqY3YOLIIDmTC8JXozsyxfYoFrqGoovdL6 S1xZwb5lR1Y0agEw9mSYBgVWMoQXvYpJ9ssqSJOZ6qNRYJdr3rzRimv9fLKd237pcci1Ev34V6l nE6+YDqudn9mELB/tlo44x2P1LO9Ry41lcnW/a2nyYgHTMlayzyCVyGw== X-Received: by 2002:a17:907:3dac:b0:b86:fed0:2b with SMTP id a640c23a62f3a-b8edf307a5emr669724566b.32.1770655970541; Mon, 09 Feb 2026 08:52:50 -0800 (PST) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Romain Caritey , Oleksii Kurochko , Alistair Francis , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH v3 12/16] xen/riscv: introduce sbi_set_timer() Date: Mon, 9 Feb 2026 17:52:25 +0100 Message-ID: <3b102fd2267c629e8505631277efc2eeae5a1a6a.1770650552.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1770655996807158500 Introduce a function pointer for sbi_set_timer(), since different OpenSBI versions may implement the TIME extension with different extension IDs and/or function IDs. If the TIME extension is not available, fall back to the legacy timer mechanism. This is useful when Xen runs as a guest under another Xen, because the TIME extension is not currently virtualised and therefore will not appear as available. Despite of the fact that sbi_set_timer_v01 is introduced and used as fall back, SBI v0.1 still isn't fully supported (with the current SBI calls usage, sbi_rfence_v01 should be introduced too), so panic() in sbi_init() isn't removed. The sbi_set_timer() pointer will be used by reprogram_timer() to program Xen=E2=80=99s physical timer as without SSTC extension there is no any other option except SBI call to do that as only M-timer is available for us. Use dprintk() for all the cases to print that a speicifc SBI extension is available as it isn't really necessary in case of release builds. Signed-off-by: Oleksii Kurochko --- Changes in v3: - Init sbi_set_timer with sbi_set_timer_v01 as fallback value. - Sort SBI IDs in the same way as SBI EXT IDs are declared. - Add __ro_after_init for sbi_set_timer variable. - use dprintk instead of printk to print information if SBI ext is availab= le. --- Changes in v2: - Move up defintion of SBI_EXT_TIME_SET_TIMER and use the same padding as defintions around it. - Add an extra comment about stime_value granuality above declaration of sbi_set_timer function pointer. - Refactor implemetation of sbi_set_timer_v02(). - Provide fallback for sbi_set_timer_v01(). - Update the commit message. --- xen/arch/riscv/include/asm/sbi.h | 18 ++++++++++++++ xen/arch/riscv/sbi.c | 40 +++++++++++++++++++++++++++++++- 2 files changed, 57 insertions(+), 1 deletion(-) diff --git a/xen/arch/riscv/include/asm/sbi.h b/xen/arch/riscv/include/asm/= sbi.h index 79f7ff5c5501..a237f8b1393c 100644 --- a/xen/arch/riscv/include/asm/sbi.h +++ b/xen/arch/riscv/include/asm/sbi.h @@ -29,6 +29,7 @@ =20 #define SBI_EXT_BASE 0x10 #define SBI_EXT_RFENCE 0x52464E43 +#define SBI_EXT_TIME 0x54494D45 =20 /* SBI function IDs for BASE extension */ #define SBI_EXT_BASE_GET_SPEC_VERSION 0x0 @@ -48,6 +49,9 @@ #define SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA 0x5 #define SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID 0x6 =20 +/* SBI function IDs for TIME extension */ +#define SBI_EXT_TIME_SET_TIMER 0x0 + #define SBI_SPEC_VERSION_MAJOR_MASK 0x7f000000 #define SBI_SPEC_VERSION_MINOR_MASK 0x00ffffff =20 @@ -134,6 +138,20 @@ int sbi_remote_hfence_gvma(const cpumask_t *cpu_mask, = vaddr_t start, int sbi_remote_hfence_gvma_vmid(const cpumask_t *cpu_mask, vaddr_t start, size_t size, unsigned long vmid); =20 +/* + * Programs the clock for next event after stime_value time. This function= also + * clears the pending timer interrupt bit. + * If the supervisor wishes to clear the timer interrupt without schedulin= g the + * next timer event, it can either request a timer interrupt infinitely far + * into the future (i.e., (uint64_t)-1), or it can instead mask the timer + * interrupt by clearing sie.STIE CSR bit. + * The stime_value parameter represents absolute time measured in ticks. + * + * This SBI call returns 0 upon success or an implementation specific nega= tive + * error code. + */ +extern int (* __ro_after_init sbi_set_timer)(uint64_t stime_value); + /* * Initialize SBI library * diff --git a/xen/arch/riscv/sbi.c b/xen/arch/riscv/sbi.c index 425dce44c679..b4a7ae6940c1 100644 --- a/xen/arch/riscv/sbi.c +++ b/xen/arch/riscv/sbi.c @@ -249,6 +249,38 @@ static int (* __ro_after_init sbi_rfence)(unsigned lon= g fid, unsigned long arg4, unsigned long arg5); =20 +static int cf_check sbi_set_timer_v02(uint64_t stime_value) +{ + struct sbiret ret; + + ret =3D sbi_ecall(SBI_EXT_TIME, SBI_EXT_TIME_SET_TIMER, stime_value, +#ifdef CONFIG_RISCV_32 + stime_value >> 32, +#else + 0, +#endif + 0, 0, 0, 0); + + return sbi_err_map_xen_errno(ret.error); +} + +static int cf_check sbi_set_timer_v01(uint64_t stime_value) +{ + struct sbiret ret; + + ret =3D sbi_ecall(SBI_EXT_0_1_SET_TIMER, 0, stime_value, +#ifdef CONFIG_RISCV_32 + stime_value >> 32, +#else + 0, +#endif + 0, 0, 0, 0); + + return sbi_err_map_xen_errno(ret.error); +} + +int (* __ro_after_init sbi_set_timer)(uint64_t stime_value) =3D sbi_set_ti= mer_v01; + int sbi_remote_sfence_vma(const cpumask_t *cpu_mask, vaddr_t start, size_t size) { @@ -324,7 +356,13 @@ int __init sbi_init(void) if ( sbi_probe_extension(SBI_EXT_RFENCE) > 0 ) { sbi_rfence =3D sbi_rfence_v02; - printk("SBI v0.2 RFENCE extension detected\n"); + dprintk(XENLOG_INFO, "SBI v0.2 RFENCE extension detected\n"); + } + + if ( sbi_probe_extension(SBI_EXT_TIME) > 0 ) + { + sbi_set_timer =3D sbi_set_timer_v02; + dprintk(XENLOG_INFO, "SBI v0.2 TIME extension detected\n"); } } else --=20 2.52.0 From nobody Tue Feb 10 23:53:55 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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[109.243.67.101]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b8edacf1564sm415776866b.52.2026.02.09.08.52.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Feb 2026 08:52:51 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: c62d15db-05d7-11f1-b162-2bf370ae4941 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1770655972; x=1771260772; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=cNbrlMqhuICu7ctpXyh9WGmkD3dnZmEYO+L7YJ0WFAc=; b=aI9cpupSblT1Z7mEaeSENuWULiI15LEQ/F89QTrUYS6Ws9zT6L3X+nkVmsaXhAsuL0 LNAbnDQ63Khm74bSBSTpF5F34H3uOFvpj/L95iwXsXgv9jxu+xyUuNGBbAZFCqK8y/An mDJ+YODacm66iTu4gtyoCpaYfgMOGKJIewENLFz5fKT+c0yt7O7H2dSQr+gbGJgwx/Gm QkxmGbLYAPCmka51V25jDrd5gL7TYCX71CRNNxFUnoxsCeeI1uVu9VBqRaCLA0koAUdn JfjVXMrsri/9SQYGatkiSkdWR9AC2LU6x04udL6KBkH2OCQs68pF9qEylPgeRrHeHm64 f2WA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1770655972; x=1771260772; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=cNbrlMqhuICu7ctpXyh9WGmkD3dnZmEYO+L7YJ0WFAc=; b=jLmvIrzqZeWpjNOSO2amS1wFw2XTTkkCUoZMaAhtX8+bDVVdRf+uneNaC/dQWhLwnL o32GYq0hmJASxGWw5D9HCCy1BKSnN/EL/HTJAaMrGi/mgx/9zpFIfflKKcLuMNEPFJtM +m+yeow5oPT/k7iPYbnluUqevJiTshnuqwqK3A6kZjxSLa8ijriZUuJcpasZi/gHDKZK 1BQKBfsgEIevk/RPFd2XehvAZtcZeWxKFnvvqlOfc73uBW9mYao0v0uBhkIgcOkbY/2W arIWG0+4WubkhOKFYnsnAhzBYA8cYMYzCw8zSIIFrlGsFS7nslPMZIyFdathj6wA8dhq I85A== X-Gm-Message-State: AOJu0Yzz3gFglC0tDkqk1vZayJUCmzgHTcvI5XKEjwQe6qConLlpLX4d t+1dyjuin0svHa1ygQ8rJZ9UeQKQQWvJ7nGgoDrW1xxe5q9vorj91isO8F1JFNlD X-Gm-Gg: AZuq6aJO7v5HCW64ZSq1skfnAjzjcIU3KQPGxgys/fOwm3y0HKbsHo6AkeqbZSYyDx9 r7BJ0cyT2ggMFCbVJRKAJRYgJVpRgWhnmqmUt/LLuwzMazOtnl5Bi2Dc71k2Mzr3Jap5jjYKplC dK336cby7BOIkJsCCyQTYPmtM05yJWzXsPFXevqFJxVDl3XWY6KUkjR/a51imhBXIsqgKgaHx3v IU+fx4V3DQFR8YIzp8D0Fghng3fV8YBEjIYiIftj1sXg0ukpOIPovP+2lwkLlBag30OxPMH3m1J dUtWEuDpTX4o9F5t5mnYLhWPDyqbSl7y3ZieTBhfW8siA4WL0F7jbUNehZpHNHtMz2f/aoW/s/S 0NTHaLYIonEB2Olt1n7FAkLzY3PzpP0U20pjHszXGvn0o/SwoufdXtfJccfySDsMXgYliIN5T2/ FMxTex/y5w05Vd1wLSCNc8vAMlDDB0ZbN0Us56/iq4axM6PDqgSDK7+w== X-Received: by 2002:a17:906:4785:b0:b8e:9d66:f5fb with SMTP id a640c23a62f3a-b8eded5bf07mr685244766b.0.1770655971561; Mon, 09 Feb 2026 08:52:51 -0800 (PST) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Romain Caritey , Oleksii Kurochko , Alistair Francis , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH v3 13/16] xen/riscv: implement reprogram_timer() via SBI Date: Mon, 9 Feb 2026 17:52:26 +0100 Message-ID: X-Mailer: git-send-email 2.52.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1770656002862158500 Content-Type: text/plain; charset="utf-8" Implement reprogram_timer() on RISC-V using the standard SBI timer call. The privileged architecture only defines machine-mode timer interrupts (using mtime/mtimecmp). Therefore, timer services for S/HS/VS mode must be provided by M-mode via SBI calls. SSTC (Supervisor-mode Timer Control) is optional and is not supported on the boards available to me, so the only viable approach today is to program the timer through SBI. reprogram_timer() enables/disables the supervisor timer interrupt and programs the next timer deadline using sbi_set_timer(). If the SBI call fails, the code panics, because sbi_set_timer() is expected to return either 0 or -ENOSUPP (this has been stable from early OpenSBI versions to the latest ones). The SBI spec does not define a standard negative error code for this call, and without SSTC there is no alternative method to program the timer, so the SBI timer call must be available. reprogram_timer() currently returns int for compatibility with the existing prototype. While it might be cleaner to return bool, keeping the existing signature avoids premature changes in case sbi_set_timer() ever needs to return other values (based on which we could try to avoid panic-ing) in the future. Signed-off-by: Oleksii Kurochko --- Changes in v3: - Correct the comments in reprogram_timer(). - Move enablement of timer interrupt after sbi_set_timer() to avoid potentially receiving a timer interrupt between these 2 operations. --- Changes in v2: - Add TODO comment above sbi_set_timer() call. - Update the commit message. --- xen/arch/riscv/stubs.c | 5 ----- xen/arch/riscv/time.c | 43 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 43 insertions(+), 5 deletions(-) diff --git a/xen/arch/riscv/stubs.c b/xen/arch/riscv/stubs.c index 1f0add97b361..cb7546558b8e 100644 --- a/xen/arch/riscv/stubs.c +++ b/xen/arch/riscv/stubs.c @@ -21,11 +21,6 @@ nodemask_t __read_mostly node_online_map =3D { { [0] =3D= 1UL } }; =20 /* time.c */ =20 -int reprogram_timer(s_time_t timeout) -{ - BUG_ON("unimplemented"); -} - void send_timer_event(struct vcpu *v) { BUG_ON("unimplemented"); diff --git a/xen/arch/riscv/time.c b/xen/arch/riscv/time.c index 2c7af0a5d63b..7efa76fdbcb1 100644 --- a/xen/arch/riscv/time.c +++ b/xen/arch/riscv/time.c @@ -7,6 +7,9 @@ #include #include =20 +#include +#include + unsigned long __ro_after_init cpu_khz; /* CPU clock frequency in kHz. */ uint64_t __ro_after_init boot_clock_cycles; =20 @@ -40,6 +43,46 @@ static void __init preinit_dt_xen_time(void) cpu_khz =3D rate / 1000; } =20 +int reprogram_timer(s_time_t timeout) +{ + uint64_t deadline, now; + int rc; + + if ( timeout =3D=3D 0 ) + { + /* Disable timer interrupt */ + csr_clear(CSR_SIE, BIT(IRQ_S_TIMER, UL)); + + return 1; + } + + deadline =3D ns_to_ticks(timeout) + boot_clock_cycles; + now =3D get_cycles(); + if ( deadline <=3D now ) + return 0; + + /* + * TODO: When the SSTC extension is supported, it would be preferable = to + * use the supervisor timer registers directly here for better + * performance, since an SBI call and mode switch would no longer + * be required. + * + * This would also reduce reliance on a specific SBI implementat= ion. + * For example, it is not ideal to panic() if sbi_set_timer() re= turns + * a non-zero value. Currently it can return 0 or -ENOSUPP, and + * without SSTC we still need an implementation because only the + * M-mode timer is available, and it can only be programmed in + * M-mode. + */ + if ( (rc =3D sbi_set_timer(deadline)) ) + panic("%s: timer wasn't set because: %d\n", __func__, rc); + + /* Enable timer interrupt */ + csr_set(CSR_SIE, BIT(IRQ_S_TIMER, UL)); + + return 1; +} + void __init preinit_xen_time(void) { if ( acpi_disabled ) --=20 2.52.0 From nobody Tue Feb 10 23:53:55 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1770656267; cv=none; d=zohomail.com; s=zohoarc; b=lGhwmzSVOvBeTyupDnSOtmhknxBahseKTbrEBnoLhpnEvBRggR+zjtPopwUW6OjvqCR8CtUGeOz8qrheDXTGDc0cbMpHm+X7pUeGSkOaglccgcudSa7sYWj3Vy/CgX4OUvkWbdILXxp2d5Jf7y0cNcbEavE9BhdO2BvtoKq+hxg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1770656267; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=imBk95+i3lrNZl16Fz7LHP6T5cVPwdF19P0a+Yv8HIE=; b=GI2MGheUIOM+QE7GzlxFpbfrJ8DIfiqdHIfe3olych8NfW/OWAzXA11ZmJRbpkipsrZpXCpSKc9Fq2BJ1n3KdobA7ctexNlqXW9H+0ZprQE7F9jB56ivVW5B1O4WtWngAOkP8Xf4xLE4pkfwd+kVkCF/SkHKJ7nyF0jNofF62uc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1770656267457511.24376960984966; Mon, 9 Feb 2026 08:57:47 -0800 (PST) Received: from list by lists.xenproject.org with outflank-mailman.1225878.1532516 (Exim 4.92) (envelope-from ) id 1vpUZs-0007TC-LU; Mon, 09 Feb 2026 16:57:36 +0000 Received: by outflank-mailman (output) from mailman id 1225878.1532516; Mon, 09 Feb 2026 16:57:36 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vpUZs-0007T5-IJ; Mon, 09 Feb 2026 16:57:36 +0000 Received: by outflank-mailman (input) for mailman id 1225878; Mon, 09 Feb 2026 16:57:35 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vpUVL-0007Zo-3Y for xen-devel@lists.xenproject.org; Mon, 09 Feb 2026 16:52:55 +0000 Received: from mail-ed1-x532.google.com (mail-ed1-x532.google.com [2a00:1450:4864:20::532]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id c6c7ab38-05d7-11f1-b162-2bf370ae4941; Mon, 09 Feb 2026 17:52:53 +0100 (CET) Received: by mail-ed1-x532.google.com with SMTP id 4fb4d7f45d1cf-65815ec51d3so4896157a12.2 for ; Mon, 09 Feb 2026 08:52:53 -0800 (PST) Received: from fedora (user-109-243-67-101.play-internet.pl. [109.243.67.101]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b8edacf1564sm415776866b.52.2026.02.09.08.52.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Feb 2026 08:52:52 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: c6c7ab38-05d7-11f1-b162-2bf370ae4941 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1770655973; x=1771260773; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=imBk95+i3lrNZl16Fz7LHP6T5cVPwdF19P0a+Yv8HIE=; b=BiCJhWGliJdA44LISFmZOUGXwVeR5m2VhAPwWpOYct+tygrQbhJ40YsW3VQ5ShbhBE 3P8SznbEmhCOIQcQKHHyntnT3DbXG9j5PLi53sG/tEZFp8MrgQpaaHco3ZWPgYvyWrGZ zLqlHygHR88oMjOQYWyfe0qD8O2KDQ7jGV564BwxOzhAH7rqUt0Wo3VGBpupMoyhTVws aVzPztwTlJuP82mzKUGWlrSRNwkmdRrHtzthdo8sSuCcKSZLEIrrO6IQ9zu5Jou4P0ZC JwWXayWhI+TMGfRWDbjFXFGilF7KdEm2HZk1BXDldJOtupsSmJOdKltpG8d35IYd4Xdk V+Ag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1770655973; x=1771260773; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=imBk95+i3lrNZl16Fz7LHP6T5cVPwdF19P0a+Yv8HIE=; b=XQPV4nkgkCmUHlvl5imlSELlKgzNiqqxqcRNl5zMcyyEs/Bs8f3gRjkTgu/TemsDAI JpubQYQSe0uUaRZqqrJ0mG3NIGZMilYDHFOGcxVOrGY4rjJg53YpsR7G2JIZp/sRfsn9 MLfv1RxGRdO8+lV7rqYtEOjxx+AJREUW4JlULTPah3LLBparsXgBnUATKLUDiNzUd30E azvgc7nzfn5BEeifIchSi9kyFqgBNSQnciw4RlQlcThxcJzyoW33q5yF6Fj1on8qJ/3H oOJDCUWG7w2qsdyA3ITj0u2KWvWRV/Bgq1g7fQC+tKVwssJFFF97k5t2K7VaRQDkBrx9 UXGQ== X-Gm-Message-State: AOJu0YwvlAfIWOfmf/UfzXeUyDQSnqCb5UY4qKAGeW4KY8g8zpsFeZ2Z u++9tNY6mYIeODNyeyx8ZD+mYsiJCfPA3IhDSMTJ/1XFD4byO5LOrsEkGIHf06DN X-Gm-Gg: AZuq6aLVFPz2lsPPDbTQdk6eZDiKcrlPfqdk3HPUivL5tnAWNMEXmIJzbAIn44SgqVO c1dJdZxXACtX23R/OIG2DbY405EecEEyBAwH5+qwaSU3PfwRkcHXQxcDVG6H6h58+wFeKogUzYi IWNoRE7Olflf3MWjzI1xjlgOGjRZP0Mko5Fk9wpuZ2uvRofXQOCGyP7OG8KWnu2m3fc5D1/dlzL xFCNoDj5hNGALYTYwqMWQfaU/yga4TwuE4xz0WxnAXZW0UKTepE0dRMSYUatm61ITDWrXSkG1uz 3bAI530CToG7ko2sINPf7Lynj5tXRCNRWn5GkKIOubrkm8UsXLkUtSuxyM0tHlJwsa65qib+NsP Bv48I+AWE2bKbzNq4mMpEXcEouUCblicoSWb3I5QJNKjXgeDBuaDJWWwNAm5Z6dEGkepKWiP64S EFWCEGSBEcRQBbpaH8TyD52P/iR5v0ukO2bZT8qVG/xrfEwd1Pa3rc+Y5hprKUnF0u X-Received: by 2002:a17:907:9449:b0:b88:5ef6:17f9 with SMTP id a640c23a62f3a-b8edf15f695mr675946466b.7.1770655972552; Mon, 09 Feb 2026 08:52:52 -0800 (PST) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Romain Caritey , Oleksii Kurochko , Alistair Francis , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH v3 14/16] xen/riscv: handle hypervisor timer interrupts Date: Mon, 9 Feb 2026 17:52:27 +0100 Message-ID: <4658719da8639b382b122bd79124381235d27aaf.1770650552.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1770656269200154100 Content-Type: text/plain; charset="utf-8" Introduce timer_interrupt() to process IRQ_S_TIMER interrupts. The handler disables further timer interrupts by clearing SIE.STIE and raises TIMER_SOFTIRQ so the generic timer subsystem can perform its processing. Update do_trap() to dispatch IRQ_S_TIMER to this new handler. Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich --- Changes in v3: - add Acked-by: Jan Beulich . --- Changes in v2: - Drop cause argument of timer_interrupt() as it isn't used inside the function and anyway it is pretty clear what is the cause inside timer_interrupt(). --- xen/arch/riscv/traps.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/xen/arch/riscv/traps.c b/xen/arch/riscv/traps.c index 676a2da55811..e8d9ca902d9c 100644 --- a/xen/arch/riscv/traps.c +++ b/xen/arch/riscv/traps.c @@ -10,6 +10,7 @@ #include #include #include +#include =20 #include #include @@ -176,6 +177,15 @@ static void check_for_pcpu_work(void) vcpu_flush_interrupts(current); } =20 +static void timer_interrupt(void) +{ + /* Disable the timer to avoid more interrupts */ + csr_clear(CSR_SIE, BIT(IRQ_S_TIMER, UL)); + + /* Signal the generic timer code to do its work */ + raise_softirq(TIMER_SOFTIRQ); +} + void do_trap(struct cpu_user_regs *cpu_regs) { register_t pc =3D cpu_regs->sepc; @@ -217,6 +227,10 @@ void do_trap(struct cpu_user_regs *cpu_regs) intc_handle_external_irqs(cpu_regs); break; =20 + case IRQ_S_TIMER: + timer_interrupt(); + break; + default: intr_handled =3D false; break; --=20 2.52.0 From nobody Tue Feb 10 23:53:55 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1770656002; cv=none; d=zohomail.com; s=zohoarc; b=ROrBhcMCOPW7ymftxIOdwVPdfR5Ympv8EuK+LswBsraWJWhrW4ZggcTp29xyb2AtcA7bLLMpBVKsiGWCymI610GGP3bX+wYv39f99fQ2XpgSHYlhV90rxxO4zmW4jbitHShAAvpRhNataz7/0eCKI42kwkzqBi7ZP7iVn3SkT4Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1770656002; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=twQjmhb1zGscONCfiElutibwq+HGssUs2R5xhfNZcQQ=; b=StCPOakhqRamObi31Y3fnn0cBZfy49sZ7gAn1FJE7mpW5qvxLxn5L/xVh5t7JHvFeuzLEfVYZnEw1Cw+l1B6WXHGQwJ3LZB1mqeRkhlXLtbcA/QxpkXk0/XypCdTzsfF+Jc15wuFrnL5DVXR/ER7NGekVj+RbsBP7dLLU32Jbpw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1770656002691286.50617997129734; Mon, 9 Feb 2026 08:53:22 -0800 (PST) Received: from list by lists.xenproject.org with outflank-mailman.1225802.1532497 (Exim 4.92) (envelope-from ) id 1vpUVO-0002vM-UD; Mon, 09 Feb 2026 16:52:58 +0000 Received: by outflank-mailman (output) from mailman id 1225802.1532497; Mon, 09 Feb 2026 16:52:58 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vpUVO-0002tp-KE; Mon, 09 Feb 2026 16:52:58 +0000 Received: by outflank-mailman (input) for mailman id 1225802; Mon, 09 Feb 2026 16:52:56 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vpUVM-0007Zd-7g for xen-devel@lists.xenproject.org; Mon, 09 Feb 2026 16:52:56 +0000 Received: from mail-ej1-x62b.google.com (mail-ej1-x62b.google.com [2a00:1450:4864:20::62b]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id c74ddf33-05d7-11f1-9ccf-f158ae23cfc8; Mon, 09 Feb 2026 17:52:54 +0100 (CET) Received: by mail-ej1-x62b.google.com with SMTP id a640c23a62f3a-b86ed375d37so551166166b.3 for ; Mon, 09 Feb 2026 08:52:54 -0800 (PST) Received: from fedora (user-109-243-67-101.play-internet.pl. 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Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich --- Changes in v3: - add Acked-by: Jan Beulich . --- Changes in v2: - Update the commit message. - Move implementation of sync_vcpu_execstate() to separate commit as it doesn't connect to tasklet subsystem. --- xen/arch/riscv/setup.c | 3 +++ xen/arch/riscv/stubs.c | 10 ---------- 2 files changed, 3 insertions(+), 10 deletions(-) diff --git a/xen/arch/riscv/setup.c b/xen/arch/riscv/setup.c index 010489f0b713..0cea1435ff32 100644 --- a/xen/arch/riscv/setup.c +++ b/xen/arch/riscv/setup.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -157,6 +158,8 @@ void __init noreturn start_xen(unsigned long bootcpu_id, panic("Booting using ACPI isn't supported\n"); } =20 + tasklet_subsys_init(); + init_IRQ(); =20 riscv_fill_hwcap(); diff --git a/xen/arch/riscv/stubs.c b/xen/arch/riscv/stubs.c index cb7546558b8e..26434166acc6 100644 --- a/xen/arch/riscv/stubs.c +++ b/xen/arch/riscv/stubs.c @@ -91,16 +91,6 @@ void continue_running(struct vcpu *same) BUG_ON("unimplemented"); } =20 -void sync_local_execstate(void) -{ - BUG_ON("unimplemented"); -} - -void sync_vcpu_execstate(struct vcpu *v) -{ - BUG_ON("unimplemented"); -} - void startup_cpu_idle_loop(void) { BUG_ON("unimplemented"); --=20 2.52.0 From nobody Tue Feb 10 23:53:55 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1770656355; cv=none; d=zohomail.com; s=zohoarc; b=IuLY0ohTItqQGjq35EmcXu77ROCgtXx9ywIYsYoajfPNyXCjmUTRI98uIXXFQSdeevDTcFM7dUL8qvIdBnwhgMDAfnU1OOjVW2Rj2bl/lC90Osjwv0ryAhDmnUi2TuEw0aj4uALchBO1bF1184XACtHTqD1kHjYc4ELJYRODvcE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1770656355; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=HyJML4Sv6DfhXqyacLnIQ1gC+Bl4EUOQWOcTO9rdOdc=; b=CiRvVTL1U3xy4O1c7GemVpnIgn7K+0ecPB0C4D9h9uuywz/KAxjrrl3vLieIKqyYAuFvsybhU8Howft+sidnrcK2LgwLKCWfzp6ycVlKiWtqcuZiaWdQgVKacmZU0BVJMJdx7kgmJJtUJhMo6kFadodBq2wAVd05IiiuZTxEVcg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1770656355649509.84571718975474; Mon, 9 Feb 2026 08:59:15 -0800 (PST) Received: from list by lists.xenproject.org with outflank-mailman.1225910.1532525 (Exim 4.92) (envelope-from ) id 1vpUbB-0000Aj-21; Mon, 09 Feb 2026 16:58:57 +0000 Received: by outflank-mailman (output) from mailman id 1225910.1532525; Mon, 09 Feb 2026 16:58:57 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vpUbA-0000Ac-Vb; Mon, 09 Feb 2026 16:58:56 +0000 Received: by outflank-mailman (input) for mailman id 1225910; Mon, 09 Feb 2026 16:58:55 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vpUVM-0007Zo-Bh for xen-devel@lists.xenproject.org; Mon, 09 Feb 2026 16:52:56 +0000 Received: from mail-ed1-x534.google.com (mail-ed1-x534.google.com [2a00:1450:4864:20::534]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id c801b671-05d7-11f1-b162-2bf370ae4941; Mon, 09 Feb 2026 17:52:55 +0100 (CET) Received: by mail-ed1-x534.google.com with SMTP id 4fb4d7f45d1cf-65808bb859cso6855045a12.2 for ; Mon, 09 Feb 2026 08:52:55 -0800 (PST) Received: from fedora (user-109-243-67-101.play-internet.pl. [109.243.67.101]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b8edacf1564sm415776866b.52.2026.02.09.08.52.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Feb 2026 08:52:54 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: c801b671-05d7-11f1-b162-2bf370ae4941 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1770655975; x=1771260775; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=HyJML4Sv6DfhXqyacLnIQ1gC+Bl4EUOQWOcTO9rdOdc=; b=f+EzXHzvTB6FHiyAY4+Jl2ixgu0bvHz0eloTerMjrqkHoybxObTysCkpnvCBsXTfSx hUxJQ8neBo2lHw3TrkpmMkvwY8NtGQbJ5qAV7AC/hplIA9KHRMzRCblskooj7rjHa9Ae uhei3rDtVw8WGYIetkknlnBbqtxc8EnFJhLQ7tUfLqYjm/PjXyZh0i2Xf3qYVhZYA0PH 7pbNL0968h5C8n85H5bwAKwmFVPm29HTGLJbl2GtyY9JH4JBYV1RJxpEpsG0Y5x9+8MR B00Ph04BR/dKSSKtb+mzI06anrH0ZGqf93krNMFt66IzM1afNvSFrLTv3KW6svvZ5L9e CIkw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1770655975; x=1771260775; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=HyJML4Sv6DfhXqyacLnIQ1gC+Bl4EUOQWOcTO9rdOdc=; b=TbffzPfQN/4vrRWBNPtzqCpQxaVn8JitH/+lvuR2a1B7Lyr2PvkZofsNOnJ3N57s8p 41CVb4vZUo6AuowcOLg/BUHBHkf4AG//W8R+ba3/fJiF8J7Nw/2ZpcYiRfd7krU2SoO8 5qK9Ee4ZKCqUggXULBr949l5sz9xc6S+3Y8o0Yr9w/BRPfTqdeTu3D1wmX898gUTj84J +08o09lrTd5+FxXHZHwAEaEzdTmMTth5CAYrxubhTl39iRJ+OBLLZkPufUfhfxeg1bbE RKyhAuEGeu4f0hwderr0hZSDiT4ZUzEWRk7SxYiushDhWqPwqJeFwdZPIZnhywsUkede TU+g== X-Gm-Message-State: AOJu0YzrGb3wvDfNQm5lrnLaOoJ0LYWwXP9sVggqoWCf+zA36HR7m4OX X+2dHfz3zEjQ4LgAsBpT5PEYHzG6fYHdJA4E44MHbKQGB7i1vfVwWicweTQDKdBD X-Gm-Gg: AZuq6aJ9Y62KokdIu1dXVkLc3JzHI0s/Eg5XHfABmHbYy8ekM7+3HwkuSckZ9TaCaOO l0qW0Yk8bT9nLGm6J86WDTB7BoHzU99oybR0ZY9QwOqH+1l/FeDBvgSVlipeWpzwZj464Ac5L7l iq3RYHXdNuqRCkC67GlrPrrVzmDCE3zXc5ToI6JhM0XAuSjCZQCmVNc6wCYVebyNHczlxC6ceW/ buGmYYkmpp9evLFfNV69NJ36T8rE35oUbdBSjAg80AtTmdhXrPyVfQehJqb6KQBIkxIu+AKw96Y zLRj6VlOzZMWocOVGslliETcYqUnSWkE2VVE7FOgk+fUUQVxRzl1oTApkKBBiQ8PJS8Ec0rURzu 4G7JFhwTXDHijxGc27CUe72IDu7ZESYQz8221T9ibVdUcfmenEsSg9KQWrnu2q7Dyuqp0rwKtZy syC+QpPXCfG8QwAVeOYyFYAPB6lU+roF+0DC88Vq6pcprWmDX6VWexcFc+vw== X-Received: by 2002:a17:906:6a18:b0:b8d:f859:d228 with SMTP id a640c23a62f3a-b8edf1a942amr632341966b.17.1770655974628; Mon, 09 Feb 2026 08:52:54 -0800 (PST) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Romain Caritey , Oleksii Kurochko , Alistair Francis , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH v3 16/16] xen/riscv: implement sync_vcpu_execstate() Date: Mon, 9 Feb 2026 17:52:29 +0100 Message-ID: X-Mailer: git-send-email 2.52.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1770656356529154101 Content-Type: text/plain; charset="utf-8" The scheduler may call this function to force synchronization of given vCPU's state. RISC-V does not support lazy context switching, so nothing is done in sync_vcpu_execstate() and sync_local_execstate(). Signed-off-by: Oleksii Kurochko --- This patch is dependent on patch from ML: [PATCH] sched: move vCPU exec state barriers --- Changes in v3: - Align sync_vcpu_execstate() with patch: [PATCH] sched: move vCPU exec state barriers --- Changes in v2: - New patch. --- xen/arch/riscv/domain.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/xen/arch/riscv/domain.c b/xen/arch/riscv/domain.c index 30a966f53c1d..ecb4ef8d0c89 100644 --- a/xen/arch/riscv/domain.c +++ b/xen/arch/riscv/domain.c @@ -245,3 +245,13 @@ void vcpu_kick(struct vcpu *v) smp_send_event_check_mask(cpumask_of(v->processor)); } } + +void sync_local_execstate(void) +{ + /* Nothing to do -- no lazy switching */ +} + +void sync_vcpu_execstate(struct vcpu *v) +{ + /* Nothing to do -- no lazy switching */ +} --=20 2.52.0