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[109.243.67.101]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-482dbd0f043sm107954345e9.7.2026.02.02.04.58.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Feb 2026 04:58:10 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: d4897cc4-0036-11f1-b161-2bf370ae4941 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1770037091; x=1770641891; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=SCI6k1gY6hOQ2mQg++ELmk05/We6ArMoGY0m7U5btes=; b=eVEIF2XKupOCYe1HF/FW+Ml5yT7nZQg28EDXtYJ4ZXqVIMuQwmrKBjiCiV2NCGjJK/ Jj4cdqRb8694nY2IQV5KTIHuDG7ehBfaAX3Qc8dcRi12y/zVII107HMvqOikkAj4EMp6 ejntekFx3AaTFLeRu1bBno+/xQAxPa7qs3Uav1uOcchlPAP+ybcxc9nX0pR95wUYPx0u oqmkeAusWfZxT/cOpePNSgfSgW+WrockMQTYct5qn+BmPPuLE/jS6UOASpi77O0JN8EK 23kwe95sC/gBOfpy0yR96PbJtSgG0TqqqjTf2i2ixiU0U+LrmXPGnC0NWKcoXMwiXHN2 hsFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1770037091; x=1770641891; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=SCI6k1gY6hOQ2mQg++ELmk05/We6ArMoGY0m7U5btes=; b=ADw+COdCO+Z0iOLzRib+j3/UKMclRB30cCUy0+29xfD/8fhnzg9BZgi6W5DNbbD70e aXf7I1izP3fpuZP3G67kziWvSjhIp0Rs46YFrHSVH7tbQ52TAdw9CJmLTDhUGw2QQpx3 23Y2cVO8g+igN+5EupTFGlreFFWQoXwAGefaQkBkoW30ec4AWxVi370nrGn3FLTQdo1J nUIRPqoN8+0W3AF1MfcmM1hif7E2VT84VBLt7UjS4jHkq3JxMi28+IY5Kbm51zRXIr6q EiUHA3Pmxzkt7PyklN+qsRcYXwpuQPMbKDNTbrgKL6yjvQArBvi6CwiKu1ooh+d815iY RC2g== X-Gm-Message-State: AOJu0YwszNlIvAUwQhspEnZDpbj+fKxw8jTB20WUCewGozKyymUAjSQ5 CFaTmMKVKHrN02wxNvXm4ZKOsxnpDTgT7EWUVzKjz/gmwruxtdcO4bHdUqHPKA== X-Gm-Gg: AZuq6aLzBIm8thjnNuwAT3iXBKddFeGgrEiiG7ALolS23QfxOwK8BlxUWWwv8w9utSz yB1RA8KT/Tb910mZtIh/VwAPYITplH2quM8zOyaQRg9gLgMCHfd9mSSirBZXYLJ7clNZDnfF7h7 edlLq1Av5NHDAuLc2QDeHLVGDGhVcejZC9yo8rckIYqarUHFb2j8sDXwD/cLTLYtWzBl/leJHl4 9R2C3f/GXFIsrovcoOW/1VbDZix8/IzA3F4VfV6m6Ahxd0cudsJSAPwiDeGd3Plbwl0HKp5ZqdU 1mTXz+o90D1v79nfN/sQZpay2sCefhOvlT9WdvGelF60ElWMCzFsA2cd3fzCa3T6f1EQw2jDo1G Rw9EYZgma3OV3RIIu2iSQ5fin4Y1RyKOCbpHvn3eY2sy+j/MOO1NotmIArqRrWqFZRAeNHli328 9GlnslKymE9AkJaU3DIz7l8r/AGm5b9vWCfqd9RJuy/jJDObwvp8wu7g== X-Received: by 2002:a05:600c:1d1b:b0:46e:59bd:f7d3 with SMTP id 5b1f17b1804b1-482db4939d8mr145289775e9.20.1770037091020; Mon, 02 Feb 2026 04:58:11 -0800 (PST) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Romain Caritey , Oleksii Kurochko , Alistair Francis , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH v1 1/3] xen/riscv: introduce struct arch_vcpu Date: Mon, 2 Feb 2026 13:57:57 +0100 Message-ID: <98214488c67fac866ba519c368aef697da2d2bb6.1770036584.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1770037123210154100 Introdce struct arch_vcpu to hold RISC-V vCPU-specific state. The structure contains: - Guest-visible CSR state, used to save and restore vCPU execution state across context switches. hstatus isn't added here as it is already part of cpu_user_regs struct. - Callee-saved registers used to preserve Xen=E2=80=99s own execution con= text when switching between vCPU stacks. It is going to be used in the following way (pseudocode): context_switch(prev_vcpu, next_vcpu): ... /* Switch from previous stack to the next stack. */ __context_switch(prev_vcpu, next_vcpu); ... schedule_tail(prev_vcpu): Save and restore vCPU's CSRs. The Xen-saved context allows __context_switch() to switch execution from the previous vCPU=E2=80=99s stack to the next vCPU=E2=80=99s stack and= later resume execution on the original stack when switching back. During vCPU creation, the Xen-saved context is going to be initialized with: - SP pointing to the newly allocated vCPU stack - RA pointing to a helper that performs final vCPU setup before transferring control to the guest After the first execution of __context_switch(), RA naturally points to the instruction following the call site, and the remaining callee-saved registers contain the Xen register state at the time of the switch. Signed-off-by: Oleksii Kurochko --- Changes in V3: - Drop gp from struct {...} xen_saved_context as it ought to be stable acc= ross Xen so there is no need to be saved/restored and, also, it shouldn't be preserved across calls according to RISC-V ABI. - Update the comment above struct {...} xen_saved_context to make it more clear. - Drop CSRs and VCSRS comments in arch_vcpu as it is clear what kind of CSR it is based on the name. - Drop __cacheline_aligned for struct arch_vcpu as proper measurements can= 't be made now so it is hard to prove that the attribute really boost performance. --- Changes in v2: - Drop hstatus from struct arch_vcpu as it is stored in struct cpu_user_re= gs which will be stored on top of vCPU's stack. - Drop the comment above ra in xen_saved_context struct as it is potential= ly misleading. --- xen/arch/riscv/include/asm/domain.h | 49 +++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/xen/arch/riscv/include/asm/domain.h b/xen/arch/riscv/include/a= sm/domain.h index 316e7c6c8448..cca39effc1ba 100644 --- a/xen/arch/riscv/include/asm/domain.h +++ b/xen/arch/riscv/include/asm/domain.h @@ -24,6 +24,55 @@ struct arch_vcpu_io { =20 struct arch_vcpu { struct vcpu_vmid vmid; + + /* + * Callee saved registers for Xen's state used to switch from + * prev's stack to the next's stack during context switch. + */ + struct + { + register_t s0; + register_t s1; + register_t s2; + register_t s3; + register_t s4; + register_t s5; + register_t s6; + register_t s7; + register_t s8; + register_t s9; + register_t s10; + register_t s11; + register_t sp; + register_t ra; + } xen_saved_context; + + register_t hedeleg; + register_t hideleg; + register_t hvip; + register_t hip; + register_t hie; + register_t hgeie; + register_t henvcfg; + register_t hcounteren; + register_t htimedelta; + register_t htval; + register_t htinst; + register_t hstateen0; +#ifdef CONFIG_RISCV_32 + register_t henvcfgh; + register_t htimedeltah; +#endif + + register_t vsstatus; + register_t vsip; + register_t vsie; + register_t vstvec; + register_t vsscratch; + register_t vscause; + register_t vstval; + register_t vsatp; + register_t vsepc; }; =20 struct paging_domain { --=20 2.52.0 From nobody Sat Feb 7 11:38:16 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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This leverages the RISC-V HFENCE.VVMA instruction, which is used to invalidate translations in the VS-stage of address translation. As for RISC-V binutils >=3D 2.39 is choosen, we can use hfence.vvma mnemoni= cs instead of defining hfence.vvma using .insn. Although it would be possible to use sbi_remote_hfence_vvma() for this purp= ose, it is unnecessary in this context since the flush is required only on the local hart. Using the SBI call would introduce additional overhead without benefit, resulting in unnecessary performance loss. Signed-off-by: Oleksii Kurochko --- xen/arch/riscv/include/asm/flushtlb.h | 7 +++++++ xen/arch/riscv/include/asm/insn-defs.h | 10 ++++++++++ 2 files changed, 17 insertions(+) create mode 100644 xen/arch/riscv/include/asm/insn-defs.h diff --git a/xen/arch/riscv/include/asm/flushtlb.h b/xen/arch/riscv/include= /asm/flushtlb.h index 4f64f9757058..b0112d416dbe 100644 --- a/xen/arch/riscv/include/asm/flushtlb.h +++ b/xen/arch/riscv/include/asm/flushtlb.h @@ -5,6 +5,7 @@ #include #include =20 +#include #include =20 struct page_info; @@ -14,6 +15,12 @@ static inline void local_hfence_gvma_all(void) asm volatile ( "hfence.gvma zero, zero" ::: "memory" ); } =20 +/* Flush VS-stage TLB for current hart. */ +static inline void flush_tlb_guest_local(void) +{ + HFENCE_VVMA(0, 0); +} + /* Flush TLB of local processor for address va. */ static inline void flush_tlb_one_local(vaddr_t va) { diff --git a/xen/arch/riscv/include/asm/insn-defs.h b/xen/arch/riscv/includ= e/asm/insn-defs.h new file mode 100644 index 000000000000..4d50b5e23c11 --- /dev/null +++ b/xen/arch/riscv/include/asm/insn-defs.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef ASM_RISCV_INSN_DEFS_H +#define ASM_RISCV_INSN_DEFS_H + +#define HFENCE_VVMA(vaddr, asid) \ + asm volatile ("hfence.vvma %0, %1" \ + :: "r"(vaddr), "r"(asid) : "memory") + +#endif /* ASM_RISCV_INSN_DEFS_H */ --=20 2.52.0 From nobody Sat Feb 7 11:38:16 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1770037128; cv=none; d=zohomail.com; s=zohoarc; b=LS1NVgWUhYqOiFEoGN/FydlNTF/FBi4Ry0EbPdY2ZqtpafPOY9v1Es8HwI3ipVGH8vA83N16DJOct6YIK7b5XHYmsT3RHdr59FM08e4BiQysI/4dvrmai96Ig+JghA/3pjFYoVSmcnVYd/Xt/BgwWdngXJ6P+ZkyBJ34Ii8l1Xs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1770037128; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=6PCN+JMwSkisOaNF3qhnnL2HUsH6g8JJShv2LCENQeM=; b=DdGcVTSifjse/jUuETDb7fme6OOZK55mRglmTAKzU+9nyVD8DRYAip4ePPLt4weFJl/n2jBFBDVqa4xNY62n/PIBHCEOMuI0w/hDJCFPmBSQVf6rC0Ztc62IFgMfEe/AwIJjUqMPm0LV/Rk5aXlkJh1mTET7w1+x7840OmM/2AQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1770037128947935.3856610559609; Mon, 2 Feb 2026 04:58:48 -0800 (PST) Received: from list by lists.xenproject.org with outflank-mailman.1218572.1527392 (Exim 4.92) (envelope-from ) id 1vmtVR-0005b2-BL; Mon, 02 Feb 2026 12:58:17 +0000 Received: by outflank-mailman (output) from mailman id 1218572.1527392; Mon, 02 Feb 2026 12:58:17 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vmtVR-0005av-8H; Mon, 02 Feb 2026 12:58:17 +0000 Received: by outflank-mailman (input) for mailman id 1218572; Mon, 02 Feb 2026 12:58:15 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vmtVP-0005NS-R4 for xen-devel@lists.xenproject.org; Mon, 02 Feb 2026 12:58:15 +0000 Received: from mail-wm1-x332.google.com (mail-wm1-x332.google.com [2a00:1450:4864:20::332]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id d5b82926-0036-11f1-9ccf-f158ae23cfc8; Mon, 02 Feb 2026 13:58:14 +0100 (CET) Received: by mail-wm1-x332.google.com with SMTP id 5b1f17b1804b1-4806b43beb6so32497125e9.3 for ; Mon, 02 Feb 2026 04:58:14 -0800 (PST) Received: from fedora (user-109-243-67-101.play-internet.pl. [109.243.67.101]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-482dbd0f043sm107954345e9.7.2026.02.02.04.58.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Feb 2026 04:58:12 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: d5b82926-0036-11f1-9ccf-f158ae23cfc8 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1770037093; x=1770641893; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=6PCN+JMwSkisOaNF3qhnnL2HUsH6g8JJShv2LCENQeM=; b=YVlBgNaCVXNtD76XpGKsE6lEJ7z4OUjIrUDUIivzutuW6f/DHJUJ3hMnPf31qB4gpN gkHuB3ykpe+Ycc9gUaj+zg4BF8K2bKzntsGVHMoHxw+5OOGRBZol2VHaEz/1oF1m7alz bCqq2jP4WWVsJzj6h5QYLKI5bJx6dcYm5JluXQDubz0qQ055NMf799lH7vAf2S9r2k/S aSwfmTIn4calC5AUXyMsIuidw5O250md8x5iocUJM659y1x3R3DuQ2l3ip4K1VlqG0sv fPfyHuUoYsQYnqUOgz3n+z/mJVvzi3sJeuaN8cyiRIpuSk97VsdyKy6R+jdDjy3cYq2o Krog== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1770037093; x=1770641893; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=6PCN+JMwSkisOaNF3qhnnL2HUsH6g8JJShv2LCENQeM=; b=uQjBEb9dDuK4mhaZVpn0FTTryVivD6KtzOjEKQG9mcXWsL2TSlhohG3C8B+SQbfp4s ZIIn10p9k5dAnYT3ngfmzVtaJ7f8lQHtvVLB8NrPhIr5TR2p2PWw6Yj0cJ1QAMJRmeNk F6HLsJ3BkuoaDXZssImmhqYaWmpUSOkHAMMakgtt6R8FJQj7zAUvoAiBaERvF+cEzMMi ENALCY+zz/blRIrErXXj9tgsELJXliZqQ6Rw/LepCU8MctRydyubJtwwl7AD11wN5Hdd ByrvPEdkP0uxAmWXSsJEL5Jv6iuMlq6A9eSqK3vgzY+OiW2mcV7OFupbMlrKg3jpoBjl v7wQ== X-Gm-Message-State: AOJu0Yw3/NQ47YT4wxmtvfBqZtNtSK+e4d+n7fpmxbRHuBW7AgdiNa6r Lr7dxOylN7fn5q4vQmK2MB2lbo2P0cyZjQmwMdFOH8YrVb0w+4MdJK9/aN5oIA== X-Gm-Gg: AZuq6aKWE58m0fWF77oANglcQFAC/nVzdigvlE0bW745XT/23JM4OhaJ2E2eFNoOfYk IGCPHtj3HvRc9A5HXr+NrQKvwYrxJZv1/CGqE2pbIou1GUYNRvG0kHs251RY1pRL7LNt4phGTY1 IZzFlRNCqpc7TDTxUKsw35ureDDEo6B8L8z70lpmZLxVzKpPtYafqBVNGq2+Kqqeuf6mchPp/TV baHnCiCGinpGBSZLJ4SKGnhEeKB5wD/81gHYyj70poNGmfs/ZK96FtEc3gr4JupEz7YdKYH797R vHp0roKE+Q+htv9USolQXlzG2NvKjGTFZWWq67ZAh0z60uZ2ePZ+hqmxK/gdclXw9Fucbc4zD5t wcZQo/ovbOrCBCCpW8gbCxqTtRsc2xWUpIBl9Otdv4zYccHW0eQpY0yqt1Ua6E3C9yjqKscgop4 Wdb8C+sIyT7aqn9ZQaetp52/KYNx+XSSRfiY3KXXipyQTQbGV+dSOk3wXe3A== X-Received: by 2002:a05:600c:1549:b0:475:dde5:d91b with SMTP id 5b1f17b1804b1-482db493944mr154293685e9.17.1770037093221; Mon, 02 Feb 2026 04:58:13 -0800 (PST) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Romain Caritey , Oleksii Kurochko , Alistair Francis , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH v1 3/3] xen/riscv: implement p2m_ctx_switch_{to,from}_state() Date: Mon, 2 Feb 2026 13:57:59 +0100 Message-ID: <2e4cd29f19945e90733ac85e023d53cecbe1d14d.1770036584.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1770037130178158500 Introduce functions required to perform a p2m context switch during a vCPU context switch. As no mechanism is provided to atomically change vsatp and hgatp together. Hence, to prevent speculative execution causing one guest=E2=80=99s VS-stage translations to be cached under another guest=E2= =80=99s VMID, world-switch code should zero vsatp in p2m_ctx_swith_from(), then construct new hgatp and write the new vsatp value in p2m_ctx_switch_to(). Signed-off-by: Oleksii Kurochko --- xen/arch/riscv/include/asm/p2m.h | 4 ++ xen/arch/riscv/p2m.c | 81 ++++++++++++++++++++++++++++++++ 2 files changed, 85 insertions(+) diff --git a/xen/arch/riscv/include/asm/p2m.h b/xen/arch/riscv/include/asm/= p2m.h index f63b5dec99b1..1d8c97326565 100644 --- a/xen/arch/riscv/include/asm/p2m.h +++ b/xen/arch/riscv/include/asm/p2m.h @@ -255,6 +255,10 @@ static inline bool p2m_is_locked(const struct p2m_doma= in *p2m) struct page_info *p2m_get_page_from_gfn(struct p2m_domain *p2m, gfn_t gfn, p2m_type_t *t); =20 + +void p2m_ctx_switch_from(struct vcpu *p); +void p2m_ctx_switch_to(struct vcpu *n); + #endif /* ASM__RISCV__P2M_H */ =20 /* diff --git a/xen/arch/riscv/p2m.c b/xen/arch/riscv/p2m.c index 0abeb374c110..af68497c4200 100644 --- a/xen/arch/riscv/p2m.c +++ b/xen/arch/riscv/p2m.c @@ -1434,3 +1434,84 @@ struct page_info *p2m_get_page_from_gfn(struct p2m_d= omain *p2m, gfn_t gfn, =20 return get_page(page, p2m->domain) ? page : NULL; } + +void p2m_ctx_switch_from(struct vcpu *p) +{ + /* + * No mechanism is provided to atomically change vsatp and hgatp + * together. Hence, to prevent speculative execution causing one + * guest=E2=80=99s VS-stage translations to be cached under another gu= est=E2=80=99s + * VMID, world-switch code should zero vsatp, then swap hgatp, then + * finally write the new vsatp value. + */ + p->arch.vsatp =3D csr_read(CSR_VSATP); + csr_write(CSR_VSATP, 0); + + /* + * No need for VS-stage TLB flush here: + * Changing satp.MODE from Bare to other modes and vice versa also + * takes effect immediately, without the need to execute an + * SFENCE.VMA instruction. + * Note that VSATP is just VS-mode=E2=80=99s version of SATP, so the m= entioned + * above should be true for VSATP. + */ + + /* + * Nothing to do with HGATP as it is constructed each time when + * p2m_ctx_switch_to() is called. + */ +} + +void p2m_ctx_switch_to(struct vcpu *n) +{ + struct vcpu_vmid *p_vmid =3D &n->arch.vmid; + uint16_t old_vmid, new_vmid; + bool need_flush; + + if ( is_idle_vcpu(n) ) + return; + + old_vmid =3D p_vmid->vmid; + need_flush =3D vmid_handle_vmenter(p_vmid); + new_vmid =3D p_vmid->vmid; + +#ifdef P2M_DEBUG + printk(XENLOG_INFO, "%pv: oldvmid(%d) new_vmid(%d), need_flush(%d)\n", + n, old_vmid, new_vmid, need_flush); +#endif + + csr_write(CSR_HGATP, construct_hgatp(p2m_get_hostp2m(current->domain), + new_vmid)); + + if ( unlikely(need_flush) ) + local_hfence_gvma_all(); + + /* + * According to the RISC-V specification, speculation can happen + * during an update of hgatp and vsatp: + * No mechanism is provided to atomically change vsatp and hgatp + * together. Hence, to prevent speculative execution causing one + * guest=E2=80=99s VS-stage translations to be cached under another = guest=E2=80=99s + * VMID, world-switch code should zero vsatp, then swap hgatp, then + * finally write the new vsatp value. Similarly, if henvcfg.PBMTE + * need be world-switched, it should be switched after zeroing vsatp + * but before writing the new vsatp value, obviating the need to + * execute an HFENCE.VVMA instruction. + * So just flush TLBs for VS-Stage and G-stage after both of regs are + * touched. + */ + flush_tlb_guest_local(); + + /* + * The vsatp register is a VSXLEN-bit read/write register that is + * VS-mode=E2=80=99s version of supervisor register satp, so the follo= wing is + * true for VSATP registers: + * Changing satp.MODE from Bare to other modes and vice versa also ta= kes + * effect immediately, without the need to execute an SFENCE.VMA + * instruction. Likewise, changes to satp.ASID take effect immediatel= y. + * Considering the mentioned above and that VS-stage TLB flush has been + * already done there is no need to flush VS-stage TLB after an update + * of VSATP from Bare mode to what is written in `n->arch.vsatp`. + */ + csr_write(CSR_VSATP, n->arch.vsatp); +} --=20 2.52.0