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[109.243.67.101]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b879513e951sm1686014966b.7.2026.01.22.08.47.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Jan 2026 08:47:40 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 1194e987-f7b2-11f0-b15e-2bf370ae4941 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1769100461; x=1769705261; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=tIURivnVVNz+Sg90MgEK4c9c+A2jqXCTv9hUdU686As=; b=WQhqzsRpWji3kJNWGbP3Rhp1SgAbH4gHXfNhHHofUvRtZPvI1zdSXBroVAFNq8W31Q PxQ/irR7Yy24poddgqj2VeWl0nZ/HKLHhGfMj+WHP1vII7bxHLfnP9kVnb49KweLLDas COIz+i15MNruyRkiyFmE5WAfPyXozxPFZle9tFH0SkOMi1GfHaDAp5IP/MWPaOHoNTAD Wf6ZtwDWck9yy0n4vJtxDsYNd7elaQ1XHeMPb6KoOH7MoJrrrnVX2PfQ6K7BbD824Omy uOUFc3Xw3RTfsXI5/Hx17VE812u1NxhWzSFlPJDfRwS6nZ/TXnIDmWrY9wOWa3L66OUZ xwDA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769100461; x=1769705261; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=tIURivnVVNz+Sg90MgEK4c9c+A2jqXCTv9hUdU686As=; b=sx9m6J93ggmO7CMyfMJTb4zoCAFN0EYOsZwioqY7wX6xKT8E5kLFRlO/GLNgmJ0lf8 mkPWHn11bpki6iD0hlOHzL4MLDCjy9+6a51RxmlmZdkWMs7ixuNmcu1cOQVIhJWOBV2c Ng+SB1Hud+r17Xm7/NBgFaN7VTzUHcFA/aLI2PMmX+P6T5oX360SjcHGSkXM1Lu3qJCa ZGDdDSznLGQ2iU2OzSQn+B+4hHmunptejn4jkG5sHAwWVWVn97z67utwWYyhOBxyfCXS CDh9UGFkUCQ6hv5cW+MqOIXA0Bf8hKijSHflZs/UgcU5NXRuJvZRj5/HBkB6uWd9Ae/p FFWw== X-Gm-Message-State: AOJu0YwsAkESGxsS/KjenWwCHM0bZYskbGN7FKNhA3PY/rKZxS8rHlIE L4mYrVcPpR1VvQWq4f+wAzJAluXdB5+tmmgtGTLis/0gsgCT7Dgh9Cd1lmui2g== X-Gm-Gg: AZuq6aI6rbwsaQiXB3mJipuJPCvLKPXjnxUXcXXwzESIvGOb5lLQ+nFXAEYcTzpe8bT E+MSQYd0niVilNgLzeTLdgJmQ2PD6HuinHOsS53iRYuVSPJ9bZjvPjKJGVJRUgGfeC4eUts9hEQ n9doz0s37Bw/dB0nO0c10tzt65oUCzbTw99GzCmf4fJcpawfERU9yu+QU9C1/8CMEdS5itCeoGO rATDzSf8xhmn4nr/7J1u1if1DsGIZQfkE4Iugb0FVDrfTMnQqZSCfLVrLFyuO36sRGXeAlqnHxZ r2WyvIN8t+TrCryIiFZDtBGUHMW+WuVbV7KeYu5KG/NczfqF6PShV8eVkiFwIMSZ62XwOYhuL6z gzrGeHpkaHZUvF6kT1atGNWDAP+QPwPi/2W929+jnwPhjGhozSSpjNiqJOHuwvlJ/aVYshkiM/H zOE5Aqm7BXn2Q6PvGqDaQUleWq5mFF4cA2VQgaVFCniH+2Ja98HZ/h9A== X-Received: by 2002:a17:907:7251:b0:b79:eba9:83b4 with SMTP id a640c23a62f3a-b885a262ce4mr3468666b.6.1769100461100; Thu, 22 Jan 2026 08:47:41 -0800 (PST) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Alistair Francis , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini , Romain Caritey Subject: [PATCH v2 01/16] xen/riscv: introduce struct arch_vcpu Date: Thu, 22 Jan 2026 17:47:16 +0100 Message-ID: X-Mailer: git-send-email 2.52.0 In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1769100491412154100 Introdce struct arch_vcpu to hold RISC-V vCPU-specific state. The structure contains: - Guest-visible CSR state, used to save and restore vCPU execution state across context switches. hstatus isn't added here as it is already part of cpu_user_regs struct. - Callee-saved registers used to preserve Xen=E2=80=99s own execution con= text when switching between vCPU stacks. It is going to be used in the following way (pseudocode): context_switch(prev_vcpu, next_vcpu): ... /* Switch from previous stack to the next stack. */ __context_switch(prev_vcpu, next_vcpu); ... schedule_tail(prev_vcpu): Save and restore vCPU's CSRs. The Xen-saved context allows __context_switch() to switch execution from the previous vCPU=E2=80=99s stack to the next vCPU=E2=80=99s stack and= later resume execution on the original stack when switching back. During vCPU creation, the Xen-saved context is going to be initialized with: - SP pointing to the newly allocated vCPU stack - RA pointing to a helper that performs final vCPU setup before transferring control to the guest After the first execution of __context_switch(), RA naturally points to the instruction following the call site, and the remaining callee-saved registers contain the Xen register state at the time of the switch. Signed-off-by: Oleksii Kurochko --- Changes in v2: - Drop hstatus from struct arch_vcpu as it is stored in struct cpu_user_re= gs which will be stored on top of vCPU's stack. - Drop the comment above ra in xen_saved_context struct as it is potential= ly misleading. --- xen/arch/riscv/include/asm/domain.h | 57 ++++++++++++++++++++++++++++- 1 file changed, 55 insertions(+), 2 deletions(-) diff --git a/xen/arch/riscv/include/asm/domain.h b/xen/arch/riscv/include/a= sm/domain.h index 316e7c6c8448..0d9b4c4b525e 100644 --- a/xen/arch/riscv/include/asm/domain.h +++ b/xen/arch/riscv/include/asm/domain.h @@ -22,9 +22,62 @@ struct hvm_domain struct arch_vcpu_io { }; =20 -struct arch_vcpu { +struct arch_vcpu +{ struct vcpu_vmid vmid; -}; + + /* + * Callee saved registers for Xen's state deep in the callframe used to + * switch from prev's stack to the next's stack during context switch. + */ + struct + { + register_t s0; + register_t s1; + register_t s2; + register_t s3; + register_t s4; + register_t s5; + register_t s6; + register_t s7; + register_t s8; + register_t s9; + register_t s10; + register_t s11; + register_t sp; + register_t gp; + register_t ra; + } xen_saved_context; + + /* CSRs */ + register_t hedeleg; + register_t hideleg; + register_t hvip; + register_t hip; + register_t hie; + register_t hgeie; + register_t henvcfg; + register_t hcounteren; + register_t htimedelta; + register_t htval; + register_t htinst; + register_t hstateen0; +#ifdef CONFIG_RISCV_32 + register_t henvcfgh; + register_t htimedeltah; +#endif + + /* VCSRs */ + register_t vsstatus; + register_t vsip; + register_t vsie; + register_t vstvec; + register_t vsscratch; + register_t vscause; + register_t vstval; + register_t vsatp; + register_t vsepc; +} __cacheline_aligned; =20 struct paging_domain { spinlock_t lock; --=20 2.52.0 From nobody Mon Jan 26 07:39:22 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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[109.243.67.101]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b879513e951sm1686014966b.7.2026.01.22.08.47.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Jan 2026 08:47:41 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 123f9bb3-f7b2-11f0-9ccf-f158ae23cfc8 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1769100462; x=1769705262; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Xs+SAk+ck32r+yVPkjsZQLd/gIzJLULQhlXaIyvjgE4=; b=irLUHRdrFHl4hUrYUNLBQvgcZvUHl/W6AhVMuC+92akbisiP7xieXVhHbHPqbGAopM 0XK9bCgoIZq0PRT4o5xchKmCKQXXwwTN8Pu7YhjtnD9c85D47LDPtZ+SB/E5n1LXSG8E /LLcpPwvw7pVp8NfNM91VM/TCYrCqyJt34+aN0AxJcOcmklEqDzho6rm27nVYfDsN3qg 3Cqt8/2z24elMWbi+1F4lyQFi1g65Uf8JtD+seRZBQ1CaglqBkV+ntSbfVD9CCsyctk5 NGwLapD54aGL21E6bPkfH9XnJOEfmnNdSOtu9uq3hWB0vYPBV4vinxHGzpc/8w6oeXQu 6R0A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769100462; x=1769705262; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=Xs+SAk+ck32r+yVPkjsZQLd/gIzJLULQhlXaIyvjgE4=; b=dtIJVq21uX872/HMxE9g+UMMcB/NHVgWxZ+EPai7+74Vm89EIFULXxVrFuVZBgaRHc Gr4jMAXFsLniLycSJHgcXZJpCEKgVDwLX7alRCExl/+Qc8yn73p6v6OGfNo4HlYaj+dK a99RlOeT619dGas4Yvd1y7NIvLmTKQpDGxgKRjxrzzONZLcEhQ2SqcD/z6jQXKa6TjMe Bxj9K3YbbXbxv2OAGTqIC65LEINSqrkH53YXHqSpd0BqXgO6+sFQOaPSpCxPtB3ZzDCS Z/3C78fuBmAhZuZsnfmA16Zm4xh9vMYlRiKJJWbsiPoJcc6c4fMUTQFC8ZgVIXIVysFG SefA== X-Gm-Message-State: AOJu0YzJGNthqEhoOd230vNQzaXw4VLVMqTSHL+Vzr5VYD2Rggp/dUmD SPHqaoWf7e4/uFeYVbBmqJ5alyBmj0IzsvclibRU+1IxgyLZWnnEObWXmJzMEw== X-Gm-Gg: AZuq6aLag382gogFX7hOA+u1MfDAKPmqsBXczLow8HmUTilL42uMMgxzNKNJ/bnEY1/ xFdyu/DVab6UNOiA1PwvkKE0btcxhCrHdn22vAQUXuYiSnBwgPCoNu9bwmuKdtXDoAk3+r1++VW okTwYJeTbBWsifDVDLsL8tHvv5qQ8RXn9hdQwypoHpvzR97TpFKzKjDe0/mrenS3q1VcSRQLCSF ayzoxrzPevc+81oO4Q+Mbc+7iIhCvnOhOInt2CGm7mq+7HjxYHyX3tqwONyqVFxBNPd8XPMMKcq b/R8WlHhlB6TJmzDN+OOOd2O8PbJKGXzyxLIvx3Goq6Okuq8lLWvjJOgower/xFIWhnpBbzsM4T i6pnoJzQ/O8mPbBBO2MBC1yACXPgoH9DovftnLnQ9bMApjXeSm4o1Hf4cCNxqvMYLLUm62Oaljx kUPuHGYahtDL8dzok9imAaJfBJJDa553anUP3ngs3QSK1mgGSAr88hkA== X-Received: by 2002:a17:907:26c8:b0:b7c:e320:5228 with SMTP id a640c23a62f3a-b8792e0e967mr1833140566b.22.1769100462166; Thu, 22 Jan 2026 08:47:42 -0800 (PST) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Alistair Francis , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini , Romain Caritey Subject: [PATCH v2 02/16] xen/riscv: implement arch_vcpu_{create,destroy}() Date: Thu, 22 Jan 2026 17:47:17 +0100 Message-ID: <08b582179ebc4241140000972d89209c84c90fa4.1769099885.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1769100488441158500 Content-Type: text/plain; charset="utf-8" Introduce architecture-specific functions to create and destroy VCPUs. Note that arch_vcpu_create() currently returns -EOPNOTSUPP, as the virtual timer and interrupt controller are not yet implemented. As part of this change, add continue_new_vcpu(), which will be used after the first context_switch() of a new vCPU. Since this functionality is not yet implemented, continue_new_vcpu() is currently provided as a stub. Update the STACK_SIZE definition and introduce STACK_ORDER (to align with other architectures) for allocating the vCPU stack. Introduce struct cpu_info to store per-vCPU state that lives at the top of the vCPU's stack. Signed-off-by: Oleksii Kurochko --- Changes in v2: - Drop BUILD_BUG_ON() in arch_vcpu_create() as a check isn't very useful. - Use vzalloc() instead of alloc_xenheap_page() to use the larger domheap = to allocate vCPU's stack. - Drop printk() inside arch_vcpu_create() to not have potential big noise in console as it could be that an amount of vCPUs is pretty big. - Use XVFREE() instead of free_xenheap_pages() as vCPU's stack allocation happens with a usage of vzalloc() now. - Drop stack field as it is enough to have only cpu_info as stack pointer could be calculated based on cpu_info. - Drop cast when v.arch.cpu_info is inialized as it is not necessary to have it. - Drop memset() for arch.cpu_info() as it is enough to have vzalloc(). --- xen/arch/riscv/Makefile | 1 + xen/arch/riscv/domain.c | 59 ++++++++++++++++++++++++++++ xen/arch/riscv/include/asm/config.h | 3 +- xen/arch/riscv/include/asm/current.h | 6 +++ xen/arch/riscv/include/asm/domain.h | 2 + xen/arch/riscv/stubs.c | 10 ----- 6 files changed, 70 insertions(+), 11 deletions(-) create mode 100644 xen/arch/riscv/domain.c diff --git a/xen/arch/riscv/Makefile b/xen/arch/riscv/Makefile index 87c1148b0010..8863d4b15605 100644 --- a/xen/arch/riscv/Makefile +++ b/xen/arch/riscv/Makefile @@ -1,5 +1,6 @@ obj-y +=3D aplic.o obj-y +=3D cpufeature.o +obj-y +=3D domain.o obj-$(CONFIG_EARLY_PRINTK) +=3D early_printk.o obj-y +=3D entry.o obj-y +=3D imsic.o diff --git a/xen/arch/riscv/domain.c b/xen/arch/riscv/domain.c new file mode 100644 index 000000000000..9c546267881b --- /dev/null +++ b/xen/arch/riscv/domain.c @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +static void continue_new_vcpu(struct vcpu *prev) +{ + BUG_ON("unimplemented\n"); +} + +static void __init __maybe_unused build_assertions(void) +{ + /* + * Enforce the requirement documented in struct cpu_info that + * guest_cpu_user_regs must be the first field. + */ + BUILD_BUG_ON(offsetof(struct cpu_info, guest_cpu_user_regs) !=3D 0); +} + +int arch_vcpu_create(struct vcpu *v) +{ + int rc =3D 0; + void *stack =3D vzalloc(STACK_SIZE); + + if ( !stack ) + return -ENOMEM; + + v->arch.cpu_info =3D stack + STACK_SIZE - sizeof(struct cpu_info); + memset(v->arch.cpu_info, 0, sizeof(*v->arch.cpu_info)); + + v->arch.xen_saved_context.sp =3D (register_t)v->arch.cpu_info; + v->arch.xen_saved_context.ra =3D (register_t)continue_new_vcpu; + + /* Idle VCPUs don't need the rest of this setup */ + if ( is_idle_vcpu(v) ) + return rc; + + /* + * As the vtimer and interrupt controller (IC) are not yet implemented, + * return an error. + * + * TODO: Drop this once the vtimer and IC are implemented. + */ + rc =3D -EOPNOTSUPP; + goto fail; + + return rc; + + fail: + arch_vcpu_destroy(v); + return rc; +} + +void arch_vcpu_destroy(struct vcpu *v) +{ + vfree((char *)v->arch.cpu_info + sizeof(struct cpu_info)); +} diff --git a/xen/arch/riscv/include/asm/config.h b/xen/arch/riscv/include/a= sm/config.h index 1e08d3bf78be..86a95df018b5 100644 --- a/xen/arch/riscv/include/asm/config.h +++ b/xen/arch/riscv/include/asm/config.h @@ -143,7 +143,8 @@ =20 #define SMP_CACHE_BYTES (1 << 6) =20 -#define STACK_SIZE PAGE_SIZE +#define STACK_ORDER 3 +#define STACK_SIZE (PAGE_SIZE << STACK_ORDER) =20 #define IDENT_AREA_SIZE 64 =20 diff --git a/xen/arch/riscv/include/asm/current.h b/xen/arch/riscv/include/= asm/current.h index 0c3ea70c2ec8..58c9f1506b7c 100644 --- a/xen/arch/riscv/include/asm/current.h +++ b/xen/arch/riscv/include/asm/current.h @@ -21,6 +21,12 @@ struct pcpu_info { /* tp points to one of these */ extern struct pcpu_info pcpu_info[NR_CPUS]; =20 +/* Per-VCPU state that lives at the top of the stack */ +struct cpu_info { + /* This should be the first member. */ + struct cpu_user_regs guest_cpu_user_regs; +}; + #define set_processor_id(id) do { \ tp->processor_id =3D (id); \ } while (0) diff --git a/xen/arch/riscv/include/asm/domain.h b/xen/arch/riscv/include/a= sm/domain.h index 0d9b4c4b525e..ec7786c76199 100644 --- a/xen/arch/riscv/include/asm/domain.h +++ b/xen/arch/riscv/include/asm/domain.h @@ -49,6 +49,8 @@ struct arch_vcpu register_t ra; } xen_saved_context; =20 + struct cpu_info *cpu_info; + /* CSRs */ register_t hedeleg; register_t hideleg; diff --git a/xen/arch/riscv/stubs.c b/xen/arch/riscv/stubs.c index 29bdb65afbdf..9e30a9a3b50b 100644 --- a/xen/arch/riscv/stubs.c +++ b/xen/arch/riscv/stubs.c @@ -121,16 +121,6 @@ void dump_pageframe_info(struct domain *d) BUG_ON("unimplemented"); } =20 -int arch_vcpu_create(struct vcpu *v) -{ - BUG_ON("unimplemented"); -} - -void arch_vcpu_destroy(struct vcpu *v) -{ - BUG_ON("unimplemented"); -} - void vcpu_switch_to_aarch64_mode(struct vcpu *v) { BUG_ON("unimplemented"); --=20 2.52.0 From nobody Mon Jan 26 07:39:22 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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[109.243.67.101]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b879513e951sm1686014966b.7.2026.01.22.08.47.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Jan 2026 08:47:42 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 12e17298-f7b2-11f0-b15e-2bf370ae4941 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1769100463; x=1769705263; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=6yeF8Jc7Y0UzeLgMob1T0cLJ1Uc8AiT2zOW9g8mOyGs=; b=dzhzdsGsNLUKHpBU1UeScuv5wScuBRKU41tApu0ec6Ko407QhGrku7BMwOcOTMVW82 mou3M9EPJIJchXivtYowS/iQA0+2HlsJ2JnNlfwEpPybLDHJimQy35bNdcVwCBBqiI+y lfEm7oonjgtr+cF96EG5QAR1KJlSAo9dcFyBpH2347BKpJuSv4UUGUOg7oFwFRB1jOYd b3U9XSuTCsXKfc7sgq3jUVDFGE2UNAjysRFU4m/na5rLyL8Fs7/ArE9OoeKEwTmmozCu 1Tr4PSIaYVbeDQWGs1kCx1hUc4seq4hkiTBFtYUHwpFtRzO7nuf+D0otCDNwWUsytFrN VZeA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769100463; x=1769705263; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=6yeF8Jc7Y0UzeLgMob1T0cLJ1Uc8AiT2zOW9g8mOyGs=; b=WY5fya9N7r/5XHy2AFxGHWjmncvj0nPZvhiqZL9HVjxHnQLof7k/2r53ZtnpQj9XOp 8GmPieC7dvMXkNqXDB/UM8fe2Kjzs6YxCrBNTTqsBjV9OJLJiPsxPChDSOFwibMrghFS 9Ki7wyimUpBdv1vvOJoBHWcIJ/CEArtsoWURWKGcrUYywhocSxXvlUrzLl7vedHlx/Hr xX4OWcY9WeOnBbpx78bxYvJgleydJFRLT/naZrKWKDjsh96RWMeplOMZc3tZvajQtkVW 3e3LrA4nXh8vw9BMm5O8jPntFmBbRK4Zi8yI+fRGbShLoPmsspKFlYS1qNgJ6Tg49jV+ svlA== X-Gm-Message-State: AOJu0YzYDl3k7LDpSrPNcGSF23TMZzKJOWknRlbJGlPWcK51wMfMsSXa LojmIOdLGNIqwjsEoDsdDr7FQAy+DSr+kWrtNz4cX5xQFBSSPQIn7lY4tuSTvA== X-Gm-Gg: AZuq6aJsIpbUBvfNeU0MUKKCtKBd093hpPJdUJCrL/zbpiGQZ/J0lLpgSDwbERmVXns sJkwO9UjWzY0vzh5ozRo5hkA3p+DmgNRwCws1RYUgSkUwcAec7sn15ULbr6/u5t8Q1dgYTHc0bj XdckiET5x34xgu8Jz8n3s9yBmTwIfUPyUpRxweftoAaYm7PvTLG/AI8ZCJ5LdJheGdWFQufDaAV eyOU2C1eMSYqK6k8ibYuzXZv2FvCeI1CgU0sfIUs/m7pustwOymx4mHClKPOXWAhtERawDGABTr 5ZGfQtBXwb+d1m8MntvQL8nnahpnoTx4Hv3ujCY+T1MAoumwQjTu825i+s5beOSXfn88CLESk/t GXUJmQoaRNSAf4ipJZemOUDPVF5rb3ucBS/Q+nSFQSBFjn1V6N/IyKiSJRCG5CcFFdpkGq9T0AZ RCXYz3Ve0Genk2iLW8eQnkSIe86BVDSCG8YYC0lSJ4+ptVypq4uEZ1Xw== X-Received: by 2002:a17:907:1ca9:b0:b87:35fc:ae5f with SMTP id a640c23a62f3a-b87930381c7mr2000586266b.52.1769100463285; Thu, 22 Jan 2026 08:47:43 -0800 (PST) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Alistair Francis , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini , Romain Caritey Subject: [PATCH v2 03/16] xen/riscv: implement vcpu_csr_init() Date: Thu, 22 Jan 2026 17:47:18 +0100 Message-ID: <57ef3bcff854d4b50641641d300b3e8aa715c3c3.1769099885.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1769100495532154100 Content-Type: text/plain; charset="utf-8" Introduce vcpu_csr_init() to set up the initial hypervisor-visible CSR state for a vCPU before it is first scheduled. The function configures trap and interrupt delegation to VS-mode by setting the appropriate bits in the hedeleg and hideleg registers, initializes hstatus so that execution enters VS-mode when control is passed to the guest, and restricts guest access to hardware performance counters by initializing hcounteren, as unrestricted access would require additional handling in Xen. When the Smstateen and SSAIA extensions are available, access to AIA CSRs and IMSIC guest interrupt files is enabled by setting the corresponding bits in hstateen0, avoiding unnecessary traps into Xen (note that SVSLCT(Supervisor Virtual Select) name is used intead of CSRIND as OpenSBI uses such name and riscv_encoding.h is mostly based on it). If the Svpbmt extension is supported, the PBMTE bit is set in henvcfg to allow its use for VS-stage address translation. Guest access to the ENVCFG CSR is also enabled by setting ENVCFG bit in hstateen0, as a guest may need to control certain characteristics of the U-mode (VU-mode when V=3D1) execution environment. For CSRs that may contain read-only bits (e.g. hedeleg, hideleg, hstateen0), the written value is re-read from hardware and cached in vcpu->arch to avoid divergence between the software state and the actual CSR contents. As hstatus is not part of struct arch_vcpu (it already resides in struct cpu_user_regs), introduce vcpu_guest_cpu_user_regs() to provide a uniform way to access hstatus and other guest CPU user registers. This establishes a consistent and well-defined initial CSR state for vCPUs prior to their first context switch. Signed-off-by: Oleksii Kurochko --- Changes in v2: - As hstatus isn't a part of arch_vcpu structure (as it is already a part = of cpu_user_regs) introduce vcpu_guest_cpu_user_regs() to be able to access hstatus and other CPU user regs. - Sort hideleg bit setting by value. Drop a stray blank. - Drop | when the first initialization of hcounteren and hennvcfg happen. - Introduce HEDELEG_DEFAULT. Sort set bits by value and use BIT() macros instead of open-coding it. - Apply pattern csr_write() -> csr_read() for hedeleg and hideleg instead of direct bit setting in v->arch.h{i,e}deleg as it could be that for some reason some bits of hedeleg and hideleg are r/o. The similar patter is used for hstateen0 as some of the bits could be r/= o. - Add check that SSAIA is avaialable before setting of SMSTATEEN0_AIA | SMSTATEEN0_IMSIC | SMSTATEEN0_SVSLCT bits. - Drop local variables hstatus, hideleg and hedeleg as they aren't used anymore. --- xen/arch/riscv/cpufeature.c | 1 + xen/arch/riscv/domain.c | 73 +++++++++++++++++++++ xen/arch/riscv/include/asm/cpufeature.h | 1 + xen/arch/riscv/include/asm/current.h | 2 + xen/arch/riscv/include/asm/riscv_encoding.h | 2 + 5 files changed, 79 insertions(+) diff --git a/xen/arch/riscv/cpufeature.c b/xen/arch/riscv/cpufeature.c index 02b68aeaa49f..03e27b037be0 100644 --- a/xen/arch/riscv/cpufeature.c +++ b/xen/arch/riscv/cpufeature.c @@ -137,6 +137,7 @@ const struct riscv_isa_ext_data __initconst riscv_isa_e= xt[] =3D { RISCV_ISA_EXT_DATA(zbb), RISCV_ISA_EXT_DATA(zbs), RISCV_ISA_EXT_DATA(smaia), + RISCV_ISA_EXT_DATA(smstateen), RISCV_ISA_EXT_DATA(ssaia), RISCV_ISA_EXT_DATA(svade), RISCV_ISA_EXT_DATA(svpbmt), diff --git a/xen/arch/riscv/domain.c b/xen/arch/riscv/domain.c index 9c546267881b..3ae5fa3a8805 100644 --- a/xen/arch/riscv/domain.c +++ b/xen/arch/riscv/domain.c @@ -5,6 +5,77 @@ #include #include =20 +#include +#include +#include + +#define HEDELEG_DEFAULT (BIT(CAUSE_MISALIGNED_FETCH, U) | \ + BIT(CAUSE_FETCH_ACCESS, U) | \ + BIT(CAUSE_ILLEGAL_INSTRUCTION, U) | \ + BIT(CAUSE_BREAKPOINT, U) | \ + BIT(CAUSE_MISALIGNED_LOAD, U) | \ + BIT(CAUSE_LOAD_ACCESS, U) | \ + BIT(CAUSE_MISALIGNED_STORE, U) | \ + BIT(CAUSE_STORE_ACCESS, U) | \ + BIT(CAUSE_USER_ECALL, U) | \ + BIT(CAUSE_FETCH_PAGE_FAULT, U) | \ + BIT(CAUSE_LOAD_PAGE_FAULT, U) | \ + BIT(CAUSE_STORE_PAGE_FAULT, U)) + +#define HIDELEG_DEFAULT (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP) + +static void vcpu_csr_init(struct vcpu *v) +{ + register_t hstateen0; + + csr_write(CSR_HEDELEG, HEDELEG_DEFAULT); + v->arch.hedeleg =3D csr_read(CSR_HEDELEG); + + vcpu_guest_cpu_user_regs(v)->hstatus =3D HSTATUS_SPV | HSTATUS_SPVP; + + csr_write(CSR_HIDELEG, HIDELEG_DEFAULT); + v->arch.hideleg =3D csr_read(CSR_HIDELEG); + + /* + * VS should access only the time counter directly. + * Everything else should trap. + */ + v->arch.hcounteren =3D HCOUNTEREN_TM; + + if ( riscv_isa_extension_available(NULL, RISCV_ISA_EXT_svpbmt) ) + { + csr_write(CSR_HENVCFG, ENVCFG_PBMTE); + v->arch.henvcfg =3D csr_read(CSR_HENVCFG); + } + + if ( riscv_isa_extension_available(NULL, RISCV_ISA_EXT_smstateen) ) + { + if (riscv_isa_extension_available(NULL, RISCV_ISA_EXT_ssaia)) + /* + * If the hypervisor extension is implemented, the same three + * bitsare defined also in hypervisor CSR hstateen0 but concern + * only the state potentially accessible to a virtual machine + * executing in privilege modes VS and VU: + * bit 60 CSRs siselect and sireg (really vsiselect and + * vsireg) + * bit 59 CSRs siph and sieh (RV32 only) and stopi (really + * vsiph, vsieh, and vstopi) + * bit 58 all state of IMSIC guest interrupt files, inclu= ding + * CSR stopei (really vstopei) + * If one of these bits is zero in hstateen0, and the same bit= is + * one in mstateen0, then an attempt to access the correspondi= ng + * state from VS or VU-mode raises a virtual instruction excep= tion. + */ + hstateen0 =3D SMSTATEEN0_AIA | SMSTATEEN0_IMSIC | SMSTATEEN0_S= VSLCT; + + /* Allow guest to access CSR_ENVCFG */ + hstateen0 |=3D SMSTATEEN0_HSENVCFG; + + csr_write(CSR_HSTATEEN0, hstateen0); + v->arch.hstateen0 =3D csr_read(CSR_HSTATEEN0); + } +} + static void continue_new_vcpu(struct vcpu *prev) { BUG_ON("unimplemented\n"); @@ -33,6 +104,8 @@ int arch_vcpu_create(struct vcpu *v) v->arch.xen_saved_context.sp =3D (register_t)v->arch.cpu_info; v->arch.xen_saved_context.ra =3D (register_t)continue_new_vcpu; =20 + vcpu_csr_init(v); + /* Idle VCPUs don't need the rest of this setup */ if ( is_idle_vcpu(v) ) return rc; diff --git a/xen/arch/riscv/include/asm/cpufeature.h b/xen/arch/riscv/inclu= de/asm/cpufeature.h index b69616038888..ef02a3e26d2c 100644 --- a/xen/arch/riscv/include/asm/cpufeature.h +++ b/xen/arch/riscv/include/asm/cpufeature.h @@ -36,6 +36,7 @@ enum riscv_isa_ext_id { RISCV_ISA_EXT_zbb, RISCV_ISA_EXT_zbs, RISCV_ISA_EXT_smaia, + RISCV_ISA_EXT_smstateen, RISCV_ISA_EXT_ssaia, RISCV_ISA_EXT_svade, RISCV_ISA_EXT_svpbmt, diff --git a/xen/arch/riscv/include/asm/current.h b/xen/arch/riscv/include/= asm/current.h index 58c9f1506b7c..5fbee8182caa 100644 --- a/xen/arch/riscv/include/asm/current.h +++ b/xen/arch/riscv/include/asm/current.h @@ -48,6 +48,8 @@ DECLARE_PER_CPU(struct vcpu *, curr_vcpu); #define get_cpu_current(cpu) per_cpu(curr_vcpu, cpu) =20 #define guest_cpu_user_regs() ({ BUG_ON("unimplemented"); NULL; }) +#define vcpu_guest_cpu_user_regs(vcpu) \ + (&(vcpu)->arch.cpu_info->guest_cpu_user_regs) =20 #define switch_stack_and_jump(stack, fn) do { \ asm volatile ( \ diff --git a/xen/arch/riscv/include/asm/riscv_encoding.h b/xen/arch/riscv/i= nclude/asm/riscv_encoding.h index 1f7e612366f8..dd15731a86fa 100644 --- a/xen/arch/riscv/include/asm/riscv_encoding.h +++ b/xen/arch/riscv/include/asm/riscv_encoding.h @@ -228,6 +228,8 @@ #define ENVCFG_CBIE_INV _UL(0x3) #define ENVCFG_FIOM _UL(0x1) =20 +#define HCOUNTEREN_TM BIT(1, U) + /* =3D=3D=3D=3D=3D User-level CSRs =3D=3D=3D=3D=3D */ =20 /* User Trap Setup (N-extension) */ --=20 2.52.0 From nobody Mon Jan 26 07:39:22 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; 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Add lockless tracking of pending vCPU interrupts using atomic bitops. Two bitmaps are introduced: - irqs_pending =E2=80=94 interrupts currently pending for the vCPU - irqs_pending_mask =E2=80=94 bits that have changed in irqs_pending The design follows a multi-producer, single-consumer model, where the consumer is the vCPU itself. Producers may set bits in irqs_pending_mask without a lock. Clearing bits in irqs_pending_mask is performed only by the consumer via xchg_acquire(). The consumer must not write to irqs_pending and must not act on bits that are not set in the mask. Otherwise, extra synchronization should be provided. On RISC-V interrupts are not injected via guest registers, so pending interrupts must be recorded in irqs_pending (using the new vcpu_{un}set_interrupt() helpers) and flushed to the guest by updating HVIP before returning control to the guest. The consumer side is implemented in a follow-up patch. A barrier between updating irqs_pending and setting the corresponding mask bit in vcpu_set_interrupt() / vcpu_unset_interrupt() guarantees that if the consumer observes a mask bit set, the corresponding pending bit is also visible. This prevents missed interrupts during the flush. Signed-off-by: Oleksii Kurochko --- Changes in V2: - Move the patch before an introduction of vtimer. - Drop bitmap_zero() of irqs_pending and irqs_pending_mask bitmaps as vcpu structure starts out all zeros. - Drop const for irq argument of vcpu_{un}set_interrupt(). - Drop check "irq < IRQ_LOCAL_MAX" in vcpu_{un}set_interrupt() as it could lead to overrun of irqs_pending and irqs_pending_mask bitmaps. - Drop IRQ_LOCAL_MAX as there is no usage for it now. --- xen/arch/riscv/domain.c | 41 +++++++++++++++++++++++++++++ xen/arch/riscv/include/asm/domain.h | 19 +++++++++++++ 2 files changed, 60 insertions(+) diff --git a/xen/arch/riscv/domain.c b/xen/arch/riscv/domain.c index 3ae5fa3a8805..3777888f34ea 100644 --- a/xen/arch/riscv/domain.c +++ b/xen/arch/riscv/domain.c @@ -5,6 +5,7 @@ #include #include =20 +#include #include #include #include @@ -130,3 +131,43 @@ void arch_vcpu_destroy(struct vcpu *v) { vfree((char *)v->arch.cpu_info + sizeof(struct cpu_info)); } + +int vcpu_set_interrupt(struct vcpu *v, unsigned int irq) +{ + /* + * We only allow VS-mode software, timer, and external + * interrupts when irq is one of the local interrupts + * defined by RISC-V privilege specification. + */ + if ( irq !=3D IRQ_VS_SOFT && + irq !=3D IRQ_VS_TIMER && + irq !=3D IRQ_VS_EXT ) + return -EINVAL; + + set_bit(irq, v->arch.irqs_pending); + smp_mb__before_atomic(); + set_bit(irq, v->arch.irqs_pending_mask); + + vcpu_kick(v); + + return 0; +} + +int vcpu_unset_interrupt(struct vcpu *v, unsigned int irq) +{ + /* + * We only allow VS-mode software, timer, external + * interrupts when irq is one of the local interrupts + * defined by RISC-V privilege specification. + */ + if ( irq !=3D IRQ_VS_SOFT && + irq !=3D IRQ_VS_TIMER && + irq !=3D IRQ_VS_EXT ) + return -EINVAL; + + clear_bit(irq, v->arch.irqs_pending); + smp_mb__before_atomic(); + set_bit(irq, v->arch.irqs_pending_mask); + + return 0; +} diff --git a/xen/arch/riscv/include/asm/domain.h b/xen/arch/riscv/include/a= sm/domain.h index ec7786c76199..b8178447c68f 100644 --- a/xen/arch/riscv/include/asm/domain.h +++ b/xen/arch/riscv/include/asm/domain.h @@ -79,6 +79,22 @@ struct arch_vcpu register_t vstval; register_t vsatp; register_t vsepc; + + /* + * VCPU interrupts + * + * We have a lockless approach for tracking pending VCPU interrupts + * implemented using atomic bitops. The irqs_pending bitmap represent + * pending interrupts whereas irqs_pending_mask represent bits changed + * in irqs_pending. Our approach is modeled around multiple producer + * and single consumer problem where the consumer is the VCPU itself. + * + * DECLARE_BITMAP() is needed here to support 64 vCPU local interrupts + * on RV32 host. + */ +#define RISCV_VCPU_NR_IRQS 64 + DECLARE_BITMAP(irqs_pending, RISCV_VCPU_NR_IRQS); + DECLARE_BITMAP(irqs_pending_mask, RISCV_VCPU_NR_IRQS); } __cacheline_aligned; =20 struct paging_domain { @@ -117,6 +133,9 @@ static inline void update_guest_memory_policy(struct vc= pu *v, =20 static inline void arch_vcpu_block(struct vcpu *v) {} =20 +int vcpu_set_interrupt(struct vcpu *v, unsigned int irq); +int vcpu_unset_interrupt(struct vcpu *v, unsigned int irq); + #endif /* ASM__RISCV__DOMAIN_H */ =20 /* --=20 2.52.0 From nobody Mon Jan 26 07:39:22 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1769100490; cv=none; d=zohomail.com; s=zohoarc; b=i42B5u9mY0Qrv716FCk0v4H+pr6lcFVrSfaFetVFnfR40ZLtNbky2ginKc9a1OT03Ci92k1DEj9sKzIKrC3jbwN2N0eo4csGbmTKzygEdYZSxrExnhi8lDbkKCc53aabGTqUACG2r0IHziWCy9hj76TA2QK8wK6v0qVdUGihVLU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1769100490; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=XPAdNKHF5EjavsXAwjuKNGFWuBxYMr4iJeXH7Q9PsSE=; b=TKWy36+J8DXlY3pX5j1CthiqqulQivIWQPaNhY7vSDXuP6lL4cYWbHBUU6rjx9gbnmgsUmqwtJqlluZmvVK3C8WxDpIp4YHOGEV020myhFzJZQcGlmCycxm48eLyLAK22DZE9M0Jlead7lvSPs/0mk1kYG6b6BMO9rvEWCG9Fbc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1769100490464813.0957994830633; Thu, 22 Jan 2026 08:48:10 -0800 (PST) Received: from list by lists.xenproject.org with outflank-mailman.1211347.1522895 (Exim 4.92) (envelope-from ) id 1vixqV-0007fE-MJ; Thu, 22 Jan 2026 16:47:47 +0000 Received: by outflank-mailman (output) from mailman id 1211347.1522895; Thu, 22 Jan 2026 16:47:47 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vixqV-0007cV-ID; Thu, 22 Jan 2026 16:47:47 +0000 Received: by outflank-mailman (input) for mailman id 1211347; Thu, 22 Jan 2026 16:47:47 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vixqU-0007Id-Vj for xen-devel@lists.xenproject.org; Thu, 22 Jan 2026 16:47:46 +0000 Received: from mail-ej1-x62b.google.com (mail-ej1-x62b.google.com [2a00:1450:4864:20::62b]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 142313d6-f7b2-11f0-b15e-2bf370ae4941; Thu, 22 Jan 2026 17:47:46 +0100 (CET) Received: by mail-ej1-x62b.google.com with SMTP id a640c23a62f3a-b8838339fc6so177815366b.0 for ; Thu, 22 Jan 2026 08:47:46 -0800 (PST) Received: from fedora (user-109-243-67-101.play-internet.pl. [109.243.67.101]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b879513e951sm1686014966b.7.2026.01.22.08.47.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Jan 2026 08:47:44 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 142313d6-f7b2-11f0-b15e-2bf370ae4941 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1769100466; x=1769705266; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=XPAdNKHF5EjavsXAwjuKNGFWuBxYMr4iJeXH7Q9PsSE=; b=D4DReNfAPDbKDfXZ9/zF05gQc9KT9hisuLnKY2ogQ3YXLLlpaedpE3RzuwlC0oM/ij leONacPy+wcBeT3IMrn6aU6WiSyiZNZl2V6StbWiXJq78sSA3A3mPF8ILfcDIxqgK596 U5D7/C+sQL3niabL9BaXxFPK5ZtVVTbo4JwlfasICzVlrdBKn3GsduMiSH1RczU9Yf2z iMFRIxSmcEFUURSWQ5Wwx4W+jXKoIvnB+/m46mkcPjPCt75MHpBz0Os4EpUFm8ck8me2 gKZPe5aah3G7rT6axasNVKnBfMLiLLJcD45ySE6KVIEpyEWpI/rTcudja61EeRpgmPL+ 8RTQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769100466; x=1769705266; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=XPAdNKHF5EjavsXAwjuKNGFWuBxYMr4iJeXH7Q9PsSE=; b=kDVC/+Ls/xf9Cz3W2N9dIKAgIRnANQI4MCsESBuZAATw2diLaSURtsWcajl+3ix2Dd BdJTz6ASnW3PQnTZGRIBlTpcIgoGFL4zf8AGLm/P2gwjo4yPJw3ubtMh5awwr4N52/A2 /sVYiX3utcz3uZYTdrWFvrX1PV2GwcJSzxaAmkzYH84RiIqtDyV+IUMKK/RUa9LXzgIE z5xWo6iE0lo6BGmP0wRuP8Z+Ran5MLmUo/8ROHI1xWn2QUyQ599kOHmaBFHTt/aCX1pd HoU7p5ANhE8UjvCyl8qqfNKq1AKuUQ9aL86dwmQ0kYAs5uLBdUCtI6Zr/tM18x0mPXii vBtw== X-Gm-Message-State: AOJu0YwBWNwuBW0KM2OuxK98jgNSRwpYz/TsVcNrfkvegRrYDTTzMI7Z 5OXrmMv6KWWh21brppvTLTmfCQFfZL3E/lduJOJiu4rrd7Z0WOcN92I35DYxkA== X-Gm-Gg: AZuq6aLdmR/A2xgQ6qh2HJbQ08E/ZCcy/2SFYtme0iuRsOYXPKiLECXqeY5Fi3Tux23 xRhxhbOjrvP7Eb1uxn0um2Rlsh+TUWD/DOP6Qe1OifaHYdQSU8tUntZFQ9KQr/JToRwERYjrZOW GSj6oDAEsSCzWdJ/ujbZqU1YJvGdTBrBiBnlcgPCJvgkXKtzPcF7LFGOP+cOVfSUyjuengPgqwQ Jjcrn9TbAn3uRpiALwSxURmHV3cBwuv134rrNX6lPM47kAXDKUWAldqF4pu0vZdO43IENXrIxs0 EA7Kx1penMkq2vGZG+32quUw4QmmN80sReod48RfBOYf8oN9uLYzUlccUsdAmWYmWMXfLoGaGAy WFO/D7s7E86uqYBq+IR5xnlXr1ED/MKAlfsX27XWKcrJVX6oLa26rQbN+HlpuzwWX5225hpo9sN sHFOhCxmOR7Cv61dHHqcx4v6yp61+hQCUtCKuCDnOLshnC1+NzHaxaSrGA8BB5uWCz X-Received: by 2002:a17:907:9803:b0:b87:7430:d5d7 with SMTP id a640c23a62f3a-b8831b40942mr252088866b.9.1769100465342; Thu, 22 Jan 2026 08:47:45 -0800 (PST) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Alistair Francis , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini , Romain Caritey Subject: [PATCH v2 05/16] xen/riscv: introduce tracking of pending vCPU interrupts, part 2 Date: Thu, 22 Jan 2026 17:47:20 +0100 Message-ID: <58a7723ec48d84b91fd4730fe3ae653f55a0fd99.1769099885.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1769100491460154100 This patch is based on Linux kernel 6.16.0. Add the consumer side (vcpu_flush_interrupts()) of the lockless pending interrupt tracking introduced in part 1 (for producers). According, to the design only one consumer is possible, and it is vCPU itself. vcpu_flush_interrupts() is expected to be ran (as guests aren't ran now due to the lack of functionality) before the hypervisor returns control to the guest. Producers may set bits in irqs_pending_mask without a lock. Clearing bits in irqs_pending_mask is performed only by the consumer via xchg() (with aquire= & release semantics). The consumer must not write to irqs_pending and must not act on bits that are not set in the mask. Otherwise, extra synchronization should be provided. The worst thing which could happen with such approach is that a new pending bit will be set to irqs_pending bitmap during update of hvip variable in vcpu_flush_interrupt() but it isn't problem as the new pending bit won't be lost and just be proceded during the next flush. It is possible a guest could have pending bit not result in the hardware register without to be marked pending in irq_pending bitmap as: According to the RISC-V ISA specification: Bits hip.VSSIP and hie.VSSIE are the interrupt-pending and interrupt-enable bits for VS-level software interrupts. VSSIP in hip is an alias (writable) of the same bit in hvip. Additionally: When bit 2 of hideleg is zero, vsip.SSIP and vsie.SSIE are read-only zeros. Else, vsip.SSIP and vsie.SSIE are aliases of hip.VSSIP and hie.VSSIE. This means the guest may modify vsip.SSIP, which implicitly updates hip.VSSIP and the bit being writable with 1 would also trigger an interrupt as according to the RISC-V spec: These conditions for an interrupt trap to occur must be evaluated in a bounded amount of time from when an interrupt becomes, or ceases to be, pending in sip, and must also be evaluated immediately following the execution of an SRET instruction or an explicit write to a CSR on which these interrupt trap conditions expressly depend (including sip, sie and sstatus). What means that IRQ_VS_SOFT must be synchronized separately, what is done in vcpu_sync_interrupts(). Note, also, that IRQ_PMU_OVF would want to be synced for the similar reason as IRQ_VS_SOFT, but isn't sync-ed now as PMU isn't supported now. For the remaining VS-level interrupt types (IRQ_VS_TIMER and IRQ_VS_EXT), the specification states they cannot be modified by the guest and are read-only: Bits hip.VSEIP and hie.VSEIE are the interrupt-pending and interrupt-enab= le bits for VS-level external interrupts. VSEIP is read-only in hip, and is the logical-OR of these interrupt sources: =E2=80=A2 bit VSEIP of hvip; =E2=80=A2 the bit of hgeip selected by hstatus.VGEIN; and =E2=80=A2 any other platform-specific external interrupt signal directe= d to VS-level. Bits hip.VSTIP and hie.VSTIE are the interrupt-pending and interrupt-enab= le bits for VS-level timer interrupts. VSTIP is read-only in hip, and is the logical-OR of hvip.VSTIP and any other platform-specific timer interrupt signal directed to VS-level. Thus, for these interrupt types, it is sufficient to use vcpu_set_interrupt= () and vcpu_unset_interrupt(), and flush them during the call of vcpu_flush_interrupts(). As AIA specs introduced hviph register which would want to be updated when guest related AIA code will be introduced vcpu_update_hvip() is introduced instead of just open-code it in vcpu_flush_interrupts(). Signed-off-by: Oleksii Kurochko --- Changes in v2: - New patch. --- xen/arch/riscv/domain.c | 65 +++++++++++++++++++++++++++++ xen/arch/riscv/include/asm/domain.h | 3 ++ 2 files changed, 68 insertions(+) diff --git a/xen/arch/riscv/domain.c b/xen/arch/riscv/domain.c index 3777888f34ea..c078d595df9c 100644 --- a/xen/arch/riscv/domain.c +++ b/xen/arch/riscv/domain.c @@ -171,3 +171,68 @@ int vcpu_unset_interrupt(struct vcpu *v, unsigned int = irq) =20 return 0; } + +static void vcpu_update_hvip(struct vcpu *v) +{ + csr_write(CSR_HVIP, v->arch.hvip); +} + +void vcpu_flush_interrupts(struct vcpu *v) +{ + register_t *hvip =3D &v->arch.hvip; + + unsigned long mask, val; + + if ( ACCESS_ONCE(v->arch.irqs_pending_mask[0]) ) + { + mask =3D xchg(&v->arch.irqs_pending_mask[0], 0UL); + val =3D ACCESS_ONCE(v->arch.irqs_pending[0]) & mask; + + *hvip &=3D ~mask; + *hvip |=3D val; + } + + /* + * Flush AIA high interrupts. + * + * It is necessary to do only for CONFIG_RISCV_32 which isn't supported + * now. + */ +#ifdef CONFIG_RISCV_32 +# error "Update hviph" +#endif + + vcpu_update_hvip(v); +} + +void vcpu_sync_interrupts(struct vcpu *v) +{ + unsigned long hvip; + + /* Read current HVIP and VSIE CSRs */ + v->arch.vsie =3D csr_read(CSR_VSIE); + + /* Sync-up HVIP.VSSIP bit changes does by Guest */ + hvip =3D csr_read(CSR_HVIP); + if ( (v->arch.hvip ^ hvip) & BIT(IRQ_VS_SOFT, UL) ) + { + if ( !test_and_set_bit(IRQ_VS_SOFT, + &v->arch.irqs_pending_mask) ) + { + if ( hvip & BIT(IRQ_VS_SOFT, UL) ) + set_bit(IRQ_VS_SOFT, &v->arch.irqs_pending); + else + clear_bit(IRQ_VS_SOFT, &v->arch.irqs_pending); + } + } + + /* + * Sync-up AIA high interrupts. + * + * It is necessary to do only for CONFIG_RISCV_32 which isn't supported + * now. + */ +#ifdef CONFIG_RISCV_32 +# error "Update vsieh" +#endif +} diff --git a/xen/arch/riscv/include/asm/domain.h b/xen/arch/riscv/include/a= sm/domain.h index b8178447c68f..fa083094b43e 100644 --- a/xen/arch/riscv/include/asm/domain.h +++ b/xen/arch/riscv/include/asm/domain.h @@ -136,6 +136,9 @@ static inline void arch_vcpu_block(struct vcpu *v) {} int vcpu_set_interrupt(struct vcpu *v, unsigned int irq); int vcpu_unset_interrupt(struct vcpu *v, unsigned int irq); =20 +void vcpu_flush_interrupts(struct vcpu *v); +void vcpu_sync_interrupts(struct vcpu *v); + #endif /* ASM__RISCV__DOMAIN_H */ =20 /* --=20 2.52.0 From nobody Mon Jan 26 07:39:22 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; 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[109.243.67.101]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b879513e951sm1686014966b.7.2026.01.22.08.47.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Jan 2026 08:47:46 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 14e09f29-f7b2-11f0-b15e-2bf370ae4941 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1769100467; x=1769705267; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ha0IH64FmrGoMb6j9b2jIRmC/orgpSfo7QhViTDdwG8=; b=YAS9O7nNZfFjmmwqZSl7XLm5X/vnqIhk1MQ7fa1h+H6Mb+5aUe67A6Eyk5Ut1Bkj3Z tqsMhJXp8Z306AE2TfGGd4FpIzGQUbpoFRMunwHVCYRQyB/pTz38plkwo9yhll3UepMW taLpSjotSX/XxmynSquAcn7y6M9JG5u/jW8kPYQJ8KFe7IRIBL6evsgT4b0S69p4574J CiLDZBdEegSylMXd84kqBC50SFHFLQGy6R+3rDDBQOYu5Y493fV969/Dcaf4FGWswS3e +GCYl3FLHjp5PeLp5Qd7ZrE3haXf7fCHu7zyjY3P6Ba0uJ9Qc0GhMkooGzEfWDhQviu6 z6Rw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769100467; x=1769705267; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=ha0IH64FmrGoMb6j9b2jIRmC/orgpSfo7QhViTDdwG8=; b=cnuxJzhX8d1O5HNCfkhu+0uJAbb0DLy4Za+Kkssx5UPJBL/2O5ZtjfJNlTSUG/RmPb lPS7msF75pkirArj4KSz1256ZdMC3I9qgtJ5x8N8M/N9a2Uu/QZaHZK9FQym+apljL7Z Z5+B9ymFeOKEQIHCajO3B9yMh8Ec1BuMdDDeMD6+TdefNsykIH0nwUVxGD5Dh1QL4n0u CHHZ6NXcj+4fqD5iLNwo/MaNy+STUvbfp8svjPuU+ARQX8K5aTUZagb9uJDPqML2zU/N xqrpgH5QmRJ7Wi7yB/XovjJVf31BVunMVe4Gp4ddsyCdoF89Y4tLZbrCqnVm7p7yVuJ8 oZmQ== X-Gm-Message-State: AOJu0YwbMLQpLjimYWSzcM/IAK+QAfKIh9tyYSRndJNYJ6bV/ZreAyzW mLUleRo9PTHqoUkWwHcKfjmawXoPUjpTtZubMZvDS+2tmLo/MJDHilIdCYlkmg== X-Gm-Gg: AZuq6aL2Wi9hkphDa8PmTlDq4PtgpDGPqg0L8eNlX5C1LISQTDa/8zKVC4s4H2a+/q5 j8Q4aOT6qBxDiEvc4ICPMD3oWGsXj0x/dMYsFg3v1ifG/NsOCgvZS1iceuGBzv0JBI9y4PyD0r8 7u8DsQdpCJAJgAMPrs2QEdaBQFM1SQPlpYrsrPzAj/bg7Re7JM8RBUZZvoz//afQmcTpPFSH0oo 4Vs8pOFMcgYX7HWEvla82Nr9tMKvVxuo8/EtyUxHtvxqpG5tImvft4RiaPSSgGZtJ+gKpZ2Hoxm HVSaXFt/fEOAVsUw8fEFOvt6eKDl4EG9XTzx8Fg/v5cOSvctABa/BPhIKlzvYekBqnEZoouQyaf 9sdLQmxTjhwM5ruo08v9T60wS5qikkl3TkwCfwZgK9dBQKZecYzcvtkbX1oYq+KP9+cGLcD20/x R7C/szD/rhIKrlFD0xkv/yCWvSYpffKw0bX3euyEjk5l9906873EsEVA== X-Received: by 2002:a17:907:1b25:b0:b80:4030:1eca with SMTP id a640c23a62f3a-b880023748emr716691166b.2.1769100466636; Thu, 22 Jan 2026 08:47:46 -0800 (PST) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk , Andrew Cooper , Anthony PERARD , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Alistair Francis , Connor Davis , Romain Caritey Subject: [PATCH v2 06/16] xen/time: move ticks<->ns helpers to common code Date: Thu, 22 Jan 2026 17:47:21 +0100 Message-ID: X-Mailer: git-send-email 2.52.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1769100499519154100 Content-Type: text/plain; charset="utf-8" ticks_to_ns() and ns_to_ticks() are not architecture-specific, so provide a common implementation that is more resilient to overflow than the historical Arm version. This is not a practical issue for Arm, as the latest ARM ARM that timer frequency should be fixed at 1 GHz and older platforms used much lower rates, which is shy of 32-bit overflow. As the helpers are declared as static inline, they should not affect x86, which does not use them. On Arm, these helpers were historically implemented as out-of-line functions because the counter frequency was originally defined as static and unavaila= ble to headers [1]. Later changes [2] removed this restriction, but the helpers remained unchanged. Now they can be implemented as static inline without any issues. Centralising the helpers avoids duplication and removes subtle differences between architectures while keeping the implementation simple. Drop redundant includes where already pulls it in. No functional change is intended. [1] ddee56dc2994 arm: driver for the generic timer for ARMv7 [2] 096578b4e489 xen: move XEN_SYSCTL_physinfo, XEN_SYSCTL_numainfo and XEN_SYSCTL_topologyinfo to common code Signed-off-by: Oleksii Kurochko Suggested-by: Jan Beulich --- Changes in v2: - Move ns_to_ticks() and ticks_to_ns() to common code. --- xen/arch/arm/include/asm/time.h | 3 --- xen/arch/arm/time.c | 11 ----------- xen/arch/arm/vtimer.c | 2 +- xen/arch/riscv/include/asm/time.h | 5 ----- xen/arch/riscv/time.c | 1 + xen/include/xen/time.h | 11 +++++++++++ 6 files changed, 13 insertions(+), 20 deletions(-) diff --git a/xen/arch/arm/include/asm/time.h b/xen/arch/arm/include/asm/tim= e.h index 49ad8c1a6d47..c194dbb9f52d 100644 --- a/xen/arch/arm/include/asm/time.h +++ b/xen/arch/arm/include/asm/time.h @@ -101,9 +101,6 @@ extern void init_timer_interrupt(void); /* Counter value at boot time */ extern uint64_t boot_count; =20 -extern s_time_t ticks_to_ns(uint64_t ticks); -extern uint64_t ns_to_ticks(s_time_t ns); - void preinit_xen_time(void); =20 void force_update_vcpu_system_time(struct vcpu *v); diff --git a/xen/arch/arm/time.c b/xen/arch/arm/time.c index cc3fcf47b66a..a12912a106a0 100644 --- a/xen/arch/arm/time.c +++ b/xen/arch/arm/time.c @@ -27,7 +27,6 @@ #include #include #include -#include #include =20 uint64_t __read_mostly boot_count; @@ -47,16 +46,6 @@ unsigned int timer_get_irq(enum timer_ppi ppi) return timer_irq[ppi]; } =20 -/*static inline*/ s_time_t ticks_to_ns(uint64_t ticks) -{ - return muldiv64(ticks, SECONDS(1), 1000 * cpu_khz); -} - -/*static inline*/ uint64_t ns_to_ticks(s_time_t ns) -{ - return muldiv64(ns, 1000 * cpu_khz, SECONDS(1)); -} - static __initdata struct dt_device_node *timer; =20 #ifdef CONFIG_ACPI diff --git a/xen/arch/arm/vtimer.c b/xen/arch/arm/vtimer.c index d2124b175521..2e85ff2b6e62 100644 --- a/xen/arch/arm/vtimer.c +++ b/xen/arch/arm/vtimer.c @@ -12,13 +12,13 @@ #include #include #include +#include #include =20 #include #include #include #include -#include #include #include #include diff --git a/xen/arch/riscv/include/asm/time.h b/xen/arch/riscv/include/asm= /time.h index 1e7801e2ea0e..be3875b9984e 100644 --- a/xen/arch/riscv/include/asm/time.h +++ b/xen/arch/riscv/include/asm/time.h @@ -24,11 +24,6 @@ static inline cycles_t get_cycles(void) return csr_read(CSR_TIME); } =20 -static inline s_time_t ticks_to_ns(uint64_t ticks) -{ - return muldiv64(ticks, MILLISECS(1), cpu_khz); -} - void preinit_xen_time(void); =20 #endif /* ASM__RISCV__TIME_H */ diff --git a/xen/arch/riscv/time.c b/xen/arch/riscv/time.c index e962f8518d78..2c7af0a5d63b 100644 --- a/xen/arch/riscv/time.c +++ b/xen/arch/riscv/time.c @@ -4,6 +4,7 @@ #include #include #include +#include #include =20 unsigned long __ro_after_init cpu_khz; /* CPU clock frequency in kHz. */ diff --git a/xen/include/xen/time.h b/xen/include/xen/time.h index fe0d7a578a99..2185dd26a439 100644 --- a/xen/include/xen/time.h +++ b/xen/include/xen/time.h @@ -8,6 +8,7 @@ #ifndef __XEN_TIME_H__ #define __XEN_TIME_H__ =20 +#include #include #include =20 @@ -75,6 +76,16 @@ extern void send_timer_event(struct vcpu *v); =20 void domain_set_time_offset(struct domain *d, int64_t time_offset_seconds); =20 +static inline s_time_t ticks_to_ns(uint64_t ticks) +{ + return muldiv64(ticks, MILLISECS(1), cpu_khz); +} + +static inline uint64_t ns_to_ticks(s_time_t ns) +{ + return muldiv64(ns, cpu_khz, MILLISECS(1)); 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[109.243.67.101]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b879513e951sm1686014966b.7.2026.01.22.08.47.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Jan 2026 08:47:47 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 15ab09f6-f7b2-11f0-9ccf-f158ae23cfc8 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1769100468; x=1769705268; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=5c7RQ6OyPVY512X4e6H+NfNdqywFVdT5uOFctDjaxTg=; b=VooXe8WAyLXjDW+yhJ90+guS+IIAI6WBzr+WJVtYthd6oo0CaZjPvp+aE29zOxq9nk U2t17X45KKW2Vob85B+1UKjMKQvIFb6pZGrlprUdeJWuw5wyeJzf7490EGmCefD9hBp1 vj/4tSuP83SgDnkeDrCaMm0Th9JW/pAztWGGef35foCBz/wdmvQ9iTgslvZq2isCl7hz 0kzp9ybZYrYrEGvcbIru85WipIXA6zcyIx83A3AEF5uLf4jXmqjGaqOODInchLQkHWqf Yf2wvJbKzy04sQnllC9oDaWDOLVzkEY7AorKY3STraE46ydxK3M0W/Zq+Tt2eBmlimyU NhrA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769100468; x=1769705268; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=5c7RQ6OyPVY512X4e6H+NfNdqywFVdT5uOFctDjaxTg=; b=SEKuRwcieNk3RGx70o2jV5jGkZaXZYyz5B9ihvl+IakNNQM03nbLafmhWb+0q1BljP Se6e367DMz0fYJ0kobcwu1kXCsMqc/N4iWTcdVojjgITZYeW0Z2ph+dq97bheHfk2hHK 6Vo6Rme03f4W3Cizii/pyvzljIU3xinBE9B4XFXdyDYc+P2lZGxsISK7VOak2BKWn3mM 29rldNYetS2pcFldJrfSs1zc9FVH4up5tOWelRyq4kFVUgOuLkTk1+b3w0Py2qXJNTkk cJ4zXw+V8Rl7zkrcSeOIwv2FBK4wH6gFLDehQd2K4G3/SZWOO/Rxjiwyhs4gGoK7l+Px lBPA== X-Gm-Message-State: AOJu0YytG2NH1KylYuLmIvIHNrMtdGU48LUq4+iJBeSd0yFVWkdLsCjD CBduFHZv/tsiYY6uibpEuZIDgOGN43qVLN502Xlr6Wy9JE5fqsFWxzAcFCy5Ig== X-Gm-Gg: AZuq6aJDd84EQWQYuin9Hk3m36/e/bxvvmKSikyQNOxDoXiyhDJzJSLe+luaNXwuk/3 qFOwqNYA0MhW09OA+XCl1QRYvCmC8G+vSiC3YUCW/x2yALP67a/zeua0vcG3LhbLjM2ES8zyZqB kTgEZIuw8109MYbxFURH52W2RL9HrGLmxgfF8B+OwVWx5vNRx5ZHePQXjXiZXU6Uk07x+je6fCY p+Zm7ud4dAe/y8dHjOmnYtR3emevA7GQfID03hFIxKNVWQxP/EZJ0XzhsMo2jog4XgP1zDUObWi aB6PfxGpA4wPan1jqo6tTtSvDlV0LX0Z29yAEJr1HGo3H7/cYuzHtgBUjWck+XUVwa52eDpYtMt hHeMvYRJlWpvNgxJF8VYR5tXYeRwPUfCok0tBqX4XUYImq9YBRyhiPvk1xRkaXOqMxTz/Z0CBEj cFSkxlsa9mGLauPvRngbual//U9Usj21QM0pIGNcA3ZD49rPWVTHfgXA== X-Received: by 2002:a17:906:f584:b0:b73:278a:a499 with SMTP id a640c23a62f3a-b879690c3ccmr1747464466b.15.1769100467976; Thu, 22 Jan 2026 08:47:47 -0800 (PST) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Alistair Francis , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini , Romain Caritey Subject: [PATCH v2 07/16] xen/riscv: introduce basic vtimer infrastructure for guests Date: Thu, 22 Jan 2026 17:47:22 +0100 Message-ID: <381c200edaff013d999c6314c20e8cc8bdb5b041.1769099885.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1769100501558154100 Lay the groundwork for guest timer support by introducing a per-vCPU virtual timer backed by Xen=E2=80=99s common timer infrastructure. The virtual timer is programmed in response to the guest SBI sbi_set_timer() call and injects a virtual supervisor timer interrupt into the vCPU when it expires. While a dedicated struct vtimer is not strictly required at present, it is expected to become necessary once SSTC support is introduced. In particular, it will need to carry additional state such as whether SSTC is enabled, the next compare value (e.g. for the VSTIMECMP CSR) to be saved and restored across context switches, and time delta state (e.g. HTIMEDELTA) required for use cases such as migration. Introducing struct vtimer now avoids a later refactoring. Signed-off-by: Oleksii Kurochko --- Changes in v2: - Drop domain_vtimer_init() as it does nothing. - Drop "struct vcpu *v;" from struct vtimer as it could be taken from arch_vcpu using container_of(). - Drop vtimer_initialized, use t->status =3D=3D TIMER_STATUS_invalid instead to understand if timer was or wasn't initialized. - Drop inclusion of xen/domain.h as xen/sched.h already includes it. - s/ xen/time.h/ xen.timer.h in vtimer.c. - Drop ULL in if-conidtion in vtimer_set_timer() as with the cast it isn't necessary to have suffix ULL. - Add migrate timer to vtimer_set_timer() to be sure that vtimer will occur on pCPU it was ran, so the signalling to that vCPU will (commonly) be cheaper. - Check if the timeout has already expired and just inject the event in vtimer_vtimer_set_timer(). - Drop const for ticks argument of vtimer_set_timer(). - Merge two patches to one: - xen/riscv: introduce vtimer - xen/riscv: introduce vtimer_set_timer() and vtimer_expired() --- xen/arch/riscv/Makefile | 1 + xen/arch/riscv/domain.c | 8 +++- xen/arch/riscv/include/asm/domain.h | 3 ++ xen/arch/riscv/include/asm/vtimer.h | 20 ++++++++ xen/arch/riscv/vtimer.c | 73 +++++++++++++++++++++++++++++ 5 files changed, 103 insertions(+), 2 deletions(-) create mode 100644 xen/arch/riscv/include/asm/vtimer.h create mode 100644 xen/arch/riscv/vtimer.c diff --git a/xen/arch/riscv/Makefile b/xen/arch/riscv/Makefile index 8863d4b15605..5bd180130165 100644 --- a/xen/arch/riscv/Makefile +++ b/xen/arch/riscv/Makefile @@ -22,6 +22,7 @@ obj-y +=3D traps.o obj-y +=3D vmid.o obj-y +=3D vm_event.o obj-y +=3D vsbi/ +obj-y +=3D vtimer.o =20 $(TARGET): $(TARGET)-syms $(OBJCOPY) -O binary -S $< $@ diff --git a/xen/arch/riscv/domain.c b/xen/arch/riscv/domain.c index c078d595df9c..e38c0db62cac 100644 --- a/xen/arch/riscv/domain.c +++ b/xen/arch/riscv/domain.c @@ -9,6 +9,7 @@ #include #include #include +#include =20 #define HEDELEG_DEFAULT (BIT(CAUSE_MISALIGNED_FETCH, U) | \ BIT(CAUSE_FETCH_ACCESS, U) | \ @@ -111,11 +112,14 @@ int arch_vcpu_create(struct vcpu *v) if ( is_idle_vcpu(v) ) return rc; =20 + if ( (rc =3D vcpu_vtimer_init(v)) ) + goto fail; + /* - * As the vtimer and interrupt controller (IC) are not yet implemented, + * As interrupt controller (IC) is not yet implemented, * return an error. * - * TODO: Drop this once the vtimer and IC are implemented. + * TODO: Drop this once IC is implemented. */ rc =3D -EOPNOTSUPP; goto fail; diff --git a/xen/arch/riscv/include/asm/domain.h b/xen/arch/riscv/include/a= sm/domain.h index fa083094b43e..482429d4ef33 100644 --- a/xen/arch/riscv/include/asm/domain.h +++ b/xen/arch/riscv/include/asm/domain.h @@ -8,6 +8,7 @@ #include =20 #include +#include =20 struct vcpu_vmid { uint64_t generation; @@ -51,6 +52,8 @@ struct arch_vcpu =20 struct cpu_info *cpu_info; =20 + struct vtimer vtimer; + /* CSRs */ register_t hedeleg; register_t hideleg; diff --git a/xen/arch/riscv/include/asm/vtimer.h b/xen/arch/riscv/include/a= sm/vtimer.h new file mode 100644 index 000000000000..0d1555511755 --- /dev/null +++ b/xen/arch/riscv/include/asm/vtimer.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * (c) 2023-2024 Vates + */ + +#ifndef ASM__RISCV__VTIMER_H +#define ASM__RISCV__VTIMER_H + +#include + +struct vtimer { + struct timer timer; +}; + +int vcpu_vtimer_init(struct vcpu *v); +void vcpu_timer_destroy(struct vcpu *v); + +void vtimer_set_timer(struct vtimer *t, uint64_t ticks); + +#endif /* ASM__RISCV__VTIMER_H */ diff --git a/xen/arch/riscv/vtimer.c b/xen/arch/riscv/vtimer.c new file mode 100644 index 000000000000..b6599fa383b8 --- /dev/null +++ b/xen/arch/riscv/vtimer.c @@ -0,0 +1,73 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +#include + +static void vtimer_expired(void *data) +{ + struct vtimer *t =3D data; + struct arch_vcpu *avcpu =3D container_of(t, struct arch_vcpu, vtimer); + struct vcpu *v =3D container_of(avcpu, struct vcpu, arch); + + vcpu_set_interrupt(v, IRQ_VS_TIMER); +} + +int vcpu_vtimer_init(struct vcpu *v) +{ + struct vtimer *t =3D &v->arch.vtimer; + + init_timer(&t->timer, vtimer_expired, t, v->processor); + + return 0; +} + +void vcpu_timer_destroy(struct vcpu *v) +{ + struct vtimer *t =3D &v->arch.vtimer; + + if ( t->timer.status =3D=3D TIMER_STATUS_invalid ) + return; + + kill_timer(&v->arch.vtimer.timer); +} + +void vtimer_set_timer(struct vtimer *t, const uint64_t ticks) +{ + struct arch_vcpu *avcpu =3D container_of(t, struct arch_vcpu, vtimer); + struct vcpu *v =3D container_of(avcpu, struct vcpu, arch); + s_time_t expires =3D ticks_to_ns(ticks - boot_clock_cycles); + + vcpu_unset_interrupt(v, IRQ_VS_TIMER); + + /* + * According to the RISC-V sbi spec: + * If the supervisor wishes to clear the timer interrupt without + * scheduling the next timer event, it can either request a timer + * interrupt infinitely far into the future (i.e., (uint64_t)-1), + * or it can instead mask the timer interrupt by clearing sie.STIE C= SR + * bit. + */ + if ( ticks =3D=3D ((uint64_t)~0) ) + { + stop_timer(&t->timer); + + return; + } + + if ( expires < NOW() ) + { + /* + * Simplify the logic if the timeout has already expired and just + * inject the event. + */ + stop_timer(&t->timer); + vcpu_set_interrupt(v, IRQ_VS_TIMER); + + return; + } + + migrate_timer(&t->timer, smp_processor_id()); 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[109.243.67.101]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b879513e951sm1686014966b.7.2026.01.22.08.47.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Jan 2026 08:47:48 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 165fde96-f7b2-11f0-9ccf-f158ae23cfc8 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1769100469; x=1769705269; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=nhPCPrLN9zev/AujtYrNqtpuJ2Oszmh0GkcNP2XIraQ=; b=MYuuD2FrcDYLOF7v8v1l0WHSzgCRmUPD5ey1IAaXSYD50YGGUBtss480sDNr37bfHl 4N0VjrFSuSPaNEoig8DmOSFevbVcjR3oXum3S1RJis7edCOLgxEfNbTylWVmSi13aWPd bzBgHHfc5K27V5iqUvhh5Gg7rcqLLeG0g5aBpetxWoI9UQS4tRLHErQ1xCCV+93ioTDZ tNxg8JwPH/aNO2s1QLna5+ePZ2voeuV3ANlOsF6N9E5wdmgHhz+i21+lcPdK0oGOqV3k 7pvyqxoGQdweItxgHKXalpI8IZ7t/BKSA+VfSVErnQw2SpdqveEZD4nKQ3oAUriB9kFY a+Mw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769100469; x=1769705269; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=nhPCPrLN9zev/AujtYrNqtpuJ2Oszmh0GkcNP2XIraQ=; b=kvZt+ECwv5gpsi8O1EiCnaMlucE8KFojUvnyMlX1f27IuqMhiTu73WN7pTzkcm7lak X/zlHHhTu0ZZHDRrOAyyxOk8fsVhMrQ4ZYsSETphCnzaJhXCNsLBrNU44Ko1Sxx/o/YA p04TZnRVM/wMK8aDEFvif6mEc7XEZycqE1ksm6M6VOoUQ+BKY1lWUfySeviHtYrHsT7L yUzh37rc6lsnkIBJVUVOo2D8OW4gXf4MwiE9ElRsIL8OUUt7vKyiX65qCd+Fu55KO4/v nqEsk+V4m6b5UQt7szlJWnjwQC9gvzElHc9Ip8O9PJa8iv0HKoYG0oMFVadPUduG+9uR b7Ow== X-Gm-Message-State: AOJu0YwhpS4beNgg/rGhTD2lvnmSm/ZpEaJHTh5zjOWa2/QY4kgy60LX bXNYElU7fhDvADR1o2L9CyHSU98jr8EuW7vyEopDhcpRk9yZU0DCf3XY+ayFwQ== X-Gm-Gg: AZuq6aJdAYih20fhC5sUtXQVBAql9lD28MnruizlXm3l+QqRd6966EPiAw/+yO3tLVA QU9vgNdwh3Btr12EHkW7HJCaOEb0hUbUzQ5QcsayqEV3Hmt3kMO2Q7og/BLSx7gfZo/Eh/kcIrI Uvqs4Y0jA16qA38tu6cqN23EHRLE+uAdVBrBFqyWdDrN2LLrbL46AoeLMvklfOHqMcJ1oO4xACq OC1NX8K66VvrtM8AV8+UM4UEpaauP59S/dS8B20KGz5bnVNuHh2YYN+8Cb1Qc9SF5F1JNM1zjgR Ocom0irAsl4aXHREa2rpN+u89IOEPVH2d0sBPbaBwztflBLGOpnmV8KtAupeB1AgmIbtyi61Pyk tvB7XN21iRrFObxZve7u0fFT+FSoVWXBFKrfwQMMcRTScFcZaQWxGHVDTNL/8fzAzgR2nNjIRNg SUlEG5MaZifYES61R2yInbPy8b33ynUjTZk/TtX1nmZGHzlK5Q1Qi6Rg== X-Received: by 2002:a17:907:7250:b0:b87:3c4a:e68f with SMTP id a640c23a62f3a-b88003423b0mr654314366b.36.1769100469187; Thu, 22 Jan 2026 08:47:49 -0800 (PST) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Alistair Francis , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini , Romain Caritey Subject: [PATCH v2 08/16] xen/riscv: add temporary stub for smp_send_event_check_mask() Date: Thu, 22 Jan 2026 17:47:23 +0100 Message-ID: <062dbab8751bd0c27b913ce78de3a3eeb0ffe22f.1769099885.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1769100499471154100 Content-Type: text/plain; charset="utf-8" RISC-V SMP support is not yet implemented, but smp_send_event_check_mask() is required by common code and vcpu_kick(), which is introduced later. Provide a temporary stub implementation that asserts the mask only targets CPU0. cpumask_subset() is used instead of cpumask_equal() because some callers (e.g. cpumask_raise_softirq() or cpu_raise_softirq_batch_finish()) may legitimately pass an empty mask, which would otherwise cause false failures. The BUG_ON() ensures that attempts to use this function with multiple CPUs are caught early once SMP support is introduced. Signed-off-by: Oleksii Kurochko --- Changes in v2: - use BUG_ON(cpumask_subset(...)) instead of "#ifdef NR_CPUS > 1". - Update the commit message. --- xen/arch/riscv/smp.c | 7 +++++++ xen/arch/riscv/stubs.c | 5 ----- 2 files changed, 7 insertions(+), 5 deletions(-) diff --git a/xen/arch/riscv/smp.c b/xen/arch/riscv/smp.c index 4ca6a4e89200..d645364ea47d 100644 --- a/xen/arch/riscv/smp.c +++ b/xen/arch/riscv/smp.c @@ -1,3 +1,4 @@ +#include #include =20 /* @@ -13,3 +14,9 @@ struct pcpu_info pcpu_info[NR_CPUS] =3D { [0 ... NR_CPUS - 1] =3D { .processor_id =3D NR_CPUS, }}; + +void smp_send_event_check_mask(const cpumask_t *mask) +{ + /* Catch missing implementation once SMP support is introduced */ + BUG_ON(!cpumask_subset(mask, cpumask_of(0))); +} diff --git a/xen/arch/riscv/stubs.c b/xen/arch/riscv/stubs.c index 9e30a9a3b50b..c5784a436574 100644 --- a/xen/arch/riscv/stubs.c +++ b/xen/arch/riscv/stubs.c @@ -65,11 +65,6 @@ int arch_monitor_domctl_event(struct domain *d, =20 /* smp.c */ =20 -void smp_send_event_check_mask(const cpumask_t *mask) -{ - BUG_ON("unimplemented"); -} - void smp_send_call_function_mask(const cpumask_t *mask) { BUG_ON("unimplemented"); --=20 2.52.0 From nobody Mon Jan 26 07:39:22 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1769100500; cv=none; d=zohomail.com; s=zohoarc; b=ROp1mfGFag0VCBn8pKRLcg/eY8uxO84JcOt11fYs5nS6GI5oQozD22+ZLrhHVnUO2jAn4fMuwD5x87F0yE/Vf5oaUntdUD9KRybIAGGG2K1VLRZKfqug/aCy+Bxf1Sy9TulXIwDn+GC4JhclBpJjlHoGlNe4emW0G+XOFRlMXBg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1769100500; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=+bOmIXS7ukX07+v1FZwQcpO5Pv22L8b7W5Nzbqzk3MM=; b=hXcVmpy0JDu6AVOyLzNFjReFXmJDQl08xp+KMCxGy0WzwmU3go9CZLUIJpw3jshPvjwRQIf5FweUGb6oeJ/asqoid3L1pBZ+P3TsqKvO3zBWVKVG7CePiKbb62MLWKszc0o1uZJEJcQBZAY7f4SyPiCrdZuQCucPNuyLz0ObBb0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1769100500643269.73396587881496; Thu, 22 Jan 2026 08:48:20 -0800 (PST) Received: from list by lists.xenproject.org with outflank-mailman.1211354.1522955 (Exim 4.92) (envelope-from ) id 1vixqc-0000jd-MM; Thu, 22 Jan 2026 16:47:54 +0000 Received: by outflank-mailman (output) from mailman id 1211354.1522955; Thu, 22 Jan 2026 16:47:54 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vixqc-0000is-9I; Thu, 22 Jan 2026 16:47:54 +0000 Received: by outflank-mailman (input) for mailman id 1211354; Thu, 22 Jan 2026 16:47:53 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vixqb-0007Ij-39 for xen-devel@lists.xenproject.org; Thu, 22 Jan 2026 16:47:53 +0000 Received: from mail-ej1-x62f.google.com (mail-ej1-x62f.google.com [2a00:1450:4864:20::62f]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 1718468b-f7b2-11f0-9ccf-f158ae23cfc8; Thu, 22 Jan 2026 17:47:51 +0100 (CET) Received: by mail-ej1-x62f.google.com with SMTP id a640c23a62f3a-b876f3f603eso174720766b.0 for ; Thu, 22 Jan 2026 08:47:51 -0800 (PST) Received: from fedora (user-109-243-67-101.play-internet.pl. [109.243.67.101]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b879513e951sm1686014966b.7.2026.01.22.08.47.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Jan 2026 08:47:49 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 1718468b-f7b2-11f0-9ccf-f158ae23cfc8 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1769100470; x=1769705270; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+bOmIXS7ukX07+v1FZwQcpO5Pv22L8b7W5Nzbqzk3MM=; b=Z56vXmNe0vZFGbiPjeQexcThGbP8NxeeLpnxV6YndwGnLUxx9Q46EDgVFU9Z8M8e7s HynSDVdmefqwWa18Y+n9yfTSAliiSRU35bu9kGc1iGQdo06xiB6jjWoQnHRhtyN+iAvw ny3I4pWBT0EIsKmWypu1rL4XjTclOrM/mvGehOS+Vzv+VvtlkPOSlR7p1mnLJrNOrv14 1UjM/ozgmm2j4one+o5LiI+KtMewX5U3RlvBA7VpXLdmrtQCRzwusQjo9/xXXgUhtUZU 08lQNDK5RW+Pi9gSGGn/6npbyH5jEDfGZup1QNskSV0CiLDCnKio2Ju82qtHA+/jMSB6 Y94A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769100470; x=1769705270; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=+bOmIXS7ukX07+v1FZwQcpO5Pv22L8b7W5Nzbqzk3MM=; b=hoxYf7+WKNChiix5c00LemQyNKebb51flxfOXlgfU64bDAN+uGDxxjZs9V1Q6zmeTN 4ZMxP5tG20bfta5RQM80hdC+Kb0+mFHMcvNyIdSV4s649HjftRrTOsD47sxIvoKLnmM/ f2D77zSLf/dcmTCEwjTO2tUFlqqFOt1UsFR4x+AbPECoWZXZCPTeZ40G2RqNCqM0buiD UeRnaqsv9TwahYrR1URiOjHUn+JUoFpuEdi+ewvyjzhjZe3P6Yg34olTYwZYOrrj+I+s WDBPo456RA7oR2kOb+o2bwsv5JozjF3iHGlotrevoGqMCaoT25kHvt7ZME7hiDtKLkwQ yrGA== X-Gm-Message-State: AOJu0Yzd+GE3oMnbSFsrUK3shf1YN+mY1RbtwLEj9GDpCxFFhxz6CR5X f1AOMCf74aPUHUqmJB0dP0UpWMlWHLuYbYE1WuzgwRsIYUl+6EXFakG147me9A== X-Gm-Gg: AZuq6aLnnmsXDCvKpq0IwcHYvjVJER95U8YgkDPQFajN9JPLDgAG7cS7Jt6uecnb50L P19CuGZSbqyXC1DTN3sIa843rpOTcUtEQkkrQKpXXFFrWVj6zoQ9Anmbni8wltATDqjqhaAxxjf HgENvcTyg5UjExuNBrMPkjVirzXrKiJ926jRZdW6B7wKikAGvJDq25VYxZPIX/WvV7QuXiKrhC/ 54BhzMb1Pmf3HrGHjnSkZ5mJtVP9S/Plcn4otzFbBvCyHPKvbPHDHNeB0w63KV0/HBeDoQX1IW8 0OcF7CyttVKeY1PHRt2DuObjrj/rH2zSbl3MkqwR0CXdAfomEqxrGtch24eULmgLc9n5yUk34ci Nb2pWCWR6rSXImrhx8O4U/nmcqqZ82J5PXJvwmYJlou/LC3fT6kFx3/y827aFF3gd3fM1CGEnVW URixcGCFGtG4xu+LGpgQRk7CNyLP5JD1QtSmofzByIW3LRBdxUY5I8Bw== X-Received: by 2002:a17:907:8dc3:b0:b88:587f:f594 with SMTP id a640c23a62f3a-b88587ffb0cmr29524266b.18.1769100470277; Thu, 22 Jan 2026 08:47:50 -0800 (PST) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Alistair Francis , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini , Romain Caritey Subject: [PATCH v2 09/16] xen/riscv: introduce vcpu_kick() implementation Date: Thu, 22 Jan 2026 17:47:24 +0100 Message-ID: <0335a7db0343d81ce4256482a464e7ba5df1c204.1769099885.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1769100502414158500 Content-Type: text/plain; charset="utf-8" Add a RISC-V implementation of vcpu_kick(), which unblocks the target vCPU and sends an event check IPI if the vCPU was running on another processor. This mirrors the behavior of Arm and enables proper vCPU wakeup handling on RISC-V. Remove the stub implementation from stubs.c, as it is now provided by arch/riscv/domain.c. Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich --- Changes in v2: - Add Acked-by: Jan Beulich . --- xen/arch/riscv/domain.c | 14 ++++++++++++++ xen/arch/riscv/stubs.c | 5 ----- 2 files changed, 14 insertions(+), 5 deletions(-) diff --git a/xen/arch/riscv/domain.c b/xen/arch/riscv/domain.c index e38c0db62cac..13ac384c4b76 100644 --- a/xen/arch/riscv/domain.c +++ b/xen/arch/riscv/domain.c @@ -1,8 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ =20 +#include #include #include #include +#include #include =20 #include @@ -240,3 +242,15 @@ void vcpu_sync_interrupts(struct vcpu *v) # error "Update vsieh" #endif } + +void vcpu_kick(struct vcpu *v) +{ + bool running =3D v->is_running; + + vcpu_unblock(v); + if ( running && v !=3D current ) + { + perfc_incr(vcpu_kick); + smp_send_event_check_mask(cpumask_of(v->processor)); + } +} diff --git a/xen/arch/riscv/stubs.c b/xen/arch/riscv/stubs.c index c5784a436574..1f0add97b361 100644 --- a/xen/arch/riscv/stubs.c +++ b/xen/arch/riscv/stubs.c @@ -208,11 +208,6 @@ void vcpu_block_unless_event_pending(struct vcpu *v) BUG_ON("unimplemented"); } =20 -void vcpu_kick(struct vcpu *v) -{ - BUG_ON("unimplemented"); -} - unsigned long hypercall_create_continuation(unsigned int op, const char *format, ...) { --=20 2.52.0 From nobody Mon Jan 26 07:39:22 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1769100504; cv=none; d=zohomail.com; s=zohoarc; b=GSkxUZT7fxp1F+ua5A9zn/tjx08ZFPtn4okGB2TMND3ktKiWqKi6gXLhFpXAFE2SCJwv188ispg7rdTSytNqWxFJbt3qmpbd45Rd2PO78gx8/+WhmQSkQEbxzTUhOrY8iuYURkmZBg/S8XpwCJLo6nxgmPxPkTYudct4XqBywGY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1769100504; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=bossoBnEH4JNpm3EBQfuiRI4dS6yLi1VOSzTCCzzE2k=; b=n/IWR7gLaWC9sLb150Irc/uFQeR92ioco5iKSpZA6eXurrfmWco9kXoJYtKCD+SocuD+f7i6mXFdORiPS9fn/HhPCOoza1bQiuoXXvqQPdyJCLwZ+R83Oj38ARMMt7ok6Fi6kz09XTPYMrB0TqZ9+1tyXoAVnCha6NaCzMUqDwg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1769100504042142.73631797256542; Thu, 22 Jan 2026 08:48:24 -0800 (PST) Received: from list by lists.xenproject.org with outflank-mailman.1211360.1522990 (Exim 4.92) (envelope-from ) id 1vixqh-0001u9-A0; Thu, 22 Jan 2026 16:47:59 +0000 Received: by outflank-mailman (output) from mailman id 1211360.1522990; Thu, 22 Jan 2026 16:47:59 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vixqg-0001t0-R9; Thu, 22 Jan 2026 16:47:58 +0000 Received: by outflank-mailman (input) for mailman id 1211360; Thu, 22 Jan 2026 16:47:57 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vixqf-0007Ij-3e for xen-devel@lists.xenproject.org; Thu, 22 Jan 2026 16:47:57 +0000 Received: from mail-ej1-x62d.google.com (mail-ej1-x62d.google.com [2a00:1450:4864:20::62d]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 17c12453-f7b2-11f0-9ccf-f158ae23cfc8; Thu, 22 Jan 2026 17:47:52 +0100 (CET) Received: by mail-ej1-x62d.google.com with SMTP id a640c23a62f3a-b7cf4a975d2so162748366b.2 for ; Thu, 22 Jan 2026 08:47:52 -0800 (PST) Received: from fedora (user-109-243-67-101.play-internet.pl. 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At present, vtimer_ctx_switch_from() is a no-op because the RISC-V SSTC extension, which provides a virtualization-aware timer, is not yet supported. Xen therefore relies the virtual (SBI-based) timer. The virtual timer uses Xen's internal timer infrastructure and must be associated with the pCPU on which the vCPU is currently running so that timer events can be delivered efficiently. As a result, vtimer_ctx_switch_t= o() migrates the timer to the target pCPU when a vCPU is scheduled in. Signed-off-by: Oleksii Kurochko --- Changes in v2: - Align the parameters names for vtimer_ctx_switch_from() and vtimer_ctx_= switch_to() in declarations to match the ones in the defintions to make Misra happy. - s/vtimer_save/vtimer_ctx_switch_from. - s/vtimer_restore/vtimer_ctx_switch_to. - Update the commit message. --- xen/arch/riscv/include/asm/vtimer.h | 3 +++ xen/arch/riscv/vtimer.c | 15 +++++++++++++++ 2 files changed, 18 insertions(+) diff --git a/xen/arch/riscv/include/asm/vtimer.h b/xen/arch/riscv/include/a= sm/vtimer.h index 0d1555511755..52b7fb7b1cbb 100644 --- a/xen/arch/riscv/include/asm/vtimer.h +++ b/xen/arch/riscv/include/asm/vtimer.h @@ -17,4 +17,7 @@ void vcpu_timer_destroy(struct vcpu *v); =20 void vtimer_set_timer(struct vtimer *t, uint64_t ticks); =20 +void vtimer_ctx_switch_from(struct vcpu *p); +void vtimer_ctx_switch_to(struct vcpu *n); + #endif /* ASM__RISCV__VTIMER_H */ diff --git a/xen/arch/riscv/vtimer.c b/xen/arch/riscv/vtimer.c index b6599fa383b8..6dfd6d836260 100644 --- a/xen/arch/riscv/vtimer.c +++ b/xen/arch/riscv/vtimer.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ =20 +#include #include #include =20 @@ -71,3 +72,17 @@ void vtimer_set_timer(struct vtimer *t, const uint64_t t= icks) migrate_timer(&t->timer, smp_processor_id()); set_timer(&t->timer, expires); } + +void vtimer_ctx_switch_from(struct vcpu *p) +{ + ASSERT(!is_idle_vcpu(p)); + + /* Nothing to do at the moment as SSTC isn't supported now. */ +} + +void vtimer_ctx_switch_to(struct vcpu *n) +{ + ASSERT(!is_idle_vcpu(n)); + + migrate_timer(&n->arch.vtimer.timer, n->processor); +} --=20 2.52.0 From nobody Mon Jan 26 07:39:22 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1769100496; cv=none; d=zohomail.com; s=zohoarc; b=n0LVUzYTsq2AeqsRSHYeEdwCKjsdXTXetIvYCqdNWy4mPJVIa/3WTIz1n2qBUQCQOWOL4nw2XqEC5WSNo6tjF6HTakTbxbq8JPLxDaDwo7qPFRcQ20MhjrwQE3OfXQ0S0+/jXU7b4JMjxVihIhSQtFLWd6DCB+iPdTGBT13nJ4c= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1769100496; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=yFNz2eINTf9rVU++UNSQJpwAORPoMimHJyiwu4QoyIk=; b=KLbxqPUMpKqJ37GLhA3rjW+yMHisOfS1OUvOAuYuZTtIq8QKMsFLL4X/uo3EJfgLp8VJoz8PPp4EsOrRFvRB6IVM3KcqKzUheWWAN0mphrQER0hl1qyks5+UTRqJkUppu+Dp5XUMa0F92QG45JN50Nme6i8BKBRVjqGWNhW2Kuk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1769100496683284.9143841788341; Thu, 22 Jan 2026 08:48:16 -0800 (PST) Received: from list by lists.xenproject.org with outflank-mailman.1211355.1522971 (Exim 4.92) (envelope-from ) id 1vixqe-00018n-7T; Thu, 22 Jan 2026 16:47:56 +0000 Received: by outflank-mailman (output) from mailman id 1211355.1522971; Thu, 22 Jan 2026 16:47:56 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vixqd-00016a-M5; Thu, 22 Jan 2026 16:47:55 +0000 Received: by outflank-mailman (input) for mailman id 1211355; Thu, 22 Jan 2026 16:47:54 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vixqc-0007Id-1p for xen-devel@lists.xenproject.org; Thu, 22 Jan 2026 16:47:54 +0000 Received: from mail-ej1-x62b.google.com (mail-ej1-x62b.google.com [2a00:1450:4864:20::62b]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 18716147-f7b2-11f0-b15e-2bf370ae4941; Thu, 22 Jan 2026 17:47:53 +0100 (CET) Received: by mail-ej1-x62b.google.com with SMTP id a640c23a62f3a-b8707005183so195855266b.0 for ; Thu, 22 Jan 2026 08:47:53 -0800 (PST) Received: from fedora (user-109-243-67-101.play-internet.pl. [109.243.67.101]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b879513e951sm1686014966b.7.2026.01.22.08.47.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Jan 2026 08:47:52 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 18716147-f7b2-11f0-b15e-2bf370ae4941 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1769100473; x=1769705273; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=yFNz2eINTf9rVU++UNSQJpwAORPoMimHJyiwu4QoyIk=; b=B39nKBiuAKmmI+eUiNNlVTEPXbQ12gOBTMtFDuNLQJ5/mvfGEJuCm2B5DCNwtg1GVc 1lvvlKIV7sLpLNKDQlnkBypxYCWQ/1HuIQdUcGfYSZ5C9conPZybhk0ceR1f+OiiqThz YWKRV8tV/PL+CTy9AkZmHuslYND5RIs9KLN+AVgRS7OnVcoG44VIdykx9Jr8JKZE3fXi I87TyyJDnZzhoNODZNLG7Fy/bAs3DESXYRafUjp8zxUX+PxobPeQwtkP0Fyd8pRFr4N+ hkNVxnFSCiYdsPjRzXueyXEQTpHe30YvwT9PMvpe7xVKyN3hceeSJJcVZLeq/a6Av2kv teJA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769100473; x=1769705273; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=yFNz2eINTf9rVU++UNSQJpwAORPoMimHJyiwu4QoyIk=; b=lqmCTUe5TfUSnK1Bu2NVpEMAIXt6yKeCjFsL2ZYTPjhf1BpXIRLKmeTWiGFm8cqbkc fG6FEIq0D6olP/U2bUHIWmRDCPLdJc5D7bshuhGWdNuqKI+Z3NN9i2Ed7zob7wDNcR2Y PpylVGECn4H/HhptWnklarHDhuazzCCS74iVTMBKrElnSLuKL/8QJYUVy/AQtvH7Lnah MJK7dC1FriSdxvYBRAmQmzR9sMP9uaDQQs0UYfPPsssVpTJG5lgoGnvKVW/Aq4etLGX4 qaMWxE8mw4YiKiUZrVPcD9IKPx8EndbSJfv5JM2anXkVv1jB20mUgfMmbX6FWbM6E5sA LkVw== X-Gm-Message-State: AOJu0Yzp3mStcLV3m5ACHpGazRmxwb/qvxAjUaQp+Xc9C/++d6WyRDYI QtTL7P2jwSVvxiYlkwAkZ8W5MhVlWaDblUIDtqwzhORHP1xzGwAmkYaBye8anQ== X-Gm-Gg: AZuq6aII4n9OtrDtGADr8gZeUN+c9TqpK31qmZPkk+lym1dcBuOUpjroEmNny2SEPJM k24r5KhlcjUwfbfq5/0NY6kFWQgi42Mj9GRv+qSNjI0FwsrGy8JqE/BM9iGUSZL5DMj0xak1qIS 7UWihf3xQRUlFMQg7KIes5jCRUrmDVHfPFzJHJv6EFqmp9MLn4iZI8wrz5sTxCYT1xD0cEUSlGz 1IAWuaVfwa0CELRzHmFcTOH8EMqm3f+mn09BmY8RPO4i0isXZlavNQhz4s7+gOQIdpnv+cGytDM nt5R1M1yd1vSP2cWgOFmXhwrWJ9yLB4yaEcslRAfinQaNKD9s3cEMkggcnnkQVMs46P5E5emIuN KM4lnm+0Oo6MleJkPwT3dzoK025AI6QwgJ0zAKbtr50jVWFo4cVTTlwfWxdRNMoCr+foyHNdSDd QDnUZJ7H49pMLX5DtABkmY/8h0Kqyopxj7B6B/EfJce5Ii/INpQKYvGKnfGNj8NJF1 X-Received: by 2002:a17:907:7256:b0:b84:40d3:43e6 with SMTP id a640c23a62f3a-b8792e0b88fmr1732932566b.6.1769100472698; Thu, 22 Jan 2026 08:47:52 -0800 (PST) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Alistair Francis , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini , Romain Caritey Subject: [PATCH v2 11/16] xen/riscv: implement SBI legacy SET_TIMER support for guests Date: Thu, 22 Jan 2026 17:47:26 +0100 Message-ID: <0cca5db24ac772b1d1145e189b26ace63ef9a58d.1769099885.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1769100498392158500 Add handling of the SBI_EXT_0_1_SET_TIMER function ID to the legacy extension ecall handler. The handler now programs the vCPU=E2=80=99s virtual timer via vtimer_set_timer() and returns SBI_SUCCESS. This enables guests using the legacy SBI timer interface to schedule timer events correctly. Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich --- Changes in v2: - Add Acked-by: Jan Beulich . --- xen/arch/riscv/vsbi/legacy-extension.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/xen/arch/riscv/vsbi/legacy-extension.c b/xen/arch/riscv/vsbi/l= egacy-extension.c index 2e8df191c295..090c23440cea 100644 --- a/xen/arch/riscv/vsbi/legacy-extension.c +++ b/xen/arch/riscv/vsbi/legacy-extension.c @@ -7,6 +7,7 @@ =20 #include #include +#include =20 static void vsbi_print_char(char c) { @@ -44,6 +45,11 @@ static int vsbi_legacy_ecall_handler(unsigned long eid, = unsigned long fid, ret =3D SBI_ERR_NOT_SUPPORTED; break; =20 + case SBI_EXT_0_1_SET_TIMER: + vtimer_set_timer(¤t->arch.vtimer, regs->a0); + regs->a0 =3D SBI_SUCCESS; + break; + default: /* * TODO: domain_crash() is acceptable here while things are still = under --=20 2.52.0 From nobody Mon Jan 26 07:39:22 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1769101154; cv=none; d=zohomail.com; s=zohoarc; b=OcoFYMpKvOjwh6Jjgb4yisGFh1yZSXzaNWlMvPFDAT99jIh3AXEVvR3Bow2BgiiBfV+EUB+zMkbCWY9pkRqoIirRLS5SODmC0BYGIYPw05xMWag+yofw5dI/ptSmwaufSvaKKUlAKQNE4NtDU483FB8cDYWYVra1aSKIADfPr3M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1769101154; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=0wg7KIGfayug5C3vvvCUGP++rm9Fv8txuX7xpHEfh2s=; b=ZrA8HroBcEZyNSt3uETABMkPrI/3kNY3Wc8E8n1SN0A6L3R5rQon9KzniBYM0LF/i2AhVve58kuG+aDjGKTReTLQvHQt55jj+/+QSnZe0Ee/0coG4VHOj8JO5a6df2Cg+zZwkbhY5Dy/iCAtM0bNCpvDVWHS8jRVCQFt1tmjy7A= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1769101154113308.54834162210796; Thu, 22 Jan 2026 08:59:14 -0800 (PST) Received: from list by lists.xenproject.org with outflank-mailman.1211533.1523075 (Exim 4.92) (envelope-from ) id 1viy1K-0002RR-24; Thu, 22 Jan 2026 16:58:58 +0000 Received: by outflank-mailman (output) from mailman id 1211533.1523075; Thu, 22 Jan 2026 16:58:58 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1viy1J-0002RK-Vm; Thu, 22 Jan 2026 16:58:57 +0000 Received: by outflank-mailman (input) for mailman id 1211533; Thu, 22 Jan 2026 16:58:56 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vixqi-0007Ij-4j for xen-devel@lists.xenproject.org; Thu, 22 Jan 2026 16:48:00 +0000 Received: from mail-ed1-x531.google.com (mail-ed1-x531.google.com [2a00:1450:4864:20::531]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 194c7e37-f7b2-11f0-9ccf-f158ae23cfc8; Thu, 22 Jan 2026 17:47:55 +0100 (CET) Received: by mail-ed1-x531.google.com with SMTP id 4fb4d7f45d1cf-655af782859so2338396a12.2 for ; Thu, 22 Jan 2026 08:47:55 -0800 (PST) Received: from fedora (user-109-243-67-101.play-internet.pl. [109.243.67.101]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b879513e951sm1686014966b.7.2026.01.22.08.47.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Jan 2026 08:47:53 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 194c7e37-f7b2-11f0-9ccf-f158ae23cfc8 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1769100474; x=1769705274; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=0wg7KIGfayug5C3vvvCUGP++rm9Fv8txuX7xpHEfh2s=; b=ZoiSw9nTLb0T4wBpp903Ds8wqM9o9Sm6Dh9J6DPgxS4HinulO1QXcmEMb4C9DuLpmM OagYuVHY3Bw79Y+iYCiqXVxHL+uJXw5KltzBwL0/6ajdr8O/4Om/E97LjTiXUCgGRJ8x Xrt9LOHfh0ZQTSp1SHWEJpDqtA5L46y38EGfxyn+HcU365obe1lUHxnh8yOj40Qoit/E PC7EeXrZYvBHVlwxvvHz6CFRsYxBPy3zgXtD/MjAz+jYAmfzaDjLB72Q+TVaJ2ekWyTH dWGrveeHMnqruGNGVXxvtoDmeHY8hgxNlijOpRaUOBN2oT9u1fGwpomrrKs/hZfP+my/ qiSw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769100474; x=1769705274; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=0wg7KIGfayug5C3vvvCUGP++rm9Fv8txuX7xpHEfh2s=; b=MdquETWtRmvFtj/w1Lh07SHWTDKrLSvmPc1zdjts6ltXPTcdRJ9f4Dda+9zXnxwFpz l0+F0dpuBCKyzIq858Ict9rZT5yBSjaHmMGVzFwi54S1fC3zvIMl0nujFLYYL8q17+SR t2EDGkXMHs663EPq7RGBft91HlOjvjNxk7HfcrDKFBqDKNW8fZcbGvbz/SDz1fn6OjcP j+2IomucNPUR+BdKsM0RgNqDuO6CI3sWC5yl5VFM4IXT5owzIar3nZj1bkACO+DBVKBF 56SwDbbucCNRYYaV6RnqUVK8VTaTwXSiVA6bpbICrAov3nXPA4x915/C1XNqsWj1erFH RzOg== X-Gm-Message-State: AOJu0YyCEibiH7J3YuE90+ESyuMd/1Pwh2XkqBk0fJYHDFdcr3AOcjdY kCYr0h89zmMS/2gdMOj4CdJ0zBskIDgsp+RD5tvuVYJEEONSTl40S0GJNSIB5w== X-Gm-Gg: AZuq6aI7JuB/+qF93qa1HDoozSwJz+6PtQzW5xMpnb8OOjowY1a2MkPRsrX4BgVt1de Zjbt8stWPhktl/r+0ToCq6SotJVxvALsasyefzgxTOfQjqezUoUSJMNMo9hk2cz6OLJ9A2f8WPE BxeQta2NUe6AsAtsztzwSvlhahGEyZYaP8Zbqd2pcSzBXXL5vzJZb5xUcgS2fC9ZTWmvIwp9LW4 XQ8mHGhd4cxat2X2x2eHyvzjAmIa/ebEV0ZAjX/bNWnr6/5U+0D97k5X2+dyWHsnSoetDgWCu+r PdyXu7MxtPCqN8ydt3/k9EJfeKV1OaEY2C8n/ytON9/EZpZTMKA202VzHj98wLTy/O9biQBE2RY iQHQDW1jLip2wh4NJ+F3d2nJeaLflm3uOjFSM5q9KsyFgPL8RvYT/cha2+iE6KlZYsQ5bbIrqo8 rTQ3nBac3Jc5UvpBbLWPIAlYGuVSYHgGT2qnBDrS4YNdHRQqVIlFXjbA== X-Received: by 2002:a17:907:c07:b0:b88:4b1f:5b1f with SMTP id a640c23a62f3a-b884b1f64c2mr111863966b.38.1769100473895; Thu, 22 Jan 2026 08:47:53 -0800 (PST) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Alistair Francis , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini , Romain Caritey Subject: [PATCH v2 12/16] xen/riscv: introduce sbi_set_timer() Date: Thu, 22 Jan 2026 17:47:27 +0100 Message-ID: <2fd4da2ad7c4af2241368edba739b24d0e976552.1769099885.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1769101155853158500 Introduce a function pointer for sbi_set_timer(), since different OpenSBI versions may implement the TIME extension with different extension IDs and/or function IDs. If the TIME extension is not available, fall back to the legacy timer mechanism. This is useful when Xen runs as a guest under another Xen, because the TIME extension is not currently virtualised and therefore will not appear as available. The sbi_set_timer() pointer will be used by reprogram_timer() to program Xen=E2=80=99s physical timer as without SSTC extension there is no any other option except SBI call to do that as only M-timer is available for us. Signed-off-by: Oleksii Kurochko --- Changes in v2: - Move up defintion of SBI_EXT_TIME_SET_TIMER and use the same padding as defintions around it. - Add an extra comment about stime_value granuality above declaration of sbi_set_timer function pointer. - Refactor implemetation of sbi_set_timer_v02(). - Provide fallback for sbi_set_timer_v01(). - Update the commit message. --- xen/arch/riscv/include/asm/sbi.h | 18 ++++++++++++++ xen/arch/riscv/sbi.c | 40 ++++++++++++++++++++++++++++++++ 2 files changed, 58 insertions(+) diff --git a/xen/arch/riscv/include/asm/sbi.h b/xen/arch/riscv/include/asm/= sbi.h index 79f7ff5c5501..e0e31d7afa20 100644 --- a/xen/arch/riscv/include/asm/sbi.h +++ b/xen/arch/riscv/include/asm/sbi.h @@ -29,6 +29,10 @@ =20 #define SBI_EXT_BASE 0x10 #define SBI_EXT_RFENCE 0x52464E43 +#define SBI_EXT_TIME 0x54494D45 + +/* SBI function IDs for TIME extension */ +#define SBI_EXT_TIME_SET_TIMER 0x0 =20 /* SBI function IDs for BASE extension */ #define SBI_EXT_BASE_GET_SPEC_VERSION 0x0 @@ -134,6 +138,20 @@ int sbi_remote_hfence_gvma(const cpumask_t *cpu_mask, = vaddr_t start, int sbi_remote_hfence_gvma_vmid(const cpumask_t *cpu_mask, vaddr_t start, size_t size, unsigned long vmid); =20 +/* + * Programs the clock for next event after stime_value time. This function= also + * clears the pending timer interrupt bit. + * If the supervisor wishes to clear the timer interrupt without schedulin= g the + * next timer event, it can either request a timer interrupt infinitely far + * into the future (i.e., (uint64_t)-1), or it can instead mask the timer + * interrupt by clearing sie.STIE CSR bit. + * The stime_value parameter represents absolute time measured in ticks. + * + * This SBI call returns 0 upon success or an implementation specific nega= tive + * error code. + */ +extern int (*sbi_set_timer)(uint64_t stime_value); + /* * Initialize SBI library * diff --git a/xen/arch/riscv/sbi.c b/xen/arch/riscv/sbi.c index 425dce44c679..2c7757c8839f 100644 --- a/xen/arch/riscv/sbi.c +++ b/xen/arch/riscv/sbi.c @@ -249,6 +249,38 @@ static int (* __ro_after_init sbi_rfence)(unsigned lon= g fid, unsigned long arg4, unsigned long arg5); =20 +static int cf_check sbi_set_timer_v02(uint64_t stime_value) +{ + struct sbiret ret; + + ret =3D sbi_ecall(SBI_EXT_TIME, SBI_EXT_TIME_SET_TIMER, stime_value, +#ifdef CONFIG_RISCV_32 + stime_value >> 32, +#else + 0, +#endif + 0, 0, 0, 0); + + return sbi_err_map_xen_errno(ret.error); +} + +static int cf_check sbi_set_timer_v01(uint64_t stime_value) +{ + struct sbiret ret; + + ret =3D sbi_ecall(SBI_EXT_0_1_SET_TIMER, 0, stime_value, +#ifdef CONFIG_RISCV_32 + stime_value >> 32, +#else + 0, +#endif + 0, 0, 0, 0); + + return sbi_err_map_xen_errno(ret.error); +} + +int (* __ro_after_init sbi_set_timer)(uint64_t stime_value); + int sbi_remote_sfence_vma(const cpumask_t *cpu_mask, vaddr_t start, size_t size) { @@ -326,6 +358,14 @@ int __init sbi_init(void) sbi_rfence =3D sbi_rfence_v02; printk("SBI v0.2 RFENCE extension detected\n"); } + + if ( sbi_probe_extension(SBI_EXT_TIME) > 0 ) + { + sbi_set_timer =3D sbi_set_timer_v02; + printk("SBI v0.2 TIME extension detected\n"); + } + else + sbi_set_timer =3D sbi_set_timer_v01; } else panic("Ooops. SBI spec version 0.1 detected. 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[109.243.67.101]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b879513e951sm1686014966b.7.2026.01.22.08.47.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Jan 2026 08:47:54 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 19f3d528-f7b2-11f0-b15e-2bf370ae4941 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1769100475; x=1769705275; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=7mbSVBQ+1aSN6DFc+pj8xuW2JrsfZRnVra8JiKBPkJ4=; b=ezhrY/ovYEQzxYAmZDG4qvkObWVczVuGVDemzRpF0LFHcxXuCNJZiu8DD7wunJ1sLL gpGup3A0FzEZsJQjBJnOviFCpbYp+tOeRmq1C5i5gFsK3VAmYKFHbMtTYxeM/oUCjZN6 NA/I43pcupB/+dikZrXJNI8Jfe9aBbO/PjBLA+6NbcRGXya/HCqK4xYu1hdQyWw7bDzT pwCqNlRdmQvLenozUdZzimWjTgsqBCY/kk0FyaX+7b0F2RHC7tEW4KG4v30OhKetgYQW JpSc+yS3ahlQgEY3fRYOPohWXuK6iO//r3eKcwfnqMOcZYK1Z+bOkjP9eZR3AIANQ4oW M2VQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769100475; x=1769705275; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=7mbSVBQ+1aSN6DFc+pj8xuW2JrsfZRnVra8JiKBPkJ4=; b=GFQbunULDnRiZibAqSyAdpxNy/5FH4QJlPBhb6y0UfF7t+cAl2UvcYoZ0x8ehoZYB4 QZSwFMOchhlCzANzAIYAjm3UWqOH7kG83yidcib6lDD5zdv3l83yihy65jXGZOGkNhux LntmqehzuEzpnawPFYnzaTm6q01l1AoJV16UmiVYjNoz5aSuIJs4Q9kcHyUYj8G20OkS 6lGXtCZXXMS8j2HLv9yUF4xhv2mnyvkgXqL5uGQG8PosEuvIlrQ7yeHuaw15xiFKqkiU 6Q1ovr0sUEzXPsSpMTttAxKCgcAqefb3XKH8/7E0o5OGIeWtvAoBHKF5P1ACmdfWhP1t ynBQ== X-Gm-Message-State: AOJu0YyN9kkke2EnF/d+4z+k5oitrrvfTJ8Ekpk9R7WmILgLEAHngZXD vakzueRZ9n3Novb9icntRB/5BYYJJdGxLkVjdSirmukvw62a2uXdE5zarqkNaA== X-Gm-Gg: AZuq6aIvp4VXgmtU1woZ9uqsg1euElExR0wo0E/Nw+YKybnpWRzgfvv3xVJ5aeQImW0 yA6KuRJbIN+sqb3M4lXItDWyeRgDbqbu66qKOmCU9jQ8XInmEzoQ/VUR5iN6euMl7bVPxAELoD3 wte2waGOkMonGkDOVc8aFczkdqwDVne5gV7doBEDzslWFalcis5Ip1PDb7oOBqDqy4rRQMtMJrf jvMLd2w11M6UKlq1L0hEDmJNxHmO6TJT5K4DSVIL9q+10m+PBeIZiiIjdcDmeVXBHgPnHNWpaP2 /a5ajNL/vMJUiT/1RLa8512kdIaBin8bruGVybHovu5marHQ6eL/Qq8xgRZR7BKfIQn7le9Rl34 sxZbqS+vAj3o2t+gQpo+VTPPGOarJb8WS17CrziUrlajShNMEUzlzCwqRYYuNkLDKDmtnNAZdu7 1JcN4OhznPviXs9SWkXMGDJbbNPqCyavg2tdo9M8ZUO25raD3gnUNHEw== X-Received: by 2002:a17:907:9805:b0:b83:6e2b:890d with SMTP id a640c23a62f3a-b8800434127mr752883766b.25.1769100475180; Thu, 22 Jan 2026 08:47:55 -0800 (PST) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Alistair Francis , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini , Romain Caritey Subject: [PATCH v2 13/16] xen/riscv: implement reprogram_timer() via SBI Date: Thu, 22 Jan 2026 17:47:28 +0100 Message-ID: <732635f43fb80daec332f78d4442b56bf5dfda98.1769099885.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1769100508495158500 Content-Type: text/plain; charset="utf-8" Implement reprogram_timer() on RISC-V using the standard SBI timer call. The privileged architecture only defines machine-mode timer interrupts (using mtime/mtimecmp). Therefore, timer services for S/HS/VS mode must be provided by M-mode via SBI calls. SSTC (Supervisor-mode Timer Control) is optional and is not supported on the boards available to me, so the only viable approach today is to program the timer through SBI. reprogram_timer() enables/disables the supervisor timer interrupt and programs the next timer deadline using sbi_set_timer(). If the SBI call fails, the code panics, because sbi_set_timer() is expected to return either 0 or -ENOSUPP (this has been stable from early OpenSBI versions to the latest ones). The SBI spec does not define a standard negative error code for this call, and without SSTC there is no alternative method to program the timer, so the SBI timer call must be available. reprogram_timer() currently returns int for compatibility with the existing prototype. While it might be cleaner to return bool, keeping the existing signature avoids premature changes in case sbi_set_timer() ever needs to return other values (based on which we could try to avoid panic-ing) in the future. Signed-off-by: Oleksii Kurochko --- Changes in v2: - Add TODO comment above sbi_set_timer() call. - Update the commit message. --- xen/arch/riscv/stubs.c | 5 ----- xen/arch/riscv/time.c | 43 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 43 insertions(+), 5 deletions(-) diff --git a/xen/arch/riscv/stubs.c b/xen/arch/riscv/stubs.c index 1f0add97b361..cb7546558b8e 100644 --- a/xen/arch/riscv/stubs.c +++ b/xen/arch/riscv/stubs.c @@ -21,11 +21,6 @@ nodemask_t __read_mostly node_online_map =3D { { [0] =3D= 1UL } }; =20 /* time.c */ =20 -int reprogram_timer(s_time_t timeout) -{ - BUG_ON("unimplemented"); -} - void send_timer_event(struct vcpu *v) { BUG_ON("unimplemented"); diff --git a/xen/arch/riscv/time.c b/xen/arch/riscv/time.c index 2c7af0a5d63b..f021ceab8ec4 100644 --- a/xen/arch/riscv/time.c +++ b/xen/arch/riscv/time.c @@ -7,6 +7,9 @@ #include #include =20 +#include +#include + unsigned long __ro_after_init cpu_khz; /* CPU clock frequency in kHz. */ uint64_t __ro_after_init boot_clock_cycles; =20 @@ -40,6 +43,46 @@ static void __init preinit_dt_xen_time(void) cpu_khz =3D rate / 1000; } =20 +int reprogram_timer(s_time_t timeout) +{ + uint64_t deadline, now; + int rc; + + if ( timeout =3D=3D 0 ) + { + /* Disable timers */ + csr_clear(CSR_SIE, BIT(IRQ_S_TIMER, UL)); + + return 1; + } + + deadline =3D ns_to_ticks(timeout) + boot_clock_cycles; + now =3D get_cycles(); + if ( deadline <=3D now ) + return 0; + + /* Enable timer */ + csr_set(CSR_SIE, BIT(IRQ_S_TIMER, UL)); + + /* + * TODO: When the SSTC extension is supported, it would be preferable = to + * use the supervisor timer registers directly here for better + * performance, since an SBI call and context switch would no lo= nger + * be required. + * + * This would also reduce reliance on a specific SBI implementat= ion. + * For example, it is not ideal to panic() if sbi_set_timer() re= turns + * a non-zero value. Currently it can return 0 or -ENOSUPP, and + * without SSTC we still need an implementation because only the + * M-mode timer is available, and it can only be programmed in + * M-mode. + */ + if ( (rc =3D sbi_set_timer(deadline)) ) + panic("%s: timer wasn't set because: %d\n", __func__, rc); + + return 1; +} + void __init preinit_xen_time(void) { if ( acpi_disabled ) --=20 2.52.0 From nobody Mon Jan 26 07:39:22 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1769100508; cv=none; d=zohomail.com; s=zohoarc; b=XB79FHyctm8n7dxPaLOHoFpZQiCu4xnJdmE+LNQ8w3ieJv10ngi6izaRLr3rSdtm5B1uUMmY0DEblHNR8eySk8LQw+MKUI8NNnGpgpDXZzRlTIAjt2/Tt4nqKY3jlkHtKQI1tWphE4BUBTcdRVDXCaajEQvISh0XfKpVHzeSlsw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1769100508; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=TbDTiLjWuEzC7c6gqH8qnfrVym3BHTcxish5wSxW7l4=; b=ibuTImXTymW1u8f3zTYPPmwBQQ2NVNHQGAoYJ8sgwqo6c6vAiOfVMhWA39kfbZlrzpbp/WY5AIrri4N8u+QV/lmhq1bfi5S1F5cr1YyntDSTU6Zwl5Op97pLlARdAcIjJfaA9B/ebiEji6Ry4nJsIGPVCmVTbMt8kmVQVWJRy0A= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1769100508746781.2937995030857; Thu, 22 Jan 2026 08:48:28 -0800 (PST) Received: from list by lists.xenproject.org with outflank-mailman.1211363.1523002 (Exim 4.92) (envelope-from ) id 1vixqj-0002PV-AZ; Thu, 22 Jan 2026 16:48:01 +0000 Received: by outflank-mailman (output) from mailman id 1211363.1523002; Thu, 22 Jan 2026 16:48:01 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vixqj-0002Mo-4B; Thu, 22 Jan 2026 16:48:01 +0000 Received: by outflank-mailman (input) for mailman id 1211363; Thu, 22 Jan 2026 16:47:58 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vixqg-0007Id-Mo for xen-devel@lists.xenproject.org; Thu, 22 Jan 2026 16:47:58 +0000 Received: from mail-ej1-x62d.google.com (mail-ej1-x62d.google.com [2a00:1450:4864:20::62d]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 1a95e4e3-f7b2-11f0-b15e-2bf370ae4941; Thu, 22 Jan 2026 17:47:57 +0100 (CET) Received: by mail-ej1-x62d.google.com with SMTP id a640c23a62f3a-b872cf905d3so179241566b.2 for ; Thu, 22 Jan 2026 08:47:57 -0800 (PST) Received: from fedora (user-109-243-67-101.play-internet.pl. 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The handler disables further timer interrupts by clearing SIE.STIE and raises TIMER_SOFTIRQ so the generic timer subsystem can perform its processing. Update do_trap() to dispatch IRQ_S_TIMER to this new handler. Signed-off-by: Oleksii Kurochko --- Changes in v2: - Drop cause argument of timer_interrupt() as it isn't used inside the function and anyway it is pretty clear what is the cause inside timer_interrupt(). --- xen/arch/riscv/traps.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/xen/arch/riscv/traps.c b/xen/arch/riscv/traps.c index e9c967786312..53f96f143823 100644 --- a/xen/arch/riscv/traps.c +++ b/xen/arch/riscv/traps.c @@ -10,6 +10,7 @@ #include #include #include +#include =20 #include #include @@ -108,6 +109,15 @@ static void do_unexpected_trap(const struct cpu_user_r= egs *regs) die(); } =20 +static void timer_interrupt(void) +{ + /* Disable the timer to avoid more interrupts */ + csr_clear(CSR_SIE, BIT(IRQ_S_TIMER, UL)); + + /* Signal the generic timer code to do its work */ + raise_softirq(TIMER_SOFTIRQ); +} + void do_trap(struct cpu_user_regs *cpu_regs) { register_t pc =3D cpu_regs->sepc; @@ -148,6 +158,10 @@ void do_trap(struct cpu_user_regs *cpu_regs) intc_handle_external_irqs(cpu_regs); break; =20 + case IRQ_S_TIMER: + timer_interrupt(); + break; + default: break; } --=20 2.52.0 From nobody Mon Jan 26 07:39:22 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1769101160; cv=none; d=zohomail.com; s=zohoarc; b=TKL0rYBxvs7RaJfJa37+ADmV1DPQd178t4rWie949PiAyRVRGZMZQvtPa9VdDtRBL+mXVZoDUhrDS0j1If3SUCIQwgDS1SJsHEWzak1zfRvTwhqdE8bPklqA3lC+yqkJNAwfDAT6lClEPCoDhRjdJ1mY/gaPn0MDPjEvCe/Q+n8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1769101160; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=dcpUeXukHvpe2V8ajAwhudISERtpAWc83oml7NTTtzQ=; b=jSACN5+mLAN4Tu9+gonuwWuF8WypQlAvcNFnelEJAozPulacsxh0VkFENwHp6oSTVYtLq0vSMwVQhAsYWO/hh1kDAzY5ErhABVDGdUA0XHUD+co2HKDKhnz5BZC+8jTeP5HFDF3gH8IJLkeKp1fBr/1puL5GMFpTJMvf51fQyJQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1769101160530680.2461891326126; Thu, 22 Jan 2026 08:59:20 -0800 (PST) Received: from list by lists.xenproject.org with outflank-mailman.1211542.1523085 (Exim 4.92) (envelope-from ) id 1viy1V-0002oU-9H; Thu, 22 Jan 2026 16:59:09 +0000 Received: by outflank-mailman (output) from mailman id 1211542.1523085; Thu, 22 Jan 2026 16:59:09 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1viy1V-0002oL-6f; Thu, 22 Jan 2026 16:59:09 +0000 Received: by outflank-mailman (input) for mailman id 1211542; Thu, 22 Jan 2026 16:59:08 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vixqj-0007Id-NY for xen-devel@lists.xenproject.org; Thu, 22 Jan 2026 16:48:01 +0000 Received: from mail-ej1-x62f.google.com (mail-ej1-x62f.google.com [2a00:1450:4864:20::62f]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 1b2afd50-f7b2-11f0-b15e-2bf370ae4941; Thu, 22 Jan 2026 17:47:58 +0100 (CET) Received: by mail-ej1-x62f.google.com with SMTP id a640c23a62f3a-b86ed375d37so142095166b.3 for ; Thu, 22 Jan 2026 08:47:58 -0800 (PST) Received: from fedora (user-109-243-67-101.play-internet.pl. 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Signed-off-by: Oleksii Kurochko --- Changes in v2: - Update the commit message. - Move implementation of sync_vcpu_execstate() to separate commit as it doesn't connect to tasklet subsystem. --- xen/arch/riscv/domain.c | 5 +++++ xen/arch/riscv/setup.c | 3 +++ xen/arch/riscv/stubs.c | 5 ----- 3 files changed, 8 insertions(+), 5 deletions(-) diff --git a/xen/arch/riscv/domain.c b/xen/arch/riscv/domain.c index 13ac384c4b76..1458902aff82 100644 --- a/xen/arch/riscv/domain.c +++ b/xen/arch/riscv/domain.c @@ -254,3 +254,8 @@ void vcpu_kick(struct vcpu *v) smp_send_event_check_mask(cpumask_of(v->processor)); } } + +void sync_local_execstate(void) +{ + /* Nothing to do -- no lazy switching */ +} diff --git a/xen/arch/riscv/setup.c b/xen/arch/riscv/setup.c index 9b4835960d20..e8dbd55ce79e 100644 --- a/xen/arch/riscv/setup.c +++ b/xen/arch/riscv/setup.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -133,6 +134,8 @@ void __init noreturn start_xen(unsigned long bootcpu_id, panic("Booting using ACPI isn't supported\n"); } =20 + tasklet_subsys_init(); + init_IRQ(); =20 riscv_fill_hwcap(); diff --git a/xen/arch/riscv/stubs.c b/xen/arch/riscv/stubs.c index cb7546558b8e..c912d46f1e42 100644 --- a/xen/arch/riscv/stubs.c +++ b/xen/arch/riscv/stubs.c @@ -91,11 +91,6 @@ void continue_running(struct vcpu *same) BUG_ON("unimplemented"); } =20 -void sync_local_execstate(void) -{ - BUG_ON("unimplemented"); -} - void sync_vcpu_execstate(struct vcpu *v) { BUG_ON("unimplemented"); --=20 2.52.0 From nobody Mon Jan 26 07:39:22 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1769101228; cv=none; d=zohomail.com; s=zohoarc; b=nAyaUv31/GXCQdmwI7q2dfuUQkURduKMNEQDAzkJffQMUkBq0uOY+8TOWZJvAKCeke5Z6I9oFg7hZ/DM5aWkvywxrawbSerPR399WmazJPXBn1MkTm75njhpwiKE/k9OY/u2Yq6OQ4niCBnzLFL4TAFNgGWfDmv36RFMWv1Zeqg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1769101228; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=KZA8ihisriROMO2vLm1yqQjETNpKnWgnKN9uanVzkRc=; b=KmLLVGssjCUgCXmqR8BA5itTvgCbC6CDznTsJSO4IOiiBc2yj3n0WoGfyrJIJNlhOY4AFf1HihoM43zQdr0aXg7251vTyxUAbXnIhe4x0+llJKp70qAchNWP6dqxBLw34VnWJ44g4DK27EfCl+VGgz+jgpn1KO3gMWX/8hx0xEs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1769101228792509.99000967408836; Thu, 22 Jan 2026 09:00:28 -0800 (PST) Received: from list by lists.xenproject.org with outflank-mailman.1211577.1523095 (Exim 4.92) (envelope-from ) id 1viy2X-0004kG-IM; Thu, 22 Jan 2026 17:00:13 +0000 Received: by outflank-mailman (output) from mailman id 1211577.1523095; Thu, 22 Jan 2026 17:00:13 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1viy2X-0004k9-FO; Thu, 22 Jan 2026 17:00:13 +0000 Received: by outflank-mailman (input) for mailman id 1211577; Thu, 22 Jan 2026 17:00:12 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vixqn-0007Ij-52 for xen-devel@lists.xenproject.org; Thu, 22 Jan 2026 16:48:05 +0000 Received: from mail-ej1-x632.google.com (mail-ej1-x632.google.com [2a00:1450:4864:20::632]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 1bd9100b-f7b2-11f0-9ccf-f158ae23cfc8; Thu, 22 Jan 2026 17:47:59 +0100 (CET) Received: by mail-ej1-x632.google.com with SMTP id a640c23a62f3a-b8842e5a2a1so115010166b.2 for ; Thu, 22 Jan 2026 08:47:59 -0800 (PST) Received: from fedora (user-109-243-67-101.play-internet.pl. [109.243.67.101]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b879513e951sm1686014966b.7.2026.01.22.08.47.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Jan 2026 08:47:57 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 1bd9100b-f7b2-11f0-9ccf-f158ae23cfc8 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1769100478; x=1769705278; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=KZA8ihisriROMO2vLm1yqQjETNpKnWgnKN9uanVzkRc=; b=aJ88qnAjcU9/TFsl0BVagsFiu/yKfXwVrWIV5Cc8TNUlkJPICwLSgHHKSk12fupVz4 zz1N5BKosEX3p01vjZaBvf7bJVWp0NZqEE75SOk7o5/otBl1XNlrME4nw5Ji+f8nSvH5 UJsuYGkdDVwnBVhLL0RQZO1uVNLhShwGapLZiqf5c4+2DThwnUVmxF+YSev1zvBXGkQy wQcDyGrhReFQ15WOxEeREYvS6IqrDWcd0rn0tZTPulnIX3wn5mE8kpiwis/b+gLb0E/S SzMjA2xNI3yabvvvREQEj5U/24S6mQKEsWHmZ3+pZGVr7efag8pGMPFVXOxaisSYL+qo nczg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769100478; x=1769705278; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=KZA8ihisriROMO2vLm1yqQjETNpKnWgnKN9uanVzkRc=; b=o0zQcqXvTt51qEL82S5Mh3EOn8x5/KuP6bx4qJptw/c2GnW31r2FAdjYsOJNJEY9ka cDghZfRsFdFT5TW4XolCO+Kg+41DdZb8H6nL56M057drRs9VB/Et7qcDfuczGTn//tcJ d2UDCQilJL/AOckZHAFPeOtDiSrYXyCKaOSflCL40nWsvv5CFr8ALu269QbSYNRduVrN fW/vwyjGneLdRNac5aN4Wo2g9woHr2uQl5IdZM8/Vpd77EOy85b1gH6++6Nt6H+tp5S/ 1S/ydyc8k7A93T0ylm2sBvonbqhRot6jV8KSQL+kHkOxqpjdC2LOe+0HPAdPzquGj/KN 7pSA== X-Gm-Message-State: AOJu0YwjnBUABx5VZLu883FougsdWlGcKnpidxEBARb9BpgGBXa6hZ3g 4ifUVZfG0rNUhSCgyprX8NE8lf5VU93pROg4UqGvnoEAcvulsIKDB69BMLcbDg== X-Gm-Gg: AZuq6aLNYu9ixBVRsPuspUkIASzQyM1dObG7HDVMrc7gofsq3Oe2Hde1ROmCz2uQUwm +9+RUaxLReUHYnv4FJa7AuabIJ+gBRJY6I4bpOgcJNgult6HK86QKzQFu0gAaXtlS0hEA8EZCf4 Dl0fcH7Pn8fTy7xNr6Lu18l4mxlxfygqmVb1Ii/6LCi0AMZPSPcnZqiojM/lZPcap6biF+SLndF vaOlSiBLT5KsfR79N87HEmLQVgVqDztPJQRpHRl8i1ivsK7XYtvCObPiCXEA7Zx5PtsCSzU5gPY Ma76zj4uO8M4z2Np7X3EvH0HLANfACyC45pfpXvfnSIDFpuZRyloYvGbRI0ZL64Of3K7EVeeqnZ shMQMGvgZSK0aCPbyp+xi4bF8jV/ypQuGNoKRfda4r1eyUaKT6RK0zH8wToKeIPffiPewniatd2 /8ga/N9N1diE24l5viwneK0k9bhWwAThA1C7X4M+/sMisAHmXqsLozNg== X-Received: by 2002:a17:907:84e:b0:b73:667e:bb29 with SMTP id a640c23a62f3a-b8792d3be61mr1668682466b.8.1769100478306; Thu, 22 Jan 2026 08:47:58 -0800 (PST) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Alistair Francis , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini , Romain Caritey Subject: [PATCH v2 16/16] xen/riscv: implement sync_vcpu_execstate() Date: Thu, 22 Jan 2026 17:47:31 +0100 Message-ID: X-Mailer: git-send-email 2.52.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1769101230139158500 Content-Type: text/plain; charset="utf-8" The scheduler may call this function to force synchronization of given vCPU's state. Although RISC-V does not support lazy context switching, a full memory barrier is still required to order observation of the saved context correctly. Signed-off-by: Oleksii Kurochko --- Changes in v2: - New patch. --- xen/arch/riscv/domain.c | 18 ++++++++++++++++++ xen/arch/riscv/stubs.c | 5 ----- 2 files changed, 18 insertions(+), 5 deletions(-) diff --git a/xen/arch/riscv/domain.c b/xen/arch/riscv/domain.c index 1458902aff82..48ba7584acaa 100644 --- a/xen/arch/riscv/domain.c +++ b/xen/arch/riscv/domain.c @@ -259,3 +259,21 @@ void sync_local_execstate(void) { /* Nothing to do -- no lazy switching */ } + +void sync_vcpu_execstate(struct vcpu *v) +{ + /* + * We don't support lazy switching. + * + * However the context may have been saved from a remote pCPU so we + * need a barrier to ensure it is observed before continuing. + * + * Per vcpu_context_saved(), the context can be observed when + * v->is_running is false (the caller should check it before calling + * this function). + * + * Note this is a full barrier to also prevent update of the context + * to happen before it was observed. + */ + smp_mb(); +} diff --git a/xen/arch/riscv/stubs.c b/xen/arch/riscv/stubs.c index c912d46f1e42..26434166acc6 100644 --- a/xen/arch/riscv/stubs.c +++ b/xen/arch/riscv/stubs.c @@ -91,11 +91,6 @@ void continue_running(struct vcpu *same) BUG_ON("unimplemented"); } =20 -void sync_vcpu_execstate(struct vcpu *v) -{ - BUG_ON("unimplemented"); -} - void startup_cpu_idle_loop(void) { BUG_ON("unimplemented"); --=20 2.52.0