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charset="utf-8" From: Jan Beulich Signed-off-by: Jan Beulich Signed-off-by: Teddy Astie --- v2: introduced xen/include/xen/lib/x86/cpu-policy.h | 27 ++++++++++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-) diff --git a/xen/include/xen/lib/x86/cpu-policy.h b/xen/include/xen/lib/x86= /cpu-policy.h index f94f23e159..c721c986cc 100644 --- a/xen/include/xen/lib/x86/cpu-policy.h +++ b/xen/include/xen/lib/x86/cpu-policy.h @@ -121,7 +121,32 @@ struct cpu_policy uint64_t :64, :64; /* Leaf 0x3 - PSN. */ uint64_t :64, :64; /* Leaf 0x4 - Structured Cache. */ uint64_t :64, :64; /* Leaf 0x5 - MONITOR. */ - uint64_t :64, :64; /* Leaf 0x6 - Therm/Perf. */ + + /* Leaf 0x6 - Therm/Perf. */ + struct { + uint32_t /* a */ + dts:1, + turbo:1, + arat:1, + :4, + hwp:1, + hwp_notification:1, + hwp_activity_window:1, + hwp_epp:1, + hwp_plr:1, + :1, + hdc:1, + :2, + hwp_peci:1, + :2, + hw_feedback:1, + :12; + uint32_t /* b */:32; + uint32_t /* c */ aperfmperf:1,=20 + :31; + uint32_t /* d */:32; + } pm; + uint64_t :64, :64; /* Leaf 0x7 - Structured Features. */ uint64_t :64, :64; /* Leaf 0x8 - rsvd */ uint64_t :64, :64; /* Leaf 0x9 - DCA */ --=20 2.51.2 -- Teddy Astie | Vates XCP-ng Developer XCP-ng & Xen Orchestra - Vates solutions web: https://vates.tech From nobody Thu Oct 30 00:19:35 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass header.i=teddy.astie@vates.tech; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=reject dis=none) header.from=vates.tech ARC-Seal: i=1; a=rsa-sha256; t=1761753602; cv=none; d=zohomail.com; s=zohoarc; b=EMVMYutjWl/rlf3JCqojh7FPGi2s96gecQso2cj5UFWq5HSjgvYdDkNgMIS05bvVOPHTCyIvECg/pHLdEiKB/4gN7Wh8bobJ3xXmylYIsvG12LVBn6J/zSR8rBhNMusyuoeKcNL2OG2vUduqdSncQAkFQ6+KbkYBnUMQBDgC1m0= ARC-Message-Signature: i=1; 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charset="utf-8" Intel provide CPU sensors through "DTS" MSRs. As there MSR are core-specific (or package-specific), we can't reliably fetch them from Dom0 directly. Expose these MSR (if supported) through XENPF_resource_op so that it is accessible through hypercall. Suggested-by: Jan Beulich Signed-off-by: Teddy Astie --- v2: - move DTS MSR out of legacy list, review MSR naming - use CPU policy instead of inline CPUID xen/arch/x86/include/asm/msr-index.h | 3 +++ xen/arch/x86/platform_hypercall.c | 6 ++++++ 2 files changed, 9 insertions(+) diff --git a/xen/arch/x86/include/asm/msr-index.h b/xen/arch/x86/include/as= m/msr-index.h index df52587c85..7c6af7bd4d 100644 --- a/xen/arch/x86/include/asm/msr-index.h +++ b/xen/arch/x86/include/asm/msr-index.h @@ -115,6 +115,9 @@ #define MCU_OPT_CTRL_GDS_MIT_DIS (_AC(1, ULL) << 4) #define MCU_OPT_CTRL_GDS_MIT_LOCK (_AC(1, ULL) << 5) =20 +#define MSR_DTS_TEMPERATURE_TARGET 0x000001a2 +#define MSR_DTS_PACKAGE_THERM_STATUS 0x000001b1 + #define MSR_FRED_RSP_SL0 0x000001cc #define MSR_FRED_RSP_SL1 0x000001cd #define MSR_FRED_RSP_SL2 0x000001ce diff --git a/xen/arch/x86/platform_hypercall.c b/xen/arch/x86/platform_hype= rcall.c index 79bb99e0b6..d9872ddd3e 100644 --- a/xen/arch/x86/platform_hypercall.c +++ b/xen/arch/x86/platform_hypercall.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include #include @@ -86,6 +87,11 @@ static bool msr_read_allowed(unsigned int msr) =20 case MSR_MCU_OPT_CTRL: return cpu_has_srbds_ctrl; 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charset="utf-8" get-intel-temp allows querying the per-core CPU temperature and per-package one on Intel processors (as usual Dom0 drivers cannot work due to misalignment between Dom0 vCPU and pCPUs). Signed-off-by: Teddy Astie --- v2: moved from a separate command to xenpm tools/misc/xenpm.c | 93 +++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 92 insertions(+), 1 deletion(-) diff --git a/tools/misc/xenpm.c b/tools/misc/xenpm.c index 682d092479..ef9abee48e 100644 --- a/tools/misc/xenpm.c +++ b/tools/misc/xenpm.c @@ -37,6 +37,7 @@ =20 static xc_interface *xc_handle; static unsigned int max_cpu_nr; +static xc_physinfo_t physinfo; =20 /* help message */ void show_help(void) @@ -93,6 +94,7 @@ void show_help(void) " units default to \= "us\" if unspecified.\n" " truncates un-repre= sentable values.\n" " 0 lets the hardwar= e decide.\n" + " get-intel-temp [cpuid] get Intel CPU temperatur= e of or all\n" " start [seconds] start collect Cx/Px stat= istics,\n" " output after CTRL-C or S= IGINT or several seconds.\n" " enable-turbo-mode [cpuid] enable Turbo Mode for pr= ocessors that support it.\n" @@ -1354,6 +1356,95 @@ void enable_turbo_mode(int argc, char *argv[]) errno, strerror(errno)); } =20 +#define MSR_DTS_THERM_STATUS 0x0000019c +#define MSR_DTS_TEMPERATURE_TARGET 0x000001a2 +#define MSR_DTS_PACKAGE_THERM_STATUS 0x000001b1 + +static int fetch_dts_temp(xc_interface *xch, uint32_t cpu, bool package, i= nt *temp) +{ + xc_resource_entry_t entries[2] =3D { + (xc_resource_entry_t){ + .idx =3D package ? MSR_DTS_PACKAGE_THERM_STATUS : MSR_DTS_THER= M_STATUS + }, + (xc_resource_entry_t){ .idx =3D MSR_DTS_TEMPERATURE_TARGET }, + }; + struct xc_resource_op ops =3D { + .cpu =3D cpu, + .entries =3D entries, + .nr_entries =3D 2, + }; + int tjmax; + + int ret =3D xc_resource_op(xch, 1, &ops); + + if ( ret <=3D 0 ) + /* This CPU isn't online or can't query this MSR */ + return ret ?: -EOPNOTSUPP; + + if ( ret =3D=3D 2 ) + tjmax =3D (entries[1].val >> 16) & 0xff; + else + { + /* + * The CPU doesn't support MSR_IA32_TEMPERATURE_TARGET, we assume = it's 100 which + * is correct aside a few selected Atom CPUs. Check coretemp sourc= e code for more + * information. + */ + fprintf(stderr, "[CPU%d] MSR_IA32_TEMPERATURE_TARGET is not suppor= ted, assume " + "tjmax=3D100=C2=B0C, readings may be incorrect\n", cpu); + tjmax =3D 100; + } + =20 + *temp =3D tjmax - ((entries[0].val >> 16) & 0xff); + return 0; +} + + +void get_intel_temp(int argc, char *argv[]) +{ + int temp, cpu =3D -1, socket; + bool has_data =3D false; + + if (argc > 0) + parse_cpuid(argv[0], &cpu); + + if (cpu !=3D -1) + { + if ( !fetch_dts_temp(xc_handle, cpu, false, &temp) ) + printf("CPU%d: %d=C2=B0C\n", cpu, temp); + else + printf("No data\n"); + return; + } + + /* Per socket measurement */ + for ( socket =3D 0, cpu =3D 0; cpu < max_cpu_nr; + socket++, cpu +=3D physinfo.cores_per_socket * physinfo.threads_= per_core ) + { + if ( !fetch_dts_temp(xc_handle, cpu, true, &temp) ) + { + has_data =3D true; + printf("Package%d: %d=C2=B0C\n", socket, temp); + } + } + + if ( has_data ) + /* Avoid inserting a trailing line if we have nothing */ + printf("\n"); + + for ( cpu =3D 0; cpu < max_cpu_nr; cpu +=3D physinfo.threads_per_core ) + { + if ( fetch_dts_temp(xc_handle, cpu, false, &temp) ) + continue; + + has_data =3D true; + printf("CPU%d: %d=C2=B0C\n", cpu, temp); + } + + if ( !has_data ) + printf("No data\n"); +} + void disable_turbo_mode(int argc, char *argv[]) { int cpuid =3D -1; @@ -1618,12 +1709,12 @@ struct { { "set-max-cstate", set_max_cstate_func}, { "enable-turbo-mode", enable_turbo_mode }, { "disable-turbo-mode", disable_turbo_mode }, + { "get-intel-temp", get_intel_temp }, }; =20 int main(int argc, char *argv[]) { int i, ret =3D 0; - xc_physinfo_t physinfo; int nr_matches =3D 0; int matches_main_options[ARRAY_SIZE(main_options)]; =20 --=20 2.51.2 -- Teddy Astie | Vates XCP-ng Developer XCP-ng & Xen Orchestra - Vates solutions web: https://vates.tech