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([94.75.70.14]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5334c75a2cbsm18101e87.187.2024.08.21.09.06.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Aug 2024 09:06:19 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 4ead5d6b-5fd7-11ef-8776-851b0ebba9a2 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1724256381; x=1724861181; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=MJcUmlEBhml/DSOe7/LwB7DMmIhQg2ECn/XQF26RxOQ=; b=aYMUKUWBVeIsGY0nZgav5EwgjquVY9n5ttkAYmXSNL2TQzkMDjqnGjN9VSJGn/iYhi H+vpBE3oTlFDH+0sHXDMajB4nejSw31t7CbvVPT1dJE5pLCqJOOWnI9bpgtVHMDKKgV4 jTA923/ab4drcg73lBeDEcMMAnjol9hWG7ZTraWI2sQ5TVVxVVFWYeCIMDVTOabl1+1m Ez+QtOzOIlxVGUWLvQMq/OXFME3LiSCuKEqRB0gP9ubPIRoKWwsasrsNmZ5Hr8t86Ewz IG2nFPCB6/zRNfcQGJ2/UE1qdcokaGAQUwHoYM+raELf+DnUX7GJS1X7J/B184e49qmq fo8A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1724256381; x=1724861181; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=MJcUmlEBhml/DSOe7/LwB7DMmIhQg2ECn/XQF26RxOQ=; b=J9wY0ER9ZEulATVrfapKMkDwfPAYyFKpfaw5oEK7S8KMgirsd1C62AxAFEnX50T0Ka Pajak1UHA4vOnbEI6mmHqdTXmcYKPgD2MKlDxLOVCoMEjy04zgjDUjwe0corS67lH3uw meQPk3aV1tFWw5FHNkIxQbHbE73SOQWyomxkh9Oio08g3c8Q0LGFlQMKiKbfQCgtqlU+ +gRDLzKroxw8OIH12OUPJD+xcHc+NFlabs01oZIlyxVaJQwTpuxrn++2SKy3k+pXv4Jh xKCnk50/2dZTUplulpXIRnkgeX02ppFA1sQ6VtNEDV6SmSWmYVTGJtLww/ZRQvNQDOcw B+bw== X-Gm-Message-State: AOJu0Ywg7NJnXNSQ7JSFz1oxHVO+z7IPoYGBPy/wEFEoU2JYLpJu1+Th mnxOWx95J9r6sTnMfBFoY4AJ1RaZ7ocYgWtvERM11VckecS1jaoOlNOwtA== X-Google-Smtp-Source: AGHT+IHNXlncZxBGdnzMvY3I4TMULDV+gDDUZIYPEq3r5sz55D2tBSipK/7C6CGpcJ+we/eb7sj4JQ== X-Received: by 2002:a05:6512:a91:b0:52f:ca2b:1d33 with SMTP id 2adb3069b0e04-53348551919mr1686167e87.20.1724256380111; Wed, 21 Aug 2024 09:06:20 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Alistair Francis , Bob Eshleman , Connor Davis , Andrew Cooper , Jan Beulich , Julien Grall , Stefano Stabellini Subject: [PATCH v5 1/7] xen/riscv: use {read,write}{b,w,l,q}_cpu() to define {read,write}_atomic() Date: Wed, 21 Aug 2024 18:06:10 +0200 Message-ID: <5140f9eb3d1cb0b69e3b1cbbcce6167ff8d59e4c.1724256026.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1724256416102116600 Content-Type: text/plain; charset="utf-8" In Xen, memory-ordered atomic operations are not necessary, based on {read,write}_atomic() implementations for other architectures. Therefore, {read,write}{b,w,l,q}_cpu() can be used instead of {read,write}{b,w,l,q}(), allowing the caller to decide if additional fences should be applied before or after {read,write}_atomic(). Change the declaration of _write_atomic() to accept a 'volatile void *' type for the 'x' argument instead of 'unsigned long'. This prevents compilation errors such as: 1."discards 'volatile' qualifier from pointer target type," which occurs due to the initialization of a volatile pointer, e.g., `volatile uint8_t *ptr =3D p;` in _add_sized(). 2."incompatible type for argument 2 of '_write_atomic'," which can occur when calling write_pte(), where 'x' is of type pte_t rather than unsigned long. Signed-off-by: Oleksii Kurochko --- Changes in v5: - new patch. --- xen/arch/riscv/include/asm/atomic.h | 25 +++++++++++-------------- 1 file changed, 11 insertions(+), 14 deletions(-) diff --git a/xen/arch/riscv/include/asm/atomic.h b/xen/arch/riscv/include/a= sm/atomic.h index 31b91a79c8..446c8c7928 100644 --- a/xen/arch/riscv/include/asm/atomic.h +++ b/xen/arch/riscv/include/asm/atomic.h @@ -31,21 +31,17 @@ =20 void __bad_atomic_size(void); =20 -/* - * Legacy from Linux kernel. For some reason they wanted to have ordered - * read/write access. Thereby read* is used instead of read*_cpu() - */ static always_inline void read_atomic_size(const volatile void *p, void *res, unsigned int size) { switch ( size ) { - case 1: *(uint8_t *)res =3D readb(p); break; - case 2: *(uint16_t *)res =3D readw(p); break; - case 4: *(uint32_t *)res =3D readl(p); break; + case 1: *(uint8_t *)res =3D readb_cpu(p); break; + case 2: *(uint16_t *)res =3D readw_cpu(p); break; + case 4: *(uint32_t *)res =3D readl_cpu(p); break; #ifndef CONFIG_RISCV_32 - case 8: *(uint32_t *)res =3D readq(p); break; + case 8: *(uint32_t *)res =3D readq_cpu(p); break; #endif default: __bad_atomic_size(); break; } @@ -58,15 +54,16 @@ static always_inline void read_atomic_size(const volati= le void *p, }) =20 static always_inline void _write_atomic(volatile void *p, - unsigned long x, unsigned int size) + volatile void *x, + unsigned int size) { switch ( size ) { - case 1: writeb(x, p); break; - case 2: writew(x, p); break; - case 4: writel(x, p); break; + case 1: writeb_cpu(*(uint8_t *)x, p); break; + case 2: writew_cpu(*(uint16_t *)x, p); break; + case 4: writel_cpu(*(uint32_t *)x, p); break; #ifndef CONFIG_RISCV_32 - case 8: writeq(x, p); break; + case 8: writeq_cpu(*(uint64_t *)x, p); break; #endif default: __bad_atomic_size(); break; } @@ -75,7 +72,7 @@ static always_inline void _write_atomic(volatile void *p, #define write_atomic(p, x) \ ({ \ typeof(*(p)) x_ =3D (x); \ - _write_atomic(p, x_, sizeof(*(p))); \ + _write_atomic(p, &x_, sizeof(*(p))); \ }) =20 static always_inline void _add_sized(volatile void *p, --=20 2.46.0 From nobody Sun Nov 24 04:23:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1724256416; cv=none; d=zohomail.com; s=zohoarc; b=dUtanQdh0cRYgQ5IjNHV+qNfrtKU9kE8k8KYP1aCorUQupK1EhWU9VS8x/yxsvVSeBKX5CS/vxq+h0LRJwmB2pUUdIw/pssFOkDP3VIsPh0GjMhM5Dn9+rSfeftxPy0S1Q+y4pYLzVsh//W609o5ySfaIQPoTFXSk45UKC+tL8Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1724256416; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=BLz0fdaEn9M6EZ8vs11WJaaTwf00UXtzFeAQe7wZRQI=; b=MJGEhZHyAWCq/6OhQrb0FQRkFLFl1iENGL0O7GyIlSzor73iIhfNtWDnwF/5dBXeMftWYJizNLez7CF09VRzGvh3guSXG6a+QOvtFWS4MM5FtB29IXiKm5HdEgZRaJKoKTIx5g2ErzzqecO/YwsFvtkpBgaUINhbzwryrb6DWwk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1724256416151839.8878634757676; Wed, 21 Aug 2024 09:06:56 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.781295.1190860 (Exim 4.92) (envelope-from ) id 1sgnqs-0004L0-Fy; Wed, 21 Aug 2024 16:06:26 +0000 Received: by outflank-mailman (output) from mailman id 781295.1190860; Wed, 21 Aug 2024 16:06:26 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1sgnqs-0004I8-80; Wed, 21 Aug 2024 16:06:26 +0000 Received: by outflank-mailman (input) for mailman id 781295; Wed, 21 Aug 2024 16:06:24 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1sgnqq-0003uu-6Z for xen-devel@lists.xenproject.org; Wed, 21 Aug 2024 16:06:24 +0000 Received: from mail-lf1-x12b.google.com (mail-lf1-x12b.google.com [2a00:1450:4864:20::12b]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 4f331334-5fd7-11ef-8776-851b0ebba9a2; Wed, 21 Aug 2024 18:06:22 +0200 (CEST) Received: by mail-lf1-x12b.google.com with SMTP id 2adb3069b0e04-52f04b4abdcso8743452e87.2 for ; Wed, 21 Aug 2024 09:06:22 -0700 (PDT) Received: from fedora.. ([94.75.70.14]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5334c75a2cbsm18101e87.187.2024.08.21.09.06.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Aug 2024 09:06:20 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 4f331334-5fd7-11ef-8776-851b0ebba9a2 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1724256382; x=1724861182; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=BLz0fdaEn9M6EZ8vs11WJaaTwf00UXtzFeAQe7wZRQI=; b=Nmu7JmS39P/F69yNrqtsZZFHoM39iDs3tEYrOU7gmqEB2EshWA930hWZPytP37KgDz To9v3pdQpYDTeb9QiP48MHjFQZLt6wgPMsTuzThTlJnjPeQE7XPlRZOpkebpwnTNbVvS NmC1nSGFDpbOnlWfBSuFvaHix0m3lx68XFN+JY3r9eK8w2ScRUaCQKrJYt71bfz0oeg3 36fIaASIHHfS17tOxiBcjX/j18UwVyyLa5PGVack93LBsx0f4bIMWtygrwpHB1+o7BOv n602xku6b4EtPa7ogT4YwON3TpHy4U7ZsOyL137b6wBzL2QNiNXmX8sdNOSVx3ODt79O 4EZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1724256382; x=1724861182; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BLz0fdaEn9M6EZ8vs11WJaaTwf00UXtzFeAQe7wZRQI=; b=nRj+nQ6mvu/tDajQ1DF7w7fKaNFF0forNyUkZgtkvl/xJYLZWopzG6kKPUhvEBHrgR iyHrUw+f9Pn8Ij6iUo61vvzE5EbqRXkIhp/FwSRlLcWiibWWExiVubLQ6gqH8KHeiUxL 78qXAqdMv/boIxIdR2S+lPDSqFBLjiaAOFHIJcl/tH6KkDXSNkNFQZal1l8BX4DF66Il o4vcD2qLdoy5nUdnq8P6vuxTYjp99Irct4eE0ZaiwW+sxZPQpkcmmhmenF7U301OHo7V BbglPPkCC/3Ta38Wl3vWdgxfTFHcmmGmGsjKKttWVGiNrtjOqKAVtsQMZK3LVSFo+kLu SpHA== X-Gm-Message-State: AOJu0YyfbzueBuY+o8580kbptSBcbp9kkQBFCJ+8Ejm9j6ua9gavhGYs 6n5aBeWktsRl27uAdUm3CGrEpCCDHS+Kw2K7G+CLlHqoHX/PUPVkqf9qnw== X-Google-Smtp-Source: AGHT+IFJURTseMyfZqkL6FC3Nxd7M5I4sZ5oyZNdRtXlsvM0rlWrb+UJIabg0mR98uJA9W0+HDtV5Q== X-Received: by 2002:a05:6512:3da1:b0:52e:98f6:c21f with SMTP id 2adb3069b0e04-533485515c7mr1994577e87.16.1724256380960; Wed, 21 Aug 2024 09:06:20 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Alistair Francis , Bob Eshleman , Connor Davis , Andrew Cooper , Jan Beulich , Julien Grall , Stefano Stabellini Subject: [PATCH v5 2/7] xen/riscv: set up fixmap mappings Date: Wed, 21 Aug 2024 18:06:11 +0200 Message-ID: <57e892d5b2c526dd44b68d4976796a25c0feca20.1724256027.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1724256418112116600 Content-Type: text/plain; charset="utf-8" Set up fixmap mappings and the L0 page table for fixmap support. Define new macros in riscv/config.h for calculating the FIXMAP_BASE address, including BOOT_FDT_VIRT_{START, SIZE}, XEN_VIRT_SIZE, and XEN_VIRT_END. Update the check for Xen size in riscv/lds.S to use XEN_VIRT_SIZE instead of a hardcoded constant. Signed-off-by: Oleksii Kurochko --- Changes in V5: - move definition of FIXMAP_ADDR() to asm/fixmap.h - add gap size equal to 2 MB ( 512 * 4K one page table entry in L1 page ta= ble ) between Xen, FDT and Fixmap. - drop the comment for FIX_LAST. - move +1 from FIX_LAST definition to FIXADDR_TOP to be aligned with Arm. ( probably everything below FIX_LAST will be moved to a separate header = in asm/generic.h ) - correct the "changes in V4: s/'fence r,r'/'fence rw, rw' - use write_atomic() in set_pte(). - introduce read_pte(). --- Changes in V4: - move definitions of XEN_VIRT_SIZE, BOOT_FDT_VIRT_{START,SIZE}, FIXMAP_{B= ASE,ADDR} below XEN_VIRT_START to have definitions appear in order. - define FIX_LAST as (FIX_MISC + 1) to have a guard slot at the end. - s/enumerated/numbered in the comment - update the cycle which looks for L1 page table in setup_fixmap_mapping_f= unction() and the comment above him. - drop fences inside write_pte() and put 'fence rw,rw' in setup_fixmap() b= efore sfence_vma(). - update the commit message - drop printk message inside setup_fixmap(). --- Changes in V3: - s/XEN_SIZE/XEN_VIRT_SIZE - drop usage of XEN_VIRT_END. - sort newly introduced defines in config.h by address - code style fixes - drop runtime check of that pte is valid as it was checked in L1 page tab= le finding cycle by BUG_ON(). - update implementation of write_pte() with FENCE rw, rw. - add BUILD_BUG_ON() to check that amount of entries aren't bigger then en= tries in page table. - drop set_fixmap, clear_fixmap declarations as they aren't used and defin= ed now - update the commit message. - s/__ASM_FIXMAP_H/ASM_FIXMAP_H - add SPDX-License-Identifier: GPL-2.0=20 --- xen/arch/riscv/include/asm/config.h | 15 ++++++++-- xen/arch/riscv/include/asm/fixmap.h | 46 +++++++++++++++++++++++++++++ xen/arch/riscv/include/asm/mm.h | 2 ++ xen/arch/riscv/include/asm/page.h | 13 ++++++++ xen/arch/riscv/mm.c | 43 +++++++++++++++++++++++++++ xen/arch/riscv/setup.c | 2 ++ xen/arch/riscv/xen.lds.S | 2 +- 7 files changed, 120 insertions(+), 3 deletions(-) create mode 100644 xen/arch/riscv/include/asm/fixmap.h diff --git a/xen/arch/riscv/include/asm/config.h b/xen/arch/riscv/include/a= sm/config.h index 50583aafdc..f55d6c45da 100644 --- a/xen/arch/riscv/include/asm/config.h +++ b/xen/arch/riscv/include/asm/config.h @@ -41,8 +41,10 @@ * Start addr | End addr | Slot | area description * =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D * ..... L2 511 Unused - * 0xffffffffc0600000 0xffffffffc0800000 L2 511 Fixmap - * 0xffffffffc0200000 0xffffffffc0600000 L2 511 FDT + * 0xffffffffc0A00000 0xffffffffc0C00000 L2 511 Fixmap + * ..... ( 2 MB gap ) + * 0xffffffffc0400000 0xffffffffc0800000 L2 511 FDT + * ..... ( 2 MB gap ) * 0xffffffffc0000000 0xffffffffc0200000 L2 511 Xen * ..... L2 510 Unused * 0x3200000000 0x7f40000000 L2 200-509 Direct map @@ -74,6 +76,15 @@ #error "unsupported RV_STAGE1_MODE" #endif =20 +#define GAP_SIZE MB(2) + +#define XEN_VIRT_SIZE MB(2) + +#define BOOT_FDT_VIRT_START (XEN_VIRT_START + XEN_VIRT_SIZE + GAP_SIZE) +#define BOOT_FDT_VIRT_SIZE MB(4) + +#define FIXMAP_BASE (BOOT_FDT_VIRT_START + BOOT_FDT_VIRT_SIZE = + GAP_SIZE) + #define DIRECTMAP_SLOT_END 509 #define DIRECTMAP_SLOT_START 200 #define DIRECTMAP_VIRT_START SLOTN(DIRECTMAP_SLOT_START) diff --git a/xen/arch/riscv/include/asm/fixmap.h b/xen/arch/riscv/include/a= sm/fixmap.h new file mode 100644 index 0000000000..63732df36c --- /dev/null +++ b/xen/arch/riscv/include/asm/fixmap.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * fixmap.h: compile-time virtual memory allocation + */ +#ifndef ASM_FIXMAP_H +#define ASM_FIXMAP_H + +#include +#include +#include + +#include + +#define FIXMAP_ADDR(n) (FIXMAP_BASE + (n) * PAGE_SIZE) + +/* Fixmap slots */ +#define FIX_PMAP_BEGIN (0) /* Start of PMAP */ +#define FIX_PMAP_END (FIX_PMAP_BEGIN + NUM_FIX_PMAP - 1) /* End of PMAP */ +#define FIX_MISC (FIX_PMAP_END + 1) /* Ephemeral mappings of hardware */ + +#define FIX_LAST FIX_MISC + +#define FIXADDR_START FIXMAP_ADDR(0) +#define FIXADDR_TOP FIXMAP_ADDR(FIX_LAST + 1) + +#ifndef __ASSEMBLY__ + +/* + * Direct access to xen_fixmap[] should only happen when {set, + * clear}_fixmap() is unusable (e.g. where we would end up to + * recursively call the helpers). + */ +extern pte_t xen_fixmap[]; + +#define fix_to_virt(slot) ((void *)FIXMAP_ADDR(slot)) + +static inline unsigned int virt_to_fix(vaddr_t vaddr) +{ + BUG_ON(vaddr >=3D FIXADDR_TOP || vaddr < FIXADDR_START); + + return ((vaddr - FIXADDR_START) >> PAGE_SHIFT); +} + +#endif /* __ASSEMBLY__ */ + +#endif /* ASM_FIXMAP_H */ diff --git a/xen/arch/riscv/include/asm/mm.h b/xen/arch/riscv/include/asm/m= m.h index 25af9e1aaa..a0bdc2bc3a 100644 --- a/xen/arch/riscv/include/asm/mm.h +++ b/xen/arch/riscv/include/asm/mm.h @@ -255,4 +255,6 @@ static inline unsigned int arch_get_dma_bitsize(void) return 32; /* TODO */ } =20 +void setup_fixmap_mappings(void); + #endif /* _ASM_RISCV_MM_H */ diff --git a/xen/arch/riscv/include/asm/page.h b/xen/arch/riscv/include/asm= /page.h index c831e16417..a7419b93b2 100644 --- a/xen/arch/riscv/include/asm/page.h +++ b/xen/arch/riscv/include/asm/page.h @@ -9,6 +9,7 @@ #include #include =20 +#include #include #include =20 @@ -81,6 +82,18 @@ static inline void flush_page_to_ram(unsigned long mfn, = bool sync_icache) BUG_ON("unimplemented"); } =20 +/* Write a pagetable entry. */ +static inline void write_pte(pte_t *p, pte_t pte) +{ + write_atomic(p, pte); +} + +/* Read a pagetable entry. */ +static inline pte_t read_pte(pte_t *p) +{ + return read_atomic(p); +} + #endif /* __ASSEMBLY__ */ =20 #endif /* _ASM_RISCV_PAGE_H */ diff --git a/xen/arch/riscv/mm.c b/xen/arch/riscv/mm.c index 7d09e781bf..b8ff91cf4e 100644 --- a/xen/arch/riscv/mm.c +++ b/xen/arch/riscv/mm.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include =20 @@ -49,6 +50,9 @@ stage1_pgtbl_root[PAGETABLE_ENTRIES]; pte_t __section(".bss.page_aligned") __aligned(PAGE_SIZE) stage1_pgtbl_nonroot[PGTBL_INITIAL_COUNT * PAGETABLE_ENTRIES]; =20 +pte_t __section(".bss.page_aligned") __aligned(PAGE_SIZE) +xen_fixmap[PAGETABLE_ENTRIES]; + #define HANDLE_PGTBL(curr_lvl_num) = \ index =3D pt_index(curr_lvl_num, page_addr); = \ if ( pte_is_valid(pgtbl[index]) ) = \ @@ -191,6 +195,45 @@ static bool __init check_pgtbl_mode_support(struct mmu= _desc *mmu_desc, return is_mode_supported; } =20 +void __init setup_fixmap_mappings(void) +{ + pte_t *pte, tmp; + unsigned int i; + + BUILD_BUG_ON(FIX_LAST >=3D PAGETABLE_ENTRIES); + + pte =3D &stage1_pgtbl_root[pt_index(HYP_PT_ROOT_LEVEL, FIXMAP_ADDR(0))= ]; + + /* + * In RISC-V page table levels are numbered from Lx to L0 where + * x is the highest page table level for currect MMU mode ( for examp= le, + * for Sv39 has 3 page tables so the x =3D 2 (L2 -> L1 -> L0) ). + * + * In this cycle we want to find L1 page table because as L0 page table + * xen_fixmap[] will be used. + */ + for ( i =3D HYP_PT_ROOT_LEVEL; i-- > 1; ) + { + BUG_ON(!pte_is_valid(*pte)); + + pte =3D (pte_t *)LOAD_TO_LINK(pte_to_paddr(*pte)); + pte =3D &pte[pt_index(i, FIXMAP_ADDR(0))]; + } + + BUG_ON(pte_is_valid(*pte)); + + tmp =3D paddr_to_pte(LINK_TO_LOAD((unsigned long)&xen_fixmap), PTE_TAB= LE); + write_pte(pte, tmp); + + RISCV_FENCE(rw, rw); + sfence_vma(); + + /* + * We only need the zeroeth table allocated, but not the PTEs set, bec= ause + * set_fixmap() will set them on the fly. + */ +} + /* * setup_initial_pagetables: * diff --git a/xen/arch/riscv/setup.c b/xen/arch/riscv/setup.c index 4defad68f4..13f0e8c77d 100644 --- a/xen/arch/riscv/setup.c +++ b/xen/arch/riscv/setup.c @@ -46,6 +46,8 @@ void __init noreturn start_xen(unsigned long bootcpu_id, test_macros_from_bug_h(); #endif =20 + setup_fixmap_mappings(); + printk("All set up\n"); =20 for ( ;; ) diff --git a/xen/arch/riscv/xen.lds.S b/xen/arch/riscv/xen.lds.S index 070b19d915..7a683f6065 100644 --- a/xen/arch/riscv/xen.lds.S +++ b/xen/arch/riscv/xen.lds.S @@ -181,6 +181,6 @@ ASSERT(!SIZEOF(.got.plt), ".got.plt non-empty") * Changing the size of Xen binary can require an update of * PGTBL_INITIAL_COUNT. */ -ASSERT(_end - _start <=3D MB(2), "Xen too large for early-boot assumptions= ") +ASSERT(_end - _start <=3D XEN_VIRT_SIZE, "Xen too large for early-boot ass= umptions") =20 ASSERT(_ident_end - _ident_start <=3D IDENT_AREA_SIZE, "identity region is= too big"); --=20 2.46.0 From nobody Sun Nov 24 04:23:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; 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([94.75.70.14]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5334c75a2cbsm18101e87.187.2024.08.21.09.06.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Aug 2024 09:06:21 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 4faece5b-5fd7-11ef-a508-bb4a2ccca743 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1724256382; x=1724861182; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=SUWnXdeASKM3s0vW7zMmdmova3lTcgmrVyUhj9D0sEQ=; b=m3j2xzRBYQz51sLqUih/NTDVf7/NSsJ4rTInJQ+Xarmkb191UgxucZ6zubyv98539m k3Ci529XmK335nFBOKLyXW71ZvUO+Y/PbnCyUnlZ5V28/dnnfWGHeotiiDFySHfmUxJ3 ioon6H4CjXdmnA96y1veJzJkSj/rTqS/a1Tw0EjhnQqu6y6OMXoZ3tPk3ZxKws3zBEP7 pg5rhlLuDuWxbiCK9//STWouHkc/+OtQM+1GTtddza0nGf99BoPKQJpdThXM6S2dGaS9 UsEACwAeW+Vh9ND5A/kBf31WcY11ecezUdDFQtTQdd2CnG+bjAdGWv4hHG/ria1shKxX DMsw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1724256382; x=1724861182; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=SUWnXdeASKM3s0vW7zMmdmova3lTcgmrVyUhj9D0sEQ=; b=lFDWd91FTkydXbgFtvEdgBjs/TsDUgoizTpJDqMr45HMK76vODA1tRuhC+j1WwyhAT XyFCyOmtWZhuy4+74LPtT8bEubyKvF18ClvL32CcCAZypQiE1cJNVKfbfPVu4ebrCk2M vc1VhGbw7JPYLjaSKVloZLAccUg3U6EDsNelJMj90M7FXg04lt3bg7IBYZAMTMPdCx6f +dLFMVF1sMDPniV4Dv5YkbfTgKP+zVa6ElBVh2C47rnkabojKYoEJV8zDf7P0wgyNKXF g1rvy0vOnH0neFpG+G4LXBlEIDEuQ2LaNZUNmJ2HrvbDbvdgtJ20EYIeWk/NU3358p6p Sk8g== X-Gm-Message-State: AOJu0YxAWxEUpL1sHLG1iG/x/Rgu7NhuoCdz0ohTqArKH16EooM75O4V d9eV/iFK8tzf7v5Gj1cTawt11updnoyqZ5OFG57fzHeQhi/9juP5pIAzYQ== X-Google-Smtp-Source: AGHT+IGly+3FqelWmnfZ4T6w26becCVTPBLUHuQXOh7Aci+pcMZxXbsLZRWwPuwV0jnSTRkjQ9mktg== X-Received: by 2002:a05:6512:1115:b0:52b:aae0:2d41 with SMTP id 2adb3069b0e04-5334caa4b27mr41128e87.28.1724256381689; Wed, 21 Aug 2024 09:06:21 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Alistair Francis , Bob Eshleman , Connor Davis , Andrew Cooper , Jan Beulich , Julien Grall , Stefano Stabellini Subject: [PATCH v5 3/7] xen/riscv: introduce asm/pmap.h header Date: Wed, 21 Aug 2024 18:06:12 +0200 Message-ID: X-Mailer: git-send-email 2.46.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1724256414099116600 Content-Type: text/plain; charset="utf-8" Introduce arch_pmap_{un}map functions and select HAS_PMAP for CONFIG_RISCV. Add pte_from_mfn() for use in arch_pmap_map(). Introduce flush_xen_tlb_one_local() and use it in arch_pmap_{un}map(). Signed-off-by: Oleksii Kurochko Reviewed-by: Jan Beulich --- Changes in V5: - Add Reviewed-by: Jan Beulich . - Fix a typo in "Changes in V4": - "drop flush_xen_tlb_range_va_local() as it isn't used in this patch" -> "drop flush_xen_tlb_range_va() as it isn't used in this patch" - "s/flush_xen_tlb_range_va_local/flush_tlb_range_va_local" -> "s/flush_xen_tlb_one_local/flush_tlb_one_local" --- Changes in V4: - mark arch_pmap_{un}map() as __init: documentation purpose and a necessary (but not sufficient) condition here, to validly use local TLB flushes only. - add flush_xen_tlb_one_local() to arch_pmap_map() as absense of "negative" TLB entrues will be guaranted only in the case when Svvptc extension is present. - s/mfn_from_pte/pte_from_mfn - drop mfn_to_xen_entry() as pte_from_mfn() does the same thing - add flags argument to pte_from_mfn(). - update the commit message. - drop flush_xen_tlb_range_va() as it isn't used in this patch - s/flush_xen_tlb_one_local/flush_tlb_one_local --- Changes in V3: - rename argument of function mfn_to_xen_entry(..., attr -> flags ). - update the code of mfn_to_xen_entry() to use flags argument. - add blank in mfn_from_pte() in return line. - introduce flush_xen_tlb_range_va_local() and use it inside arch_pmap_{un= }map(). - s/__ASM_PMAP_H__/ASM_PMAP_H - add SPDX-License-Identifier: GPL-2.0=20 --- xen/arch/riscv/Kconfig | 1 + xen/arch/riscv/include/asm/flushtlb.h | 6 +++++ xen/arch/riscv/include/asm/page.h | 6 +++++ xen/arch/riscv/include/asm/pmap.h | 36 +++++++++++++++++++++++++++ 4 files changed, 49 insertions(+) create mode 100644 xen/arch/riscv/include/asm/pmap.h diff --git a/xen/arch/riscv/Kconfig b/xen/arch/riscv/Kconfig index 259eea8d3b..0112aa8778 100644 --- a/xen/arch/riscv/Kconfig +++ b/xen/arch/riscv/Kconfig @@ -3,6 +3,7 @@ config RISCV select FUNCTION_ALIGNMENT_16B select GENERIC_BUG_FRAME select HAS_DEVICE_TREE + select HAS_PMAP =20 config RISCV_64 def_bool y diff --git a/xen/arch/riscv/include/asm/flushtlb.h b/xen/arch/riscv/include= /asm/flushtlb.h index 7ce32bea0b..f4a735fd6c 100644 --- a/xen/arch/riscv/include/asm/flushtlb.h +++ b/xen/arch/riscv/include/asm/flushtlb.h @@ -5,6 +5,12 @@ #include #include =20 +/* Flush TLB of local processor for address va. */ +static inline void flush_tlb_one_local(vaddr_t va) +{ + asm volatile ( "sfence.vma %0" :: "r" (va) : "memory" ); +} + /* * Filter the given set of CPUs, removing those that definitely flushed th= eir * TLB since @page_timestamp. diff --git a/xen/arch/riscv/include/asm/page.h b/xen/arch/riscv/include/asm= /page.h index a7419b93b2..55916eaa92 100644 --- a/xen/arch/riscv/include/asm/page.h +++ b/xen/arch/riscv/include/asm/page.h @@ -94,6 +94,12 @@ static inline pte_t read_pte(pte_t *p) return read_atomic(p); } =20 +static inline pte_t pte_from_mfn(mfn_t mfn, unsigned int flags) +{ + unsigned long pte =3D (mfn_x(mfn) << PTE_PPN_SHIFT) | flags; + return (pte_t){ .pte =3D pte }; +} + #endif /* __ASSEMBLY__ */ =20 #endif /* _ASM_RISCV_PAGE_H */ diff --git a/xen/arch/riscv/include/asm/pmap.h b/xen/arch/riscv/include/asm= /pmap.h new file mode 100644 index 0000000000..60065c996f --- /dev/null +++ b/xen/arch/riscv/include/asm/pmap.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef ASM_PMAP_H +#define ASM_PMAP_H + +#include +#include +#include +#include + +#include +#include +#include + +static inline void __init arch_pmap_map(unsigned int slot, mfn_t mfn) +{ + pte_t *entry =3D &xen_fixmap[slot]; + pte_t pte; + + ASSERT(!pte_is_valid(*entry)); + + pte =3D pte_from_mfn(mfn, PAGE_HYPERVISOR_RW); + write_pte(entry, pte); + + flush_tlb_one_local(FIXMAP_ADDR(slot)); +} + +static inline void __init arch_pmap_unmap(unsigned int slot) +{ + pte_t pte =3D {}; + + write_pte(&xen_fixmap[slot], pte); + + flush_tlb_one_local(FIXMAP_ADDR(slot)); +} + +#endif /* ASM_PMAP_H */ --=20 2.46.0 From nobody Sun Nov 24 04:23:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1724256411; cv=none; d=zohomail.com; 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([94.75.70.14]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5334c75a2cbsm18101e87.187.2024.08.21.09.06.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Aug 2024 09:06:22 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 50147560-5fd7-11ef-8776-851b0ebba9a2 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1724256383; x=1724861183; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=eIHhs5IXiWMtLXpZ4bVpcdEviO9myYu2vT9d0eE7bZY=; b=NrHgAFgaZGQ5NaUhdRTGs9gRRhpUjgWB/MXm2BqgaN9avVgaruc2/2CGnnu520KV8s MnnNZNyF/yrZMuDDKqqnzHHqNRknjcIo0Neoy8MFpfIJMenRUFq20K1mAH3M51LJMFjt 8JkRKcFmZg+x5Q5lviNbMN/uiucBUaFV6m94fj1VoZRXwBXvtiX5trjJJObZNZKRep6h 6HiJQX7Y9S9PN6OKYTVQNxmwjSHX3Z/dtqgTM8tfW8oMwP9ZqOASX4INI4tZcPPRnPmE 7HmWELLM0RlHzw51I/ZG61BC6vsyPzKJhZuTAe8Y0S1qIWqk8EcvwVvyy8zepuBk0OSv DYPQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1724256383; x=1724861183; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=eIHhs5IXiWMtLXpZ4bVpcdEviO9myYu2vT9d0eE7bZY=; b=F+q5Rwl5CnJf2Sd6NRfNDzN7jjFHA5OhMXJ9ExGtJY3izp6AaAPoCme2eMFNfeud/0 4qwBxq73QPl88yqa8zP9PCYRId185fZuo4GjwFC9K650m5saMIiIkkzRFE+EdxtRkF3H w8RtKVL0bgOJKqXn+/JvA9yYfG6L76dyvnHDoJJLEx06ttnEcKgKH/0tD/c/gogU8yg/ toJjeHhCsZkphjap9GOe93bctoBRt+bOP31L+IuR29ajqOUc5/NArEHWdI/m3URE5lyd 34RkpzWq9FYCWlf7zsn1W4VYj/iODgz07+ktVsjpgxKBWsV7z1J3XCltvbT21IEjd46w Bc5g== X-Gm-Message-State: AOJu0Yx9SseI4pP5KLbvUCSIK+esaBfmAZfzP4LrwmhUcQ2lbq6QsbEt svZDnyEodwDtT9a6Nrgr6HZyAOB3f2zAvaKLVIDD/2OsTz9MD+PSqSR4Qw== X-Google-Smtp-Source: AGHT+IG6t1lR0jPw4fuojzNy3cEPAh/mC8nhkhX+GydsIroadODO5JHSLlrqrXr7W6b2SoluyjhMnQ== X-Received: by 2002:a05:6512:b10:b0:52e:fc7b:39cb with SMTP id 2adb3069b0e04-533485599aamr1902798e87.26.1724256382485; Wed, 21 Aug 2024 09:06:22 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Alistair Francis , Bob Eshleman , Connor Davis , Andrew Cooper , Jan Beulich , Julien Grall , Stefano Stabellini Subject: [PATCH v5 4/7] xen/riscv: introduce functionality to work with CPU info Date: Wed, 21 Aug 2024 18:06:13 +0200 Message-ID: <03a703996ae7300a9eda54283711b19c42a7d116.1724256027.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1724256412097116600 Content-Type: text/plain; charset="utf-8" Introduce struct pcpu_info to store pCPU-related information. Initially, it includes only processor_id and hart id, but it will be extended to include guest CPU information and temporary variables for saving/restoring vCPU registers. Add set_processor_id() and get_processor_id() functions to set and retrieve the processor_id stored in pcpu_info. Introduce cpuid_to_hartid_map() to convert Xen logical CPUs to hart IDs (physical CPU IDs). Define smp_processor_id() to provide accurate information, replacing the previous "dummy" value of 0. Initialize tp registers to point to pcpu_info[0]. Set processor_id to 0 for logical CPU 0 and store the physical CPU ID in pcpu_info[0]. Signed-off-by: Oleksii Kurochko --- Changes in V5: - add hart_id to pcpu_info; - add comments to pcpu_info members. - define INVALID_HARTID as ULONG_MAX as mhart_id register has MXLEN which = is equal to 32 for RV-32 and 64 for RV-64. - add hart_id to pcpu_info structure. - drop cpuid_to_hartid_map[] and use pcpu_info[] for the same purpose. - introduce new function setup_tp(cpuid). - add the FIXME commit on top of pcpu_info[]. - setup TP register before start_xen() being called. - update the commit message. - change "commit message" to "comment" in "Changes in V4" in "update the c= omment above the code of TP..." --- Changes in V4: - wrap id with () inside set_processor_id(). - code style fixes - update BUG_ON(id > NR_CPUS) in smp_processor_id() and drop the comment above BUG_ON(). - s/__cpuid_to_hartid_map/cpuid_to_hartid_map - s/cpuid_to_hartid_map/cpuid_to_harti ( here cpuid_to_hartid_map is the n= ame of the macros ). - update the comment above the code of TP register initialization in start_xen(). - s/smp_setup_processor_id/smp_setup_bootcpu_id - update the commit message. - cleanup headers which are included in --- Changes in V3: - new patch. --- xen/arch/riscv/Makefile | 2 ++ xen/arch/riscv/include/asm/processor.h | 29 ++++++++++++++++++++++++-- xen/arch/riscv/include/asm/smp.h | 11 ++++++++++ xen/arch/riscv/riscv64/head.S | 4 ++++ xen/arch/riscv/setup.c | 5 +++++ xen/arch/riscv/smp.c | 21 +++++++++++++++++++ xen/arch/riscv/smpboot.c | 8 +++++++ 7 files changed, 78 insertions(+), 2 deletions(-) create mode 100644 xen/arch/riscv/smp.c create mode 100644 xen/arch/riscv/smpboot.c diff --git a/xen/arch/riscv/Makefile b/xen/arch/riscv/Makefile index 81b77b13d6..334fd24547 100644 --- a/xen/arch/riscv/Makefile +++ b/xen/arch/riscv/Makefile @@ -4,6 +4,8 @@ obj-y +=3D mm.o obj-$(CONFIG_RISCV_64) +=3D riscv64/ obj-y +=3D sbi.o obj-y +=3D setup.o +obj-y +=3D smp.o +obj-y +=3D smpboot.o obj-y +=3D stubs.o obj-y +=3D traps.o obj-y +=3D vm_event.o diff --git a/xen/arch/riscv/include/asm/processor.h b/xen/arch/riscv/includ= e/asm/processor.h index 3ae164c265..98c45afb6c 100644 --- a/xen/arch/riscv/include/asm/processor.h +++ b/xen/arch/riscv/include/asm/processor.h @@ -12,8 +12,33 @@ =20 #ifndef __ASSEMBLY__ =20 -/* TODO: need to be implemeted */ -#define smp_processor_id() 0 +#include + +register struct pcpu_info *tp asm ("tp"); + +struct pcpu_info { + unsigned int processor_id; /* Xen CPU id */ + unsigned long hart_id; /* physical CPU id */ +}; + +/* tp points to one of these */ +extern struct pcpu_info pcpu_info[NR_CPUS]; + +#define get_processor_id() (tp->processor_id) +#define set_processor_id(id) do { \ + tp->processor_id =3D (id); \ +} while (0) + +static inline unsigned int smp_processor_id(void) +{ + unsigned int id; + + id =3D get_processor_id(); + + BUG_ON(id > NR_CPUS); + + return id; +} =20 /* On stack VCPU state */ struct cpu_user_regs diff --git a/xen/arch/riscv/include/asm/smp.h b/xen/arch/riscv/include/asm/= smp.h index b1ea91b1eb..2b719616ee 100644 --- a/xen/arch/riscv/include/asm/smp.h +++ b/xen/arch/riscv/include/asm/smp.h @@ -5,6 +5,10 @@ #include #include =20 +#include + +#define INVALID_HARTID ULONG_MAX + DECLARE_PER_CPU(cpumask_var_t, cpu_sibling_mask); DECLARE_PER_CPU(cpumask_var_t, cpu_core_mask); =20 @@ -14,6 +18,13 @@ DECLARE_PER_CPU(cpumask_var_t, cpu_core_mask); */ #define park_offline_cpus false =20 +void smp_set_bootcpu_id(unsigned long boot_cpu_hartid); + +/* + * Mapping between linux logical cpu index and hartid. + */ +#define cpuid_to_hartid(cpu) pcpu_info[cpu].hart_id + #endif =20 /* diff --git a/xen/arch/riscv/riscv64/head.S b/xen/arch/riscv/riscv64/head.S index 3261e9fce8..9e5b9a0708 100644 --- a/xen/arch/riscv/riscv64/head.S +++ b/xen/arch/riscv/riscv64/head.S @@ -55,6 +55,10 @@ FUNC(start) */ jal reset_stack =20 + /* Xen's boot cpu id is equal to 0 so setup TP register for it */ + mv a0, x0 + jal setup_tp + /* restore hart_id ( bootcpu_id ) and dtb address */ mv a0, s0 mv a1, s1 diff --git a/xen/arch/riscv/setup.c b/xen/arch/riscv/setup.c index 13f0e8c77d..e15f34509c 100644 --- a/xen/arch/riscv/setup.c +++ b/xen/arch/riscv/setup.c @@ -8,6 +8,7 @@ #include =20 #include +#include #include =20 void arch_get_xen_caps(xen_capabilities_info_t *info) @@ -40,6 +41,10 @@ void __init noreturn start_xen(unsigned long bootcpu_id, { remove_identity_mapping(); =20 + set_processor_id(0); + + smp_set_bootcpu_id(bootcpu_id); + trap_init(); =20 #ifdef CONFIG_SELF_TESTS diff --git a/xen/arch/riscv/smp.c b/xen/arch/riscv/smp.c new file mode 100644 index 0000000000..478ea5aeab --- /dev/null +++ b/xen/arch/riscv/smp.c @@ -0,0 +1,21 @@ +#include + +/* + * FIXME: make pcpu_info[] dynamically allocated when necessary + * functionality will be ready + */ +/* tp points to one of these per cpu */ +struct pcpu_info pcpu_info[NR_CPUS] =3D { { 0, INVALID_HARTID } }; + +void setup_tp(unsigned int cpuid) +{ + /* + * tp register contains an address of physical cpu information. + * So write physical CPU info of cpuid to tp register. + * It will be used later by get_processor_id() ( look at + * ): + * #define get_processor_id() (tp->processor_id) + */ + asm volatile ( "mv tp, %0" + :: "r" ((unsigned long)&pcpu_info[cpuid]) : "memory" ); +} diff --git a/xen/arch/riscv/smpboot.c b/xen/arch/riscv/smpboot.c new file mode 100644 index 0000000000..34319f8875 --- /dev/null +++ b/xen/arch/riscv/smpboot.c @@ -0,0 +1,8 @@ +#include +#include +#include + +void __init smp_set_bootcpu_id(unsigned long boot_cpu_hartid) +{ + cpuid_to_hartid(0) =3D boot_cpu_hartid; +} --=20 2.46.0 From nobody Sun Nov 24 04:23:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; 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([94.75.70.14]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5334c75a2cbsm18101e87.187.2024.08.21.09.06.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Aug 2024 09:06:23 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 50985ebb-5fd7-11ef-a508-bb4a2ccca743 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1724256384; x=1724861184; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=0FpDkLbWKJAQ3CiJs4AaAzuGNEeRXZNpELOZW6xj11I=; b=iOctuW/oqjLEbz5oAoRlKz0CK+D7YMHCVkm4WPgJn0BdHqQzI/596wO8wJy8I+M5Nw AOtu5E/xeMFLgeOwCsHifrrHG1SpnnzFsIXipmQkB5tU9Gb29frAkkQpjY4mZHMQuAbm e/aUhdrYlNkfrOdDoqep07JuAevqr3E8n1r9a14iAekd0UY9+uMZBFFsjT//W0LKo5mH Yqp4XXAyuc794i7x2tIA9qefQuyr0YSGlDaeM3crd0gSUCUUkK2fUpIDThjHAyxvlhLl xrcLJEMaLztLUeendLydHGYLfKRo7pDpXg5upsuHynjkbMdpqgwcSVsmIxUSk3PvMpF7 59xQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1724256384; x=1724861184; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0FpDkLbWKJAQ3CiJs4AaAzuGNEeRXZNpELOZW6xj11I=; b=IwfuoS338Y2R0jVP5+qp7aaBix6AOSssgr1lTSXJFRyZMiOUV7j2eXWsKCrJD01n20 go7NBQBIJhY6WroHNIpceTkd7DxrvY3QbSUCHe9yLoQlQ+AoK55apu9qcBV1Aq/F/uY1 B0+UzVjW+joyhQvOOXx/i8r7IWtsFolh5EiNftedojfszK9SGZrL6qjqRvaPFprwHupU hu4PpWdeyWBRQM+YAhVFrBdl2ydea2t1wmb/HfVKGJr8oACgjH5iT0TPTrzYu36J2Uq/ JHPKBTSMGTTexVwQC4dV8oLNTnJET4xcp0IQdyt/0+J0H3x/l6YtY56nvGosQoxPxR/W kuog== X-Gm-Message-State: AOJu0YxaP5gC0qv3zCjNjDn++oJXTmgnunMhwHU9giioigCsHAzKSaUw HS6V3MCCW6EEuXiL83Me3U2wWG/PXmhhcExomXx+4MHhgn1PpoMgUAysfw== X-Google-Smtp-Source: AGHT+IHDSkBdGU14z0nurNEnNn+IlCY9hD/KtUz/3ycdD6y5OmmVKv9FNLxHQ6bKIEmQ2z6OMu8PPA== X-Received: by 2002:a05:6512:ba9:b0:533:45c9:67fe with SMTP id 2adb3069b0e04-533485d78dbmr2504042e87.48.1724256383343; Wed, 21 Aug 2024 09:06:23 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Alistair Francis , Bob Eshleman , Connor Davis , Andrew Cooper , Jan Beulich , Julien Grall , Stefano Stabellini Subject: [PATCH v5 5/7] xen/riscv: introduce and initialize SBI RFENCE extension Date: Wed, 21 Aug 2024 18:06:14 +0200 Message-ID: <69da9fc18b9987285e4037ef08714e8f9faa66a7.1724256027.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1724256418130116600 Content-Type: text/plain; charset="utf-8" Introduce functions to work with the SBI RFENCE extension for issuing various fence operations to remote CPUs. Add the sbi_init() function along with auxiliary functions and macro definitions for proper initialization and checking the availability of SBI extensions. Currently, this is implemented only for RFENCE. Introduce sbi_remote_sfence_vma() to send SFENCE_VMA instructions to a set of target HARTs. This will support the implementation of flush_xen_tlb_range_va(). Integrate __sbi_rfence_v02 from Linux kernel 6.6.0-rc4 with minimal modifications: - Adapt to Xen code style. - Use cpuid_to_hartid() instead of cpuid_to_hartid_map[]. - Update BIT(...) to BIT(..., UL). - Rename __sbi_rfence_v02_call to sbi_rfence_v02_real and remove the unused arg5. - Handle NULL cpu_mask to execute rfence on all CPUs by calling sbi_rfence_v02_real(..., 0UL, -1UL,...) instead of creating hmask. Signed-off-by: Oleksii Kurochko --- Changes in V5: - update the comment for sbi_has_rfence(). - update the comment for sbi_remote_sfence_vma(). - update the prototype of sbi_remote_sfence_vma() and declare cpu_mask argument as pointer to const. - use MASK_EXTR() for sbi_{major, minor}_version(). - redefine SBI_SPEC_VERSION_MAJOR_MASK as 0x7F000000 - drop SBI_SPEC_VERSION_MAJOR_SHIFT as unneeded. - add BUG_ON(ret.value < 0) inside sbi_ext_base_func() to be sure that ret.value is always >=3D 0 as SBI spec explicitly doesn't say that. - s/__sbi_rfence_v02_real/sbi_rfence_v02_real - s/__sbi_rfence_v02/sbi_rfence_v02 - s/__sbi_rfence/sbi_rfence - fold cases inside sbi_rfence_v02_real() - mark sbi_rfence_v02 with cf_check. - code style fixes in sbi_rfence_v02(). - add the comment with explanation of algorithm used in sbi_rfence_v02(). - use __ro_after_init for sbi_rfence variable. - add ASSERT(sbi_rfebce) inside sbi_remote_sfence_vma to be sure that it is not NULL. - drop local variable ret inside sbi_init() and init sbi_spec_version directly by return value of sbi_get_spec_version() as this function should always be must always succeed. - add the comment above sbi_get_spec_version(). - add BUG_ON for sbi_fw_id and sbi_fw_version() to be sure that they have correct values. - make sbi_fw_id, sbi_fw_version as local because they are used only once for printk(). - s/veriosn/version - drop BUG_ON("At the moment flush_xen_tlb_range_va() uses SBI rfence...") as now we have ASSERT() in the flace where sbi_rfence is actually used. - update the commit message. - s/BUG_ON("Ooops. SBI spec version 0.1 detected. Need to add support")/pa= nic("Ooops. SBI ..."); --- Changes in V4: - update the commit message. - code style fixes - update return type of sbi_has_rfence() from int to bool and drop conditional operator inside implementation. - Update mapping of SBI_ERR_FAILURE in sbi_err_map_xen_errno(). - Update return type of sbi_spec_is_0_1() and drop conditional operator inside implementation. - s/0x%lx/%#lx - update the comment above declaration of sbi_remote_sfence_vma() with more detailed explanation what the function does. - update prototype of sbi_remote_sfence_vma(). Now it receives cpumask_t and returns int. - refactor __sbi_rfence_v02() take from the Linux kernel as it takes into account a case that hart id could be from different hbase. For example, the case when hart IDs are the following 0, 3, 65, 2. Or the case when hart IDs are unsorted: 0 3 1 2. - drop sbi_cpumask_to_hartmask() as it is not needed anymore - Update the prototype of sbi_remote_sfence_vma() and implemntation accord= ingly to the fact it returns 'int'. - s/flush_xen_tlb_one_local/flush_tlb_one_local --- Changes in V3: - new patch. --- xen/arch/riscv/include/asm/sbi.h | 63 +++++++ xen/arch/riscv/sbi.c | 273 ++++++++++++++++++++++++++++++- xen/arch/riscv/setup.c | 3 + 3 files changed, 338 insertions(+), 1 deletion(-) diff --git a/xen/arch/riscv/include/asm/sbi.h b/xen/arch/riscv/include/asm/= sbi.h index 0e6820a4ed..76921d4cd1 100644 --- a/xen/arch/riscv/include/asm/sbi.h +++ b/xen/arch/riscv/include/asm/sbi.h @@ -12,8 +12,41 @@ #ifndef __ASM_RISCV_SBI_H__ #define __ASM_RISCV_SBI_H__ =20 +#include + #define SBI_EXT_0_1_CONSOLE_PUTCHAR 0x1 =20 +#define SBI_EXT_BASE 0x10 +#define SBI_EXT_RFENCE 0x52464E43 + +/* SBI function IDs for BASE extension */ +#define SBI_EXT_BASE_GET_SPEC_VERSION 0x0 +#define SBI_EXT_BASE_GET_IMP_ID 0x1 +#define SBI_EXT_BASE_GET_IMP_VERSION 0x2 +#define SBI_EXT_BASE_PROBE_EXT 0x3 + +/* SBI function IDs for RFENCE extension */ +#define SBI_EXT_RFENCE_REMOTE_FENCE_I 0x0 +#define SBI_EXT_RFENCE_REMOTE_SFENCE_VMA 0x1 +#define SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID 0x2 +#define SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA 0x3 +#define SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID 0x4 +#define SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA 0x5 +#define SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID 0x6 + +#define SBI_SPEC_VERSION_MAJOR_MASK 0x7F000000 +#define SBI_SPEC_VERSION_MINOR_MASK 0xffffff + +/* SBI return error codes */ +#define SBI_SUCCESS 0 +#define SBI_ERR_FAILURE (-1) +#define SBI_ERR_NOT_SUPPORTED (-2) +#define SBI_ERR_INVALID_PARAM (-3) +#define SBI_ERR_DENIED (-4) +#define SBI_ERR_INVALID_ADDRESS (-5) + +#define SBI_SPEC_VERSION_DEFAULT 0x1 + struct sbiret { long error; long value; @@ -31,4 +64,34 @@ struct sbiret sbi_ecall(unsigned long ext, unsigned long= fid, */ void sbi_console_putchar(int ch); =20 +/* + * Check underlying SBI implementation has RFENCE + * + * @return true for supported AND false for not-supported + */ +bool sbi_has_rfence(void); + +/* + * Instructs the remote harts to execute one or more SFENCE.VMA + * instructions, covering the range of virtual addresses between + * [start_addr, start_addr + size). + * + * Returns 0 if IPI was sent to all the targeted harts successfully + * or negative value if start_addr or size is not valid. + * + * @hart_mask a cpu mask containing all the target harts. + * @param start virtual address start + * @param size virtual address range size + */ +int sbi_remote_sfence_vma(const cpumask_t *cpu_mask, + unsigned long start_addr, + unsigned long size); + +/* + * Initialize SBI library + * + * @return 0 on success, otherwise negative errno on failure + */ +int sbi_init(void); + #endif /* __ASM_RISCV_SBI_H__ */ diff --git a/xen/arch/riscv/sbi.c b/xen/arch/riscv/sbi.c index 0ae166c861..c4036c8e4b 100644 --- a/xen/arch/riscv/sbi.c +++ b/xen/arch/riscv/sbi.c @@ -5,13 +5,26 @@ * (anup.patel@wdc.com). * * Modified by Bobby Eshleman (bobby.eshleman@gmail.com). + * Modified by Oleksii Kurochko (oleksii.kurochko@gmail.com). * * Copyright (c) 2019 Western Digital Corporation or its affiliates. - * Copyright (c) 2021-2023 Vates SAS. + * Copyright (c) 2021-2024 Vates SAS. */ =20 +#include +#include +#include +#include +#include +#include +#include +#include + +#include #include =20 +static unsigned long __ro_after_init sbi_spec_version =3D SBI_SPEC_VERSION= _DEFAULT; + struct sbiret sbi_ecall(unsigned long ext, unsigned long fid, unsigned long arg0, unsigned long arg1, unsigned long arg2, unsigned long arg3, @@ -38,7 +51,265 @@ struct sbiret sbi_ecall(unsigned long ext, unsigned lon= g fid, return ret; } =20 +static int sbi_err_map_xen_errno(int err) +{ + switch ( err ) + { + case SBI_SUCCESS: + return 0; + case SBI_ERR_DENIED: + return -EACCES; + case SBI_ERR_INVALID_PARAM: + return -EINVAL; + case SBI_ERR_INVALID_ADDRESS: + return -EFAULT; + case SBI_ERR_NOT_SUPPORTED: + return -EOPNOTSUPP; + case SBI_ERR_FAILURE: + fallthrough; + default: + return -ENOSYS; + }; +} + void sbi_console_putchar(int ch) { sbi_ecall(SBI_EXT_0_1_CONSOLE_PUTCHAR, 0, ch, 0, 0, 0, 0, 0); } + +static unsigned long sbi_major_version(void) +{ + return MASK_EXTR(sbi_spec_version, SBI_SPEC_VERSION_MAJOR_MASK); +} + +static unsigned long sbi_minor_version(void) +{ + return MASK_EXTR(sbi_spec_version, SBI_SPEC_VERSION_MINOR_MASK); +} + +static long sbi_ext_base_func(long fid) +{ + struct sbiret ret; + + ret =3D sbi_ecall(SBI_EXT_BASE, fid, 0, 0, 0, 0, 0, 0); + + /* + * I wasn't able to find a case in the SBI spec where sbiret.value + * could be negative. + * + * Unfortunately, the spec does not specify the possible values of + * sbiret.value, but based on the description of the SBI function, + * ret.value >=3D 0 when sbiret.error =3D 0. SPI spec specify only + * possible value for sbiret.error (<=3D 0 whwere 0 is SBI_SUCCESS ). + * + * Just to be sure that SBI base extension functions one day won't + * start to return a negative value for sbiret.value when + * sbiret.error < 0 BUG_ON() is added. + */ + BUG_ON(ret.value < 0); + + if ( !ret.error ) + return ret.value; + else + return ret.error; +} + +static int sbi_rfence_v02_real(unsigned long fid, + unsigned long hmask, unsigned long hbase, + unsigned long start, unsigned long size, + unsigned long arg4) +{ + struct sbiret ret =3D {0}; + int result =3D 0; + + switch ( fid ) + { + case SBI_EXT_RFENCE_REMOTE_FENCE_I: + ret =3D sbi_ecall(SBI_EXT_RFENCE, fid, hmask, hbase, + 0, 0, 0, 0); + break; + + case SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA: + case SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA: + case SBI_EXT_RFENCE_REMOTE_SFENCE_VMA: + ret =3D sbi_ecall(SBI_EXT_RFENCE, fid, hmask, hbase, + start, size, 0, 0); + break; + + case SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID: + case SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID: + case SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID: + ret =3D sbi_ecall(SBI_EXT_RFENCE, fid, hmask, hbase, + start, size, arg4, 0); + break; + + default: + printk("%s: unknown function ID [%lu]\n", + __func__, fid); + result =3D -EINVAL; + break; + }; + + if ( ret.error ) + { + result =3D sbi_err_map_xen_errno(ret.error); + printk("%s: hbase=3D%lu hmask=3D%#lx failed (error %d)\n", + __func__, hbase, hmask, result); + } + + return result; +} + +static int cf_check sbi_rfence_v02(unsigned long fid, + const cpumask_t *cpu_mask, + unsigned long start, unsigned long size, + unsigned long arg4, unsigned long arg5) +{ + unsigned long hartid, cpuid, hmask =3D 0, hbase =3D 0, htop =3D 0; + int result; + + /* + * hart_mask_base can be set to -1 to indicate that hart_mask can be + * ignored and all available harts must be considered. + */ + if ( !cpu_mask ) + return sbi_rfence_v02_real(fid, 0UL, -1UL, start, size, arg4); + + for_each_cpu ( cpuid, cpu_mask ) + { + /* + * Hart IDs might not necessarily be numbered contiguously in + * a multiprocessor system, but at least one hart must have a + * hart ID of zero. + * + * This means that it is possible for the hart ID mapping to look l= ike: + * 0, 1, 3, 65, 66, 69 + * In such cases, more than one call to sbi_rfence_v02_real() will = be + * needed, as a single hmask can only cover sizeof(unsigned long) C= PUs: + * 1. sbi_rfence_v02_real(hmask=3D0b1011, hbase=3D0) + * 2. sbi_rfence_v02_real(hmask=3D0b1011, hbase=3D65) + * + * The algorithm below tries to batch as many harts as possible bef= ore + * making an SBI call. However, batching may not always be possible. + * For example, consider the hart ID mapping: + * 0, 64, 1, 65, 2, 66 + */ + hartid =3D cpuid_to_hartid(cpuid); + if ( hmask ) + { + if ( hartid + BITS_PER_LONG <=3D htop || + hbase + BITS_PER_LONG <=3D hartid ) + { + result =3D sbi_rfence_v02_real(fid, hmask, hbase, + start, size, arg4); + if ( result ) + return result; + hmask =3D 0; + } + else if ( hartid < hbase ) + { + /* shift the mask to fit lower hartid */ + hmask <<=3D hbase - hartid; + hbase =3D hartid; + } + } + + if ( !hmask ) + { + hbase =3D hartid; + htop =3D hartid; + } + else if ( hartid > htop ) + htop =3D hartid; + + hmask |=3D BIT(hartid - hbase, UL); + } + + if ( hmask ) + { + result =3D sbi_rfence_v02_real(fid, hmask, hbase, + start, size, arg4); + if ( result ) + return result; + } + + return 0; +} + +static int (* __ro_after_init sbi_rfence)(unsigned long fid, + const cpumask_t *cpu_mask, + unsigned long start, + unsigned long size, + unsigned long arg4, + unsigned long arg5); + +int sbi_remote_sfence_vma(const cpumask_t *cpu_mask, + unsigned long start_addr, + unsigned long size) +{ + ASSERT(sbi_rfence); + + return sbi_rfence(SBI_EXT_RFENCE_REMOTE_SFENCE_VMA, + cpu_mask, start_addr, size, 0, 0); +} + +/* This function must always succeed. */ +#define sbi_get_spec_version() \ + sbi_ext_base_func(SBI_EXT_BASE_GET_SPEC_VERSION) + +#define sbi_get_firmware_id() \ + sbi_ext_base_func(SBI_EXT_BASE_GET_IMP_ID) + +#define sbi_get_firmware_version() \ + sbi_ext_base_func(SBI_EXT_BASE_GET_IMP_VERSION) + +int sbi_probe_extension(long extid) +{ + struct sbiret ret; + + ret =3D sbi_ecall(SBI_EXT_BASE, SBI_EXT_BASE_PROBE_EXT, extid, + 0, 0, 0, 0, 0); + if ( !ret.error && ret.value ) + return ret.value; + + return -EOPNOTSUPP; +} + +static bool sbi_spec_is_0_1(void) +{ + return (sbi_spec_version =3D=3D SBI_SPEC_VERSION_DEFAULT); +} + +bool sbi_has_rfence(void) +{ + return (sbi_rfence !=3D NULL); +} + +int __init sbi_init(void) +{ + sbi_spec_version =3D sbi_get_spec_version(); + + printk("SBI specification v%lu.%lu detected\n", + sbi_major_version(), sbi_minor_version()); + + if ( !sbi_spec_is_0_1() ) + { + long sbi_fw_id =3D sbi_get_firmware_id(); + long sbi_fw_version =3D sbi_get_firmware_version(); + + BUG_ON((sbi_fw_id < 0) || (sbi_fw_version < 0)); + + printk("SBI implementation ID=3D%#lx Version=3D%#lx\n", + sbi_fw_id, sbi_fw_version); + + if ( sbi_probe_extension(SBI_EXT_RFENCE) > 0 ) + { + sbi_rfence =3D sbi_rfence_v02; + printk("SBI v0.2 RFENCE extension detected\n"); + } + } + else + panic("Ooops. SBI spec version 0.1 detected. Need to add support"); + + return 0; +} diff --git a/xen/arch/riscv/setup.c b/xen/arch/riscv/setup.c index e15f34509c..f147ba672f 100644 --- a/xen/arch/riscv/setup.c +++ b/xen/arch/riscv/setup.c @@ -8,6 +8,7 @@ #include =20 #include +#include #include #include =20 @@ -47,6 +48,8 @@ void __init noreturn start_xen(unsigned long bootcpu_id, =20 trap_init(); =20 + sbi_init(); + #ifdef CONFIG_SELF_TESTS test_macros_from_bug_h(); #endif --=20 2.46.0 From nobody Sun Nov 24 04:23:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1724256418; cv=none; d=zohomail.com; s=zohoarc; b=XykZq6C4O7lfow5L4UCs1hWZsnJibIzgvoHr3uk6MaVFrVnH1JrKjyMK2F7RCq8KhTxLfj4jUwV+06APeQ4H5i2QslfpTJYkfF0y5dKjuQo7vzS6y17/gVZb35XkYdclYkY5+ST4BmxHmjVabuvwnJGEBIW616JcM/Lyd5TUh0g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1724256418; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=rDV1tsPkyyZ0s31JtDUobwApmNzZwqQvW5WKBrf+ijM=; b=fS2ajLh0axmUQLP+ozZNmOVaW01+DzlV2f7pdwHfwg81IySXWPkIdheFWNnsdmAf01etFKUeOrdRVo06qQm08K2pi4Gm78Kl3jW3LcKEFwT6sb2cJsKoY7av7eIaye0+HtLdW4StadRmlhEpOkGycrzT35KILqJ1tCd6QL06Kms= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 172425641896494.46956584519683; Wed, 21 Aug 2024 09:06:58 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.781298.1190895 (Exim 4.92) (envelope-from ) id 1sgnqv-0005Il-4s; Wed, 21 Aug 2024 16:06:29 +0000 Received: by outflank-mailman (output) from mailman id 781298.1190895; Wed, 21 Aug 2024 16:06:29 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1sgnqu-0005Gc-Qe; Wed, 21 Aug 2024 16:06:28 +0000 Received: by outflank-mailman (input) for mailman id 781298; Wed, 21 Aug 2024 16:06:27 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1sgnqs-0003sE-Te for xen-devel@lists.xenproject.org; Wed, 21 Aug 2024 16:06:27 +0000 Received: from mail-lf1-x134.google.com (mail-lf1-x134.google.com [2a00:1450:4864:20::134]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 5136678b-5fd7-11ef-a508-bb4a2ccca743; Wed, 21 Aug 2024 18:06:25 +0200 (CEST) Received: by mail-lf1-x134.google.com with SMTP id 2adb3069b0e04-5334c4cc17fso230257e87.2 for ; Wed, 21 Aug 2024 09:06:25 -0700 (PDT) Received: from fedora.. ([94.75.70.14]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5334c75a2cbsm18101e87.187.2024.08.21.09.06.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Aug 2024 09:06:23 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 5136678b-5fd7-11ef-a508-bb4a2ccca743 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1724256385; x=1724861185; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=rDV1tsPkyyZ0s31JtDUobwApmNzZwqQvW5WKBrf+ijM=; b=eeo05hGViEiI7CAgy6qEBQ/58vf4PMNICbjCCeVo7Bi9NOJsm6Qk/4C6E/XHxUeLQQ FN3gTivCdBsFvUiwUXsTsGsaMimPceyv3uwq3r1efkHT2qPRGKfWTFrh7ezwY3mvrFeq 5x0lHAxunRLNrMZzOYsSg6Mkj9hELUVERlXzHMF6DWIShDJVm29QdYl4tLC9SVJg01hJ wej8R5+RRr6w5PaqS8tOqyz72SHmJuQshGjmD9pqKsIekGQFrG3K6GLY3xpxfS7gDQUQ /7ExJq/qw3h5e+absQwXoNpQ+W7kwTa9MHdnbEYBFjeVRIwgHfbRkpWJ6cz3K8IURqps 4brA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1724256385; x=1724861185; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rDV1tsPkyyZ0s31JtDUobwApmNzZwqQvW5WKBrf+ijM=; b=qVhUkoe9Fi01o+OR12jst9+j5wL1fvFadDgz+zyWC4WDT0xpubDkNfFTolIKSeydOI nD80k3kR2vN74GjCgZ0NSuyx3KborGA1RoYU4tsK3r1pYwYxj6YoZjVu1Yheh+xwi4ji yNgT2wklq5p2ikRq4NzhEfWrJzGbO+k3JUlMHwUtUkS1shEz+8SMtlCA+8P6/JAugKg2 tkLp0ZStYQTwab3b+hFJwNcbDGkIc/U2YgnZ71gh20rv0FBZh3+Pw1uEItPLgxpCtc9l SNPNxYzxKHSk3Awjb7UdtNeBhIMXjnCkPo6YdxIGJYBrPlJQUq8EnrmpH2KZmE1GNqqd 8pew== X-Gm-Message-State: AOJu0YzREQ7H2d9+DLj8sxVVUSvAI4UFHwqVPE9MlUVPhOfUSWkZBgZM BUB1jOnsDyusXsduDF0KQctjc1ymq6ih1AHUTonzQnbbC4oDb1gnWJJdSg== X-Google-Smtp-Source: AGHT+IHkJMA6ZZyJm2XOTUKm9KDM2CMTVwxBL7LghDaYLdumE2y3Rrvrz3/hda0YCi9QCwZqzhEtbg== X-Received: by 2002:a05:6512:3f12:b0:52c:d819:517e with SMTP id 2adb3069b0e04-533485a6c58mr1902513e87.30.1724256384211; Wed, 21 Aug 2024 09:06:24 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Alistair Francis , Bob Eshleman , Connor Davis , Andrew Cooper , Jan Beulich , Julien Grall , Stefano Stabellini Subject: [PATCH v5 6/7] xen/riscv: page table handling Date: Wed, 21 Aug 2024 18:06:15 +0200 Message-ID: <090e617d88b279ae88f1a7859875a7e1a0c6ae73.1724256027.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1724256427733116600 Content-Type: text/plain; charset="utf-8" Implement map_pages_to_xen() which requires several functions to manage page tables and entries: - pt_update() - pt_mapping_level() - pt_update_entry() - pt_next_level() - pt_check_entry() To support these operations, add functions for creating, mapping, and unmapping Xen tables: - create_table() - map_table() - unmap_table() Introduce internal macros starting with PTE_* for convenience. These macros closely resemble PTE bits, with the exception of PTE_SMALL, which indicates that 4KB is needed. In addition introduce flush_tlb_range_va() for TLB flushing across CPUs after updating the PTE for the requested mapping. Signed-off-by: Oleksii Kurochko --- Changes in V5: - s/xen_{un}map/{un}map - introduce PTE_SMALL instead of PTE_BLOCK. - update the comment above defintion of PTE_4K_PAGES. - code style fixes. - s/RV_STAGE1_MODE > SATP_MODE_SV48/RV_STAGE1_MODE > SATP_MODE_SV39 around DECLARE_OFFSETS macros. - change type of root_maddr from unsgined long to maddr_t. - drop duplicated check ( if (rc) break ) in pt_update() inside while cycl= e. - s/1U/1UL - put 'spin_unlock(&xen_pt_lock);' ahead of TLB flush in pt_update(). - update the commit message. - update the comment above ASSERT() in map_pages_to_xen() and also update the check within ASSERT() to check that flags has PTE_VALID bit set. - update the comment above pt_update() function. - add the comment inside pt_check_entry(). - update the TLB flushing region in pt_update(). - s/alloc_only/alloc_tbl --- Changes in V4: - update the commit message. - drop xen_ prefix for functions: xen_pt_update(), xen_pt_mapping_level(), xen_pt_update_entry(), xen_pt_next_level(), xen_pt_check_entry(). - drop 'select GENERIC_PT' for CONFIG_RISCV. There is no GENERIC_PT anymor= e. - update implementation of flush_xen_tlb_range_va and s/flush_xen_tlb_rang= e_va/flush_tlb_range_va - s/pte_get_mfn/mfn_from_pte. Others similar definitions I decided not to = touch as they were introduced before and this patter of naming such type of macro= s will be applied for newly introduced macros. - drop _PAGE_* definitions and use analogues of PTE_*. - introduce PTE_{W,X,R}_MASK and drop PAGE_{XN,W,X}_MASK. Also drop _PAGE_= {*}_BIT - introduce PAGE_HYPERVISOR_RX. - drop unused now l3_table_offset. - drop struct pt_t as it was used only for one function. If it will be nee= ded in the future pt_t will be re-introduced. - code styles fixes in pte_is_table(). drop level argument from t. - update implementation and prototype of pte_is_mapping(). - drop level argument from pt_next_level(). - introduce definition of SATP_PPN_MASK. - isolate PPN of CSR_SATP before shift by PAGE_SHIFT. - drop set_permission() functions as it is not used more then once. - update prototype of pt_check_entry(): drop level argument as it is not u= sed. - pt_check_entry(): - code style fixes - update the sanity check when modifying an entry - update the sanity check when when removing a mapping. - s/read_only/alloc_only. - code style fixes for pt_next_level(). - pt_update_entry() changes: - drop arch_level variable inisde pt_update_entry() - drop convertion near virt to paddr_t in DECLARE_OFFSETS(offsets, virt); - pull out "goto out inside first 'for' cycle. - drop braces for 'if' cases which has only one line. - ident 'out' label with one blank. - update the comment above alloc_only and also definition to take into account that if pte population was requested or not. - drop target variable and rename arch_target argument of the function to target. - pt_mapping_level() changes: - move the check if PTE_BLOCK should be mapped on the top of the functio= n. - change int i to unsigned int and update 'for' cycle correspondingly. - update prototye of pt_update(): - drop the comment above nr_mfns and drop const to be consistent with o= ther arguments. - always flush TLB at the end of the function as non-present entries can= be put in the TLB. - add fence before TLB flush to ensure that PTEs are all updated before = flushing. - s/XEN_TABLE_NORMAL_PAGE/XEN_TABLE_NORMAL - add a check in map_pages_to_xen() the mfn is not INVALID_MFN. - add the comment on top of pt_update() how mfn =3D INVALID_MFN is conside= red. - s/_PAGE_BLOCK/PTE_BLOCK. - add the comment with additional explanation for PTE_BLOCK. - drop defintion of FIRST_SIZE as it isn't used. --- Changes in V3: - new patch. ( Technically it is reworked version of the generic approach which I tried to suggest in the previous version ) --- xen/arch/riscv/Makefile | 1 + xen/arch/riscv/include/asm/flushtlb.h | 12 + xen/arch/riscv/include/asm/mm.h | 2 + xen/arch/riscv/include/asm/page.h | 57 +++ xen/arch/riscv/include/asm/riscv_encoding.h | 1 + xen/arch/riscv/mm.c | 9 - xen/arch/riscv/pt.c | 420 ++++++++++++++++++++ 7 files changed, 493 insertions(+), 9 deletions(-) create mode 100644 xen/arch/riscv/pt.c diff --git a/xen/arch/riscv/Makefile b/xen/arch/riscv/Makefile index 334fd24547..d058ea4e95 100644 --- a/xen/arch/riscv/Makefile +++ b/xen/arch/riscv/Makefile @@ -1,6 +1,7 @@ obj-$(CONFIG_EARLY_PRINTK) +=3D early_printk.o obj-y +=3D entry.o obj-y +=3D mm.o +obj-y +=3D pt.o obj-$(CONFIG_RISCV_64) +=3D riscv64/ obj-y +=3D sbi.o obj-y +=3D setup.o diff --git a/xen/arch/riscv/include/asm/flushtlb.h b/xen/arch/riscv/include= /asm/flushtlb.h index f4a735fd6c..031d781aa2 100644 --- a/xen/arch/riscv/include/asm/flushtlb.h +++ b/xen/arch/riscv/include/asm/flushtlb.h @@ -5,12 +5,24 @@ #include #include =20 +#include + /* Flush TLB of local processor for address va. */ static inline void flush_tlb_one_local(vaddr_t va) { asm volatile ( "sfence.vma %0" :: "r" (va) : "memory" ); } =20 +/* + * Flush a range of VA's hypervisor mappings from the TLB of all + * processors in the inner-shareable domain. + */ +static inline void flush_tlb_range_va(vaddr_t va, size_t size) +{ + BUG_ON(!sbi_has_rfence()); + sbi_remote_sfence_vma(NULL, va, size); +} + /* * Filter the given set of CPUs, removing those that definitely flushed th= eir * TLB since @page_timestamp. diff --git a/xen/arch/riscv/include/asm/mm.h b/xen/arch/riscv/include/asm/m= m.h index a0bdc2bc3a..ce1557bb27 100644 --- a/xen/arch/riscv/include/asm/mm.h +++ b/xen/arch/riscv/include/asm/mm.h @@ -42,6 +42,8 @@ static inline void *maddr_to_virt(paddr_t ma) #define virt_to_mfn(va) __virt_to_mfn(va) #define mfn_to_virt(mfn) __mfn_to_virt(mfn) =20 +#define mfn_from_pte(pte) maddr_to_mfn(pte_to_paddr(pte)) + struct page_info { /* Each frame can be threaded onto a doubly-linked list. */ diff --git a/xen/arch/riscv/include/asm/page.h b/xen/arch/riscv/include/asm= /page.h index 55916eaa92..f148d82261 100644 --- a/xen/arch/riscv/include/asm/page.h +++ b/xen/arch/riscv/include/asm/page.h @@ -21,6 +21,11 @@ #define XEN_PT_LEVEL_MAP_MASK(lvl) (~(XEN_PT_LEVEL_SIZE(lvl) - 1)) #define XEN_PT_LEVEL_MASK(lvl) (VPN_MASK << XEN_PT_LEVEL_SHIFT(lvl)) =20 +/* + * PTE format: + * | XLEN-1 10 | 9 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 + * PFN reserved for SW D A G U X W R V + */ #define PTE_VALID BIT(0, UL) #define PTE_READABLE BIT(1, UL) #define PTE_WRITABLE BIT(2, UL) @@ -34,15 +39,53 @@ #define PTE_LEAF_DEFAULT (PTE_VALID | PTE_READABLE | PTE_WRITAB= LE) #define PTE_TABLE (PTE_VALID) =20 +#define PAGE_HYPERVISOR_RO (PTE_VALID | PTE_READABLE) #define PAGE_HYPERVISOR_RW (PTE_VALID | PTE_READABLE | PTE_WRITAB= LE) +#define PAGE_HYPERVISOR_RX (PTE_VALID | PTE_READABLE | PTE_EXECUT= ABLE) =20 #define PAGE_HYPERVISOR PAGE_HYPERVISOR_RW =20 +/* + * The PTE format does not contain the following bits within itself; + * they are created artificially to inform the Xen page table + * handling algorithm. These bits should not be explicitly written + * to the PTE entry. + */ +#define PTE_SMALL BIT(10, UL) +#define PTE_POPULATE BIT(11, UL) + +#define PTE_R_MASK(x) ((x) & PTE_READABLE) +#define PTE_W_MASK(x) ((x) & PTE_WRITABLE) +#define PTE_X_MASK(x) ((x) & PTE_EXECUTABLE) + +#define PTE_RWX_MASK(x) ((x) & (PTE_READABLE | PTE_WRITABLE | PTE_EXECUTAB= LE)) + /* Calculate the offsets into the pagetables for a given VA */ #define pt_linear_offset(lvl, va) ((va) >> XEN_PT_LEVEL_SHIFT(lvl)) =20 #define pt_index(lvl, va) (pt_linear_offset((lvl), (va)) & VPN_MASK) =20 +#define PAGETABLE_ORDER_MASK ((_AC(1, U) << PAGETABLE_ORDER) - 1) +#define TABLE_OFFSET(offs) (_AT(unsigned int, offs) & PAGETABLE_ORDER_MASK) + +#if RV_STAGE1_MODE > SATP_MODE_SV39 +#error "need to to update DECLARE_OFFSETS macros" +#else + +#define l0_table_offset(va) TABLE_OFFSET(pt_linear_offset(0, va)) +#define l1_table_offset(va) TABLE_OFFSET(pt_linear_offset(1, va)) +#define l2_table_offset(va) TABLE_OFFSET(pt_linear_offset(2, va)) + +/* Generate an array @var containing the offset for each level from @addr = */ +#define DECLARE_OFFSETS(var, addr) \ + const unsigned int var[] =3D { \ + l0_table_offset(addr), \ + l1_table_offset(addr), \ + l2_table_offset(addr), \ + } + +#endif + /* Page Table entry */ typedef struct { #ifdef CONFIG_RISCV_64 @@ -68,6 +111,20 @@ static inline bool pte_is_valid(pte_t p) return p.pte & PTE_VALID; } =20 +inline bool pte_is_table(const pte_t p) +{ + return ((p.pte & (PTE_VALID | + PTE_READABLE | + PTE_WRITABLE | + PTE_EXECUTABLE)) =3D=3D PTE_VALID); +} + +static inline bool pte_is_mapping(const pte_t p) +{ + return (p.pte & PTE_VALID) && + (p.pte & (PTE_WRITABLE | PTE_EXECUTABLE)); +} + static inline void invalidate_icache(void) { BUG_ON("unimplemented"); diff --git a/xen/arch/riscv/include/asm/riscv_encoding.h b/xen/arch/riscv/i= nclude/asm/riscv_encoding.h index 58abe5eccc..d80cef0093 100644 --- a/xen/arch/riscv/include/asm/riscv_encoding.h +++ b/xen/arch/riscv/include/asm/riscv_encoding.h @@ -164,6 +164,7 @@ #define SSTATUS_SD SSTATUS64_SD #define SATP_MODE SATP64_MODE #define SATP_MODE_SHIFT SATP64_MODE_SHIFT +#define SATP_PPN_MASK _UL(0x00000FFFFFFFFFFF) =20 #define HGATP_PPN HGATP64_PPN #define HGATP_VMID_SHIFT HGATP64_VMID_SHIFT diff --git a/xen/arch/riscv/mm.c b/xen/arch/riscv/mm.c index b8ff91cf4e..e8430def14 100644 --- a/xen/arch/riscv/mm.c +++ b/xen/arch/riscv/mm.c @@ -369,12 +369,3 @@ int destroy_xen_mappings(unsigned long s, unsigned lon= g e) BUG_ON("unimplemented"); return -1; } - -int map_pages_to_xen(unsigned long virt, - mfn_t mfn, - unsigned long nr_mfns, - unsigned int flags) -{ - BUG_ON("unimplemented"); - return -1; -} diff --git a/xen/arch/riscv/pt.c b/xen/arch/riscv/pt.c new file mode 100644 index 0000000000..15eb02fe9e --- /dev/null +++ b/xen/arch/riscv/pt.c @@ -0,0 +1,420 @@ +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +static inline const mfn_t get_root_page(void) +{ + paddr_t root_maddr =3D (csr_read(CSR_SATP) & SATP_PPN_MASK) << PAGE_SH= IFT; + + return maddr_to_mfn(root_maddr); +} + +/* Sanity check of the entry. */ +static bool pt_check_entry(pte_t entry, mfn_t mfn, unsigned int flags) +{ + /* + * See the comment about the possible combination of (mfn, flags) in + * the comment above pt_update(). + */ + + /* Sanity check when modifying an entry. */ + if ( (flags & PTE_VALID) && mfn_eq(mfn, INVALID_MFN) ) + { + /* We don't allow modifying an invalid entry. */ + if ( !pte_is_valid(entry) ) + { + printk("Modifying invalid entry is not allowed.\n"); + return false; + } + + /* We don't allow modifying a table entry */ + if ( pte_is_table(entry) ) + { + printk("Modifying a table entry is not allowed.\n"); + return false; + } + } + /* Sanity check when inserting a mapping */ + else if ( flags & PTE_VALID ) + { + /* We should be here with a valid MFN. */ + ASSERT(!mfn_eq(mfn, INVALID_MFN)); + + /* + * We don't allow replacing any valid entry. + * + * Note that the function pt_update() relies on this + * assumption and will skip the TLB flush (when Svvptc + * extension will be ratified). The function will need + * to be updated if the check is relaxed. + */ + if ( pte_is_valid(entry) ) + { + if ( pte_is_mapping(entry) ) + printk("Changing MFN for a valid entry is not allowed (%#"= PRI_mfn" -> %#"PRI_mfn").\n", + mfn_x(mfn_from_pte(entry)), mfn_x(mfn)); + else + printk("Trying to replace a table with a mapping.\n"); + return false; + } + } + /* Sanity check when removing a mapping. */ + else if ( (flags & (PTE_VALID | PTE_POPULATE)) =3D=3D 0 ) + { + /* We should be here with an invalid MFN. */ + ASSERT(mfn_eq(mfn, INVALID_MFN)); + + /* We don't allow removing a table */ + if ( pte_is_table(entry) ) + { + printk("Removing a table is not allowed.\n"); + return false; + } + } + /* Sanity check when populating the page-table. No check so far. */ + else + { + ASSERT(flags & PTE_POPULATE); + /* We should be here with an invalid MFN */ + ASSERT(mfn_eq(mfn, INVALID_MFN)); + } + + return true; +} + +static pte_t *map_table(mfn_t mfn) +{ + /* + * During early boot, map_domain_page() may be unusable. Use the + * PMAP to map temporarily a page-table. + */ + if ( system_state =3D=3D SYS_STATE_early_boot ) + return pmap_map(mfn); + + return map_domain_page(mfn); +} + +static void unmap_table(const pte_t *table) +{ + /* + * During early boot, map_table() will not use map_domain_page() + * but the PMAP. + */ + if ( system_state =3D=3D SYS_STATE_early_boot ) + pmap_unmap(table); + else + unmap_domain_page(table); +} + +static int create_table(pte_t *entry) +{ + mfn_t mfn; + void *p; + pte_t pte; + + if ( system_state !=3D SYS_STATE_early_boot ) + { + struct page_info *pg =3D alloc_domheap_page(NULL, 0); + + if ( pg =3D=3D NULL ) + return -ENOMEM; + + mfn =3D page_to_mfn(pg); + } + else + mfn =3D alloc_boot_pages(1, 1); + + p =3D map_table(mfn); + clear_page(p); + unmap_table(p); + + pte =3D pte_from_mfn(mfn, PTE_TABLE); + write_pte(entry, pte); + + return 0; +} + +#define XEN_TABLE_MAP_FAILED 0 +#define XEN_TABLE_SUPER_PAGE 1 +#define XEN_TABLE_NORMAL 2 + +/* + * Take the currently mapped table, find the corresponding entry, + * and map the next table, if available. + * + * The alloc_tbl parameters indicates whether intermediate tables should + * be allocated when not present. + * + * Return values: + * XEN_TABLE_MAP_FAILED: Either alloc_only was set and the entry + * was empty, or allocating a new page failed. + * XEN_TABLE_NORMAL: next level or leaf mapped normally + * XEN_TABLE_SUPER_PAGE: The next entry points to a superpage. + */ +static int pt_next_level(bool alloc_tbl, pte_t **table, unsigned int offse= t) +{ + pte_t *entry; + int ret; + mfn_t mfn; + + entry =3D *table + offset; + + if ( !pte_is_valid(*entry) ) + { + if ( alloc_tbl ) + return XEN_TABLE_MAP_FAILED; + + ret =3D create_table(entry); + if ( ret ) + return XEN_TABLE_MAP_FAILED; + } + + if ( pte_is_mapping(*entry) ) + return XEN_TABLE_SUPER_PAGE; + + mfn =3D mfn_from_pte(*entry); + + unmap_table(*table); + *table =3D map_table(mfn); + + return XEN_TABLE_NORMAL; +} + +/* Update an entry at the level @target. */ +static int pt_update_entry(mfn_t root, unsigned long virt, + mfn_t mfn, unsigned int target, + unsigned int flags) +{ + int rc; + unsigned int level =3D HYP_PT_ROOT_LEVEL; + pte_t *table; + /* + * The intermediate page table shouldn't be allocated when MFN isn't + * valid and we are not populating page table. + * This means we either modify permissions or remove an entry, or + * inserting brand new entry. + * + * See the comment above pt_update() for an additional explanation abo= ut + * combinations of (mfn, flags). + */ + bool alloc_tbl =3D mfn_eq(mfn, INVALID_MFN) && !(flags & PTE_POPULATE); + pte_t pte, *entry; + + /* convenience aliases */ + DECLARE_OFFSETS(offsets, virt); + + table =3D map_table(root); + for ( ; level > target; level-- ) + { + rc =3D pt_next_level(alloc_tbl, &table, offsets[level]); + if ( rc =3D=3D XEN_TABLE_MAP_FAILED ) + { + rc =3D 0; + + /* + * We are here because pt_next_level has failed to map + * the intermediate page table (e.g the table does not exist + * and the pt is read-only). It is a valid case when + * removing a mapping as it may not exist in the page table. + * In this case, just ignore it. + */ + if ( flags & PTE_VALID ) + { + printk("%s: Unable to map level %u\n", __func__, level); + rc =3D -ENOENT; + } + + goto out; + } + else if ( rc !=3D XEN_TABLE_NORMAL ) + break; + } + + if ( level !=3D target ) + { + printk("%s: Shattering superpage is not supported\n", __func__); + rc =3D -EOPNOTSUPP; + goto out; + } + + entry =3D table + offsets[level]; + + rc =3D -EINVAL; + if ( !pt_check_entry(*entry, mfn, flags) ) + goto out; + + /* We are removing the page */ + if ( !(flags & PTE_VALID) ) + memset(&pte, 0x00, sizeof(pte)); + else + { + /* We are inserting a mapping =3D> Create new pte. */ + if ( !mfn_eq(mfn, INVALID_MFN) ) + pte =3D pte_from_mfn(mfn, PTE_VALID); + else /* We are updating the permission =3D> Copy the current pte. = */ + pte =3D *entry; + + /* update permission according to the flags */ + pte.pte |=3D PTE_RWX_MASK(flags) | PTE_ACCESSED | PTE_DIRTY; + } + + write_pte(entry, pte); + + rc =3D 0; + + out: + unmap_table(table); + + return rc; +} + +/* Return the level where mapping should be done */ +static int pt_mapping_level(unsigned long vfn, mfn_t mfn, unsigned long nr, + unsigned int flags) +{ + unsigned int level =3D 0; + unsigned long mask; + unsigned int i; + + /* Use blocking mapping unless the caller requests 4K mapping */ + if ( unlikely(flags & PTE_SMALL) ) + return level; + + /* + * Don't take into account the MFN when removing mapping (i.e + * MFN_INVALID) to calculate the correct target order. + * + * `vfn` and `mfn` must be both superpage aligned. + * They are or-ed together and then checked against the size of + * each level. + * + * `left` is not included and checked separately to allow + * superpage mapping even if it is not properly aligned (the + * user may have asked to map 2MB + 4k). + */ + mask =3D !mfn_eq(mfn, INVALID_MFN) ? mfn_x(mfn) : 0; + mask |=3D vfn; + + for ( i =3D HYP_PT_ROOT_LEVEL; i !=3D 0; i-- ) + { + if ( !(mask & (BIT(XEN_PT_LEVEL_ORDER(i), UL) - 1)) && + (nr >=3D BIT(XEN_PT_LEVEL_ORDER(i), UL)) ) + { + level =3D i; + break; + } + } + + return level; +} + +static DEFINE_SPINLOCK(xen_pt_lock); + +/* + * If `mfn` equals `INVALID_MFN`, it indicates that the following page tab= le + * update operation might be related to either populating the table ( + * PTE_POPULATE will be set additionaly), destroying a mapping, or modifyi= ng + * an existing mapping. + * + * If `mfn` is valid and flags has PTE_VALID bit set then it means that + * inserting will be done. + */ +static int pt_update(unsigned long virt, + mfn_t mfn, + unsigned long nr_mfns, + unsigned int flags) +{ + int rc =3D 0; + unsigned long vfn =3D virt >> PAGE_SHIFT; + unsigned long left =3D nr_mfns; + + const mfn_t root =3D get_root_page(); + + /* + * It is bad idea to have mapping both writeable and + * executable. + * When modifying/creating mapping (i.e PTE_VALID is set), + * prevent any update if this happen. + */ + if ( (flags & PTE_VALID) && PTE_W_MASK(flags) && PTE_X_MASK(flags) ) + { + printk("Mappings should not be both Writeable and Executable.\n"); + return -EINVAL; + } + + if ( !IS_ALIGNED(virt, PAGE_SIZE) ) + { + printk("The virtual address is not aligned to the page-size.\n"); + return -EINVAL; + } + + spin_lock(&xen_pt_lock); + + while ( left ) + { + unsigned int order, level; + + level =3D pt_mapping_level(vfn, mfn, left, flags); + order =3D XEN_PT_LEVEL_ORDER(level); + + ASSERT(left >=3D BIT(order, UL)); + + rc =3D pt_update_entry(root, vfn << PAGE_SHIFT, mfn, level, flags); + if ( rc ) + break; + + vfn +=3D 1UL << order; + if ( !mfn_eq(mfn, INVALID_MFN) ) + mfn =3D mfn_add(mfn, 1UL << order); + + left -=3D (1UL << order); + } + + /* Ensure that PTEs are all updated before flushing */ + RISCV_FENCE(rw, rw); + + spin_unlock(&xen_pt_lock); + + /* + * Always flush TLB at the end of the function as non-present entries + * can be put in the TLB. + * + * The remote fence operation applies to the entire address space if + * either: + * - start and size are both 0, or + * - size is equal to 2^XLEN-1. + * + * TODO: come up with something which will allow not to flash the enti= re + * address space. + */ + flush_tlb_range_va(0, 0); + + return rc; +} + +int map_pages_to_xen(unsigned long virt, + mfn_t mfn, + unsigned long nr_mfns, + unsigned int flags) +{ + /* + * Ensure that flags has PTE_VALID bit as map_pages_to_xen() is suppos= ed + * to create a mapping. + * + * Ensure that we have a valid MFN before proceeding. + * + * If the MFN is invalid, pt_update() might misinterpret the operation, + * treating it as either a population, a mapping destruction, + * or a mapping modification. + */ + ASSERT(!mfn_eq(mfn, INVALID_MFN) || (flags & PTE_VALID)); + + return pt_update(virt, mfn, nr_mfns, flags); +} --=20 2.46.0 From nobody Sun Nov 24 04:23:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; 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([94.75.70.14]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5334c75a2cbsm18101e87.187.2024.08.21.09.06.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Aug 2024 09:06:24 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 518bb267-5fd7-11ef-8776-851b0ebba9a2 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1724256386; x=1724861186; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=r+WwxRSxk0qCYUDqFKxcxr8bTjqN9cnWLzbcX46CN8Q=; b=nfXcXXqZRgsY/pNqgs76Eq8QzdlIYiHPAu6UnbTNYlYOXYMlVbUcgHFfImms2V3ebB nP5te9gk9oZfTt+R2Y81mtHRqSsMrGx5xsQf+oPfya/gjxr7o4nodHzWQduifLONzieo apGKgL2dWD2xWXnaVVPKIwLCuf7ZSYPsVaV8ARWvM0NdAz7kNbM2E3+duwccaG0zSfkq qlC6V1yHH9lvxOr3y5qa1MjnvQZ+q03gD2y93wHiFkmPrmCLr6OTn27116tD4Z3dLvcX TiPm56vDjNtiGIVe6pU4UBwcCY1oDth1FgXONfr5OCMScHMk/9/XQ6aPA8TAtInxbvUS uTNQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1724256386; x=1724861186; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=r+WwxRSxk0qCYUDqFKxcxr8bTjqN9cnWLzbcX46CN8Q=; b=XrDJuKG/AGd8srfOOZ9DPwziyuXYLmOgOkfVx/Q27kFX1WO6xS9TR07A/qeeiCdXKI Px0+dEtvNUuYTZ47Fh+wMBbqzGI7PlLZhJP/2jsjW2aGLavRgoOVfjGTfFNJJ5mhbK6V CmfGOFILsz/hTj0bHpbbmkFv3qJF1H2ChFHDqcpbZkVcS5gEQDoAb/k/zo3k5XO98juy aiLv92FzLdyXhyrI1WWIQ9GUO6hDnY2KHgeRCxey0Lb6tsjAcIbjbEaOuH5Vj/LpBqxE wNbmV7WgjL8kyy7puDGNy5BvToiNPL+rYQxrWZd/fvAQ1QWL2IO+c7mtzDNMPbLgspL0 ax5A== X-Gm-Message-State: AOJu0YzHjFw51JNiX+xem4TKMflq1/8vsAj09G9/QxJV9CTpx9l6DehG LJu/n9NDhxii9FymCgSfUa6WCE88iEqSnhxoFbWfkRbeKGRDhEID3ccxsA== X-Google-Smtp-Source: AGHT+IFqxrXDaah+BbfdhrfjN9h4mYDI3oI4pO8J9A7mOr/p/0aQb2HnPhoznB6GwK1pSZzXIysnOw== X-Received: by 2002:a05:6512:234e:b0:531:4c6d:b8ef with SMTP id 2adb3069b0e04-5334854a59fmr2037352e87.6.1724256384896; Wed, 21 Aug 2024 09:06:24 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Alistair Francis , Bob Eshleman , Connor Davis , Andrew Cooper , Jan Beulich , Julien Grall , Stefano Stabellini Subject: [PATCH v5 7/7] xen/riscv: introduce early_fdt_map() Date: Wed, 21 Aug 2024 18:06:16 +0200 Message-ID: <4f6573d6b0d996b2c2bc4721de74e9bb51baec8c.1724256027.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1724256428688116600 Content-Type: text/plain; charset="utf-8" Introduce function which allows to map FDT to Xen. Also, initialization of device_tree_flattened happens using early_fdt_map(). Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich --- Changes in V5: - drop usage of PTE_BLOCK for flag argument of map_pages_to_xen() in early= _fdt_map() as block mapping is now default behaviour. Also PTE_BLOCK was dropped in= the patch "xen/riscv: page table handling". --- Changes in V4: - s/_PAGE_BLOCK/PTE_BLOCK - Add Acked-by: Jan Beulich - unwarap two lines in panic() in case when device_tree_flattened is NULL so grep-ing for any part of the message line will always produce a hit. - slightly update the commit message. --- Changes in V3: - Code style fixes - s/SZ_2M/MB(2) - fix condition to check if early_fdt_map() in setup.c return NULL or not. --- Changes in V2: - rework early_fdt_map to use map_pages_to_xen() - move call early_fdt_map() to C code after MMU is enabled. --- xen/arch/riscv/include/asm/mm.h | 2 ++ xen/arch/riscv/mm.c | 55 +++++++++++++++++++++++++++++++++ xen/arch/riscv/setup.c | 7 +++++ 3 files changed, 64 insertions(+) diff --git a/xen/arch/riscv/include/asm/mm.h b/xen/arch/riscv/include/asm/m= m.h index ce1557bb27..4b7b00b850 100644 --- a/xen/arch/riscv/include/asm/mm.h +++ b/xen/arch/riscv/include/asm/mm.h @@ -259,4 +259,6 @@ static inline unsigned int arch_get_dma_bitsize(void) =20 void setup_fixmap_mappings(void); =20 +void *early_fdt_map(paddr_t fdt_paddr); + #endif /* _ASM_RISCV_MM_H */ diff --git a/xen/arch/riscv/mm.c b/xen/arch/riscv/mm.c index e8430def14..4a628aef83 100644 --- a/xen/arch/riscv/mm.c +++ b/xen/arch/riscv/mm.c @@ -1,13 +1,16 @@ /* SPDX-License-Identifier: GPL-2.0-only */ =20 +#include #include #include #include #include +#include #include #include #include #include +#include =20 #include #include @@ -369,3 +372,55 @@ int destroy_xen_mappings(unsigned long s, unsigned lon= g e) BUG_ON("unimplemented"); return -1; } + +void * __init early_fdt_map(paddr_t fdt_paddr) +{ + /* We are using 2MB superpage for mapping the FDT */ + paddr_t base_paddr =3D fdt_paddr & XEN_PT_LEVEL_MAP_MASK(1); + paddr_t offset; + void *fdt_virt; + uint32_t size; + int rc; + + /* + * Check whether the physical FDT address is set and meets the minimum + * alignment requirement. Since we are relying on MIN_FDT_ALIGN to be = at + * least 8 bytes so that we always access the magic and size fields + * of the FDT header after mapping the first chunk, double check if + * that is indeed the case. + */ + BUILD_BUG_ON(MIN_FDT_ALIGN < 8); + if ( !fdt_paddr || fdt_paddr % MIN_FDT_ALIGN ) + return NULL; + + /* The FDT is mapped using 2MB superpage */ + BUILD_BUG_ON(BOOT_FDT_VIRT_START % MB(2)); + + rc =3D map_pages_to_xen(BOOT_FDT_VIRT_START, maddr_to_mfn(base_paddr), + MB(2) >> PAGE_SHIFT, + PAGE_HYPERVISOR_RO); + if ( rc ) + panic("Unable to map the device-tree.\n"); + + offset =3D fdt_paddr % XEN_PT_LEVEL_SIZE(1); + fdt_virt =3D (void *)BOOT_FDT_VIRT_START + offset; + + if ( fdt_magic(fdt_virt) !=3D FDT_MAGIC ) + return NULL; + + size =3D fdt_totalsize(fdt_virt); + if ( size > BOOT_FDT_VIRT_SIZE ) + return NULL; + + if ( (offset + size) > MB(2) ) + { + rc =3D map_pages_to_xen(BOOT_FDT_VIRT_START + MB(2), + maddr_to_mfn(base_paddr + MB(2)), + MB(2) >> PAGE_SHIFT, + PAGE_HYPERVISOR_RO); + if ( rc ) + panic("Unable to map the device-tree\n"); + } + + return fdt_virt; +} diff --git a/xen/arch/riscv/setup.c b/xen/arch/riscv/setup.c index f147ba672f..c9a6909c91 100644 --- a/xen/arch/riscv/setup.c +++ b/xen/arch/riscv/setup.c @@ -2,6 +2,7 @@ =20 #include #include +#include #include #include =20 @@ -56,6 +57,12 @@ void __init noreturn start_xen(unsigned long bootcpu_id, =20 setup_fixmap_mappings(); =20 + device_tree_flattened =3D early_fdt_map(dtb_addr); + if ( !device_tree_flattened ) + panic("Invalid device tree blob at physical address %#lx. The DTB = must be 8-byte aligned and must not exceed %lld bytes in size.\n\n" + "Please check your bootloader.\n", + dtb_addr, BOOT_FDT_VIRT_SIZE); + printk("All set up\n"); =20 for ( ;; ) --=20 2.46.0