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Fri, 9 Aug 2024 06:09:19 -0400 (EDT) (envelope-from sakib@darkstar.site) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 71e093e4-5637-11ef-bc04-fd08da9f4363 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed; d=pobox.com; h=from:to:cc :subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; s=sasl; bh=FcgplM/ww4dhD8AId/NsW6zg4 b4Mk/iLAAxsyvZiVYY=; b=TayMRCp8yrrOqu0YzcfEfILF52M95JlZcBbTb+JtL hk9gdbbDZFdKpWIF4OAAyt7LgC6YZeH9XH+v9rcbZDJ66Zj1qUZ4ftMzzf+gs4eU xhmamxoJMjT/aWn1xnZ+JIcaO4Na9+laHECzJdPxCqWS8KBn6hYgiPOZczIbnm+Y WM= From: Sergiy Kibrik To: xen-devel@lists.xenproject.org Cc: Sergiy Kibrik , Jan Beulich , Andrew Cooper , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [XEN PATCH v1 1/2] x86/intel: optional build of intel.c Date: Fri, 9 Aug 2024 13:09:17 +0300 Message-Id: <25e80b9271607da56abf9d4193e4d91b3d00bd9c.1723196909.git.Sergiy_Kibrik@epam.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-Pobox-Relay-ID: 710E7172-5637-11EF-9160-2BAEEB2EC81B-90055647!pb-smtp1.pobox.com Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @pobox.com) X-ZM-MESSAGEID: 1723198179509116600 Content-Type: text/plain; charset="utf-8" With specific config option INTEL in place and most of the code that depends on intel.c now can be optionally enabled/disabled it's now possible to put the whole intel.c under INTEL option as well. This will allow for a Xen bui= ld without Intel CPU support. Signed-off-by: Sergiy Kibrik --- xen/arch/x86/cpu/Makefile | 6 +++--- xen/arch/x86/cpu/common.c | 4 +++- xen/arch/x86/include/asm/processor.h | 7 ++++--- 3 files changed, 10 insertions(+), 7 deletions(-) diff --git a/xen/arch/x86/cpu/Makefile b/xen/arch/x86/cpu/Makefile index eafce5f204..020c86bda3 100644 --- a/xen/arch/x86/cpu/Makefile +++ b/xen/arch/x86/cpu/Makefile @@ -6,10 +6,10 @@ obj-y +=3D amd.o obj-y +=3D centaur.o obj-y +=3D common.o obj-y +=3D hygon.o -obj-y +=3D intel.o -obj-y +=3D intel_cacheinfo.o +obj-$(CONFIG_INTEL) +=3D intel.o +obj-$(CONFIG_INTEL) +=3D intel_cacheinfo.o obj-y +=3D mwait-idle.o -obj-y +=3D shanghai.o +obj-$(CONFIG_INTEL) +=3D shanghai.o obj-y +=3D vpmu.o obj-$(CONFIG_AMD) +=3D vpmu_amd.o obj-$(CONFIG_INTEL) +=3D vpmu_intel.o diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c index ff4cd22897..50ce13f81c 100644 --- a/xen/arch/x86/cpu/common.c +++ b/xen/arch/x86/cpu/common.c @@ -336,11 +336,13 @@ void __init early_cpu_init(bool verbose) =20 c->x86_vendor =3D x86_cpuid_lookup_vendor(ebx, ecx, edx); switch (c->x86_vendor) { +#ifdef CONFIG_INTEL case X86_VENDOR_INTEL: intel_unlock_cpuid_leaves(c); actual_cpu =3D intel_cpu_dev; break; + case X86_VENDOR_SHANGHAI: actual_cpu =3D shanghai_cpu_dev; break; +#endif case X86_VENDOR_AMD: actual_cpu =3D amd_cpu_dev; break; case X86_VENDOR_CENTAUR: actual_cpu =3D centaur_cpu_dev; break; - case X86_VENDOR_SHANGHAI: actual_cpu =3D shanghai_cpu_dev; break; case X86_VENDOR_HYGON: actual_cpu =3D hygon_cpu_dev; break; default: actual_cpu =3D default_cpu; diff --git a/xen/arch/x86/include/asm/processor.h b/xen/arch/x86/include/as= m/processor.h index 66463f6a6d..a88d45252b 100644 --- a/xen/arch/x86/include/asm/processor.h +++ b/xen/arch/x86/include/asm/processor.h @@ -507,15 +507,16 @@ static inline uint8_t get_cpu_family(uint32_t raw, ui= nt8_t *model, extern int8_t opt_tsx; extern bool rtm_disabled; void tsx_init(void); +void update_mcu_opt_ctrl(void); +void set_in_mcu_opt_ctrl(uint32_t mask, uint32_t val); #else #define opt_tsx 0 /* explicitly indicate TSX is off */ #define rtm_disabled false /* RTM was not force-disabled */ static inline void tsx_init(void) {} +static inline void update_mcu_opt_ctrl(void) {} +static inline void set_in_mcu_opt_ctrl(uint32_t mask, uint32_t val) {} #endif =20 -void update_mcu_opt_ctrl(void); -void set_in_mcu_opt_ctrl(uint32_t mask, uint32_t val); - enum ap_boot_method { AP_BOOT_NORMAL, AP_BOOT_SKINIT, --=20 2.25.1 From nobody Thu Nov 21 19:53:18 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail(p=quarantine dis=quarantine) header.from=epam.com ARC-Seal: i=1; a=rsa-sha256; t=1723198302; cv=none; d=zohomail.com; s=zohoarc; b=hS3HVb6XVcL6GsgD35GWUv9KwbI4Ec3nlUAieBOQGGJRL1HYjJyARTsbllwiHpBsUuczAFtTrbVTC50iCiIJleN6/U5tjYRO90zHz2tbhC0Noqebr2g3H53Z73YwH8DDXlfT0CxddiocZvUouBoT+6AlKbxLxM9e6veZC4uXUO8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; 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Fri, 9 Aug 2024 06:11:23 -0400 (EDT) (envelope-from sakib@darkstar.site) Received: from localhost (unknown [185.130.54.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by pb-smtp1.pobox.com (Postfix) with ESMTPSA id 85467186E8; Fri, 9 Aug 2024 06:11:22 -0400 (EDT) (envelope-from sakib@darkstar.site) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: bb57f72e-5637-11ef-bc04-fd08da9f4363 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed; d=pobox.com; h=from:to:cc :subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; s=sasl; bh=ojiKxXFKhugIX7qMuxIF0x+el EBDUt8AoK9fdheBKz0=; b=N6Xf0d6ExwA7PjY/19wATQGl6mBbbrks7ML9o9RLI 4DizJKTCh57db7gJ5TQOBHqAjhjUU+iEcoY9baKFzqOQnpt8tgibhGa3xbzK5O+9 Np/cgmV1FEZgORxiNvaqVn3EyzBBXeRKkd+Lh+HIyxmtRDC8Qq4sqMNv+g/SRbYF zI= From: Sergiy Kibrik To: xen-devel@lists.xenproject.org Cc: Sergiy Kibrik , Jan Beulich , Andrew Cooper , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [XEN PATCH v1 2/2] x86/amd: optional build of amd.c Date: Fri, 9 Aug 2024 13:11:20 +0300 Message-Id: <5632b05e993cca78a58b800dd37165ccd80b944f.1723196909.git.Sergiy_Kibrik@epam.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-Pobox-Relay-ID: BA99E13C-5637-11EF-970D-2BAEEB2EC81B-90055647!pb-smtp1.pobox.com Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @pobox.com) X-ZM-MESSAGEID: 1723198303983116600 Content-Type: text/plain; charset="utf-8" Similar to making Intel CPU support optional -- as we've got CONFIG_AMD opt= ion now, we can put arch/x86/cpu/amd.c under it and make it possible to build Xen without AMD CPU support. One possible use case is to dispose of dead co= de in Intel-only systems. Signed-off-by: Sergiy Kibrik --- xen/arch/x86/cpu/Makefile | 4 ++-- xen/arch/x86/cpu/common.c | 4 +++- xen/arch/x86/include/asm/amd.h | 22 ++++++++++++++++++++++ xen/arch/x86/spec_ctrl.c | 2 ++ 4 files changed, 29 insertions(+), 3 deletions(-) diff --git a/xen/arch/x86/cpu/Makefile b/xen/arch/x86/cpu/Makefile index 020c86bda3..5efd87be38 100644 --- a/xen/arch/x86/cpu/Makefile +++ b/xen/arch/x86/cpu/Makefile @@ -2,10 +2,10 @@ obj-y +=3D mcheck/ obj-y +=3D microcode/ obj-y +=3D mtrr/ =20 -obj-y +=3D amd.o +obj-$(CONFIG_AMD) +=3D amd.o obj-y +=3D centaur.o obj-y +=3D common.o -obj-y +=3D hygon.o +obj-$(CONFIG_AMD) +=3D hygon.o obj-$(CONFIG_INTEL) +=3D intel.o obj-$(CONFIG_INTEL) +=3D intel_cacheinfo.o obj-y +=3D mwait-idle.o diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c index 50ce13f81c..7be689c2e3 100644 --- a/xen/arch/x86/cpu/common.c +++ b/xen/arch/x86/cpu/common.c @@ -341,9 +341,11 @@ void __init early_cpu_init(bool verbose) actual_cpu =3D intel_cpu_dev; break; case X86_VENDOR_SHANGHAI: actual_cpu =3D shanghai_cpu_dev; break; #endif +#ifdef CONFIG_AMD case X86_VENDOR_AMD: actual_cpu =3D amd_cpu_dev; break; - case X86_VENDOR_CENTAUR: actual_cpu =3D centaur_cpu_dev; break; case X86_VENDOR_HYGON: actual_cpu =3D hygon_cpu_dev; break; +#endif + case X86_VENDOR_CENTAUR: actual_cpu =3D centaur_cpu_dev; break; default: actual_cpu =3D default_cpu; if (!verbose) diff --git a/xen/arch/x86/include/asm/amd.h b/xen/arch/x86/include/asm/amd.h index fa4e0fc766..a2481eddc7 100644 --- a/xen/arch/x86/include/asm/amd.h +++ b/xen/arch/x86/include/asm/amd.h @@ -158,13 +158,21 @@ #define is_zen4_uarch() boot_cpu_has(X86_FEATURE_AUTO_IBRS) =20 struct cpuinfo_x86; +#ifdef CONFIG_AMD int cpu_has_amd_erratum(const struct cpuinfo_x86 *cpu, int osvw_id, ...); +#else +static inline int cpu_has_amd_erratum(const struct cpuinfo_x86 *cpu, int o= svw_id, ...) +{ + return false; +} +#endif =20 extern s8 opt_allow_unsafe; =20 void fam10h_check_enable_mmcfg(void); void check_enable_amd_mmconf_dmi(void); =20 +#ifdef CONFIG_AMD extern bool amd_acpi_c1e_quirk; void amd_check_disable_c1e(unsigned int port, u8 value); =20 @@ -173,5 +181,19 @@ extern bool amd_virt_spec_ctrl; bool amd_setup_legacy_ssbd(void); void amd_set_legacy_ssbd(bool enable); void amd_set_cpuid_user_dis(bool enable); +#else +static inline void amd_set_cpuid_user_dis(bool enable) {} +static inline void amd_set_legacy_ssbd(bool enable) {} +static inline bool amd_setup_legacy_ssbd(void) +{ + return false; +} + +#define amd_acpi_c1e_quirk (false) +#define amd_virt_spec_ctrl (false) +#define amd_legacy_ssbd (false) + +static inline void amd_check_disable_c1e(unsigned int port, u8 value) {} +#endif =20 #endif /* __AMD_H__ */ diff --git a/xen/arch/x86/spec_ctrl.c b/xen/arch/x86/spec_ctrl.c index 92405b8be7..8231515c80 100644 --- a/xen/arch/x86/spec_ctrl.c +++ b/xen/arch/x86/spec_ctrl.c @@ -1884,10 +1884,12 @@ void __init init_speculation_mitigations(void) setup_force_cpu_cap(X86_FEATURE_SC_MSR_HVM); } =20 +#ifdef CONFIG_AMD /* Support VIRT_SPEC_CTRL.SSBD if AMD_SSBD is not available. */ if ( opt_msr_sc_hvm && !cpu_has_amd_ssbd && (cpu_has_virt_ssbd || (amd_legacy_ssbd && amd_setup_legacy_ssbd()= )) ) amd_virt_spec_ctrl =3D true; +#endif =20 /* Figure out default_xen_spec_ctrl. */ if ( has_spec_ctrl && ibrs ) --=20 2.25.1