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charset="utf-8" From: Xenia Ragiadakou Introduce two new Kconfig options, AMD_SVM and INTEL_VMX, to allow code specific to each virtualization technology to be separated and, when not required, stripped. CONFIG_AMD_SVM will be used to enable virtual machine extensions on platfor= ms that implement the AMD Virtualization Technology (AMD-V). CONFIG_INTEL_VMX will be used to enable virtual machine extensions on platf= orms that implement the Intel Virtualization Technology (Intel VT-x). Both features depend on HVM support. Since, at this point, disabling any of them would cause Xen to not compile, the options are enabled by default if HVM and are not selectable by the use= r. No functional change intended. Signed-off-by: Xenia Ragiadakou Signed-off-by: Sergiy Kibrik Acked-by: Jan Beulich --- changes in v5: - change kconfig option name SVM/VMX -> AMD_SVM/INTEL_VMX changes in v3: - tag added changes in v2: - simplify kconfig expression to def_bool HVM - keep file list in Makefile in alphabetical order --- xen/arch/x86/Kconfig | 6 ++++++ xen/arch/x86/hvm/Makefile | 4 ++-- xen/arch/x86/mm/Makefile | 3 ++- xen/arch/x86/mm/hap/Makefile | 2 +- 4 files changed, 11 insertions(+), 4 deletions(-) diff --git a/xen/arch/x86/Kconfig b/xen/arch/x86/Kconfig index 7e03e4bc55..fa5405e0d3 100644 --- a/xen/arch/x86/Kconfig +++ b/xen/arch/x86/Kconfig @@ -122,6 +122,12 @@ config HVM =20 If unsure, say Y. =20 +config AMD_SVM + def_bool HVM + +config INTEL_VMX + def_bool HVM + config XEN_SHSTK bool "Supervisor Shadow Stacks" depends on HAS_AS_CET_SS diff --git a/xen/arch/x86/hvm/Makefile b/xen/arch/x86/hvm/Makefile index 3464191544..4c1fa5c6c2 100644 --- a/xen/arch/x86/hvm/Makefile +++ b/xen/arch/x86/hvm/Makefile @@ -1,5 +1,5 @@ -obj-y +=3D svm/ -obj-y +=3D vmx/ +obj-$(CONFIG_AMD_SVM) +=3D svm/ +obj-$(CONFIG_INTEL_VMX) +=3D vmx/ obj-y +=3D viridian/ =20 obj-y +=3D asid.o diff --git a/xen/arch/x86/mm/Makefile b/xen/arch/x86/mm/Makefile index 0803ac9297..52c5abdfee 100644 --- a/xen/arch/x86/mm/Makefile +++ b/xen/arch/x86/mm/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_MEM_SHARING) +=3D mem_sharing.o obj-$(CONFIG_HVM) +=3D nested.o obj-$(CONFIG_HVM) +=3D p2m.o obj-y +=3D p2m-basic.o -obj-$(CONFIG_HVM) +=3D p2m-ept.o p2m-pod.o p2m-pt.o +obj-$(CONFIG_INTEL_VMX) +=3D p2m-ept.o +obj-$(CONFIG_HVM) +=3D p2m-pod.o p2m-pt.o obj-y +=3D paging.o obj-y +=3D physmap.o diff --git a/xen/arch/x86/mm/hap/Makefile b/xen/arch/x86/mm/hap/Makefile index 8ef54b1faa..67c29b2162 100644 --- a/xen/arch/x86/mm/hap/Makefile +++ b/xen/arch/x86/mm/hap/Makefile @@ -3,4 +3,4 @@ obj-y +=3D guest_walk_2.o obj-y +=3D guest_walk_3.o obj-y +=3D guest_walk_4.o obj-y +=3D nested_hap.o -obj-y +=3D nested_ept.o +obj-$(CONFIG_INTEL_VMX) +=3D nested_ept.o --=20 2.25.1 From nobody Mon Nov 25 05:27:17 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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a=rsa-sha256; c=relaxed; d=pobox.com; h=from:to:cc :subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; s=sasl; bh=fZgepJ99FLaK7AHeqjTZAWTib QvdlwNx7oQOyRXLmVM=; b=PjYmm5j2TCZQntY56hr0kLmHYUa/aIkKBsNAOzSve K6iC8xwmrgGSKfX3X/a6oc2cC2D3ahdKPUfGKV4W+Qr12EH7h2HEG4UA7s6hv22l T2p6p/ChqOSnN0jtt65axxcAyn8cD6jXlSj01+C9WzZWI9mmHYIURWtDgxxiESJY Zk= From: Sergiy Kibrik To: xen-devel@lists.xenproject.org Cc: Sergiy Kibrik , Alexandru Isaila , Petre Pircalabu , Andrew Cooper , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Jan Beulich , Stefano Stabellini , Xenia Ragiadakou , Tamas K Lengyel Subject: [XEN PATCH v5 02/13] x86/monitor: guard altp2m usage Date: Tue, 30 Jul 2024 13:18:18 +0300 Message-Id: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-Pobox-Relay-ID: 0CA62FEA-4E5D-11EF-BF3D-92D9AF168FA5-90055647!pb-smtp20.pobox.com Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @pobox.com) X-ZM-MESSAGEID: 1722334735681116600 Content-Type: text/plain; charset="utf-8" Explicitly check whether altp2m is on for domain when getting altp2m index. If explicit call to altp2m_active() always returns false, DCE will remove call to altp2m_vcpu_idx(). p2m_get_mem_access() expects 0 as altp2m_idx parameter when altp2m not acti= ve or not supported, so 0 is a fallback value then. The puspose of that is later to be able to disable altp2m support and exclude its code from the build completely, when not supported by target platform (as of now it's supported for VT-d only). Also all other calls to altp2m_vcpu_idx() are guarded by altp2m_active(), so this change puts usage of this routine in line with the rest of code. Signed-off-by: Sergiy Kibrik CC: Tamas K Lengyel CC: Jan Beulich Acked-by: Tamas K Lengyel --- changes in v5: - changed patch description changes in v2: - patch description changed, removed VMX mentioning - guard by altp2m_active() instead of hvm_altp2m_supported() --- xen/arch/x86/hvm/monitor.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/xen/arch/x86/hvm/monitor.c b/xen/arch/x86/hvm/monitor.c index 2a8ff07ec9..74621000b2 100644 --- a/xen/arch/x86/hvm/monitor.c +++ b/xen/arch/x86/hvm/monitor.c @@ -262,6 +262,8 @@ bool hvm_monitor_check_p2m(unsigned long gla, gfn_t gfn= , uint32_t pfec, struct vcpu *curr =3D current; vm_event_request_t req =3D {}; paddr_t gpa =3D (gfn_to_gaddr(gfn) | (gla & ~PAGE_MASK)); + unsigned int altp2m_idx =3D altp2m_active(curr->domain) ? + altp2m_vcpu_idx(curr) : 0; int rc; =20 ASSERT(curr->arch.vm_event->send_event); @@ -270,7 +272,7 @@ bool hvm_monitor_check_p2m(unsigned long gla, gfn_t gfn= , uint32_t pfec, * p2m_get_mem_access() can fail from a invalid MFN and return -ESRCH * in which case access must be restricted. */ - rc =3D p2m_get_mem_access(curr->domain, gfn, &access, altp2m_vcpu_idx(= curr)); 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Tue, 30 Jul 2024 06:20:34 -0400 (EDT) (envelope-from sakib@darkstar.site) Received: from localhost (unknown [185.130.54.90]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by pb-smtp20.pobox.com (Postfix) with ESMTPSA id E6F173543C; Tue, 30 Jul 2024 06:20:29 -0400 (EDT) (envelope-from sakib@darkstar.site) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 5bf26ede-4e5d-11ef-8776-851b0ebba9a2 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed; d=pobox.com; h=from:to:cc :subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; s=sasl; bh=Ily8J/O+RwpKuEMEVWmpbQY+A 5ZLNIXdklAbdyftYqw=; b=gPvbyx6TzGtHVI55TGXvS4g+slOmVkqyoJJye03ro R2SwrVzrP2cmh6YepESBFyr45FEHtwuYWadfJgpgjIzPt9WDggLlI/1aJdcIiFP9 HWvHiwjVOoyt5Fv9D3uS92QdngkesfsPCZFR5xScyCRTN9xfpOnb/pTY7a/S6UUc z4= From: Sergiy Kibrik To: xen-devel@lists.xenproject.org Cc: Sergiy Kibrik , Jan Beulich , Andrew Cooper , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini , Xenia Ragiadakou , Tamas K Lengyel Subject: [XEN PATCH v5 03/13] x86: introduce CONFIG_ALTP2M Kconfig option Date: Tue, 30 Jul 2024 13:20:26 +0300 Message-Id: <93cb9a86c76a8d7cb24df916a4049b92bfb24459.1722333634.git.Sergiy_Kibrik@epam.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-Pobox-Relay-ID: 58BF2B84-4E5D-11EF-A1B7-92D9AF168FA5-90055647!pb-smtp20.pobox.com Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @pobox.com) X-ZM-MESSAGEID: 1722334870299116600 Content-Type: text/plain; charset="utf-8" Add new option to make altp2m code inclusion optional. Currently altp2m implemented for Intel EPT only, so option is dependant on = VMX. Also the prompt itself depends on EXPERT=3Dy, so that option is available for fine-tuning, if one want to play around with it. Use this option instead of more generic CONFIG_HVM option. That implies the possibility to build hvm code without altp2m support, hence we need to declare altp2m routines for hvm code to compile successful= ly (altp2m_vcpu_initialise(), altp2m_vcpu_destroy(), altp2m_vcpu_enable_ve()) Also guard altp2m routines, so that they can be disabled completely in the build -- when target platform does not actually support altp2m (AMD-V & ARM as of now). Signed-off-by: Sergiy Kibrik Reviewed-by: Jan Beulich CC: Tamas K Lengyel CC: Stefano Stabellini --- changes in v5: - change kconfig option name VMX -> INTEL_VMX changes in v4: - move static inline stub for p2m_altp2m_check() from under CONFIG_HVM und= er CONFIG_ALTP2M - keep AP2MGET_prepopulate/AP2MGET_query under CONFIG_ALTP2M as Jan sugges= ted changes in v3: - added help text - use conditional prompt depending on EXPERT=3Dy - corrected & extended patch description - put a blank line before #ifdef CONFIG_ALTP2M - sqashed in a separate patch for guarding altp2m code with CONFIG_ALTP2M = option --- xen/arch/x86/Kconfig | 11 +++++++++++ xen/arch/x86/include/asm/altp2m.h | 5 ++++- xen/arch/x86/include/asm/hvm/hvm.h | 2 +- xen/arch/x86/include/asm/p2m.h | 23 ++++++++++++++++++----- xen/arch/x86/mm/Makefile | 2 +- 5 files changed, 35 insertions(+), 8 deletions(-) diff --git a/xen/arch/x86/Kconfig b/xen/arch/x86/Kconfig index fa5405e0d3..cd81fd1675 100644 --- a/xen/arch/x86/Kconfig +++ b/xen/arch/x86/Kconfig @@ -358,6 +358,17 @@ config REQUIRE_NX was unavailable. However, if enabled, Xen will no longer boot on any CPU which is lacking NX support. =20 +config ALTP2M + bool "Alternate P2M support" if EXPERT + default y + depends on INTEL_VMX + help + Alternate-p2m allows a guest to manage multiple p2m guest physical + "memory views" (as opposed to a single p2m). + Useful for memory introspection. + + If unsure, stay with defaults. + endmenu =20 source "common/Kconfig" diff --git a/xen/arch/x86/include/asm/altp2m.h b/xen/arch/x86/include/asm/a= ltp2m.h index e5e59cbd68..c57a8c5588 100644 --- a/xen/arch/x86/include/asm/altp2m.h +++ b/xen/arch/x86/include/asm/altp2m.h @@ -7,7 +7,7 @@ #ifndef __ASM_X86_ALTP2M_H #define __ASM_X86_ALTP2M_H =20 -#ifdef CONFIG_HVM +#ifdef CONFIG_ALTP2M =20 #include #include /* for struct vcpu, struct domain */ @@ -39,6 +39,9 @@ static inline bool altp2m_active(const struct domain *d) =20 /* Only declaration is needed. DCE will optimise it out when linking. */ uint16_t altp2m_vcpu_idx(const struct vcpu *v); +void altp2m_vcpu_initialise(struct vcpu *v); +void altp2m_vcpu_destroy(struct vcpu *v); +int altp2m_vcpu_enable_ve(struct vcpu *v, gfn_t gfn); void altp2m_vcpu_disable_ve(struct vcpu *v); =20 #endif diff --git a/xen/arch/x86/include/asm/hvm/hvm.h b/xen/arch/x86/include/asm/= hvm/hvm.h index 277648dd18..34824af6df 100644 --- a/xen/arch/x86/include/asm/hvm/hvm.h +++ b/xen/arch/x86/include/asm/hvm/hvm.h @@ -670,7 +670,7 @@ static inline bool hvm_hap_supported(void) /* returns true if hardware supports alternate p2m's */ static inline bool hvm_altp2m_supported(void) { - return hvm_funcs.caps.altp2m; + return IS_ENABLED(CONFIG_ALTP2M) && hvm_funcs.caps.altp2m; } =20 /* Returns true if we have the minimum hardware requirements for nested vi= rt */ diff --git a/xen/arch/x86/include/asm/p2m.h b/xen/arch/x86/include/asm/p2m.h index c1478ffc36..e6de37f108 100644 --- a/xen/arch/x86/include/asm/p2m.h +++ b/xen/arch/x86/include/asm/p2m.h @@ -577,7 +577,7 @@ static inline gfn_t mfn_to_gfn(const struct domain *d, = mfn_t mfn) return _gfn(mfn_x(mfn)); } =20 -#ifdef CONFIG_HVM +#ifdef CONFIG_ALTP2M #define AP2MGET_prepopulate true #define AP2MGET_query false =20 @@ -589,6 +589,16 @@ static inline gfn_t mfn_to_gfn(const struct domain *d,= mfn_t mfn) int altp2m_get_effective_entry(struct p2m_domain *ap2m, gfn_t gfn, mfn_t *= mfn, p2m_type_t *t, p2m_access_t *a, bool prepopulate); +#else +static inline int _altp2m_get_effective_entry(struct p2m_domain *ap2m, + gfn_t gfn, mfn_t *mfn, + p2m_type_t *t, p2m_access_t *= a) +{ + ASSERT_UNREACHABLE(); + return -EOPNOTSUPP; +} +#define altp2m_get_effective_entry(ap2m, gfn, mfn, t, a, prepopulate) \ + _altp2m_get_effective_entry(ap2m, gfn, mfn, t, a) #endif =20 /* Init the datastructures for later use by the p2m code */ @@ -914,9 +924,6 @@ static inline bool p2m_set_altp2m(struct vcpu *v, unsig= ned int idx) /* Switch alternate p2m for a single vcpu */ bool p2m_switch_vcpu_altp2m_by_id(struct vcpu *v, unsigned int idx); =20 -/* Check to see if vcpu should be switched to a different p2m. */ -void p2m_altp2m_check(struct vcpu *v, uint16_t idx); - /* Flush all the alternate p2m's for a domain */ void p2m_flush_altp2m(struct domain *d); =20 @@ -952,9 +959,15 @@ int p2m_set_altp2m_view_visibility(struct domain *d, u= nsigned int altp2m_idx, uint8_t visible); #else /* !CONFIG_HVM */ struct p2m_domain *p2m_get_altp2m(struct vcpu *v); -static inline void p2m_altp2m_check(struct vcpu *v, uint16_t idx) {} #endif /* CONFIG_HVM */ =20 +#ifdef CONFIG_ALTP2M +/* Check to see if vcpu should be switched to a different p2m. */ +void p2m_altp2m_check(struct vcpu *v, uint16_t idx); +#else +static inline void p2m_altp2m_check(struct vcpu *v, uint16_t idx) {} +#endif + /* p2m access to IOMMU flags */ static inline unsigned int p2m_access_to_iommu_flags(p2m_access_t p2ma) { diff --git a/xen/arch/x86/mm/Makefile b/xen/arch/x86/mm/Makefile index 52c5abdfee..0345388359 100644 --- a/xen/arch/x86/mm/Makefile +++ b/xen/arch/x86/mm/Makefile @@ -1,7 +1,7 @@ obj-y +=3D shadow/ obj-$(CONFIG_HVM) +=3D hap/ =20 -obj-$(CONFIG_HVM) +=3D altp2m.o +obj-$(CONFIG_ALTP2M) +=3D altp2m.o obj-$(CONFIG_HVM) +=3D guest_walk_2.o guest_walk_3.o guest_walk_4.o obj-$(CONFIG_SHADOW_PAGING) +=3D guest_walk_4.o obj-$(CONFIG_MEM_ACCESS) +=3D mem_access.o --=20 2.25.1 From nobody Mon Nov 25 05:27:17 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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a=rsa-sha256; c=relaxed; d=pobox.com; h=from:to:cc :subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; s=sasl; bh=TrLfjt8TdLelwfW8Lze4IzwKh TmEd5lEptuf7ypFWEE=; b=nnZs0xj86rR+RqSmSfDvwtfQ1DrI5FMbwPfiQxZQo dgxNsf44mYHw9SR+DTCGlht4bY5OrtbLUugGwUyG6JbXtwLI5XHBrQ0elsnOXdtv bZ7qDPfdri17x1N+gzwBbyg6Jlc6vO7OG90ufu4mQ41CLMKgygcA4aLtjOTQURmb eg= From: Sergiy Kibrik To: xen-devel@lists.xenproject.org Cc: Sergiy Kibrik , Jan Beulich , Andrew Cooper , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini , Xenia Ragiadakou Subject: [XEN PATCH v5 04/13] x86: introduce using_{svm,vmx}() helpers Date: Tue, 30 Jul 2024 13:22:34 +0300 Message-Id: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-Pobox-Relay-ID: A5378916-4E5D-11EF-A135-92D9AF168FA5-90055647!pb-smtp20.pobox.com Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @pobox.com) X-ZM-MESSAGEID: 1722334992806116600 Content-Type: text/plain; charset="utf-8" As we now have AMD_SVM/INTEL_VMX config options for enabling/disabling these features completely in the build, we need some build-time checks to ensure = that vmx/svm code can be used and things compile. Macros cpu_has_{svm,vmx} used = to be doing such checks at runtime, however they do not check if SVM/VMX support = is enabled in the build. Also cpu_has_{svm,vmx} can potentially be called from non-{VMX,SVM} build yet running on {VMX,SVM}-enabled CPU, so would correctly indicate that VMX/= SVM is indeed supported by CPU, but code to drive it can't be used. New routines using_{vmx,svm}() indicate that both CPU _and_ build provide corresponding technology support, while cpu_has_{vmx,svm} still remains for informational runtime purpose, just as their naming suggests. These new helpers are used right away in several sites, namely guard calls = to start_nested_{svm,vmx} and start_{svm,vmx} to fix a build when INTEL_VMX=3D= n or AMD_SVM=3Dn. Signed-off-by: Sergiy Kibrik Reviewed-by: Jan Beulich --- changes in v5: - change kconfig option name SVM/VMX -> AMD_SVM/INTEL_VMX changes in v4: - make using_{vmx,svm} static inline functions instead of macros - squash patch with 2 other patches where using_{vmx,svm} are being used - changed patch description changes in v3: - introduce separate macros instead of modifying behaviour of cpu_has_{vmx= ,svm} --- xen/arch/x86/hvm/hvm.c | 4 ++-- xen/arch/x86/hvm/nestedhvm.c | 4 ++-- xen/arch/x86/include/asm/hvm/hvm.h | 10 ++++++++++ 3 files changed, 14 insertions(+), 4 deletions(-) diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c index 7f4b627b1f..057c61b4c3 100644 --- a/xen/arch/x86/hvm/hvm.c +++ b/xen/arch/x86/hvm/hvm.c @@ -155,9 +155,9 @@ static int __init cf_check hvm_enable(void) { const struct hvm_function_table *fns =3D NULL; =20 - if ( cpu_has_vmx ) + if ( using_vmx() ) fns =3D start_vmx(); - else if ( cpu_has_svm ) + else if ( using_svm() ) fns =3D start_svm(); =20 if ( fns =3D=3D NULL ) diff --git a/xen/arch/x86/hvm/nestedhvm.c b/xen/arch/x86/hvm/nestedhvm.c index 451c4da6d4..5009167372 100644 --- a/xen/arch/x86/hvm/nestedhvm.c +++ b/xen/arch/x86/hvm/nestedhvm.c @@ -155,9 +155,9 @@ static int __init cf_check nestedhvm_setup(void) * done, so that if (for example) HAP is disabled, nested virt is * disabled as well. */ - if ( cpu_has_vmx ) + if ( using_vmx() ) start_nested_vmx(&hvm_funcs); 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a=rsa-sha256; c=relaxed; d=pobox.com; h=from:to:cc :subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; s=sasl; bh=a9yGdN5UJg74MWMxngSXjpTTe p0k3IjQWp09AuJ1Dr4=; b=XwrMsGtXTcFgWsWWkAnoLbo9HfyuFdQuWG1ZFUgyT 9qP9gHtzWXZAiX41CWso32jrJdFkHMTN+/zhpUCnS0AnPpKtEmlEfsSE7KURkg2S I/mUWyxbOcgS29RyZTi16gOGRA6+CxNvrQfODwptHjADsXTGvsnAlOuuRpbDlzKE 3k= From: Sergiy Kibrik To: xen-devel@lists.xenproject.org Cc: Xenia Ragiadakou , Jan Beulich , Andrew Cooper , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini , Xenia Ragiadakou , Sergiy Kibrik Subject: [XEN PATCH v5 05/13] x86/p2m: guard EPT functions with using_vmx() check Date: Tue, 30 Jul 2024 13:24:41 +0300 Message-Id: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-Pobox-Relay-ID: F0AA9974-4E5D-11EF-963E-92D9AF168FA5-90055647!pb-smtp20.pobox.com Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @pobox.com) X-ZM-MESSAGEID: 1722335113369116600 Content-Type: text/plain; charset="utf-8" From: Xenia Ragiadakou Replace cpu_has_vmx check with using_vmx(), so that DCE would remove calls to functions ept_p2m_init() and ept_p2m_uninit() on non-VMX build. Since currently Intel EPT implementation depends on CONFIG_INTEL_VMX config option, when VMX is off these functions are unavailable. Signed-off-by: Xenia Ragiadakou Signed-off-by: Sergiy Kibrik Acked-by: Jan Beulich --- changes in v5: - changed description changes in v4: - changed description a bit - added tag - adjusted call to using_vmx(), as it has become an inline function changes in v3: - using_vmx instead of IS_ENABLED(CONFIG_VMX) - updated description --- xen/arch/x86/mm/p2m-basic.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/xen/arch/x86/mm/p2m-basic.c b/xen/arch/x86/mm/p2m-basic.c index 08007a687c..e126fda267 100644 --- a/xen/arch/x86/mm/p2m-basic.c +++ b/xen/arch/x86/mm/p2m-basic.c @@ -40,7 +40,7 @@ static int p2m_initialise(struct domain *d, struct p2m_do= main *p2m) p2m_pod_init(p2m); p2m_nestedp2m_init(p2m); =20 - if ( hap_enabled(d) && cpu_has_vmx ) + if ( hap_enabled(d) && using_vmx() ) ret =3D ept_p2m_init(p2m); else p2m_pt_init(p2m); @@ -72,7 +72,7 @@ struct p2m_domain *p2m_init_one(struct domain *d) void p2m_free_one(struct p2m_domain *p2m) { p2m_free_logdirty(p2m); - if ( hap_enabled(p2m->domain) && cpu_has_vmx ) + if ( hap_enabled(p2m->domain) && using_vmx() ) ept_p2m_uninit(p2m); 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charset="utf-8" From: Xenia Ragiadakou Replace cpu_has_vmx check with using_vmx(), so that not only VMX support in= CPU is being checked at runtime, but also at build time we ensure the availabil= ity of functions vmx_vmcs_enter() & vmx_vmcs_exit(). Also since CONFIG_VMX is checked in using_vmx and it depends on CONFIG_HVM, we can drop #ifdef CONFIG_HVM lines around using_vmx. Signed-off-by: Xenia Ragiadakou Signed-off-by: Sergiy Kibrik Acked-by: Jan Beulich --- changes in v4: - adjusted call to using_vmx(), as it has become an inline function - added tag - description changed a bit for more clarity changes in v3: -using_vmx instead of IS_ENABLED(CONFIG_VMX) - updated description --- xen/arch/x86/traps.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c index ee91fc56b1..d2af6d70d2 100644 --- a/xen/arch/x86/traps.c +++ b/xen/arch/x86/traps.c @@ -676,7 +676,6 @@ void vcpu_show_execution_state(struct vcpu *v) =20 vcpu_pause(v); /* acceptably dangerous */ =20 -#ifdef CONFIG_HVM /* * For VMX special care is needed: Reading some of the register state = will * require VMCS accesses. Engaging foreign VMCSes involves acquiring o= f a @@ -684,12 +683,11 @@ void vcpu_show_execution_state(struct vcpu *v) * region. Despite this being a layering violation, engage the VMCS ri= ght * here. This then also avoids doing so several times in close success= ion. */ - if ( cpu_has_vmx && is_hvm_vcpu(v) ) + if ( using_vmx() && is_hvm_vcpu(v) ) { ASSERT(!in_irq()); vmx_vmcs_enter(v); } -#endif =20 /* Prevent interleaving of output. */ flags =3D console_lock_recursive_irqsave(); @@ -714,10 +712,8 @@ void vcpu_show_execution_state(struct vcpu *v) console_unlock_recursive_irqrestore(flags); } =20 -#ifdef CONFIG_HVM - if ( cpu_has_vmx && is_hvm_vcpu(v) ) + if ( using_vmx() && is_hvm_vcpu(v) ) vmx_vmcs_exit(v); -#endif =20 vcpu_unpause(v); } --=20 2.25.1 From nobody Mon Nov 25 05:27:17 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; 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charset="utf-8" From: Xenia Ragiadakou Replace cpu_has_svm check with using_svm(), so that not only SVM support in= CPU is being checked at runtime, but also at build time we ensure the availabil= ity of functions svm_load_segs() and svm_load_segs_prefetch(). Since SVM depends on HVM, it can be used alone. Signed-off-by: Xenia Ragiadakou Signed-off-by: Sergiy Kibrik Acked-by: Jan Beulich --- changes in v4: - changed patch subject line - adjusted call to using_svm(), as it has become an inline function - use #ifdef CONFIG_PV - description changed a bit for more clarity - added tag changes in v3: - using_svm instead of IS_ENABLED(CONFIG_SVM) - updated description --- xen/arch/x86/domain.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/xen/arch/x86/domain.c b/xen/arch/x86/domain.c index ccadfe0c9e..05cb9f7a4c 100644 --- a/xen/arch/x86/domain.c +++ b/xen/arch/x86/domain.c @@ -1732,11 +1732,9 @@ static void load_segments(struct vcpu *n) if ( !(n->arch.flags & TF_kernel_mode) ) SWAP(gsb, gss); =20 -#ifdef CONFIG_HVM - if ( cpu_has_svm && (uregs->fs | uregs->gs) <=3D 3 ) + if ( using_svm() && (uregs->fs | uregs->gs) <=3D 3 ) fs_gs_done =3D svm_load_segs(n->arch.pv.ldt_ents, LDT_VIRT_STA= RT(n), n->arch.pv.fs_base, gsb, gss); -#endif } =20 if ( !fs_gs_done ) @@ -2049,9 +2047,9 @@ static void __context_switch(void) =20 write_ptbase(n); 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charset="utf-8" From: Xenia Ragiadakou The symbol svm_stgi_label is AMD-V specific so guard its usage in common co= de with CONFIG_AMD_SVM. Since SVM depends on HVM, it can be used alone. Also, use #ifdef instead of #if. No functional change intended. Signed-off-by: Xenia Ragiadakou Signed-off-by: Sergiy Kibrik Acked-by: Jan Beulich --- changes in v5: - change kconfig option name SVM -> AMD_SVM --- xen/arch/x86/oprofile/op_model_athlon.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/xen/arch/x86/oprofile/op_model_athlon.c b/xen/arch/x86/oprofil= e/op_model_athlon.c index 69fd3fcc86..782fa606ee 100644 --- a/xen/arch/x86/oprofile/op_model_athlon.c +++ b/xen/arch/x86/oprofile/op_model_athlon.c @@ -320,7 +320,7 @@ static int cf_check athlon_check_ctrs( struct vcpu *v =3D current; unsigned int const nr_ctrs =3D model->num_counters; =20 -#if CONFIG_HVM +#ifdef CONFIG_AMD_SVM struct cpu_user_regs *guest_regs =3D guest_cpu_user_regs(); =20 if (!guest_mode(regs) && --=20 2.25.1 From nobody Mon Nov 25 05:27:17 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; 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a=rsa-sha256; c=relaxed; d=pobox.com; h=from:to:cc :subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; s=sasl; bh=TYiTEy4cUxeBQmG3mkiO34ODY 8YMOMAHGuXGuqNEmg4=; b=b8NKrxhlTE9+AcL/Xyfp2QPq0pnohHav+Hz1on2dq aAWDm2DTADa1yu4GH42GK5pbEU+E8xiOjd0LTDsOXlTK58nUP2GHC8HaV2jBx2U1 2suGzTELfA+KbAbvrHrQ/oF/YwvsVl9zPKxsjL5Oi1Oe7wrFqkYJxVtG1ygtcQ6X PM= From: Sergiy Kibrik To: xen-devel@lists.xenproject.org Cc: Sergiy Kibrik , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Jan Beulich , Stefano Stabellini , Xenia Ragiadakou , Paul Durrant , Andrew Cooper Subject: [XEN PATCH v5 09/13] x86/vmx: guard access to cpu_has_vmx_* in common code Date: Tue, 30 Jul 2024 13:33:03 +0300 Message-Id: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-Pobox-Relay-ID: 1BA55366-4E5F-11EF-BB9B-9625FCCAB05B-90055647!pb-smtp21.pobox.com Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @pobox.com) X-ZM-MESSAGEID: 1722335615616116600 Content-Type: text/plain; charset="utf-8" There're several places in common code, outside of arch/x86/hvm/vmx, where cpu_has_vmx_* get accessed without checking whether VMX supported fir= st. These macros rely on global variables defined in vmx code, so when VMX supp= ort is disabled accesses to these variables turn into build failures. To overcome these failures, build-time check is done before accessing global variables, so that DCE would remove these variables. Signed-off-by: Sergiy Kibrik Acked-by: Paul Durrant CC: Andrew Cooper CC: Jan Beulich --- changes in v5: - change kconfig option name VMX -> INTEL_VMX - do not change .c files, only modify macros in vmcs.h changes in v4: - use IS_ENABLED(CONFIG_VMX) instead of using_vmx changes in v3: - using_vmx instead of cpu_has_vmx - clarify description on why this change needed --- xen/arch/x86/include/asm/hvm/vmx/vmcs.h | 33 ++++++++++++++++--------- 1 file changed, 22 insertions(+), 11 deletions(-) diff --git a/xen/arch/x86/include/asm/hvm/vmx/vmcs.h b/xen/arch/x86/include= /asm/hvm/vmx/vmcs.h index 58140af691..34898d9612 100644 --- a/xen/arch/x86/include/asm/hvm/vmx/vmcs.h +++ b/xen/arch/x86/include/asm/hvm/vmx/vmcs.h @@ -300,13 +300,15 @@ extern u64 vmx_ept_vpid_cap; #define cpu_has_wbinvd_exiting \ (vmx_secondary_exec_control & SECONDARY_EXEC_WBINVD_EXITING) #define cpu_has_vmx_virtualize_apic_accesses \ - (vmx_secondary_exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) + (IS_ENABLED(CONFIG_INTEL_VMX) && \ + vmx_secondary_exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) #define cpu_has_vmx_tpr_shadow \ (vmx_cpu_based_exec_control & CPU_BASED_TPR_SHADOW) #define cpu_has_vmx_vnmi \ (vmx_pin_based_exec_control & PIN_BASED_VIRTUAL_NMIS) #define cpu_has_vmx_msr_bitmap \ - (vmx_cpu_based_exec_control & CPU_BASED_ACTIVATE_MSR_BITMAP) + (IS_ENABLED(CONFIG_INTEL_VMX) && \ + vmx_cpu_based_exec_control & CPU_BASED_ACTIVATE_MSR_BITMAP) #define cpu_has_vmx_secondary_exec_control \ (vmx_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) #define cpu_has_vmx_tertiary_exec_control \ @@ -316,11 +318,13 @@ extern u64 vmx_ept_vpid_cap; #define cpu_has_vmx_dt_exiting \ (vmx_secondary_exec_control & SECONDARY_EXEC_DESCRIPTOR_TABLE_EXITING) #define cpu_has_vmx_rdtscp \ - (vmx_secondary_exec_control & SECONDARY_EXEC_ENABLE_RDTSCP) + (IS_ENABLED(CONFIG_INTEL_VMX) && \ + vmx_secondary_exec_control & SECONDARY_EXEC_ENABLE_RDTSCP) #define cpu_has_vmx_vpid \ (vmx_secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID) #define cpu_has_monitor_trap_flag \ - (vmx_cpu_based_exec_control & CPU_BASED_MONITOR_TRAP_FLAG) + (IS_ENABLED(CONFIG_INTEL_VMX) && \ + vmx_cpu_based_exec_control & CPU_BASED_MONITOR_TRAP_FLAG) #define cpu_has_vmx_pat \ (vmx_vmentry_control & VM_ENTRY_LOAD_GUEST_PAT) #define cpu_has_vmx_efer \ @@ -333,13 +337,17 @@ extern u64 vmx_ept_vpid_cap; #define cpu_has_vmx_ple \ (vmx_secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING) #define cpu_has_vmx_invpcid \ - (vmx_secondary_exec_control & SECONDARY_EXEC_ENABLE_INVPCID) + (IS_ENABLED(CONFIG_INTEL_VMX) && \ + vmx_secondary_exec_control & SECONDARY_EXEC_ENABLE_INVPCID) #define cpu_has_vmx_apic_reg_virt \ - (vmx_secondary_exec_control & SECONDARY_EXEC_APIC_REGISTER_VIRT) + (IS_ENABLED(CONFIG_INTEL_VMX) && \ + vmx_secondary_exec_control & SECONDARY_EXEC_APIC_REGISTER_VIRT) #define cpu_has_vmx_virtual_intr_delivery \ - (vmx_secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) + (IS_ENABLED(CONFIG_INTEL_VMX) && \ + vmx_secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) #define cpu_has_vmx_virtualize_x2apic_mode \ - (vmx_secondary_exec_control & SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE) + (IS_ENABLED(CONFIG_INTEL_VMX) && \ + vmx_secondary_exec_control & SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE) #define cpu_has_vmx_posted_intr_processing \ (vmx_pin_based_exec_control & PIN_BASED_POSTED_INTERRUPT) #define cpu_has_vmx_vmcs_shadowing \ @@ -347,14 +355,17 @@ extern u64 vmx_ept_vpid_cap; #define cpu_has_vmx_vmfunc \ (vmx_secondary_exec_control & SECONDARY_EXEC_ENABLE_VM_FUNCTIONS) #define cpu_has_vmx_virt_exceptions \ - (vmx_secondary_exec_control & SECONDARY_EXEC_ENABLE_VIRT_EXCEPTIONS) + (IS_ENABLED(CONFIG_INTEL_VMX) && \ + vmx_secondary_exec_control & SECONDARY_EXEC_ENABLE_VIRT_EXCEPTIONS) #define cpu_has_vmx_pml \ (vmx_secondary_exec_control & SECONDARY_EXEC_ENABLE_PML) #define cpu_has_vmx_mpx \ - ((vmx_vmexit_control & VM_EXIT_CLEAR_BNDCFGS) && \ + (IS_ENABLED(CONFIG_INTEL_VMX) && \ + (vmx_vmexit_control & VM_EXIT_CLEAR_BNDCFGS) && \ (vmx_vmentry_control & VM_ENTRY_LOAD_BNDCFGS)) #define cpu_has_vmx_xsaves \ - (vmx_secondary_exec_control & SECONDARY_EXEC_XSAVES) + (IS_ENABLED(CONFIG_INTEL_VMX) && \ + vmx_secondary_exec_control & SECONDARY_EXEC_XSAVES) #define cpu_has_vmx_tsc_scaling \ (vmx_secondary_exec_control & SECONDARY_EXEC_TSC_SCALING) #define cpu_has_vmx_bus_lock_detection \ --=20 2.25.1 From nobody Mon Nov 25 05:27:17 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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a=rsa-sha256; c=relaxed; d=pobox.com; h=from:to:cc :subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; s=sasl; bh=ZWslkpob5/V135B4z/OMGz0wX maU/UJuAqh6Fq+RDfA=; b=XOp0rSK/zbpFTz0gM5wxM1MKCs75QVNnw8ssI6Xju okdVvjsIjTpS5shTxmaYiOwdFfhRb7oR5uf6D40D0a476aBDo5Z/chbhQsftjoNq JcwipDge7w72QFTHK/MugtEUoBFpbeadF/Y1coPlvMxzZPkZP/Si77FMipfg8hNC 1I= From: Sergiy Kibrik To: xen-devel@lists.xenproject.org Cc: Sergiy Kibrik , Andrew Cooper , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Jan Beulich , Stefano Stabellini , Xenia Ragiadakou Subject: [XEN PATCH v5 10/13] x86/vpmu: guard calls to vmx/svm functions Date: Tue, 30 Jul 2024 13:35:09 +0300 Message-Id: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-Pobox-Relay-ID: 66ADABE2-4E5F-11EF-ABA6-9625FCCAB05B-90055647!pb-smtp21.pobox.com Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @pobox.com) X-ZM-MESSAGEID: 1722335736119116600 Content-Type: text/plain; charset="utf-8" If VMX/SVM disabled in the build, we may still want to have vPMU drivers for PV guests. Yet in such case before using VMX/SVM features and functions we = have to explicitly check if they're available in the build. For this purpose (and also not to complicate conditionals) two helpers introduced -- is_{vmx,svm}_vcpu(v) that check both HVM & VMX/SVM conditions at the same t= ime, and they replace is_hvm_vcpu(v) macro in Intel/AMD PMU drivers. Signed-off-by: Sergiy Kibrik CC: Jan Beulich Reviewed-by: Jan Beulich --- changes in v5: - change kconfig option name SVM/VMX -> AMD_SVM/INTEL_VMX - replace is_hvm_vcpu() with is_{svm,vmx}_vcpu() changes in v4: - use IS_ENABLED(CONFIG_{VMX,SVM}) instead of using_{vmx,svm} - fix typo changes in v3: - introduced macro is_{vmx,svm}_vcpu(v) - changed description - reordered patch, do not modify conditionals w/ cpu_has_vmx_msr_bitmap ch= eck --- xen/arch/x86/cpu/vpmu_amd.c | 11 ++++++----- xen/arch/x86/cpu/vpmu_intel.c | 32 +++++++++++++++++--------------- 2 files changed, 23 insertions(+), 20 deletions(-) diff --git a/xen/arch/x86/cpu/vpmu_amd.c b/xen/arch/x86/cpu/vpmu_amd.c index 97e6315bd9..a082450e92 100644 --- a/xen/arch/x86/cpu/vpmu_amd.c +++ b/xen/arch/x86/cpu/vpmu_amd.c @@ -27,6 +27,7 @@ #define is_pmu_enabled(msr) ((msr) & (1ULL << MSR_F10H_EVNTSEL_EN_SHIFT)) #define set_guest_mode(msr) ((msr) |=3D (1ULL << MSR_F10H_EVNTSEL_GO_SHIFT= )) #define is_overflowed(msr) (!((msr) & (1ULL << (MSR_F10H_COUNTER_LENGTH - = 1)))) +#define is_svm_vcpu(v) (IS_ENABLED(CONFIG_AMD_SVM) && is_hvm_vcpu(v)) =20 static unsigned int __read_mostly num_counters; static const u32 __read_mostly *counters; @@ -289,7 +290,7 @@ static int cf_check amd_vpmu_save(struct vcpu *v, bool= to_guest) =20 context_save(v); =20 - if ( !vpmu_is_set(vpmu, VPMU_RUNNING) && is_hvm_vcpu(v) && + if ( !vpmu_is_set(vpmu, VPMU_RUNNING) && is_svm_vcpu(v) && is_msr_bitmap_on(vpmu) ) amd_vpmu_unset_msr_bitmap(v); =20 @@ -349,7 +350,7 @@ static int cf_check amd_vpmu_do_wrmsr(unsigned int msr,= uint64_t msr_content) return -EINVAL; =20 /* For all counters, enable guest only mode for HVM guest */ - if ( is_hvm_vcpu(v) && (type =3D=3D MSR_TYPE_CTRL) && + if ( is_svm_vcpu(v) && (type =3D=3D MSR_TYPE_CTRL) && !is_guest_mode(msr_content) ) { set_guest_mode(msr_content); @@ -363,7 +364,7 @@ static int cf_check amd_vpmu_do_wrmsr(unsigned int msr,= uint64_t msr_content) return 0; vpmu_set(vpmu, VPMU_RUNNING); =20 - if ( is_hvm_vcpu(v) && is_msr_bitmap_on(vpmu) ) + if ( is_svm_vcpu(v) && is_msr_bitmap_on(vpmu) ) amd_vpmu_set_msr_bitmap(v); } =20 @@ -372,7 +373,7 @@ static int cf_check amd_vpmu_do_wrmsr(unsigned int msr,= uint64_t msr_content) (is_pmu_enabled(msr_content) =3D=3D 0) && vpmu_is_set(vpmu, VPMU_R= UNNING) ) { vpmu_reset(vpmu, VPMU_RUNNING); - if ( is_hvm_vcpu(v) && is_msr_bitmap_on(vpmu) ) + if ( is_svm_vcpu(v) && is_msr_bitmap_on(vpmu) ) amd_vpmu_unset_msr_bitmap(v); release_pmu_ownership(PMU_OWNER_HVM); } @@ -415,7 +416,7 @@ static void cf_check amd_vpmu_destroy(struct vcpu *v) { struct vpmu_struct *vpmu =3D vcpu_vpmu(v); =20 - if ( is_hvm_vcpu(v) && is_msr_bitmap_on(vpmu) ) + if ( is_svm_vcpu(v) && is_msr_bitmap_on(vpmu) ) amd_vpmu_unset_msr_bitmap(v); =20 xfree(vpmu->context); diff --git a/xen/arch/x86/cpu/vpmu_intel.c b/xen/arch/x86/cpu/vpmu_intel.c index cd414165df..085495ab5f 100644 --- a/xen/arch/x86/cpu/vpmu_intel.c +++ b/xen/arch/x86/cpu/vpmu_intel.c @@ -54,6 +54,8 @@ #define MSR_PMC_ALIAS_MASK (~(MSR_IA32_PERFCTR0 ^ MSR_IA32_A_PERFCTR= 0)) static bool __read_mostly full_width_write; =20 +#define is_vmx_vcpu(v) (IS_ENABLED(CONFIG_INTEL_VMX) && is_hvm_vcpu(v)) + /* * MSR_CORE_PERF_FIXED_CTR_CTRL contains the configuration of all fixed * counters. 4 bits for every counter. @@ -266,10 +268,10 @@ static inline void __core2_vpmu_save(struct vcpu *v) rdmsrl(MSR_P6_EVNTSEL(i), xen_pmu_cntr_pair[i].control); } =20 - if ( !is_hvm_vcpu(v) ) + if ( !is_vmx_vcpu(v) ) rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, core2_vpmu_cxt->global_status); /* Save MSR to private context to make it fork-friendly */ - else if ( mem_sharing_enabled(v->domain) ) + else if ( is_vmx_vcpu(v) && mem_sharing_enabled(v->domain) ) vmx_read_guest_msr(v, MSR_CORE_PERF_GLOBAL_CTRL, &core2_vpmu_cxt->global_ctrl); } @@ -278,7 +280,7 @@ static int cf_check core2_vpmu_save(struct vcpu *v, boo= l to_guest) { struct vpmu_struct *vpmu =3D vcpu_vpmu(v); =20 - if ( !is_hvm_vcpu(v) ) + if ( !is_vmx_vcpu(v) ) wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0); =20 if ( !vpmu_are_all_set(vpmu, VPMU_CONTEXT_SAVE | VPMU_CONTEXT_LOADED) ) @@ -287,7 +289,7 @@ static int cf_check core2_vpmu_save(struct vcpu *v, boo= l to_guest) __core2_vpmu_save(v); =20 /* Unset PMU MSR bitmap to trap lazy load. */ - if ( !vpmu_is_set(vpmu, VPMU_RUNNING) && is_hvm_vcpu(v) && + if ( !vpmu_is_set(vpmu, VPMU_RUNNING) && is_vmx_vcpu(v) && cpu_has_vmx_msr_bitmap ) core2_vpmu_unset_msr_bitmap(v); =20 @@ -326,14 +328,14 @@ static inline void __core2_vpmu_load(struct vcpu *v) if ( vpmu_is_set(vcpu_vpmu(v), VPMU_CPU_HAS_DS) ) wrmsrl(MSR_IA32_DS_AREA, core2_vpmu_cxt->ds_area); =20 - if ( !is_hvm_vcpu(v) ) + if ( !is_vmx_vcpu(v) ) { wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, core2_vpmu_cxt->global_ovf_c= trl); core2_vpmu_cxt->global_ovf_ctrl =3D 0; wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, core2_vpmu_cxt->global_ctrl); } /* Restore MSR from context when used with a fork */ - else if ( mem_sharing_is_fork(v->domain) ) + else if ( is_vmx_vcpu(v) && mem_sharing_is_fork(v->domain) ) vmx_write_guest_msr(v, MSR_CORE_PERF_GLOBAL_CTRL, core2_vpmu_cxt->global_ctrl); } @@ -381,7 +383,7 @@ static int core2_vpmu_verify(struct vcpu *v) } =20 if ( vpmu_is_set(vpmu, VPMU_CPU_HAS_DS) && - !(is_hvm_vcpu(v) + !(is_vmx_vcpu(v) ? is_canonical_address(core2_vpmu_cxt->ds_area) : __addr_ok(core2_vpmu_cxt->ds_area)) ) return -EINVAL; @@ -442,7 +444,7 @@ static int cf_check core2_vpmu_alloc_resource(struct vc= pu *v) if ( !acquire_pmu_ownership(PMU_OWNER_HVM) ) return 0; =20 - if ( is_hvm_vcpu(v) ) + if ( is_vmx_vcpu(v) ) { if ( vmx_add_host_load_msr(v, MSR_CORE_PERF_GLOBAL_CTRL, 0) ) goto out_err; @@ -513,7 +515,7 @@ static int core2_vpmu_msr_common_check(u32 msr_index, i= nt *type, int *index) __core2_vpmu_load(current); vpmu_set(vpmu, VPMU_CONTEXT_LOADED); =20 - if ( is_hvm_vcpu(current) && cpu_has_vmx_msr_bitmap ) + if ( is_vmx_vcpu(current) && cpu_has_vmx_msr_bitmap ) core2_vpmu_set_msr_bitmap(current); } return 1; @@ -562,7 +564,7 @@ static int cf_check core2_vpmu_do_wrmsr(unsigned int ms= r, uint64_t msr_content) return -EINVAL; if ( vpmu_is_set(vpmu, VPMU_CPU_HAS_DS) ) { - if ( !(is_hvm_vcpu(v) ? is_canonical_address(msr_content) + if ( !(is_vmx_vcpu(v) ? is_canonical_address(msr_content) : __addr_ok(msr_content)) ) { gdprintk(XENLOG_WARNING, @@ -584,7 +586,7 @@ static int cf_check core2_vpmu_do_wrmsr(unsigned int ms= r, uint64_t msr_content) if ( msr_content & fixed_ctrl_mask ) return -EINVAL; =20 - if ( is_hvm_vcpu(v) ) + if ( is_vmx_vcpu(v) ) vmx_read_guest_msr(v, MSR_CORE_PERF_GLOBAL_CTRL, &core2_vpmu_cxt->global_ctrl); else @@ -653,7 +655,7 @@ static int cf_check core2_vpmu_do_wrmsr(unsigned int ms= r, uint64_t msr_content) if ( blocked ) return -EINVAL; =20 - if ( is_hvm_vcpu(v) ) + if ( is_vmx_vcpu(v) ) vmx_read_guest_msr(v, MSR_CORE_PERF_GLOBAL_CTRL, &core2_vpmu_cxt->global_ctrl); else @@ -672,7 +674,7 @@ static int cf_check core2_vpmu_do_wrmsr(unsigned int ms= r, uint64_t msr_content) wrmsrl(msr, msr_content); else { - if ( is_hvm_vcpu(v) ) + if ( is_vmx_vcpu(v) ) vmx_write_guest_msr(v, MSR_CORE_PERF_GLOBAL_CTRL, msr_content); else wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, msr_content); @@ -706,7 +708,7 @@ static int cf_check core2_vpmu_do_rdmsr(unsigned int ms= r, uint64_t *msr_content) *msr_content =3D core2_vpmu_cxt->global_status; break; case MSR_CORE_PERF_GLOBAL_CTRL: - if ( is_hvm_vcpu(v) ) + if ( is_vmx_vcpu(v) ) vmx_read_guest_msr(v, MSR_CORE_PERF_GLOBAL_CTRL, msr_conte= nt); else rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, *msr_content); @@ -808,7 +810,7 @@ static void cf_check core2_vpmu_destroy(struct vcpu *v) vpmu->context =3D NULL; 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charset="utf-8" From: Xenia Ragiadakou VIO_realmode_completion is specific to vmx realmode and thus the function arch_vcpu_ioreq_completion() has actual handling work only in VMX-enabled b= uild, as for the rest x86 and ARM build configurations it is basically a stub. Here a separate configuration option ARCH_IOREQ_COMPLETION introduced that = tells whether the platform we're building for requires any specific ioreq complet= ion handling. As of now only VMX has such requirement, so the option is selected by INTEL_VMX, for other configurations a generic default stub is provided (it is ARM's version of arch_vcpu_ioreq_completion() moved to common header= ). Signed-off-by: Xenia Ragiadakou Signed-off-by: Sergiy Kibrik CC: Julien Grall CC: Jan Beulich --- changes in v5: - introduce ARCH_IOREQ_COMPLETION option & put arch_vcpu_ioreq_completion(= ) under it - description changed changes in v4: - move whole arch_vcpu_ioreq_completion() under CONFIG_VMX and remove ARM's variant of this handler, as Julien suggested changes in v1: - put VIO_realmode_completion enum under #ifdef CONFIG_VMX --- xen/Kconfig | 3 +++ xen/arch/arm/ioreq.c | 6 ------ xen/arch/x86/Kconfig | 1 + xen/arch/x86/hvm/ioreq.c | 2 ++ xen/include/xen/ioreq.h | 10 ++++++++++ 5 files changed, 16 insertions(+), 6 deletions(-) diff --git a/xen/Kconfig b/xen/Kconfig index e459cdac0c..4f477fa39b 100644 --- a/xen/Kconfig +++ b/xen/Kconfig @@ -95,4 +95,7 @@ config LTO config ARCH_SUPPORTS_INT128 bool =20 +config ARCH_IOREQ_COMPLETION + bool + source "Kconfig.debug" diff --git a/xen/arch/arm/ioreq.c b/xen/arch/arm/ioreq.c index 5df755b48b..2e829d2e7f 100644 --- a/xen/arch/arm/ioreq.c +++ b/xen/arch/arm/ioreq.c @@ -135,12 +135,6 @@ bool arch_ioreq_complete_mmio(void) return false; } =20 -bool arch_vcpu_ioreq_completion(enum vio_completion completion) -{ - ASSERT_UNREACHABLE(); - return true; -} - /* * The "legacy" mechanism of mapping magic pages for the IOREQ servers * is x86 specific, so the following hooks don't need to be implemented on= Arm: diff --git a/xen/arch/x86/Kconfig b/xen/arch/x86/Kconfig index cd81fd1675..eff9eedc19 100644 --- a/xen/arch/x86/Kconfig +++ b/xen/arch/x86/Kconfig @@ -127,6 +127,7 @@ config AMD_SVM =20 config INTEL_VMX def_bool HVM + select ARCH_IOREQ_COMPLETION =20 config XEN_SHSTK bool "Supervisor Shadow Stacks" diff --git a/xen/arch/x86/hvm/ioreq.c b/xen/arch/x86/hvm/ioreq.c index 4eb7a70182..0153ac4195 100644 --- a/xen/arch/x86/hvm/ioreq.c +++ b/xen/arch/x86/hvm/ioreq.c @@ -29,6 +29,7 @@ bool arch_ioreq_complete_mmio(void) return handle_mmio(); } =20 +#ifdef CONFIG_ARCH_IOREQ_COMPLETION bool arch_vcpu_ioreq_completion(enum vio_completion completion) { switch ( completion ) @@ -51,6 +52,7 @@ bool arch_vcpu_ioreq_completion(enum vio_completion compl= etion) =20 return true; } +#endif =20 static gfn_t hvm_alloc_legacy_ioreq_gfn(struct ioreq_server *s) { diff --git a/xen/include/xen/ioreq.h b/xen/include/xen/ioreq.h index cd399adf17..31d88eb2fe 100644 --- a/xen/include/xen/ioreq.h +++ b/xen/include/xen/ioreq.h @@ -111,7 +111,17 @@ void ioreq_domain_init(struct domain *d); int ioreq_server_dm_op(struct xen_dm_op *op, struct domain *d, bool *const= _op); =20 bool arch_ioreq_complete_mmio(void); + +#ifdef CONFIG_ARCH_IOREQ_COMPLETION bool arch_vcpu_ioreq_completion(enum vio_completion completion); +#else +static inline bool arch_vcpu_ioreq_completion(enum vio_completion completi= on) +{ + ASSERT_UNREACHABLE(); + return true; +} +#endif + int arch_ioreq_server_map_pages(struct ioreq_server *s); void arch_ioreq_server_unmap_pages(struct ioreq_server *s); void arch_ioreq_server_enable(struct ioreq_server *s); --=20 2.25.1 From nobody Mon Nov 25 05:27:17 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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a=rsa-sha256; c=relaxed; d=pobox.com; h=from:to:cc :subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; s=sasl; bh=20gz3fWtI75N+KDktRlgBWgUQ 6Rep9w3jgom4UXRHu4=; b=pmIJ1TprgfIJprwHbYQgyIvJ6ug/BVHXtV3XPXygW 9e/ndA58yuCuWywOItW/xAqaVz9fpNBq+PvEQwxStPPhIjMrtdndazTZKHwguppR 73MOu/b5a6cyw6gBogVDGiBgkvdF3hw79DCTPHe3ToonCHasbnkzcc+FbOikHDIU u0= From: Sergiy Kibrik To: xen-devel@lists.xenproject.org Cc: Sergiy Kibrik , Jan Beulich , Andrew Cooper , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini , Xenia Ragiadakou Subject: [XEN PATCH v5 12/13] x86/vmx: replace CONFIG_HVM with CONFIG_INTEL_VMX in vmx.h Date: Tue, 30 Jul 2024 13:39:22 +0300 Message-Id: <11e0804a979f7ee7279bbf4741be0b2019967f37.1722333634.git.Sergiy_Kibrik@epam.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-Pobox-Relay-ID: FD66FCD2-4E5F-11EF-BFA6-9625FCCAB05B-90055647!pb-smtp21.pobox.com Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @pobox.com) X-ZM-MESSAGEID: 1722335991280116600 Content-Type: text/plain; charset="utf-8" As now we got a separate config option for VMX which itself depends on CONFIG_HVM, we need to use it to provide vmx_pi_hooks_{assign,deassign} stubs for case when VMX is disabled while HVM is enabled. Signed-off-by: Sergiy Kibrik Acked-by: Jan Beulich --- changes in v5: - change kconfig option name VMX -> INTEL_VMX changes in v4: - added tag changes in v3: - use CONFIG_VMX instead of CONFIG_HVM to provide stubs, instead of guardi= ng calls to vmx_pi_hooks_{assign,deassign} in iommu/vt-d code --- xen/arch/x86/include/asm/hvm/vmx/vmx.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/xen/arch/x86/include/asm/hvm/vmx/vmx.h b/xen/arch/x86/include/= asm/hvm/vmx/vmx.h index 1489dd05c2..f0ec459622 100644 --- a/xen/arch/x86/include/asm/hvm/vmx/vmx.h +++ b/xen/arch/x86/include/asm/hvm/vmx/vmx.h @@ -599,7 +599,7 @@ void vmx_pi_desc_fixup(unsigned int cpu); =20 void vmx_sync_exit_bitmap(struct vcpu *v); =20 -#ifdef CONFIG_HVM +#ifdef CONFIG_INTEL_VMX void vmx_pi_hooks_assign(struct domain *d); void vmx_pi_hooks_deassign(struct domain *d); #else --=20 2.25.1 From nobody Mon Nov 25 05:27:17 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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a=rsa-sha256; c=relaxed; d=pobox.com; h=from:to:cc :subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; s=sasl; bh=PLWtHtTVfhKJOmXqlZPRu0lCA GY1YvlMSG00r7Ubp84=; b=XVYLtJbJQYRYqEmkmnVIlq1bf4jiTsiMMtj6IZys6 WTImyCfFEwdqsDrRIAMQq1YBx7FQxBzvq/Z3kyvUGyxYTJdXcz8dY8JaFh7ie3O9 LJEWmPAL0rI3hDV75HaraKMiQfA5sndGf2rGMgZWsAMi5R6DsFDjyGkFDISQppg6 q8= From: Sergiy Kibrik To: xen-devel@lists.xenproject.org Cc: Xenia Ragiadakou , Jan Beulich , Andrew Cooper , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini , Xenia Ragiadakou , Sergiy Kibrik Subject: [XEN PATCH v5 13/13] x86/hvm: make AMD-V and Intel VT-x support configurable Date: Tue, 30 Jul 2024 13:41:29 +0300 Message-Id: <827008e4af26814e4cd4bf6abbb92c77fc136aa8.1722333634.git.Sergiy_Kibrik@epam.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-Pobox-Relay-ID: 4901D3BA-4E60-11EF-9654-9625FCCAB05B-90055647!pb-smtp21.pobox.com Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @pobox.com) X-ZM-MESSAGEID: 1722336117757116600 Content-Type: text/plain; charset="utf-8" From: Xenia Ragiadakou Provide the user with configuration control over the cpu virtualization sup= port in Xen by making AMD_SVM and INTEL_VMX options user selectable. To preserve the current default behavior, both options depend on HVM and default to value of HVM. To prevent users from unknowingly disabling virtualization support, make the controls user selectable only if EXPERT is enabled. No functional change intended. Signed-off-by: Xenia Ragiadakou Signed-off-by: Sergiy Kibrik Reviewed-by: Stefano Stabellini Acked-by: Jan Beulich --- changes in v5: - change kconfig option name SVM/VMX -> AMD_SVM/INTEL_VMX changes in v3: - only tags added changes in v2: - remove dependency of build options IOMMU/AMD_IOMMU on VMX/SVM options --- xen/arch/x86/Kconfig | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/xen/arch/x86/Kconfig b/xen/arch/x86/Kconfig index eff9eedc19..f6a90d71fb 100644 --- a/xen/arch/x86/Kconfig +++ b/xen/arch/x86/Kconfig @@ -123,11 +123,25 @@ config HVM If unsure, say Y. =20 config AMD_SVM - def_bool HVM + bool "AMD-V" if EXPERT + depends on HVM + default HVM + help + Enables virtual machine extensions on platforms that implement the + AMD Virtualization Technology (AMD-V). + If your system includes a processor with AMD-V support, say Y. + If in doubt, say Y. =20 config INTEL_VMX - def_bool HVM + bool "Intel VT-x" if EXPERT + depends on HVM + default HVM select ARCH_IOREQ_COMPLETION + help + Enables virtual machine extensions on platforms that implement the + Intel Virtualization Technology (Intel VT-x). + If your system includes a processor with Intel VT-x support, say Y. + If in doubt, say Y. =20 config XEN_SHSTK bool "Supervisor Shadow Stacks" --=20 2.25.1