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Smith" Subject: [PATCH v12 1/8] xen/riscv: disable unnecessary configs Date: Wed, 29 May 2024 21:55:02 +0200 Message-ID: <35cf9d52e538aab964a3ecc050260abb3f27c60d.1717008161.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1717012543836100001 Content-Type: text/plain; charset="utf-8" Disables unnecessary configs for two cases: 1. By utilizing EXTRA_FIXED_RANDCONFIG for randconfig builds (GitLab CI job= s). 2. By using tiny64_defconfig for non-randconfig builds. Only configs which lead to compilation issues were disabled. Remove lines related to disablement of configs which aren't affected compilation: -# CONFIG_SCHED_CREDIT is not set -# CONFIG_SCHED_RTDS is not set -# CONFIG_SCHED_NULL is not set -# CONFIG_SCHED_ARINC653 is not set -# CONFIG_TRACEBUFFER is not set -# CONFIG_HYPFS is not set -# CONFIG_SPECULATIVE_HARDEN_ARRAY is not set To allow CONFIG_ARGO build happy it was included to as ARGO requires p2m_type_t ( p2m_ram_rw ) and declaration of check_get_page_from_gfn() from xen/p2m-common.h. Also, it was included to asm/p2m.h as after the latter was included to the compilation error that EINVAL, EOPNOTSUPP aren't declared started to occur. CONFIG_XSM=3Dn as it requires an introduction of: * boot_module_find_by_kind() * BOOTMOD_XSM * struct bootmodule * copy_from_paddr() The mentioned things aren't introduced now. CPU_BOOT_TIME_CPUPOOLS requires an introduction of cpu_physical_id() and acpi_disabled, so it is disabled for now. PERF_COUNTERS requires asm/perf.h and asm/perfc-defn.h, so it is also disabled for now, as RISC-V hasn't introduced this headers yet. LIVEPATCH isn't ready for RISC-V too and it can be overriden by randconfig, so to avoid compilation errors for randconfig it is disabled for now. Signed-off-by: Oleksii Kurochko Acked-by: Andrew Cooper --- Changes in V10-V12: - Nothing changed. Only rebase. --- Changes in V9: - update the commit message: add info about LIVEPATCH and PERF_COUNTERS. --- Changes in V8: - disabled CPU_BOOT_TIME_CPUPOOLS as it requires an introduction of cpu_ph= ysical_id() and acpi_disabled. - leave XSM disabled, add explanation in the commit message. - drop HYPFS as the patch was provided to resolve compilation issue when t= his condif is enabled for RISC-V. - include asm/p2m.h to asm/domain.h, and xen/errno.h to asm/p2m.h to drop = ARGO config from tiny64_defconfing and build.yaml. - update the commit message. --- Changes in V7: - Disable only configs which cause compilation issues. - Update the commit message. --- Changes in V6: - Nothing changed. Only rebase. --- Changes in V5: - Rebase and drop duplicated configs in EXTRA_FIXED_RANDCONFIG list - Update the commit message --- Changes in V4: - Nothing changed. Only rebase --- Changes in V3: - Remove EXTRA_FIXED_RANDCONFIG for non-randconfig jobs. For non-randconfig jobs, it is sufficient to disable configs by using th= e defconfig. - Remove double blank lines in build.yaml file before archlinux-current-gc= c-riscv64-debug --- Changes in V2: - update the commit message. - remove xen/arch/riscv/Kconfig changes. --- automation/gitlab-ci/build.yaml | 4 ++++ xen/arch/riscv/configs/tiny64_defconfig | 12 +++++------- xen/arch/riscv/include/asm/domain.h | 2 ++ xen/arch/riscv/include/asm/p2m.h | 2 ++ 4 files changed, 13 insertions(+), 7 deletions(-) diff --git a/automation/gitlab-ci/build.yaml b/automation/gitlab-ci/build.y= aml index 5985be9378..3290a36dca 100644 --- a/automation/gitlab-ci/build.yaml +++ b/automation/gitlab-ci/build.yaml @@ -379,10 +379,14 @@ alpine-3.18-gcc-debug-arm64: .riscv-fixed-randconfig: variables: &riscv-fixed-randconfig EXTRA_FIXED_RANDCONFIG: | + CONFIG_BOOT_TIME_CPUPOOLS=3Dn CONFIG_COVERAGE=3Dn CONFIG_EXPERT=3Dy CONFIG_GRANT_TABLE=3Dn CONFIG_MEM_ACCESS=3Dn + CONFIG_PERF_COUNTERS=3Dn + CONFIG_LIVEPATCH=3Dn + CONFIG_XSM=3Dn =20 archlinux-current-gcc-riscv64-debug: extends: .gcc-riscv64-cross-build-debug diff --git a/xen/arch/riscv/configs/tiny64_defconfig b/xen/arch/riscv/confi= gs/tiny64_defconfig index 09defe236b..fc7a04872f 100644 --- a/xen/arch/riscv/configs/tiny64_defconfig +++ b/xen/arch/riscv/configs/tiny64_defconfig @@ -1,12 +1,10 @@ -# CONFIG_SCHED_CREDIT is not set -# CONFIG_SCHED_RTDS is not set -# CONFIG_SCHED_NULL is not set -# CONFIG_SCHED_ARINC653 is not set -# CONFIG_TRACEBUFFER is not set -# CONFIG_HYPFS is not set +# CONFIG_BOOT_TIME_CPUPOOLS is not set # CONFIG_GRANT_TABLE is not set -# CONFIG_SPECULATIVE_HARDEN_ARRAY is not set # CONFIG_MEM_ACCESS is not set +# CONFIG_PERF_COUNTERS is not set +# CONFIG_COVERAGE is not set +# CONFIG_LIVEPATCH is not set +# CONFIG_XSM is not set =20 CONFIG_RISCV_64=3Dy CONFIG_DEBUG=3Dy diff --git a/xen/arch/riscv/include/asm/domain.h b/xen/arch/riscv/include/a= sm/domain.h index 027bfa8a93..16a9dd57aa 100644 --- a/xen/arch/riscv/include/asm/domain.h +++ b/xen/arch/riscv/include/asm/domain.h @@ -5,6 +5,8 @@ #include #include =20 +#include + struct hvm_domain { uint64_t params[HVM_NR_PARAMS]; diff --git a/xen/arch/riscv/include/asm/p2m.h b/xen/arch/riscv/include/asm/= p2m.h index 387f372b5d..26860c0ae7 100644 --- a/xen/arch/riscv/include/asm/p2m.h +++ b/xen/arch/riscv/include/asm/p2m.h @@ -2,6 +2,8 @@ #ifndef __ASM_RISCV_P2M_H__ #define __ASM_RISCV_P2M_H__ =20 +#include + #include =20 #define paddr_bits PADDR_BITS --=20 2.45.0 From nobody Sun Nov 24 16:33:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1717012538; cv=none; d=zohomail.com; s=zohoarc; b=eTvjTsfu6Yq1SRD/QjK2M2CCwFtV08Tko5Zrab2YA3bwspSk5OkDzrZ7iheRbV7coH9t0gMtj+ilV3iWpZAObIoWHCMjtrvH8FHB74dQZW0L7SnGxB4d4V0BSyNjQa1H4gGMBSCXoL9cFJ+dgGqHn4GzP+5G67aFzeVbKlRPtuU= ARC-Message-Signature: i=1; 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([94.75.70.14]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5297066b249sm1344203e87.178.2024.05.29.12.55.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 May 2024 12:55:14 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 5e3be7a4-1df5-11ef-90a1-e314d9c70b13 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1717012515; x=1717617315; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=YVBXN5m3ZDHo1lfuHzyltxfOnJFU0pSyHgrlkIAnckU=; b=VkJ8aBeqhPAZRb9xwykDdEuUB4rbf6kjOkRcirCWCsp4BZ3ghATBXhqvnH90nca+g5 DifOsL/aYoIeD6+NV1sANXb/Fj73BWJSe49uYJCAMzEMzuPhUZ48opNbQn1CA+X599iL 5qbgl06f8/Rj6TJICFvgb7QLZBhjaUf7ca9sdxjaFU6T3okhdfVv3JPEphJRVzD1Bmnc EVVioO+rkbVoQwagIgrNMFJPC4KcS3+EbeN9XhDVTX6gl7VxvkDm1UwsI4Swm9DOLDcn +uLZRLtedlCSWBTqSAIwp8jeN/XwrunPwIHj5gqq++zQmhUDWKE7Vu+v1bN+3j7P9HO8 3E5g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1717012515; x=1717617315; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YVBXN5m3ZDHo1lfuHzyltxfOnJFU0pSyHgrlkIAnckU=; b=AJKtaYlN7J0Gxsil+NxQ3zA01V+mv5FQHhKRLdmM70Imo7J5oPr3CzYfvtOQIVnd0i lWY+MEZgMQLeAArLTaoOgCyT3QtqKWZ4zTyCVCYejg7VEpBIZCR8qFWbrfyeD28pQDxy kQAgamQCCkntdW1LtGybbPBkYGompWfTAfw0aeTAta+MG4lAkw4kb8kWQri6OglCmSLh UdrEF6bCCK+IhMDjBzxazD784VF5kcTbOU0Crj1CcNbT3omjpACU8O8Z9xkwb4ovH78n 8NiMFPEdUAHNGdO4t+jHj1FGkPRmDwyEADPzKWfBu/hct+OQRY0vlFbPDXugvfOG0+h3 Qi3Q== X-Gm-Message-State: AOJu0YxStiB55mIq0s7IyCIe/X2I7HutEBybS+fXZuMvEa215zUtt8eo 3O7b4J8e+K9ttBitWcbJldiTLTUuMIubMCX+kqAzHYKYL6T64Po7v2sXq1qB X-Google-Smtp-Source: AGHT+IGxVp6idhC7Wfi+drTwdCPMybv1eYUhKHQinDOkohJRTyyuhIhTpio2EZiatCVKYOV4qkkf7w== X-Received: by 2002:ac2:4839:0:b0:529:b3c9:7261 with SMTP id 2adb3069b0e04-52b7d40f4c4mr106781e87.5.1717012514495; Wed, 29 May 2024 12:55:14 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk , Andrew Cooper , George Dunlap , Jan Beulich , Shawn Anastasio , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Subject: [PATCH v12 2/8] xen: introduce generic non-atomic test_*bit() Date: Wed, 29 May 2024 21:55:03 +0200 Message-ID: <526d2a5a76f03aa0e3cc7ee3192b1c87834f0e9e.1717008161.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1717012539847100003 Content-Type: text/plain; charset="utf-8" The following generic functions were introduced: * test_bit * generic__test_and_set_bit * generic__test_and_clear_bit * generic__test_and_change_bit These functions and macros can be useful for architectures that don't have corresponding arch-specific instructions. Also, the patch introduces the following generics which are used by the functions mentioned above: * BITOP_BITS_PER_WORD * BITOP_MASK * BITOP_WORD * BITOP_TYPE The following approach was chosen for generic*() and arch*() bit operation functions: If the bit operation function that is going to be generic starts with the prefix "__", then the corresponding generic/arch function will also contain the "__" prefix. For example: * test_bit() will be defined using arch_test_bit() and generic_test_bit(). * __test_and_set_bit() will be defined using arch__test_and_set_bit() and generic__test_and_set_bit(). Signed-off-by: Oleksii Kurochko Reviewed-by: Jan Beulich --- Changes in V12: - revert change of moving the definition of BITS_PER_BYTE from /bito= ps.h to xen/bitops.h. ( a separate patch will be provided to put BITS_PER_BYTE to proper place= ) - drop comments on top of generic_*() functions and update the comments ab= ove __test_*() and test_bit(). - update how static inline __test_*() are defined ( drop pointless fallbac= k #define ) and test_bit(). - drop the footer after Signed-off-by. --- Changes in V11: - fix identation in generic_test_bit() function. - move definition of BITS_PER_BYTE from /bitops.h to xen/bitops.h - drop the changes in arm64/livepatch.c. - update the the comments on top of functions: generic__test_and_set_bit()= , generic__test_and_clear_bit(), generic__test_and_change_bit(), generic_test_bit(). - Update footer after Signed-off section. - Rebase the patch on top of staging branch, so it can be merged when nece= ssary approves will be given. - ? add Reviewed-by: Jan Beulich . --- Changes in V10: - update the commit message. ( re-order paragraphs and add explanation usa= ge of prefix "__" in bit operation function names ) - add parentheses around the whole expression of bitop_bad_size() macros. - move macros bitop_bad_size() above asm/bitops.h as it is not arch-specif= ic anymore and there is no need for overriding it. - drop macros check_bitop_size() and use "if ( bitop_bad_size(addr) ) __bi= top_bad_size();" implictly where it is needed. - in use 'int' as a first parameter for __test_and_*(), gen= eric__test_and_*() to be consistent with how the mentioned functions were declared in the origina= l per-arch functions. - add 'const' to p variable in generic_test_bit(). - move definition of BITOP_BITS_PER_WORD and bitop_uint_t to xen/bitops.h = as we don't allow for arch overrides these definitions anymore. --- Changes in V9: - move up xen/bitops.h in ppc/asm/page.h. - update defintion of arch_check_bitop_size. And drop correspondent macros from x86/asm/bitops.h - drop parentheses in generic__test_and_set_bit() for definition of local variable p. - fix indentation inside #ifndef BITOP_TYPE...#endif - update the commit message. --- Changes in V8: - drop __pure for function which uses volatile. - drop unnessary () in generic__test_and_change_bit() for addr casting. - update prototype of generic_test_bit() and test_bit(): now it returns b= ool instead of int. - update generic_test_bit() to use BITOP_MASK(). - Deal with fls{l} changes: it should be in the patch with introduced gen= eric fls{l}. - add a footer with explanation of dependency on an uncommitted patch aft= er Signed-off. - abstract bitop_size(). - move BITOP_TYPE define to . --- Changes in V7: - move everything to xen/bitops.h to follow the same approach for all gen= eric bit ops. - put together BITOP_BITS_PER_WORD and bitops_uint_t. - make BITOP_MASK more generic. - drop #ifdef ... #endif around BITOP_MASK, BITOP_WORD as they are generic enough. - drop "_" for generic__{test_and_set_bit,...}(). - drop " !=3D 0" for functions which return bool. - add volatile during the cast for generic__{...}(). - update the commit message. - update arch related code to follow the proposed generic approach. --- Changes in V6: - Nothing changed ( only rebase ) --- Changes in V5: - new patch --- xen/arch/arm/include/asm/bitops.h | 67 -------------- xen/arch/ppc/include/asm/bitops.h | 52 ----------- xen/arch/ppc/include/asm/page.h | 2 +- xen/arch/ppc/mm-radix.c | 2 +- xen/arch/x86/include/asm/bitops.h | 31 ++----- xen/include/xen/bitops.h | 146 ++++++++++++++++++++++++++++++ 6 files changed, 157 insertions(+), 143 deletions(-) diff --git a/xen/arch/arm/include/asm/bitops.h b/xen/arch/arm/include/asm/b= itops.h index 8f4bdc09d1..3c023103f7 100644 --- a/xen/arch/arm/include/asm/bitops.h +++ b/xen/arch/arm/include/asm/bitops.h @@ -22,9 +22,6 @@ #define __set_bit(n,p) set_bit(n,p) #define __clear_bit(n,p) clear_bit(n,p) =20 -#define BITOP_BITS_PER_WORD 32 -#define BITOP_MASK(nr) (1UL << ((nr) % BITOP_BITS_PER_WORD)) -#define BITOP_WORD(nr) ((nr) / BITOP_BITS_PER_WORD) #define BITS_PER_BYTE 8 =20 #define ADDR (*(volatile int *) addr) @@ -76,70 +73,6 @@ bool test_and_change_bit_timeout(int nr, volatile void *= p, bool clear_mask16_timeout(uint16_t mask, volatile void *p, unsigned int max_try); =20 -/** - * __test_and_set_bit - Set a bit and return its old value - * @nr: Bit to set - * @addr: Address to count from - * - * This operation is non-atomic and can be reordered. - * If two examples of this operation race, one can appear to succeed - * but actually fail. You must protect multiple accesses with a lock. - */ -static inline int __test_and_set_bit(int nr, volatile void *addr) -{ - unsigned int mask =3D BITOP_MASK(nr); - volatile unsigned int *p =3D - ((volatile unsigned int *)addr) + BITOP_WORD(nr); - unsigned int old =3D *p; - - *p =3D old | mask; - return (old & mask) !=3D 0; -} - -/** - * __test_and_clear_bit - Clear a bit and return its old value - * @nr: Bit to clear - * @addr: Address to count from - * - * This operation is non-atomic and can be reordered. - * If two examples of this operation race, one can appear to succeed - * but actually fail. You must protect multiple accesses with a lock. - */ -static inline int __test_and_clear_bit(int nr, volatile void *addr) -{ - unsigned int mask =3D BITOP_MASK(nr); - volatile unsigned int *p =3D - ((volatile unsigned int *)addr) + BITOP_WORD(nr); - unsigned int old =3D *p; - - *p =3D old & ~mask; - return (old & mask) !=3D 0; -} - -/* WARNING: non atomic and it can be reordered! */ -static inline int __test_and_change_bit(int nr, - volatile void *addr) -{ - unsigned int mask =3D BITOP_MASK(nr); - volatile unsigned int *p =3D - ((volatile unsigned int *)addr) + BITOP_WORD(nr); - unsigned int old =3D *p; - - *p =3D old ^ mask; - return (old & mask) !=3D 0; -} - -/** - * test_bit - Determine whether a bit is set - * @nr: bit number to test - * @addr: Address to start counting from - */ -static inline int test_bit(int nr, const volatile void *addr) -{ - const volatile unsigned int *p =3D (const volatile unsigned int *)= addr; - return 1UL & (p[BITOP_WORD(nr)] >> (nr & (BITOP_BITS_PER_WORD-1))); -} - #define arch_ffs(x) ((x) ? 1 + __builtin_ctz(x) : 0) #define arch_ffsl(x) ((x) ? 1 + __builtin_ctzl(x) : 0) #define arch_fls(x) ((x) ? 32 - __builtin_clz(x) : 0) diff --git a/xen/arch/ppc/include/asm/bitops.h b/xen/arch/ppc/include/asm/b= itops.h index 8119b5ace8..eb3355812e 100644 --- a/xen/arch/ppc/include/asm/bitops.h +++ b/xen/arch/ppc/include/asm/bitops.h @@ -15,9 +15,6 @@ #define __set_bit(n, p) set_bit(n, p) #define __clear_bit(n, p) clear_bit(n, p) =20 -#define BITOP_BITS_PER_WORD 32 -#define BITOP_MASK(nr) (1U << ((nr) % BITOP_BITS_PER_WORD)) -#define BITOP_WORD(nr) ((nr) / BITOP_BITS_PER_WORD) #define BITS_PER_BYTE 8 =20 /* PPC bit number conversion */ @@ -69,17 +66,6 @@ static inline void clear_bit(int nr, volatile void *addr) clear_bits(BITOP_MASK(nr), (volatile unsigned int *)addr + BITOP_WORD(= nr)); } =20 -/** - * test_bit - Determine whether a bit is set - * @nr: bit number to test - * @addr: Address to start counting from - */ -static inline int test_bit(int nr, const volatile void *addr) -{ - const volatile unsigned int *p =3D addr; - return 1 & (p[BITOP_WORD(nr)] >> (nr & (BITOP_BITS_PER_WORD - 1))); -} - static inline unsigned int test_and_clear_bits( unsigned int mask, volatile unsigned int *p) @@ -133,44 +119,6 @@ static inline int test_and_set_bit(unsigned int nr, vo= latile void *addr) (volatile unsigned int *)addr + BITOP_WORD(nr)) !=3D 0; } =20 -/** - * __test_and_set_bit - Set a bit and return its old value - * @nr: Bit to set - * @addr: Address to count from - * - * This operation is non-atomic and can be reordered. - * If two examples of this operation race, one can appear to succeed - * but actually fail. You must protect multiple accesses with a lock. - */ -static inline int __test_and_set_bit(int nr, volatile void *addr) -{ - unsigned int mask =3D BITOP_MASK(nr); - volatile unsigned int *p =3D (volatile unsigned int *)addr + BITOP_WOR= D(nr); - unsigned int old =3D *p; - - *p =3D old | mask; - return (old & mask) !=3D 0; -} - -/** - * __test_and_clear_bit - Clear a bit and return its old value - * @nr: Bit to clear - * @addr: Address to count from - * - * This operation is non-atomic and can be reordered. - * If two examples of this operation race, one can appear to succeed - * but actually fail. You must protect multiple accesses with a lock. - */ -static inline int __test_and_clear_bit(int nr, volatile void *addr) -{ - unsigned int mask =3D BITOP_MASK(nr); - volatile unsigned int *p =3D (volatile unsigned int *)addr + BITOP_WOR= D(nr); - unsigned int old =3D *p; - - *p =3D old & ~mask; - return (old & mask) !=3D 0; -} - #define arch_ffs(x) ((x) ? 1 + __builtin_ctz(x) : 0) #define arch_ffsl(x) ((x) ? 1 + __builtin_ctzl(x) : 0) #define arch_fls(x) ((x) ? 32 - __builtin_clz(x) : 0) diff --git a/xen/arch/ppc/include/asm/page.h b/xen/arch/ppc/include/asm/pag= e.h index 890e285051..6d4cd2611c 100644 --- a/xen/arch/ppc/include/asm/page.h +++ b/xen/arch/ppc/include/asm/page.h @@ -2,9 +2,9 @@ #ifndef _ASM_PPC_PAGE_H #define _ASM_PPC_PAGE_H =20 +#include #include =20 -#include #include =20 #define PDE_VALID PPC_BIT(0) diff --git a/xen/arch/ppc/mm-radix.c b/xen/arch/ppc/mm-radix.c index ab5a10695c..9055730997 100644 --- a/xen/arch/ppc/mm-radix.c +++ b/xen/arch/ppc/mm-radix.c @@ -1,11 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include #include #include #include #include #include =20 -#include #include #include #include diff --git a/xen/arch/x86/include/asm/bitops.h b/xen/arch/x86/include/asm/b= itops.h index fc9fe73ad5..8ee5cbf127 100644 --- a/xen/arch/x86/include/asm/bitops.h +++ b/xen/arch/x86/include/asm/bitops.h @@ -19,9 +19,6 @@ #define ADDR (*(volatile int *) addr) #define CONST_ADDR (*(const volatile int *) addr) =20 -extern void __bitop_bad_size(void); -#define bitop_bad_size(addr) (sizeof(*(addr)) < 4) - /** * set_bit - Atomically set a bit in memory * @nr: the bit to set @@ -175,7 +172,7 @@ static inline int test_and_set_bit(int nr, volatile voi= d *addr) }) =20 /** - * __test_and_set_bit - Set a bit and return its old value + * arch__test_and_set_bit - Set a bit and return its old value * @nr: Bit to set * @addr: Address to count from * @@ -183,7 +180,7 @@ static inline int test_and_set_bit(int nr, volatile voi= d *addr) * If two examples of this operation race, one can appear to succeed * but actually fail. You must protect multiple accesses with a lock. */ -static inline int __test_and_set_bit(int nr, void *addr) +static inline int arch__test_and_set_bit(int nr, volatile void *addr) { int oldbit; =20 @@ -194,10 +191,7 @@ static inline int __test_and_set_bit(int nr, void *add= r) =20 return oldbit; } -#define __test_and_set_bit(nr, addr) ({ \ - if ( bitop_bad_size(addr) ) __bitop_bad_size(); \ - __test_and_set_bit(nr, addr); \ -}) +#define arch__test_and_set_bit arch__test_and_set_bit =20 /** * test_and_clear_bit - Clear a bit and return its old value @@ -224,7 +218,7 @@ static inline int test_and_clear_bit(int nr, volatile v= oid *addr) }) =20 /** - * __test_and_clear_bit - Clear a bit and return its old value + * arch__test_and_clear_bit - Clear a bit and return its old value * @nr: Bit to set * @addr: Address to count from * @@ -232,7 +226,7 @@ static inline int test_and_clear_bit(int nr, volatile v= oid *addr) * If two examples of this operation race, one can appear to succeed * but actually fail. You must protect multiple accesses with a lock. */ -static inline int __test_and_clear_bit(int nr, void *addr) +static inline int arch__test_and_clear_bit(int nr, volatile void *addr) { int oldbit; =20 @@ -243,13 +237,10 @@ static inline int __test_and_clear_bit(int nr, void *= addr) =20 return oldbit; } -#define __test_and_clear_bit(nr, addr) ({ \ - if ( bitop_bad_size(addr) ) __bitop_bad_size(); \ - __test_and_clear_bit(nr, addr); \ -}) +#define arch__test_and_clear_bit arch__test_and_clear_bit =20 /* WARNING: non atomic and it can be reordered! */ -static inline int __test_and_change_bit(int nr, void *addr) +static inline int arch__test_and_change_bit(int nr, volatile void *addr) { int oldbit; =20 @@ -260,10 +251,7 @@ static inline int __test_and_change_bit(int nr, void *= addr) =20 return oldbit; } -#define __test_and_change_bit(nr, addr) ({ \ - if ( bitop_bad_size(addr) ) __bitop_bad_size(); \ - __test_and_change_bit(nr, addr); \ -}) +#define arch__test_and_change_bit arch__test_and_change_bit =20 /** * test_and_change_bit - Change a bit and return its new value @@ -307,8 +295,7 @@ static inline int variable_test_bit(int nr, const volat= ile void *addr) return oldbit; } =20 -#define test_bit(nr, addr) ({ \ - if ( bitop_bad_size(addr) ) __bitop_bad_size(); \ +#define arch_test_bit(nr, addr) ({ \ __builtin_constant_p(nr) ? \ constant_test_bit(nr, addr) : \ variable_test_bit(nr, addr); \ diff --git a/xen/include/xen/bitops.h b/xen/include/xen/bitops.h index 6a5e28730a..be54122556 100644 --- a/xen/include/xen/bitops.h +++ b/xen/include/xen/bitops.h @@ -4,6 +4,17 @@ #include #include =20 +#define BITOP_BITS_PER_WORD 32 +typedef uint32_t bitop_uint_t; + +#define BITOP_MASK(nr) ((bitop_uint_t)1 << ((nr) % BITOP_BITS_PER_WORD)) + +#define BITOP_WORD(nr) ((nr) / BITOP_BITS_PER_WORD) + +extern void __bitop_bad_size(void); + +#define bitop_bad_size(addr) (sizeof(*(addr)) < sizeof(bitop_uint_t)) + #include =20 /* @@ -94,6 +105,141 @@ static always_inline __pure unsigned int fls64(uint64_= t x) =20 /* --------------------- Please tidy below here --------------------- */ =20 +static always_inline bool +generic__test_and_set_bit(int nr, volatile void *addr) +{ + bitop_uint_t mask =3D BITOP_MASK(nr); + volatile bitop_uint_t *p =3D (volatile bitop_uint_t *)addr + BITOP_WOR= D(nr); + bitop_uint_t old =3D *p; + + *p =3D old | mask; + return (old & mask); +} + +static always_inline bool +generic__test_and_clear_bit(int nr, volatile void *addr) +{ + bitop_uint_t mask =3D BITOP_MASK(nr); + volatile bitop_uint_t *p =3D (volatile bitop_uint_t *)addr + BITOP_WOR= D(nr); + bitop_uint_t old =3D *p; + + *p =3D old & ~mask; + return (old & mask); +} + +static always_inline bool +generic__test_and_change_bit(int nr, volatile void *addr) +{ + bitop_uint_t mask =3D BITOP_MASK(nr); + volatile bitop_uint_t *p =3D (volatile bitop_uint_t *)addr + BITOP_WOR= D(nr); + bitop_uint_t old =3D *p; + + *p =3D old ^ mask; + return (old & mask); +} + +static always_inline bool generic_test_bit(int nr, const volatile void *ad= dr) +{ + bitop_uint_t mask =3D BITOP_MASK(nr); + const volatile bitop_uint_t *p =3D + (const volatile bitop_uint_t *)addr + BITOP_WORD(nr); + + return (*p & mask); +} + +/** + * __test_and_set_bit - Set a bit and return its old value + * @nr: Bit to set + * @addr: Address to count from + * + * This operation is non-atomic and can be reordered. + * If two instances of this operation race, both may update memory with + * their view of the new value, not taking into account the update the + * respectively other one did. It should be protected from potentially + * racy behavior. + */ +static always_inline bool +__test_and_set_bit(int nr, volatile void *addr) +{ +#ifdef arch__test_and_set_bit + return arch__test_and_set_bit(nr, addr); +#else + return generic__test_and_set_bit(nr, addr); +#endif +} +#define __test_and_set_bit(nr, addr) ({ \ + if ( bitop_bad_size(addr) ) __bitop_bad_size(); \ + __test_and_set_bit(nr, addr); \ +}) + +/** + * __test_and_clear_bit - Clear a bit and return its old value + * @nr: Bit to clear + * @addr: Address to count from + * + * This operation is non-atomic and can be reordered. + * If two instances of this operation race, both may update memory with + * their view of the new value, not taking into account the update the + * respectively other one did. It should be protected from potentially + * racy behavior. + */ +static always_inline bool +__test_and_clear_bit(int nr, volatile void *addr) +{ +#ifdef arch__test_and_clear_bit + return arch__test_and_clear_bit(nr, addr); +#else + return generic__test_and_clear_bit(nr, addr); +#endif +} +#define __test_and_clear_bit(nr, addr) ({ \ + if ( bitop_bad_size(addr) ) __bitop_bad_size(); \ + __test_and_clear_bit(nr, addr); \ +}) + +/** + * __test_and_change_bit - Change a bit and return its old value + * @nr: Bit to change + * @addr: Address to count from + * + * This operation is non-atomic and can be reordered. + * If two instances of this operation race, both may update memory with + * their view of the new value, not taking into account the update the + * respectively other one did. It should be protected from potentially + * racy behavior. + */ +static always_inline bool +__test_and_change_bit(int nr, volatile void *addr) +{ +#ifdef arch__test_and_change_bit + return arch__test_and_change_bit(nr, addr); +#else + return generic__test_and_change_bit(nr, addr); +#endif +} +#define __test_and_change_bit(nr, addr) ({ \ + if ( bitop_bad_size(addr) ) __bitop_bad_size(); \ + __test_and_change_bit(nr, addr); \ +}) + +/** + * test_bit - Determine whether a bit is set + * @nr: bit number to test + * @addr: Address to start counting from + */ +static always_inline bool test_bit(int nr, const volatile void *addr) +{ +#ifdef arch_test_bit + return arch_test_bit(nr, addr); +#else + return generic_test_bit(nr, addr); +#endif +} +#define test_bit(nr, addr) ({ \ + if ( bitop_bad_size(addr) ) __bitop_bad_size(); \ + test_bit(nr, addr); \ +}) + #ifndef find_next_bit /** * find_next_bit - find the next set bit in a memory region --=20 2.45.0 From nobody Sun Nov 24 16:33:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1717012538; cv=none; d=zohomail.com; s=zohoarc; b=Y9pSsxeJmd3cnMTr78BchyxQi9wcdY+6S/6JxlRvzKIyt93khgqFHZRE0N6p6jlBpEYfxR+AF3/Gr9aLU7fzBp/gUbuIYjLZbq1ibBxzcTa7VIqPxuGAKDUfovIRYAAwvh1ZsQrzme1TKU+Rm3/MRBjO6kYZWIquZm7gSI0z0Vg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1717012538; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=5j/RmSAlhCXJU1vUCQMT/ujGfnXfs53M7nbtzjes1TI=; b=hQsU60MWROdu8cT4x87dHSLIY1ZCYoF5MWVobkUdPLeXkdJciFsLw0UtkgRseOjOxJGEeDmeJ5pJdcCxUq+L0ep+oPQQFvrvo8iJJgN9q7BqHIwieZ7HHfIA+079mltzbzeOh1G0lJSLPj8Ka1l9Ju0jgO7ABLAF22xAQJeOaEE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1717012538958291.9041720291349; Wed, 29 May 2024 12:55:38 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.732323.1138282 (Exim 4.92) (envelope-from ) id 1sCPOJ-000409-Om; Wed, 29 May 2024 19:55:19 +0000 Received: by outflank-mailman (output) from mailman id 732323.1138282; Wed, 29 May 2024 19:55:19 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1sCPOJ-0003yY-Fp; Wed, 29 May 2024 19:55:19 +0000 Received: by outflank-mailman (input) for mailman id 732323; Wed, 29 May 2024 19:55:17 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1sCPOH-0003Q0-PQ for xen-devel@lists.xenproject.org; Wed, 29 May 2024 19:55:17 +0000 Received: from mail-lf1-x132.google.com (mail-lf1-x132.google.com [2a00:1450:4864:20::132]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 5e624e07-1df5-11ef-b4bb-af5377834399; Wed, 29 May 2024 21:55:16 +0200 (CEST) Received: by mail-lf1-x132.google.com with SMTP id 2adb3069b0e04-52ac99930c6so270039e87.0 for ; Wed, 29 May 2024 12:55:16 -0700 (PDT) Received: from fedora.. ([94.75.70.14]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5297066b249sm1344203e87.178.2024.05.29.12.55.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 May 2024 12:55:15 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 5e624e07-1df5-11ef-b4bb-af5377834399 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1717012515; x=1717617315; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=5j/RmSAlhCXJU1vUCQMT/ujGfnXfs53M7nbtzjes1TI=; b=fEUhk5AA8ukCLPi7XQ2/NiqZL+ep3PgY6SLKzfRFoN1Ujeyophk2ftajYp5oyr/FUB KaUQsk6i2vEWk2Q1CJ2J6jx/V/ESUXfVEAav7eSpNFaNKKVgvpfNrVKZGwMRzh6OPWE3 VRFUQasY09XWkdfdq0iC78BTWlZDNAGdNf5m2Oy+WQryFb5IosO/xkHu6M2LoDRvycQY FfJ2CQQOM1UM/v1iDd54C1/dRBeq87X0Jqz02yLF+xTwCC7DWsZYSwZ5D2mQGGH6MCLV YSxNjBAH9Zq4IZrIt+Ctlo98jUiAMRvoCu/VtPO6KfaQCzDOHS/yejHr9xoNe1boBpqp Ljtw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1717012515; x=1717617315; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5j/RmSAlhCXJU1vUCQMT/ujGfnXfs53M7nbtzjes1TI=; b=kBQxKH8TZKI8yuefj7eIHjF4MpnOqi6tCj1X8TNLZx/jSDoAEXpT0BZm2JYrVC35gL ZtXG9SNSovJHjgDT0TsLRVX+0HlTo5CNm3rwPfnsmLGtbsD/9ZAVCF3eu4vzvtz0TW5m F85LMKBHvGjgWo0YVvyXL59+2mhdcwX5PrDSuRWel105srLzPBBfQiEDUFbQpAGPYd/l 03b8YbK8Edb0xyHXoufed4oQnzZ319fePGDep50clSiZV/ZDQ64W+dg/bp+M5/0SI+2z kbn1AG9wGEqcXp4KO46IN8vN3g1BpXpiMqVXSsUBDRy3Vt0VYXhOoTrSA8wkNs5LER75 WFEg== X-Gm-Message-State: AOJu0Yz7gmJnk4ougoN37KtlgI7JV9B9v7Do2vKKUVcBxree66niXr0V fYPRJt0MM2JMGZYUBg69Mfjpdn1BWZfrGQN0ALiA1yJgZxX3c+CRbiJNqJNh X-Google-Smtp-Source: AGHT+IHsKzwdLJDunzsII+Oo8Y+RSm0pjg/FSCmVV8H2Jruqwk6TXnOHVvqxpsKkabpyMwtmcSKuRg== X-Received: by 2002:a19:ca06:0:b0:518:dae6:d0ec with SMTP id 2adb3069b0e04-52b7d418d7amr115370e87.4.1717012515204; Wed, 29 May 2024 12:55:15 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Alistair Francis , Bob Eshleman , Connor Davis , Andrew Cooper , George Dunlap , Jan Beulich , Julien Grall , Stefano Stabellini Subject: [PATCH v12 3/8] xen/riscv: introduce bitops.h Date: Wed, 29 May 2024 21:55:04 +0200 Message-ID: X-Mailer: git-send-email 2.45.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1717012539840100002 Content-Type: text/plain; charset="utf-8" Taken from Linux-6.4.0-rc1 Xen's bitops.h consists of several Linux's headers: * linux/arch/include/asm/bitops.h: * The following function were removed as they aren't used in Xen: * test_and_set_bit_lock * clear_bit_unlock * __clear_bit_unlock * The following functions were renamed in the way how they are used by common code: * __test_and_set_bit * __test_and_clear_bit * The declaration and implementation of the following functios were updated to make Xen build happy: * clear_bit * set_bit * __test_and_clear_bit * __test_and_set_bit Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich --- Changes in V11-V12: - Nothing changed. Only rebase was done. --- Changes in V10: - update the error message BITS_PER_LONG -> BITOP_BITS_PER_WORD --- Changes in V9: - add Acked-by: Jan Beulich - drop redefinition of bitop_uint_t in asm/types.h as some operation in Xe= n common code expects to work with 32-bit quantities. - s/BITS_PER_LONG/BITOP_BITS_PER_WORD in asm/bitops.h around __AMO() macro= s. --- Changes in V8: - define bitop_uint_t in after the changes in patch related = to introduction of "introduce generic non-atomic test_*bit()". - drop duplicated __set_bit() and __clear_bit(). - drop duplicated comment: /* Based on linux/arch/include/asm/bitops.h */. - update type of res and mask in test_and_op_bit_ord(): unsigned long -> b= itop_uint_t. - drop 1 padding blank in test_and_op_bit_ord(). - update definition of test_and_set_bit(),test_and_clear_bit(),test_and_ch= ange_bit: change return type to bool. - change addr argument type of test_and_change_bit(): unsigned long * -> v= oid *. - move test_and_change_bit() closer to other test_and-s function. - Code style fixes: tabs -> space. - s/#undef __op_bit/#undef op_bit. - update the commit message: delete information about generic-non-atomic.h= changes as now it is a separate patch. --- Changes in V7: - Update the commit message. - Drop "__" for __op_bit and __op_bit_ord as they are atomic. - add comment above __set_bit and __clear_bit about why they are defined a= s atomic. - align bitops_uint_t with __AMO(). - make changes after generic non-atomic test_*bit() were changed. - s/__asm__ __volatile__/asm volatile --- Changes in V6: - rebase clean ups were done: drop unused asm-generic includes --- Changes in V5: - new patch --- xen/arch/riscv/include/asm/bitops.h | 137 ++++++++++++++++++++++++++++ 1 file changed, 137 insertions(+) create mode 100644 xen/arch/riscv/include/asm/bitops.h diff --git a/xen/arch/riscv/include/asm/bitops.h b/xen/arch/riscv/include/a= sm/bitops.h new file mode 100644 index 0000000000..7f7af3fda1 --- /dev/null +++ b/xen/arch/riscv/include/asm/bitops.h @@ -0,0 +1,137 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (C) 2012 Regents of the University of California */ + +#ifndef _ASM_RISCV_BITOPS_H +#define _ASM_RISCV_BITOPS_H + +#include + +#if BITOP_BITS_PER_WORD =3D=3D 64 +#define __AMO(op) "amo" #op ".d" +#elif BITOP_BITS_PER_WORD =3D=3D 32 +#define __AMO(op) "amo" #op ".w" +#else +#error "Unexpected BITOP_BITS_PER_WORD" +#endif + +/* Based on linux/arch/include/asm/bitops.h */ + +/* + * Non-atomic bit manipulation. + * + * Implemented using atomics to be interrupt safe. Could alternatively + * implement with local interrupt masking. + */ +#define __set_bit(n, p) set_bit(n, p) +#define __clear_bit(n, p) clear_bit(n, p) + +#define test_and_op_bit_ord(op, mod, nr, addr, ord) \ +({ \ + bitop_uint_t res, mask; \ + mask =3D BITOP_MASK(nr); \ + asm volatile ( \ + __AMO(op) #ord " %0, %2, %1" \ + : "=3Dr" (res), "+A" (addr[BITOP_WORD(nr)]) \ + : "r" (mod(mask)) \ + : "memory"); \ + ((res & mask) !=3D 0); \ +}) + +#define op_bit_ord(op, mod, nr, addr, ord) \ + asm volatile ( \ + __AMO(op) #ord " zero, %1, %0" \ + : "+A" (addr[BITOP_WORD(nr)]) \ + : "r" (mod(BITOP_MASK(nr))) \ + : "memory"); + +#define test_and_op_bit(op, mod, nr, addr) \ + test_and_op_bit_ord(op, mod, nr, addr, .aqrl) +#define op_bit(op, mod, nr, addr) \ + op_bit_ord(op, mod, nr, addr, ) + +/* Bitmask modifiers */ +#define NOP(x) (x) +#define NOT(x) (~(x)) + +/** + * test_and_set_bit - Set a bit and return its old value + * @nr: Bit to set + * @addr: Address to count from + */ +static inline bool test_and_set_bit(int nr, volatile void *p) +{ + volatile bitop_uint_t *addr =3D p; + + return test_and_op_bit(or, NOP, nr, addr); +} + +/** + * test_and_clear_bit - Clear a bit and return its old value + * @nr: Bit to clear + * @addr: Address to count from + */ +static inline bool test_and_clear_bit(int nr, volatile void *p) +{ + volatile bitop_uint_t *addr =3D p; + + return test_and_op_bit(and, NOT, nr, addr); +} + +/** + * test_and_change_bit - Toggle (change) a bit and return its old value + * @nr: Bit to change + * @addr: Address to count from + * + * This operation is atomic and cannot be reordered. + * It also implies a memory barrier. + */ +static inline bool test_and_change_bit(int nr, volatile void *p) +{ + volatile bitop_uint_t *addr =3D p; + + return test_and_op_bit(xor, NOP, nr, addr); +} + +/** + * set_bit - Atomically set a bit in memory + * @nr: the bit to set + * @addr: the address to start counting from + * + * Note that @nr may be almost arbitrarily large; this function is not + * restricted to acting on a single-word quantity. + */ +static inline void set_bit(int nr, volatile void *p) +{ + volatile bitop_uint_t *addr =3D p; + + op_bit(or, NOP, nr, addr); +} + +/** + * clear_bit - Clears a bit in memory + * @nr: Bit to clear + * @addr: Address to start counting from + */ +static inline void clear_bit(int nr, volatile void *p) +{ + volatile bitop_uint_t *addr =3D p; + + op_bit(and, NOT, nr, addr); +} + +#undef test_and_op_bit +#undef op_bit +#undef NOP +#undef NOT +#undef __AMO + +#endif /* _ASM_RISCV_BITOPS_H */ + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ --=20 2.45.0 From nobody Sun Nov 24 16:33:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; 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([94.75.70.14]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5297066b249sm1344203e87.178.2024.05.29.12.55.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 May 2024 12:55:15 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 5ef92ff7-1df5-11ef-90a1-e314d9c70b13 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1717012516; x=1717617316; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=h3OBfOym5W7zP/NOzLdy/wTYIWbuyzij9mGpUhq8jn8=; b=FXOMKagBdb7WBn+WKoaoOCl3NTDtgwaYgcP/t2jk/vaIqJx0mgssV5tsMsOHSNj5+r 6hKjE4djiOUkCVb3ZcL8/K9vdZWtZAKmmQTEz6DpjNusjCvAoerw61Hbl19ytQRGNvRQ nOsyzWt4KA4feEQf3W9Sze3v5v3CBVjSRkcZAKDxDoJ6iOQB9et0Rq+v4ZS/EkSKZl3l c5Vgbo9+8GVVVejgGqxBKShA4c4tM2AbhOQZfMbdrlxStcZ5+S0NLEPFv570TY5EsSvs v5GkEDgPnnLl7yItr6Ds7JshotbqkN1UBSnLncPh3dyj02qoN9+xZgWWAUqZ5vBqP73Q XLiQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1717012516; x=1717617316; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=h3OBfOym5W7zP/NOzLdy/wTYIWbuyzij9mGpUhq8jn8=; b=Z0ZZdRN50W+xs5/y8py/Meh0yfcvs7H7lRSKgFcd3W8YI60klAbvksdXjixZLQsFKs uKu6kvPMQz/aVwIH55OnhL8MIXWU0a20Npj6cwyNjjlMOORS518k8A0WtRRyHSrnubbM Qp52pqAO3NVpj/hIL9/7ol//wpi/PEqkT66KZblClUfFoa8RbDsI9qF7Tw8i+rI2ivS0 U+4TdeniShfSZ6/ykV7qXcZJoKZC+wKB4anS0Fmhf8CkS1ssCJZiuxd1KbmCG4jDCNjZ H3Gyo3ZfUUvmEGYnbwRm3rjlKGPDh6QyM8cU++g7Cc9N0sBFEicffXRajNspoNpQpo++ euiw== X-Gm-Message-State: AOJu0YwyyDeKXVgxnsL+mIxkcybcCjhfnAomUcKetK+FMCQLNtjo+m1x 9vhcIoq3a/F6qQbN1bDudeXPYdnJkfVdmJgrZxnFgww/4IDqSgHA9Da/NmkP X-Google-Smtp-Source: AGHT+IF8TRHBMLnG7vbLddBJSm+lXJuXkNyuIx+55aDyvR4lh964SVdEQEN1swQiiL5CcERQAR3igQ== X-Received: by 2002:ac2:5f08:0:b0:52b:797f:b21f with SMTP id 2adb3069b0e04-52b7d47a923mr117416e87.51.1717012516270; Wed, 29 May 2024 12:55:16 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Alistair Francis , Bob Eshleman , Connor Davis , Andrew Cooper , George Dunlap , Jan Beulich , Julien Grall , Stefano Stabellini Subject: [PATCH v12 4/8] xen/riscv: add definition of __read_mostly Date: Wed, 29 May 2024 21:55:05 +0200 Message-ID: X-Mailer: git-send-email 2.45.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1717012545854100005 Content-Type: text/plain; charset="utf-8" The definition of __read_mostly should be removed in: https://lore.kernel.org/xen-devel/f25eb5c9-7c14-6e23-8535-2c66772b333e@suse= .com/ The patch introduces it in arch-specific header to not block enabling of full Xen build for RISC-V. Signed-off-by: Oleksii Kurochko --- - [PATCH] move __read_mostly to xen/cache.h [2] Right now, the patch series doesn't have a direct dependency on [2] and it provides __read_mostly in the patch: [PATCH v3 26/34] xen/riscv: add definition of __read_mostly However, it will be dropped as soon as [2] is merged or at least when the final version of the patch [2] is provided. Considering that there is still no still final decision regarding patch [2]= my suggestion is to merge RISC-V specific patch and just drop the changes in patch [2]. [2] https://lore.kernel.org/xen-devel/f25eb5c9-7c14-6e23-8535-2c66772b333e@= suse.com/ --- Changes in V9-V12: - Only rebase was done. --- Change in V8: - update the footer after Signed-off. --- Changes in V4-V7: - Nothing changed. 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Wed, 29 May 2024 12:55:17 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Alistair Francis , Bob Eshleman , Connor Davis , Andrew Cooper , George Dunlap , Jan Beulich , Julien Grall , Stefano Stabellini Subject: [PATCH v12 5/8] xen/riscv: add minimal stuff to mm.h to build full Xen Date: Wed, 29 May 2024 21:55:06 +0200 Message-ID: X-Mailer: git-send-email 2.45.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1717012545981100008 Content-Type: text/plain; charset="utf-8" Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich --- Changes in V8-V12: - Nothing changed only rebase. --- Changes in V7: - update argument type of maddr_to_virt() function: unsigned long -> paddr= _t - rename argument of PFN_ORDER(): pfn -> pg. - add Acked-by: Jan Beulich --- Changes in V6: - drop __virt_to_maddr() ( transform to macro ) and __maddr_to_virt ( rena= me to maddr_to_virt ). - parenthesize va in definition of vmap_to_mfn(). - Code style fixes. --- Changes in V5: - update the comment around "struct domain *domain;" : zero -> NULL - fix ident. for unsigned long val; - put page_to_virt() and virt_to_page() close to each other. - drop unnessary leading underscore - drop a space before the comment: /* Count of uses of this frame as its c= urrent type. */ - drop comment about a page 'not as a shadow'. it is not necessary for RIS= C-V --- Changes in V4: - update an argument name of PFN_ORDERN macros. - drop pad at the end of 'struct page_info'. - Change message -> subject in "Changes in V3" - delete duplicated macros from riscv/mm.h - fix identation in struct page_info - align comment for PGC_ macros - update definitions of domain_set_alloc_bitsize() and domain_clamp_alloc_= bitsize() - drop unnessary comments. - s/BUG/BUG_ON("...") - define __virt_to_maddr, __maddr_to_virt as stubs - add inclusion of xen/mm-frame.h for mfn_x and others - include "xen/mm.h" instead of "asm/mm.h" to fix compilation issues: In file included from arch/riscv/setup.c:7: ./arch/riscv/include/asm/mm.h:60:28: error: field 'list' has incomplete ty= pe 60 | struct page_list_entry list; | ^~~~ ./arch/riscv/include/asm/mm.h:81:43: error: 'MAX_ORDER' undeclared here (n= ot in a function) 81 | unsigned long first_dirty:MAX_ORDER + 1; | ^~~~~~~~~ ./arch/riscv/include/asm/mm.h:81:31: error: bit-field 'first_dirty' width = not an integer constant 81 | unsigned long first_dirty:MAX_ORDER + 1; - Define __virt_to_mfn() and __mfn_to_virt() using maddr_to_mfn() and mfn_= to_maddr(). --- Changes in V3: - update the commit title - introduce DIRECTMAP_VIRT_START. - drop changes related pfn_to_paddr() and paddr_to_pfn as they were remvoe= in [PATCH v2 32/39] xen/riscv: add minimal stuff to asm/page.h to build ful= l Xen - code style fixes. - drop get_page_nr and put_page_nr as they don't need for time being - drop CONFIG_STATIC_MEMORY related things - code style fixes --- Changes in V2: - define stub for arch_get_dma_bitsize(void) --- xen/arch/riscv/include/asm/mm.h | 240 ++++++++++++++++++++++++++++++++ xen/arch/riscv/mm.c | 2 +- xen/arch/riscv/setup.c | 2 +- 3 files changed, 242 insertions(+), 2 deletions(-) diff --git a/xen/arch/riscv/include/asm/mm.h b/xen/arch/riscv/include/asm/m= m.h index 07c7a0abba..cc4a07a71c 100644 --- a/xen/arch/riscv/include/asm/mm.h +++ b/xen/arch/riscv/include/asm/mm.h @@ -3,11 +3,246 @@ #ifndef _ASM_RISCV_MM_H #define _ASM_RISCV_MM_H =20 +#include +#include +#include +#include +#include + #include =20 #define pfn_to_paddr(pfn) ((paddr_t)(pfn) << PAGE_SHIFT) #define paddr_to_pfn(pa) ((unsigned long)((pa) >> PAGE_SHIFT)) =20 +#define paddr_to_pdx(pa) mfn_to_pdx(maddr_to_mfn(pa)) +#define gfn_to_gaddr(gfn) pfn_to_paddr(gfn_x(gfn)) +#define gaddr_to_gfn(ga) _gfn(paddr_to_pfn(ga)) +#define mfn_to_maddr(mfn) pfn_to_paddr(mfn_x(mfn)) +#define maddr_to_mfn(ma) _mfn(paddr_to_pfn(ma)) +#define vmap_to_mfn(va) maddr_to_mfn(virt_to_maddr((vaddr_t)(va))) +#define vmap_to_page(va) mfn_to_page(vmap_to_mfn(va)) + +static inline void *maddr_to_virt(paddr_t ma) +{ + BUG_ON("unimplemented"); + return NULL; +} + +#define virt_to_maddr(va) ({ BUG_ON("unimplemented"); 0; }) + +/* Convert between Xen-heap virtual addresses and machine frame numbers. */ +#define __virt_to_mfn(va) mfn_x(maddr_to_mfn(virt_to_maddr(va))) +#define __mfn_to_virt(mfn) maddr_to_virt(mfn_to_maddr(_mfn(mfn))) + +/* + * We define non-underscored wrappers for above conversion functions. + * These are overriden in various source files while underscored version + * remain intact. + */ +#define virt_to_mfn(va) __virt_to_mfn(va) +#define mfn_to_virt(mfn) __mfn_to_virt(mfn) + +struct page_info +{ + /* Each frame can be threaded onto a doubly-linked list. */ + struct page_list_entry list; + + /* Reference count and various PGC_xxx flags and fields. */ + unsigned long count_info; + + /* Context-dependent fields follow... */ + union { + /* Page is in use: ((count_info & PGC_count_mask) !=3D 0). */ + struct { + /* Type reference count and various PGT_xxx flags and fields. = */ + unsigned long type_info; + } inuse; + + /* Page is on a free list: ((count_info & PGC_count_mask) =3D=3D 0= ). */ + union { + struct { + /* + * Index of the first *possibly* unscrubbed page in the bu= ddy. + * One more bit than maximum possible order to accommodate + * INVALID_DIRTY_IDX. + */ +#define INVALID_DIRTY_IDX ((1UL << (MAX_ORDER + 1)) - 1) + unsigned long first_dirty:MAX_ORDER + 1; + + /* Do TLBs need flushing for safety before next page use? = */ + bool need_tlbflush:1; + +#define BUDDY_NOT_SCRUBBING 0 +#define BUDDY_SCRUBBING 1 +#define BUDDY_SCRUB_ABORT 2 + unsigned long scrub_state:2; + }; + + unsigned long val; + } free; + } u; + + union { + /* Page is in use */ + struct { + /* Owner of this page (NULL if page is anonymous). */ + struct domain *domain; + } inuse; + + /* Page is on a free list. */ + struct { + /* Order-size of the free chunk this page is the head of. */ + unsigned int order; + } free; + } v; + + union { + /* + * Timestamp from 'TLB clock', used to avoid extra safety flushes. + * Only valid for: a) free pages, and b) pages with zero type count + */ + uint32_t tlbflush_timestamp; + }; +}; + +#define frame_table ((struct page_info *)FRAMETABLE_VIRT_START) + +/* PDX of the first page in the frame table. */ +extern unsigned long frametable_base_pdx; + +/* Convert between machine frame numbers and page-info structures. */ +#define mfn_to_page(mfn) \ + (frame_table + (mfn_to_pdx(mfn) - frametable_base_pdx)) +#define page_to_mfn(pg) \ + pdx_to_mfn((unsigned long)((pg) - frame_table) + frametable_base_pdx) + +static inline void *page_to_virt(const struct page_info *pg) +{ + return mfn_to_virt(mfn_x(page_to_mfn(pg))); +} + +/* Convert between Xen-heap virtual addresses and page-info structures. */ +static inline struct page_info *virt_to_page(const void *v) +{ + BUG_ON("unimplemented"); + return NULL; +} + +/* + * Common code requires get_page_type and put_page_type. + * We don't care about typecounts so we just do the minimum to make it + * happy. + */ +static inline int get_page_type(struct page_info *page, unsigned long type) +{ + return 1; +} + +static inline void put_page_type(struct page_info *page) +{ +} + +static inline void put_page_and_type(struct page_info *page) +{ + put_page_type(page); + put_page(page); +} + +/* + * RISC-V does not have an M2P, but common code expects a handful of + * M2P-related defines and functions. Provide dummy versions of these. + */ +#define INVALID_M2P_ENTRY (~0UL) +#define SHARED_M2P_ENTRY (~0UL - 1UL) +#define SHARED_M2P(_e) ((_e) =3D=3D SHARED_M2P_ENTRY) + +#define set_gpfn_from_mfn(mfn, pfn) do { (void)(mfn), (void)(pfn); } while= (0) +#define mfn_to_gfn(d, mfn) ((void)(d), _gfn(mfn_x(mfn))) + +#define PDX_GROUP_SHIFT (PAGE_SHIFT + VPN_BITS) + +static inline unsigned long domain_get_maximum_gpfn(struct domain *d) +{ + BUG_ON("unimplemented"); + return 0; +} + +static inline long arch_memory_op(int op, XEN_GUEST_HANDLE_PARAM(void) arg) +{ + BUG_ON("unimplemented"); + return 0; +} + +/* + * On RISCV, all the RAM is currently direct mapped in Xen. + * Hence return always true. + */ +static inline bool arch_mfns_in_directmap(unsigned long mfn, unsigned long= nr) +{ + return true; +} + +#define PG_shift(idx) (BITS_PER_LONG - (idx)) +#define PG_mask(x, idx) (x ## UL << PG_shift(idx)) + +#define PGT_none PG_mask(0, 1) /* no special uses of this page = */ +#define PGT_writable_page PG_mask(1, 1) /* has writable mappings? = */ +#define PGT_type_mask PG_mask(1, 1) /* Bits 31 or 63. = */ + +/* Count of uses of this frame as its current type. */ +#define PGT_count_width PG_shift(2) +#define PGT_count_mask ((1UL << PGT_count_width) - 1) + +/* + * Page needs to be scrubbed. Since this bit can only be set on a page tha= t is + * free (i.e. in PGC_state_free) we can reuse PGC_allocated bit. + */ +#define _PGC_need_scrub _PGC_allocated +#define PGC_need_scrub PGC_allocated + +/* Cleared when the owning guest 'frees' this page. */ +#define _PGC_allocated PG_shift(1) +#define PGC_allocated PG_mask(1, 1) +/* Page is Xen heap? */ +#define _PGC_xen_heap PG_shift(2) +#define PGC_xen_heap PG_mask(1, 2) +/* Page is broken? */ +#define _PGC_broken PG_shift(7) +#define PGC_broken PG_mask(1, 7) +/* Mutually-exclusive page states: { inuse, offlining, offlined, free }. */ +#define PGC_state PG_mask(3, 9) +#define PGC_state_inuse PG_mask(0, 9) +#define PGC_state_offlining PG_mask(1, 9) +#define PGC_state_offlined PG_mask(2, 9) +#define PGC_state_free PG_mask(3, 9) +#define page_state_is(pg, st) (((pg)->count_info&PGC_state) =3D=3D PGC_sta= te_##st) + +/* Count of references to this frame. */ +#define PGC_count_width PG_shift(9) +#define PGC_count_mask ((1UL << PGC_count_width) - 1) + +#define _PGC_extra PG_shift(10) +#define PGC_extra PG_mask(1, 10) + +#define is_xen_heap_page(page) ((page)->count_info & PGC_xen_heap) +#define is_xen_heap_mfn(mfn) \ + (mfn_valid(mfn) && is_xen_heap_page(mfn_to_page(mfn))) + +#define is_xen_fixed_mfn(mfn) \ + ((mfn_to_maddr(mfn) >=3D virt_to_maddr((vaddr_t)_start)) && \ + (mfn_to_maddr(mfn) <=3D virt_to_maddr((vaddr_t)_end - 1))) + +#define page_get_owner(p) (p)->v.inuse.domain +#define page_set_owner(p, d) ((p)->v.inuse.domain =3D (d)) + +/* TODO: implement */ +#define mfn_valid(mfn) ({ (void)(mfn); 0; }) + +#define domain_set_alloc_bitsize(d) ((void)(d)) +#define domain_clamp_alloc_bitsize(d, b) ((void)(d), (b)) + +#define PFN_ORDER(pg) ((pg)->v.free.order) + extern unsigned char cpu0_boot_stack[]; =20 void setup_initial_pagetables(void); @@ -20,4 +255,9 @@ unsigned long calc_phys_offset(void); =20 void turn_on_mmu(unsigned long ra); =20 +static inline unsigned int arch_get_dma_bitsize(void) +{ + return 32; /* TODO */ +} + #endif /* _ASM_RISCV_MM_H */ diff --git a/xen/arch/riscv/mm.c b/xen/arch/riscv/mm.c index 053f043a3d..fe3a43be20 100644 --- a/xen/arch/riscv/mm.c +++ b/xen/arch/riscv/mm.c @@ -5,12 +5,12 @@ #include #include #include +#include #include =20 #include #include #include -#include #include #include =20 diff --git a/xen/arch/riscv/setup.c b/xen/arch/riscv/setup.c index 6593f601c1..98a94c4c48 100644 --- a/xen/arch/riscv/setup.c +++ b/xen/arch/riscv/setup.c @@ -2,9 +2,9 @@ =20 #include #include +#include =20 #include -#include =20 /* Xen stack for bringing up the first CPU. */ unsigned char __initdata cpu0_boot_stack[STACK_SIZE] --=20 2.45.0 From nobody Sun Nov 24 16:33:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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([94.75.70.14]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5297066b249sm1344203e87.178.2024.05.29.12.55.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 May 2024 12:55:17 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 5ff10d06-1df5-11ef-90a1-e314d9c70b13 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1717012518; x=1717617318; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=HT5eQZFG3kOfjlltqo/sjfVASYxX5jfFvb3QP7WAnA4=; b=j8M6/thJwD6aBd8mAkZQP6aKlla6gkO38+sWFUhn5FkbvpBcF7CVDpNcXrlQvRlL4t dWlnN8gMX6FN1RE1wQAylp6BNRY5/8tSeRaKoc1MrQqlQAylPcLkN2u5JMLsbHxD3XD2 9hSt1CjhZO5I5/f8gTXEoASwUL9spknkOcDimjaqNLce/z0egmZe/DJwnKV2Ycb37HbI 29/WuvKgwbunptpTHTTiNiBNjT6qnkvujRgsK6BYzUOXIxrHtnwFt8vrjxKQqh/qk4tc em+YVEsBMdOVLFZGuvQe44u2Z6xN6bPDq9V2TDEfYDZlMM7GJJUgGgCBEIVtcAjv5uX7 /XDw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1717012518; x=1717617318; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HT5eQZFG3kOfjlltqo/sjfVASYxX5jfFvb3QP7WAnA4=; b=F9Wf8OsduInVIXZc/W4GR/3pycUH2aCzObD66NLVH0/2UBGrtmKY6eIO+NLhswUWNN lWyFQtYW54M9DBeDUGOIbYvLyUOnN2+wzSNHqtmcRV6oq1kzL2NzUZThDuTfebWzY+3m D6hymlha7/rzJtkfEAPTwEs4e8jVF0p/t+DT6B5nyO1UUO2GpYf7sjpmNXoi4fmf/Xak y6B0a1AaYtMA865U2+h838VnHUExFyKerVODuBGwYakZgna1Gs0S2kK4mdtH5b0FeFaw BM4mBZhxw1oV5uXi5HsvLeL1Myj6wDBw9gHILaumRVS5KctHAUGlO/ZR/rqeAXCwUKI1 TeKQ== X-Gm-Message-State: AOJu0YyoZ21ZBil0TROmyE28SKBdqm4Wal+5lmGwBGpbFK9qK1/2bU9L TUQGPfJ5VgGU4K14cxeDt0CuaI9E1hQylXj0IQYKqgskh3H2B04Ar1P3XVup X-Google-Smtp-Source: AGHT+IENbAEXIatG6RzIfpPoL19Qek9oosir4ctTUoquQPNkD+5xNxItPVUgu7SlQtOFp7OajD8J+A== X-Received: by 2002:a05:6512:3b06:b0:52a:d87f:60e3 with SMTP id 2adb3069b0e04-52b7d48c622mr148339e87.57.1717012517792; Wed, 29 May 2024 12:55:17 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Alistair Francis , Bob Eshleman , Connor Davis , Andrew Cooper , George Dunlap , Jan Beulich , Julien Grall , Stefano Stabellini Subject: [PATCH v12 6/8] xen/riscv: add minimal amount of stubs to build full Xen Date: Wed, 29 May 2024 21:55:07 +0200 Message-ID: <4e5b814c3f73bd4ae6bb80296e17ac80bd8d224a.1717008161.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1717012543879100002 Content-Type: text/plain; charset="utf-8" Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich --- Changes in V7-V12: - Only rebase was done. --- Changes in V6: - update the commit in stubs.c around /* ... common/irq.c ... */ - add Acked-by: Jan Beulich --- Changes in V5: - drop unrelated changes - assert_failed("unimplmented...") change to BUG_ON() --- Changes in V4: - added new stubs which are necessary for compilation after rebase: __cpu= _up(), __cpu_disable(), __cpu_die() from smpboot.c - back changes related to printk() in early_printk() as they should be re= moved in the next patch to avoid compilation error. - update definition of cpu_khz: __read_mostly -> __ro_after_init. - drop vm_event_reset_vmtrace(). It is defibed in asm-generic/vm_event.h. - move vm_event_*() functions from stubs.c to riscv/vm_event.c. - s/BUG/BUG_ON("unimplemented") in stubs.c - back irq_actor_none() and irq_actor_none() as common/irq.c isn't compil= ed at this moment, so this function are needed to avoid compilation error. - defined max_page to avoid compilation error, it will be removed as soon= as common/page_alloc.c will be compiled. --- Changes in V3: - code style fixes. - update attribute for frametable_base_pdx and frametable_virt_end to __r= o_after_init. insteaf of read_mostly. - use BUG() instead of assert_failed/WARN for newly introduced stubs. - drop "#include " in stubs.c and use forward declarati= on instead. - drop ack_node() and end_node() as they aren't used now. --- Changes in V2: - define udelay stub - remove 'select HAS_PDX' from RISC-V Kconfig because of https://lore.kernel.org/xen-devel/20231006144405.1078260-1-andrew.cooper= 3@citrix.com/ --- xen/arch/riscv/Makefile | 1 + xen/arch/riscv/mm.c | 50 +++++ xen/arch/riscv/setup.c | 8 + xen/arch/riscv/stubs.c | 439 ++++++++++++++++++++++++++++++++++++++++ xen/arch/riscv/traps.c | 25 +++ 5 files changed, 523 insertions(+) create mode 100644 xen/arch/riscv/stubs.c diff --git a/xen/arch/riscv/Makefile b/xen/arch/riscv/Makefile index 1ed1a8369b..60afbc0ad9 100644 --- a/xen/arch/riscv/Makefile +++ b/xen/arch/riscv/Makefile @@ -4,6 +4,7 @@ obj-y +=3D mm.o obj-$(CONFIG_RISCV_64) +=3D riscv64/ obj-y +=3D sbi.o obj-y +=3D setup.o +obj-y +=3D stubs.o obj-y +=3D traps.o obj-y +=3D vm_event.o =20 diff --git a/xen/arch/riscv/mm.c b/xen/arch/riscv/mm.c index fe3a43be20..2c3fb7d72e 100644 --- a/xen/arch/riscv/mm.c +++ b/xen/arch/riscv/mm.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ =20 +#include #include #include #include @@ -14,6 +15,9 @@ #include #include =20 +unsigned long __ro_after_init frametable_base_pdx; +unsigned long __ro_after_init frametable_virt_end; + struct mmu_desc { unsigned int num_levels; unsigned int pgtbl_count; @@ -294,3 +298,49 @@ unsigned long __init calc_phys_offset(void) phys_offset =3D load_start - XEN_VIRT_START; return phys_offset; } + +void put_page(struct page_info *page) +{ + BUG_ON("unimplemented"); +} + +unsigned long get_upper_mfn_bound(void) +{ + /* No memory hotplug yet, so current memory limit is the final one. */ + return max_page - 1; +} + +void arch_dump_shared_mem_info(void) +{ + BUG_ON("unimplemented"); +} + +int populate_pt_range(unsigned long virt, unsigned long nr_mfns) +{ + BUG_ON("unimplemented"); + return -1; +} + +int xenmem_add_to_physmap_one(struct domain *d, unsigned int space, + union add_to_physmap_extra extra, + unsigned long idx, gfn_t gfn) +{ + BUG_ON("unimplemented"); + + return 0; +} + +int destroy_xen_mappings(unsigned long s, unsigned long e) +{ + BUG_ON("unimplemented"); + return -1; +} + +int map_pages_to_xen(unsigned long virt, + mfn_t mfn, + unsigned long nr_mfns, + unsigned int flags) +{ + BUG_ON("unimplemented"); + return -1; +} diff --git a/xen/arch/riscv/setup.c b/xen/arch/riscv/setup.c index 98a94c4c48..8bb5bdb2ae 100644 --- a/xen/arch/riscv/setup.c +++ b/xen/arch/riscv/setup.c @@ -1,11 +1,19 @@ /* SPDX-License-Identifier: GPL-2.0-only */ =20 +#include #include #include #include =20 +#include + #include =20 +void arch_get_xen_caps(xen_capabilities_info_t *info) +{ + BUG_ON("unimplemented"); +} + /* Xen stack for bringing up the first CPU. */ unsigned char __initdata cpu0_boot_stack[STACK_SIZE] __aligned(STACK_SIZE); diff --git a/xen/arch/riscv/stubs.c b/xen/arch/riscv/stubs.c new file mode 100644 index 0000000000..8285bcffef --- /dev/null +++ b/xen/arch/riscv/stubs.c @@ -0,0 +1,439 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#include +#include +#include +#include +#include +#include + +#include + +/* smpboot.c */ + +cpumask_t cpu_online_map; +cpumask_t cpu_present_map; +cpumask_t cpu_possible_map; + +/* ID of the PCPU we're running on */ +DEFINE_PER_CPU(unsigned int, cpu_id); +/* XXX these seem awfully x86ish... */ +/* representing HT siblings of each logical CPU */ +DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_mask); +/* representing HT and core siblings of each logical CPU */ +DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_mask); + +nodemask_t __read_mostly node_online_map =3D { { [0] =3D 1UL } }; + +/* + * max_page is defined in page_alloc.c which isn't complied for now. + * definition of max_page will be remove as soon as page_alloc is built. + */ +unsigned long __read_mostly max_page; + +/* time.c */ + +unsigned long __ro_after_init cpu_khz; /* CPU clock frequency in kHz. */ + +s_time_t get_s_time(void) +{ + BUG_ON("unimplemented"); +} + +int reprogram_timer(s_time_t timeout) +{ + BUG_ON("unimplemented"); +} + +void send_timer_event(struct vcpu *v) +{ + BUG_ON("unimplemented"); +} + +void domain_set_time_offset(struct domain *d, int64_t time_offset_seconds) +{ + BUG_ON("unimplemented"); +} + +/* shutdown.c */ + +void machine_restart(unsigned int delay_millisecs) +{ + BUG_ON("unimplemented"); +} + +void machine_halt(void) +{ + BUG_ON("unimplemented"); +} + +/* domctl.c */ + +long arch_do_domctl(struct xen_domctl *domctl, struct domain *d, + XEN_GUEST_HANDLE_PARAM(xen_domctl_t) u_domctl) +{ + BUG_ON("unimplemented"); +} + +void arch_get_domain_info(const struct domain *d, + struct xen_domctl_getdomaininfo *info) +{ + BUG_ON("unimplemented"); +} + +void arch_get_info_guest(struct vcpu *v, vcpu_guest_context_u c) +{ + BUG_ON("unimplemented"); +} + +/* monitor.c */ + +int arch_monitor_domctl_event(struct domain *d, + struct xen_domctl_monitor_op *mop) +{ + BUG_ON("unimplemented"); +} + +/* smp.c */ + +void arch_flush_tlb_mask(const cpumask_t *mask) +{ + BUG_ON("unimplemented"); +} + +void smp_send_event_check_mask(const cpumask_t *mask) +{ + BUG_ON("unimplemented"); +} + +void smp_send_call_function_mask(const cpumask_t *mask) +{ + BUG_ON("unimplemented"); +} + +/* irq.c */ + +struct pirq *alloc_pirq_struct(struct domain *d) +{ + BUG_ON("unimplemented"); +} + +int pirq_guest_bind(struct vcpu *v, struct pirq *pirq, int will_share) +{ + BUG_ON("unimplemented"); +} + +void pirq_guest_unbind(struct domain *d, struct pirq *pirq) +{ + BUG_ON("unimplemented"); +} + +void pirq_set_affinity(struct domain *d, int pirq, const cpumask_t *mask) +{ + BUG_ON("unimplemented"); +} + +hw_irq_controller no_irq_type =3D { + .typename =3D "none", + .startup =3D irq_startup_none, + .shutdown =3D irq_shutdown_none, + .enable =3D irq_enable_none, + .disable =3D irq_disable_none, +}; + +int arch_init_one_irq_desc(struct irq_desc *desc) +{ + BUG_ON("unimplemented"); +} + +void smp_send_state_dump(unsigned int cpu) +{ + BUG_ON("unimplemented"); +} + +/* domain.c */ + +DEFINE_PER_CPU(struct vcpu *, curr_vcpu); +unsigned long __per_cpu_offset[NR_CPUS]; + +void context_switch(struct vcpu *prev, struct vcpu *next) +{ + BUG_ON("unimplemented"); +} + +void continue_running(struct vcpu *same) +{ + BUG_ON("unimplemented"); +} + +void sync_local_execstate(void) +{ + BUG_ON("unimplemented"); +} + +void sync_vcpu_execstate(struct vcpu *v) +{ + BUG_ON("unimplemented"); +} + +void startup_cpu_idle_loop(void) +{ + BUG_ON("unimplemented"); +} + +void free_domain_struct(struct domain *d) +{ + BUG_ON("unimplemented"); +} + +void dump_pageframe_info(struct domain *d) +{ + BUG_ON("unimplemented"); +} + +void free_vcpu_struct(struct vcpu *v) +{ + BUG_ON("unimplemented"); +} + +int arch_vcpu_create(struct vcpu *v) +{ + BUG_ON("unimplemented"); +} + +void arch_vcpu_destroy(struct vcpu *v) +{ + BUG_ON("unimplemented"); +} + +void vcpu_switch_to_aarch64_mode(struct vcpu *v) +{ + BUG_ON("unimplemented"); +} + +int arch_sanitise_domain_config(struct xen_domctl_createdomain *config) +{ + BUG_ON("unimplemented"); +} + +int arch_domain_create(struct domain *d, + struct xen_domctl_createdomain *config, + unsigned int flags) +{ + BUG_ON("unimplemented"); +} + +int arch_domain_teardown(struct domain *d) +{ + BUG_ON("unimplemented"); +} + +void arch_domain_destroy(struct domain *d) +{ + BUG_ON("unimplemented"); +} + +void arch_domain_shutdown(struct domain *d) +{ + BUG_ON("unimplemented"); +} + +void arch_domain_pause(struct domain *d) +{ + BUG_ON("unimplemented"); +} + +void arch_domain_unpause(struct domain *d) +{ + BUG_ON("unimplemented"); +} + +int arch_domain_soft_reset(struct domain *d) +{ + BUG_ON("unimplemented"); +} + +void arch_domain_creation_finished(struct domain *d) +{ + BUG_ON("unimplemented"); +} + +int arch_set_info_guest(struct vcpu *v, vcpu_guest_context_u c) +{ + BUG_ON("unimplemented"); +} + +int arch_initialise_vcpu(struct vcpu *v, XEN_GUEST_HANDLE_PARAM(void) arg) +{ + BUG_ON("unimplemented"); +} + +int arch_vcpu_reset(struct vcpu *v) +{ + BUG_ON("unimplemented"); +} + +int domain_relinquish_resources(struct domain *d) +{ + BUG_ON("unimplemented"); +} + +void arch_dump_domain_info(struct domain *d) +{ + BUG_ON("unimplemented"); +} + +void arch_dump_vcpu_info(struct vcpu *v) +{ + BUG_ON("unimplemented"); +} + +void vcpu_mark_events_pending(struct vcpu *v) +{ + BUG_ON("unimplemented"); +} + +void vcpu_update_evtchn_irq(struct vcpu *v) +{ + BUG_ON("unimplemented"); +} + +void vcpu_block_unless_event_pending(struct vcpu *v) +{ + BUG_ON("unimplemented"); +} + +void vcpu_kick(struct vcpu *v) +{ + BUG_ON("unimplemented"); +} + +struct domain *alloc_domain_struct(void) +{ + BUG_ON("unimplemented"); +} + +struct vcpu *alloc_vcpu_struct(const struct domain *d) +{ + BUG_ON("unimplemented"); +} + +unsigned long +hypercall_create_continuation(unsigned int op, const char *format, ...) +{ + BUG_ON("unimplemented"); +} + +int __init parse_arch_dom0_param(const char *s, const char *e) +{ + BUG_ON("unimplemented"); +} + +/* guestcopy.c */ + +unsigned long raw_copy_to_guest(void *to, const void *from, unsigned int l= en) +{ + BUG_ON("unimplemented"); +} + +unsigned long raw_copy_from_guest(void *to, const void __user *from, + unsigned int len) +{ + BUG_ON("unimplemented"); +} + +/* sysctl.c */ + +long arch_do_sysctl(struct xen_sysctl *sysctl, + XEN_GUEST_HANDLE_PARAM(xen_sysctl_t) u_sysctl) +{ + BUG_ON("unimplemented"); +} + +void arch_do_physinfo(struct xen_sysctl_physinfo *pi) +{ + BUG_ON("unimplemented"); +} + +/* p2m.c */ + +int arch_set_paging_mempool_size(struct domain *d, uint64_t size) +{ + BUG_ON("unimplemented"); +} + +int unmap_mmio_regions(struct domain *d, + gfn_t start_gfn, + unsigned long nr, + mfn_t mfn) +{ + BUG_ON("unimplemented"); +} + +int map_mmio_regions(struct domain *d, + gfn_t start_gfn, + unsigned long nr, + mfn_t mfn) +{ + BUG_ON("unimplemented"); +} + +int set_foreign_p2m_entry(struct domain *d, const struct domain *fd, + unsigned long gfn, mfn_t mfn) +{ + BUG_ON("unimplemented"); +} + +/* Return the size of the pool, in bytes. */ +int arch_get_paging_mempool_size(struct domain *d, uint64_t *size) +{ + BUG_ON("unimplemented"); +} + +/* delay.c */ + +void udelay(unsigned long usecs) +{ + BUG_ON("unimplemented"); +} + +/* guest_access.h */=20 + +static inline unsigned long raw_clear_guest(void *to, unsigned int len) +{ + BUG_ON("unimplemented"); +} + +/* smpboot.c */ + +int __cpu_up(unsigned int cpu) +{ + BUG_ON("unimplemented"); +} + +void __cpu_disable(void) +{ + BUG_ON("unimplemented"); +} + +void __cpu_die(unsigned int cpu) +{ + BUG_ON("unimplemented"); +} + +/* + * The following functions are defined in common/irq.c, but common/irq.c i= sn't + * built for now. These changes will be removed there when common/irq.c is + * ready. + */ + +void cf_check irq_actor_none(struct irq_desc *desc) +{ + BUG_ON("unimplemented"); +} + +unsigned int cf_check irq_startup_none(struct irq_desc *desc) +{ + BUG_ON("unimplemented"); + + return 0; +} diff --git a/xen/arch/riscv/traps.c b/xen/arch/riscv/traps.c index ccd3593f5a..5415cf8d90 100644 --- a/xen/arch/riscv/traps.c +++ b/xen/arch/riscv/traps.c @@ -4,6 +4,10 @@ * * RISC-V Trap handlers */ + +#include +#include + #include #include =20 @@ -11,3 +15,24 @@ void do_trap(struct cpu_user_regs *cpu_regs) { die(); } + +void vcpu_show_execution_state(struct vcpu *v) +{ + BUG_ON("unimplemented"); +} + +void show_execution_state(const struct cpu_user_regs *regs) +{ + printk("implement show_execution_state(regs)\n"); +} + +void arch_hypercall_tasklet_result(struct vcpu *v, long res) +{ + BUG_ON("unimplemented"); +} + +enum mc_disposition arch_do_multicall_call(struct mc_state *state) +{ + BUG_ON("unimplemented"); + return mc_continue; +} --=20 2.45.0 From nobody Sun Nov 24 16:33:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1717012544; cv=none; d=zohomail.com; s=zohoarc; b=kdnU2doetU9HaPp/0/ZhpLCrQVdQHeYICLNiaCV5F2F18+Hpu6+IsB5EYDuD/UvIz8pLRy/TZqxQmiGGe9bRAwpNfRcJlZ6pc+tegkqeuztJnOTwWCv6jmwKNEibWCf6DkBew/YONG1yewsg68fCyBlQnpTyNkukAtOoWNjC8S8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1717012544; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=RB69PkHLC0P/c7KJEa2nAcuiiLx+QigdAnc7qWzg1l4=; b=CamgLLNto+9KJgy3FFqjz3R9InsiZJ8UpxUKg9qXOJJC8dX6AdfF3NhnAUtwHYJX9IyhN+OPPk5XSUAXVyA1vYI8r0N8gCHlXUAz2tuLhruA11mrmFi2cbujkCP4Exg3XQHu/zmNTar05KNoOUZ23v/XljjOZLihbjt+iT5MdjQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1717012544577677.9190390350637; Wed, 29 May 2024 12:55:44 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.732326.1138320 (Exim 4.92) (envelope-from ) id 1sCPON-0005Bn-UN; Wed, 29 May 2024 19:55:23 +0000 Received: by outflank-mailman (output) from mailman id 732326.1138320; Wed, 29 May 2024 19:55:23 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1sCPON-0005B5-Q0; Wed, 29 May 2024 19:55:23 +0000 Received: by outflank-mailman (input) for mailman id 732326; Wed, 29 May 2024 19:55:20 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1sCPOK-0003Nf-77 for xen-devel@lists.xenproject.org; Wed, 29 May 2024 19:55:20 +0000 Received: from mail-lf1-x12a.google.com (mail-lf1-x12a.google.com [2a00:1450:4864:20::12a]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 60881d7a-1df5-11ef-90a1-e314d9c70b13; Wed, 29 May 2024 21:55:19 +0200 (CEST) Received: by mail-lf1-x12a.google.com with SMTP id 2adb3069b0e04-52a6ef5e731so236760e87.0 for ; Wed, 29 May 2024 12:55:19 -0700 (PDT) Received: from fedora.. ([94.75.70.14]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5297066b249sm1344203e87.178.2024.05.29.12.55.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 May 2024 12:55:18 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 60881d7a-1df5-11ef-90a1-e314d9c70b13 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1717012519; x=1717617319; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=RB69PkHLC0P/c7KJEa2nAcuiiLx+QigdAnc7qWzg1l4=; b=ZdoiPYve5Ig14vbzHhUPSfvKDnbmzOTLlhgqdc1YrraXzJPtpQS+5GPILCstLUNt86 cgn3RgnwNicgPagmprQQPqZzBZ1Uv8iVaMwX9o5yoBgEdaaQUmt0cy2NLg4+GGp4xaZW POJIYT15Y8jzWwBzc9XgOvRXGCIvCqxun+6BPG0AhM9QEzWf2KHDDUxpDiJWquGfkOnY g9HCIlvRAsnvkuuajWz5ZhIIYdoGkZ9oHIV/wxzyvBOQMANbW+LmdjnWhUcPsf8TJAAp iBUSTn0XD7c6uH3W0fCKi5GzkYD6xg5CJ67t5QdxQy0QwzxCeMWITS60YmNx9IQBZfvl +5Tg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1717012519; x=1717617319; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RB69PkHLC0P/c7KJEa2nAcuiiLx+QigdAnc7qWzg1l4=; b=KrGQfEyzqiMKNiMI0bMd8ySwK+JHX7y5GZh2s8eQReW/GrSyFcRpFzq53nARJ46LoQ lIF10gpnABILlhIYUodtxmZ3Bc9AyjcF6uJAX62WWn7A+KAybT2BNz1eM00WblePQIoD AUPMsMmbg/OFUkF+sXKPTAYcA6OP6WVr5uC7hp4JCoVyuwWfM3O5DgpLgMqdAWuETJ0g uX9eiTIjsyBDneREGVzWxwhyEB4d55r6lm2cbm4uMFcvzKxdfvM9eUli8vTMo8FGnZR6 nZvYgaF8YHeY/VivaDlngviTj6nPT2xfk5tq+5IOg1TOU90GGxFSaUAadtbZ7na/3XCF FCjQ== X-Gm-Message-State: AOJu0YzJA4gDaCXYZ4RqhBfPNtSVnSebHxpSsJZ++2H6A+XjlDW89RJV D7ahh1cWYpD9R9EcP5SGw1/54YwUFYUoByUuZm7FRriYqwS4HVPDg3hC/B8U X-Google-Smtp-Source: AGHT+IEdszj2ogMZI1dkrwdXUnmCfQoc81L+BYRLNYf+UmK0Mq/P+Qp3C8Sbi01ORtNa1IAloSaJmg== X-Received: by 2002:a05:6512:358f:b0:51d:1002:520d with SMTP id 2adb3069b0e04-52b7d4905b8mr101793e87.64.1717012518832; Wed, 29 May 2024 12:55:18 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Alistair Francis , Bob Eshleman , Connor Davis , Andrew Cooper , George Dunlap , Jan Beulich , Julien Grall , Stefano Stabellini Subject: [PATCH v12 7/8] xen/riscv: enable full Xen build Date: Wed, 29 May 2024 21:55:08 +0200 Message-ID: <1cea913117f771a5f3b4404d7bfb7e1329f3f38e.1717008161.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1717012545896100007 Content-Type: text/plain; charset="utf-8" Signed-off-by: Oleksii Kurochko Reviewed-by: Jan Beulich --- At least this patch cann't be merged w/o Andrew's patch series is merged a= s ffs related functions are used from that patch series: https://lore.kernel.org/xen-devel/20240313172716.2325427-1-andrew.cooper3= @citrix.com/T/#t --- Changes in V5-V12: - Nothing changed. Only rebase. - Add the footer after Signed-off section. --- Changes in V4: - drop stubs for irq_actor_none() and irq_actor_none() as common/irq.c is = compiled now. - drop defintion of max_page in stubs.c as common/page_alloc.c is compiled= now. - drop printk() related changes in riscv/early_printk.c as common version = will be used. --- Changes in V3: - Reviewed-by: Jan Beulich - unrealted change dropped in tiny64_defconfig --- Changes in V2: - Nothing changed. Only rebase. --- xen/arch/riscv/Makefile | 16 +++- xen/arch/riscv/arch.mk | 4 - xen/arch/riscv/early_printk.c | 168 ---------------------------------- xen/arch/riscv/stubs.c | 24 ----- 4 files changed, 15 insertions(+), 197 deletions(-) diff --git a/xen/arch/riscv/Makefile b/xen/arch/riscv/Makefile index 60afbc0ad9..81b77b13d6 100644 --- a/xen/arch/riscv/Makefile +++ b/xen/arch/riscv/Makefile @@ -12,10 +12,24 @@ $(TARGET): $(TARGET)-syms $(OBJCOPY) -O binary -S $< $@ =20 $(TARGET)-syms: $(objtree)/prelink.o $(obj)/xen.lds - $(LD) $(XEN_LDFLAGS) -T $(obj)/xen.lds -N $< $(build_id_linker) -o $@ + $(LD) $(XEN_LDFLAGS) -T $(obj)/xen.lds -N $< \ + $(objtree)/common/symbols-dummy.o -o $(dot-target).0 + $(NM) -pa --format=3Dsysv $(dot-target).0 \ + | $(objtree)/tools/symbols $(all_symbols) --sysv --sort \ + > $(dot-target).0.S + $(MAKE) $(build)=3D$(@D) $(dot-target).0.o + $(LD) $(XEN_LDFLAGS) -T $(obj)/xen.lds -N $< \ + $(dot-target).0.o -o $(dot-target).1 + $(NM) -pa --format=3Dsysv $(dot-target).1 \ + | $(objtree)/tools/symbols $(all_symbols) --sysv --sort \ + > $(dot-target).1.S + $(MAKE) $(build)=3D$(@D) $(dot-target).1.o + $(LD) $(XEN_LDFLAGS) -T $(obj)/xen.lds -N $< $(build_id_linker) \ + $(dot-target).1.o -o $@ $(NM) -pa --format=3Dsysv $@ \ | $(objtree)/tools/symbols --all-symbols --xensyms --sysv --sort \ > $@.map + rm -f $(@D)/.$(@F).[0-9]* =20 $(obj)/xen.lds: $(src)/xen.lds.S FORCE $(call if_changed_dep,cpp_lds_S) diff --git a/xen/arch/riscv/arch.mk b/xen/arch/riscv/arch.mk index 8c071aff65..17827c302c 100644 --- a/xen/arch/riscv/arch.mk +++ b/xen/arch/riscv/arch.mk @@ -38,7 +38,3 @@ extensions :=3D $(subst $(space),,$(extensions)) # -mcmodel=3Dmedlow would force Xen into the lower half. =20 CFLAGS +=3D $(riscv-generic-flags)$(extensions) -mstrict-align -mcmodel=3D= medany - -# TODO: Drop override when more of the build is working -override ALL_OBJS-y =3D arch/$(SRCARCH)/built_in.o -override ALL_LIBS-y =3D diff --git a/xen/arch/riscv/early_printk.c b/xen/arch/riscv/early_printk.c index 60742a042d..610c814f54 100644 --- a/xen/arch/riscv/early_printk.c +++ b/xen/arch/riscv/early_printk.c @@ -40,171 +40,3 @@ void early_printk(const char *str) str++; } } - -/* - * The following #if 1 ... #endif should be removed after printk - * and related stuff are ready. - */ -#if 1 - -#include -#include - -/** - * strlen - Find the length of a string - * @s: The string to be sized - */ -size_t (strlen)(const char * s) -{ - const char *sc; - - for (sc =3D s; *sc !=3D '\0'; ++sc) - /* nothing */; - return sc - s; -} - -/** - * memcpy - Copy one area of memory to another - * @dest: Where to copy to - * @src: Where to copy from - * @count: The size of the area. - * - * You should not use this function to access IO space, use memcpy_toio() - * or memcpy_fromio() instead. - */ -void *(memcpy)(void *dest, const void *src, size_t count) -{ - char *tmp =3D (char *) dest, *s =3D (char *) src; - - while (count--) - *tmp++ =3D *s++; - - return dest; -} - -int vsnprintf(char* str, size_t size, const char* format, va_list args) -{ - size_t i =3D 0; /* Current position in the output string */ - size_t written =3D 0; /* Total number of characters written */ - char* dest =3D str; - - while ( format[i] !=3D '\0' && written < size - 1 ) - { - if ( format[i] =3D=3D '%' ) - { - i++; - - if ( format[i] =3D=3D '\0' ) - break; - - if ( format[i] =3D=3D '%' ) - { - if ( written < size - 1 ) - { - dest[written] =3D '%'; - written++; - } - i++; - continue; - } - - /* - * Handle format specifiers. - * For simplicity, only %s and %d are implemented here. - */ - - if ( format[i] =3D=3D 's' ) - { - char* arg =3D va_arg(args, char*); - size_t arglen =3D strlen(arg); - - size_t remaining =3D size - written - 1; - - if ( arglen > remaining ) - arglen =3D remaining; - - memcpy(dest + written, arg, arglen); - - written +=3D arglen; - i++; - } - else if ( format[i] =3D=3D 'd' ) - { - int arg =3D va_arg(args, int); - - /* Convert the integer to string representation */ - char numstr[32]; /* Assumes a maximum of 32 digits */ - int numlen =3D 0; - int num =3D arg; - size_t remaining; - - if ( arg < 0 ) - { - if ( written < size - 1 ) - { - dest[written] =3D '-'; - written++; - } - - num =3D -arg; - } - - do - { - numstr[numlen] =3D '0' + num % 10; - num =3D num / 10; - numlen++; - } while ( num > 0 ); - - /* Reverse the string */ - for (int j =3D 0; j < numlen / 2; j++) - { - char tmp =3D numstr[j]; - numstr[j] =3D numstr[numlen - 1 - j]; - numstr[numlen - 1 - j] =3D tmp; - } - - remaining =3D size - written - 1; - - if ( numlen > remaining ) - numlen =3D remaining; - - memcpy(dest + written, numstr, numlen); - - written +=3D numlen; - i++; - } - } - else - { - if ( written < size - 1 ) - { - dest[written] =3D format[i]; - written++; - } - i++; - } - } - - if ( size > 0 ) - dest[written] =3D '\0'; - - return written; -} - -void printk(const char *format, ...) -{ - static char buf[1024]; - - va_list args; - va_start(args, format); - - (void)vsnprintf(buf, sizeof(buf), format, args); - - early_printk(buf); - - va_end(args); -} - -#endif - diff --git a/xen/arch/riscv/stubs.c b/xen/arch/riscv/stubs.c index 8285bcffef..bda35fc347 100644 --- a/xen/arch/riscv/stubs.c +++ b/xen/arch/riscv/stubs.c @@ -24,12 +24,6 @@ DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_mask); =20 nodemask_t __read_mostly node_online_map =3D { { [0] =3D 1UL } }; =20 -/* - * max_page is defined in page_alloc.c which isn't complied for now. - * definition of max_page will be remove as soon as page_alloc is built. - */ -unsigned long __read_mostly max_page; - /* time.c */ =20 unsigned long __ro_after_init cpu_khz; /* CPU clock frequency in kHz. */ @@ -419,21 +413,3 @@ void __cpu_die(unsigned int cpu) { BUG_ON("unimplemented"); } - -/* - * The following functions are defined in common/irq.c, but common/irq.c i= sn't - * built for now. These changes will be removed there when common/irq.c is - * ready. - */ - -void cf_check irq_actor_none(struct irq_desc *desc) -{ - BUG_ON("unimplemented"); -} - -unsigned int cf_check irq_startup_none(struct irq_desc *desc) -{ - BUG_ON("unimplemented"); - - return 0; -} --=20 2.45.0 From nobody Sun Nov 24 16:33:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1717012543; cv=none; d=zohomail.com; s=zohoarc; b=B8NLqwJIQbM3mrjx0YFTjetLOfeY4BRA+5Q0frOmZhM7oNJ6qd4CZyJlCIbgSK2aEOZjuPLjerx2LLiCnJlzadPMZugTqVuU/3d3FerwqhZv0L0xl2YI0803TOEe5haZtnF0XtBC7uwM/qWSapHy8ZLjh0NB4qPvNoMSQ4RhsA8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1717012543; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=hr0rCeOkEj/7qjuywq9V+WOZcGXF4MF4JxLpkyei6eA=; b=g8zyfOmjxCKdmpXyaoO/7NUbHAnMKT79oW3Go6p8AkfiyUSzgghmyO99QlGh4+nVEmxMQ3TgJodPJtmUsygpjoq7OMGFJDi2BzSMmA8RjqgbPQ2C/bNZQhBnmTZZDSYwj9yqwmOQgAklfA01DKF1xI8EqJOMtT0zOcvd4Pu03F8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1717012543672178.92830985967407; Wed, 29 May 2024 12:55:43 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.732327.1138325 (Exim 4.92) (envelope-from ) id 1sCPOO-0005GH-CO; Wed, 29 May 2024 19:55:24 +0000 Received: by outflank-mailman (output) from mailman id 732327.1138325; Wed, 29 May 2024 19:55:24 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1sCPOO-0005FX-5u; Wed, 29 May 2024 19:55:24 +0000 Received: by outflank-mailman (input) for mailman id 732327; Wed, 29 May 2024 19:55:22 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1sCPOM-0003Q0-2p for xen-devel@lists.xenproject.org; Wed, 29 May 2024 19:55:22 +0000 Received: from mail-lf1-x12e.google.com (mail-lf1-x12e.google.com [2a00:1450:4864:20::12e]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 6115c601-1df5-11ef-b4bb-af5377834399; Wed, 29 May 2024 21:55:20 +0200 (CEST) Received: by mail-lf1-x12e.google.com with SMTP id 2adb3069b0e04-52ae38957e8so180184e87.1 for ; Wed, 29 May 2024 12:55:20 -0700 (PDT) Received: from fedora.. ([94.75.70.14]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5297066b249sm1344203e87.178.2024.05.29.12.55.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 May 2024 12:55:19 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 6115c601-1df5-11ef-b4bb-af5377834399 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1717012520; x=1717617320; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=hr0rCeOkEj/7qjuywq9V+WOZcGXF4MF4JxLpkyei6eA=; b=cEmnx+D3ywjqDiQ61TqSFWgsXFMvhEbYnI/hRZEw8VaE8AEDKhpM2CW7mNyuIYjKya YTWqefzvZRF7/t7Ip+0l5WO5po5RT7mRuvyOL9IL6IGHp4U/3IQSKbQ8imhZI1zmf6pb 3g/7cKLnCa03a5u/aqvKL0efgsaSeSzrKQOXVNr06o44+ldfZhnsCv93UAR/CdIjv7YJ LWy5nfyWpJ718esvrHeBwKdwX1qS5o3l2krweiFz5nIjGjJ/pMQ7pxqbgrxu5tl3t0ZM ahiqdLG8kVb4Wdw4B4R3Uww4F08lkBWJcT4jWadlTN3SIHJr7BuHAi1ysCI5rLe7zJkF vD1Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1717012520; x=1717617320; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hr0rCeOkEj/7qjuywq9V+WOZcGXF4MF4JxLpkyei6eA=; b=rX4lmIOo87FzgGPJ+4n2W3oTC1Fa2k6e9uWPegTvePDCFwGeuZkfY+xVAF7YMQj34A z78e3WZej2K9SuRTf1872jmtEfqC54USl/WZUJxU5roS17M5fjdPwY/2HmoIHtsMlBjq uBak8n48sLvHxJYVX/TB5iQLD6qmiKiS0k/VgnNIcpFTRs8EG1uPXLMKxDO5Cbrxnf3v qE0S7Y4UXfmz5p2sWcjEOuzJLstXCH6LgEE50AtX+rgNxawUxJr0vR++z6VOs6JbCUq9 wmnQcZziRDthkJlTb6K6rK58pt6/48JfiY2r7aLMD3z9ZSJCqxIUutLIX2yYOQn/uV3U nopQ== X-Gm-Message-State: AOJu0YyRiAvqDZ/6EkIWOINDsFwL8dty0934uUF/zQaFlGwmAy4UZqwZ jQDgo05jYQds2WAwg8OuNSpBdj+gAFHO1sRSw4T377iacblFauylF51V4x2v X-Google-Smtp-Source: AGHT+IHZb5bjx6as4NkrWWXbmTHBBqMPT5aoF6PiwOXbVfFYazz9oHCuIHZn3+RaT6A7TSxMotIgCg== X-Received: by 2002:a05:6512:40b:b0:528:4841:e4a1 with SMTP id 2adb3069b0e04-52b7d432e94mr105642e87.40.1717012519811; Wed, 29 May 2024 12:55:19 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Andrew Cooper , George Dunlap , Jan Beulich , Julien Grall , Stefano Stabellini Subject: [PATCH v12 8/8] xen/README: add compiler and binutils versions for RISC-V64 Date: Wed, 29 May 2024 21:55:09 +0200 Message-ID: X-Mailer: git-send-email 2.45.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1717012545859100006 Content-Type: text/plain; charset="utf-8" This patch doesn't represent a strict lower bound for GCC and GNU Binutils; rather, these versions are specifically employed by the Xen RISC-V container and are anticipated to undergo continuous testing. Older GCC and GNU Binutils would work, but this is not a guarantee. While it is feasible to utilize Clang, it's important to note that, currently, there is no Xen RISC-V CI job in place to verify the seamless functioning of the build with Clang. Signed-off-by: Oleksii Kurochko -- Changes in V5-V12: - Nothing changed. Only rebase. --- Changes in V6: - update the message in README. --- Changes in V5: - update the commit message and README file with additional explanation a= bout GCC and GNU Binutils version. Additionally, it was added information about Clan= g. --- Changes in V4: - Update version of GCC (12.2) and GNU Binutils (2.39) to the version which are in Xen's contrainter for RISC-V --- Changes in V3: - new patch --- README | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/README b/README index c8a108449e..30da5ff9c0 100644 --- a/README +++ b/README @@ -48,6 +48,10 @@ provided by your OS distributor: - For ARM 64-bit: - GCC 5.1 or later - GNU Binutils 2.24 or later + - For RISC-V 64-bit: + - GCC 12.2 or later + - GNU Binutils 2.39 or later + Older GCC and GNU Binutils would work, but this is not a guarant= ee. * POSIX compatible awk * Development install of zlib (e.g., zlib-dev) * Development install of Python 2.7 or later (e.g., python-dev) --=20 2.45.0