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charset="utf-8" All hardware with VT-d has CMPXCHG16B support. Check this at initialisation time, and remove the effectively-dead logic for the non-cx16 case. Suggested-by: Andrew Cooper Signed-off-by: Teddy Astie --- xen/drivers/passthrough/vtd/iommu.c | 73 ++++++++++------------------- 1 file changed, 25 insertions(+), 48 deletions(-) diff --git a/xen/drivers/passthrough/vtd/iommu.c b/xen/drivers/passthrough/= vtd/iommu.c index c7110af7c9..9c787ba9eb 100644 --- a/xen/drivers/passthrough/vtd/iommu.c +++ b/xen/drivers/passthrough/vtd/iommu.c @@ -1482,7 +1482,7 @@ int domain_context_mapping_one( { struct domain_iommu *hd =3D dom_iommu(domain); struct context_entry *context, *context_entries, lctxt; - __uint128_t old; + __uint128_t res, old; uint64_t maddr; uint16_t seg =3D iommu->drhd->segment, prev_did =3D 0; struct domain *prev_dom =3D NULL; @@ -1580,55 +1580,23 @@ int domain_context_mapping_one( ASSERT(!context_fault_disable(lctxt)); } =20 - if ( cpu_has_cx16 ) - { - __uint128_t res =3D cmpxchg16b(context, &old, &lctxt.full); - - /* - * Hardware does not update the context entry behind our backs, - * so the return value should match "old". - */ - if ( res !=3D old ) - { - if ( pdev ) - check_cleanup_domid_map(domain, pdev, iommu); - printk(XENLOG_ERR - "%pp: unexpected context entry %016lx_%016lx (expected = %016lx_%016lx)\n", - &PCI_SBDF(seg, bus, devfn), - (uint64_t)(res >> 64), (uint64_t)res, - (uint64_t)(old >> 64), (uint64_t)old); - rc =3D -EILSEQ; - goto unlock; - } - } - else if ( !prev_dom || !(mode & MAP_WITH_RMRR) ) - { - context_clear_present(*context); - iommu_sync_cache(context, sizeof(*context)); + res =3D cmpxchg16b(context, &old, &lctxt.full); =20 - write_atomic(&context->hi, lctxt.hi); - /* No barrier should be needed between these two. */ - write_atomic(&context->lo, lctxt.lo); - } - else /* Best effort, updating DID last. */ + /* + * Hardware does not update the context entry behind our backs, + * so the return value should match "old". + */ + if ( res !=3D old ) { - /* - * By non-atomically updating the context entry's DID field last, - * during a short window in time TLB entries with the old domain = ID - * but the new page tables may be inserted. This could affect I/O - * of other devices using this same (old) domain ID. Such updati= ng - * therefore is not a problem if this was the only device associa= ted - * with the old domain ID. Diverting I/O of any of a dying domai= n's - * devices to the quarantine page tables is intended anyway. - */ - if ( !(mode & (MAP_OWNER_DYING | MAP_SINGLE_DEVICE)) ) - printk(XENLOG_WARNING VTDPREFIX - " %pp: reassignment may cause %pd data corruption\n", - &PCI_SBDF(seg, bus, devfn), prev_dom); - - write_atomic(&context->lo, lctxt.lo); - /* No barrier should be needed between these two. */ - write_atomic(&context->hi, lctxt.hi); + if ( pdev ) + check_cleanup_domid_map(domain, pdev, iommu); + printk(XENLOG_ERR + "%pp: unexpected context entry %016lx_%016lx (expected %01= 6lx_%016lx)\n", + &PCI_SBDF(seg, bus, devfn), + (uint64_t)(res >> 64), (uint64_t)res, + (uint64_t)(old >> 64), (uint64_t)old); + rc =3D -EILSEQ; + goto unlock; } =20 iommu_sync_cache(context, sizeof(struct context_entry)); @@ -2630,6 +2598,15 @@ static int __init cf_check vtd_setup(void) int ret; bool reg_inval_supported =3D true; =20 + if ( unlikely(!cpu_has_cx16) ) + { + printk(XENLOG_ERR VTDPREFIX + "IOMMU: CPU doesn't support CMPXCHG16B, disabling\n"); + + ret =3D -ENODEV; + goto error; + } + if ( list_empty(&acpi_drhd_units) ) { ret =3D -ENODEV; --=20 2.44.0 Teddy Astie | Vates XCP-ng Intern XCP-ng & Xen Orchestra - Vates solutions web: https://vates.tech From nobody Sun Feb 8 07:07:32 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass header.i=teddy.astie@vates.tech; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=quarantine dis=none) header.from=vates.tech ARC-Seal: i=1; a=rsa-sha256; t=1713183420; cv=none; d=zohomail.com; s=zohoarc; b=hP9GLFqmaLs+ma8Ia3bFHTGB97Yr8StuLecOYcM4Y+5asUvX1TXqZRoQ62btIuRU8ecpDyWlt+4cl3SokYHG+cY72/d5HeWcu03/0l7Nwn7bXx4sxDUISh9KmDN6nFXkN+mriGBesSanyjB6kKgLIYbyTrEDV4ZD6hXYUIi/RpQ= ARC-Message-Signature: i=1; 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charset="utf-8" All hardware with AMD-Vi has CMPXCHG16 support. Check this at initialisation time, and remove the effectively-dead logic for the non-cx16 case. Suggested-by: Andrew Cooper Signed-off-by: Teddy Astie --- xen/drivers/passthrough/amd/iommu_map.c | 42 +++++++-------------- xen/drivers/passthrough/amd/pci_amd_iommu.c | 6 +++ 2 files changed, 20 insertions(+), 28 deletions(-) diff --git a/xen/drivers/passthrough/amd/iommu_map.c b/xen/drivers/passthro= ugh/amd/iommu_map.c index e0f4fe736a..f67975e700 100644 --- a/xen/drivers/passthrough/amd/iommu_map.c +++ b/xen/drivers/passthrough/amd/iommu_map.c @@ -167,15 +167,14 @@ int amd_iommu_set_root_page_table(struct amd_iommu_dt= e *dte, { bool valid =3D flags & SET_ROOT_VALID; =20 - if ( dte->v && dte->tv && - (cpu_has_cx16 || (flags & SET_ROOT_WITH_UNITY_MAP)) ) + if ( dte->v && dte->tv ) { union { struct amd_iommu_dte dte; uint64_t raw64[4]; __uint128_t raw128[2]; } ldte =3D { .dte =3D *dte }; - __uint128_t old =3D ldte.raw128[0]; + __uint128_t res, old =3D ldte.raw128[0]; int ret =3D 0; =20 ldte.dte.domain_id =3D domain_id; @@ -185,33 +184,20 @@ int amd_iommu_set_root_page_table(struct amd_iommu_dt= e *dte, ldte.dte.paging_mode =3D paging_mode; ldte.dte.v =3D valid; =20 - if ( cpu_has_cx16 ) - { - __uint128_t res =3D cmpxchg16b(dte, &old, &ldte.raw128[0]); + res =3D cmpxchg16b(dte, &old, &ldte.raw128[0]); =20 - /* - * Hardware does not update the DTE behind our backs, so the - * return value should match "old". - */ - if ( res !=3D old ) - { - printk(XENLOG_ERR - "Dom%d: unexpected DTE %016lx_%016lx (expected %016= lx_%016lx)\n", - domain_id, - (uint64_t)(res >> 64), (uint64_t)res, - (uint64_t)(old >> 64), (uint64_t)old); - ret =3D -EILSEQ; - } - } - else /* Best effort, updating domain_id last. */ + /* + * Hardware does not update the DTE behind our backs, so the + * return value should match "old". + */ + if ( res !=3D old ) { - uint64_t *ptr =3D (void *)dte; - - write_atomic(ptr + 0, ldte.raw64[0]); - /* No barrier should be needed between these two. */ - write_atomic(ptr + 1, ldte.raw64[1]); - - ret =3D 1; + printk(XENLOG_ERR + "Dom%d: unexpected DTE %016lx_%016lx (expected %016lx_%= 016lx)\n", + domain_id, + (uint64_t)(res >> 64), (uint64_t)res, + (uint64_t)(old >> 64), (uint64_t)old); + ret =3D -EILSEQ; } =20 return ret; diff --git a/xen/drivers/passthrough/amd/pci_amd_iommu.c b/xen/drivers/pass= through/amd/pci_amd_iommu.c index f6efd88e36..3a6a23f706 100644 --- a/xen/drivers/passthrough/amd/pci_amd_iommu.c +++ b/xen/drivers/passthrough/amd/pci_amd_iommu.c @@ -305,6 +305,12 @@ static int __init cf_check iov_detect(void) if ( !iommu_enable && !iommu_intremap ) return 0; =20 + if ( unlikely(!cpu_has_cx16) ) + { + printk("AMD-Vi: CPU doesn't support CMPXCHG16B, disabling\n"); + return -ENODEV; + } + if ( (init_done ? amd_iommu_init_late() : amd_iommu_init(false)) !=3D 0 ) { --=20 2.44.0 Teddy Astie | Vates XCP-ng Intern XCP-ng & Xen Orchestra - Vates solutions web: https://vates.tech From nobody Sun Feb 8 07:07:32 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; 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charset="utf-8" This flag was only used in case cx16 is not available, as those code paths = no longer exist, this flag now does basically nothing. Signed-off-by: Teddy Astie --- xen/drivers/passthrough/vtd/iommu.c | 12 +++--------- xen/drivers/passthrough/vtd/vtd.h | 5 ++--- 2 files changed, 5 insertions(+), 12 deletions(-) diff --git a/xen/drivers/passthrough/vtd/iommu.c b/xen/drivers/passthrough/= vtd/iommu.c index 9c787ba9eb..7c6bae0256 100644 --- a/xen/drivers/passthrough/vtd/iommu.c +++ b/xen/drivers/passthrough/vtd/iommu.c @@ -1692,15 +1692,9 @@ static int domain_context_mapping(struct domain *dom= ain, u8 devfn, break; } =20 - if ( domain !=3D pdev->domain && pdev->domain !=3D dom_io ) - { - if ( pdev->domain->is_dying ) - mode |=3D MAP_OWNER_DYING; - else if ( drhd && - !any_pdev_behind_iommu(pdev->domain, pdev, drhd->iommu) = && - !pdev->phantom_stride ) - mode |=3D MAP_SINGLE_DEVICE; - } + if ( domain !=3D pdev->domain && pdev->domain !=3D dom_io && + pdev->domain->is_dying ) + mode |=3D MAP_OWNER_DYING; =20 switch ( pdev->type ) { diff --git a/xen/drivers/passthrough/vtd/vtd.h b/xen/drivers/passthrough/vt= d/vtd.h index cb2df76eed..43f06a353d 100644 --- a/xen/drivers/passthrough/vtd/vtd.h +++ b/xen/drivers/passthrough/vtd/vtd.h @@ -28,9 +28,8 @@ */ #define MAP_WITH_RMRR (1u << 0) #define MAP_OWNER_DYING (1u << 1) -#define MAP_SINGLE_DEVICE (1u << 2) -#define MAP_ERROR_RECOVERY (1u << 3) -#define UNMAP_ME_PHANTOM_FUNC (1u << 4) +#define MAP_ERROR_RECOVERY (1u << 2) +#define UNMAP_ME_PHANTOM_FUNC (1u << 3) =20 /* Allow for both IOAPIC and IOSAPIC. */ #define IO_xAPIC_route_entry IO_APIC_route_entry --=20 2.44.0 Teddy Astie | Vates XCP-ng Intern XCP-ng & Xen Orchestra - Vates solutions web: https://vates.tech From nobody Sun Feb 8 07:07:32 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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charset="utf-8" All hardware with VT-d has CMPXCHG16B support. Check this at initialisation time, and remove the effectively-dead logic for the non-cx16 case. Suggested-by: Andrew Cooper Signed-off-by: Teddy Astie --- xen/drivers/passthrough/vtd/intremap.c | 70 ++++++++------------------ xen/drivers/passthrough/vtd/iommu.c | 7 +-- 2 files changed, 21 insertions(+), 56 deletions(-) diff --git a/xen/drivers/passthrough/vtd/intremap.c b/xen/drivers/passthrou= gh/vtd/intremap.c index c504852eb8..7d4d907b4f 100644 --- a/xen/drivers/passthrough/vtd/intremap.c +++ b/xen/drivers/passthrough/vtd/intremap.c @@ -150,6 +150,13 @@ bool __init cf_check intel_iommu_supports_eim(void) if ( !iommu_qinval || !iommu_intremap || list_empty(&acpi_drhd_units) ) return false; =20 + if ( unlikely(!cpu_has_cx16) ) + { + printk(XENLOG_WARNING VTDPREFIX + "CPU doesn't support CMPXCHG16B, disable interrupt remappin= g\n"); + return false; + } + /* We MUST have a DRHD unit for each IOAPIC. */ for ( apic =3D 0; apic < nr_ioapics; apic++ ) if ( !ioapic_to_drhd(IO_APIC_ID(apic)) ) @@ -173,47 +180,26 @@ bool __init cf_check intel_iommu_supports_eim(void) * Assume iremap_lock has been acquired. It is to make sure software will = not * change the same IRTE behind us. With this assumption, if only high qwor= d or * low qword in IRTE is to be updated, this function's atomic variant can - * present an atomic update to VT-d hardware even when cmpxchg16b - * instruction is not supported. + * present an atomic update to VT-d hardware. */ static void update_irte(struct vtd_iommu *iommu, struct iremap_entry *entr= y, const struct iremap_entry *new_ire, bool atomic) { - ASSERT(spin_is_locked(&iommu->intremap.lock)); + __uint128_t ret; + struct iremap_entry old_ire; =20 - if ( cpu_has_cx16 ) - { - __uint128_t ret; - struct iremap_entry old_ire; + ASSERT(spin_is_locked(&iommu->intremap.lock)); =20 - old_ire =3D *entry; - ret =3D cmpxchg16b(entry, &old_ire, new_ire); + old_ire =3D *entry; + ret =3D cmpxchg16b(entry, &old_ire, new_ire); =20 - /* - * In the above, we use cmpxchg16 to atomically update the 128-bit - * IRTE, and the hardware cannot update the IRTE behind us, so - * the return value of cmpxchg16 should be the same as old_ire. - * This ASSERT validate it. - */ - ASSERT(ret =3D=3D old_ire.val); - } - else - { - /* - * VT-d hardware doesn't update IRTEs behind us, nor the software - * since we hold iremap_lock. If the caller wants VT-d hardware to - * always see a consistent entry, but we can't meet it, a bug will - * be raised. - */ - if ( entry->lo =3D=3D new_ire->lo ) - write_atomic(&entry->hi, new_ire->hi); - else if ( entry->hi =3D=3D new_ire->hi ) - write_atomic(&entry->lo, new_ire->lo); - else if ( !atomic ) - *entry =3D *new_ire; - else - BUG(); - } + /* + * In the above, we use cmpxchg16 to atomically update the 128-bit + * IRTE, and the hardware cannot update the IRTE behind us, so + * the return value of cmpxchg16 should be the same as old_ire. + * This ASSERT validate it. + */ + ASSERT(ret =3D=3D old_ire.val); } =20 /* Mark specified intr remap entry as free */ @@ -395,7 +381,6 @@ static int ioapic_rte_to_remap_entry(struct vtd_iommu *= iommu, /* Indicate remap format. */ remap_rte->format =3D 1; =20 - /* If cmpxchg16b is not available the caller must mask the IO-APIC pin= . */ update_irte(iommu, iremap_entry, &new_ire, !init && !masked); iommu_sync_cache(iremap_entry, sizeof(*iremap_entry)); iommu_flush_iec_index(iommu, 0, index); @@ -437,21 +422,6 @@ void cf_check io_apic_write_remap_rte( bool masked =3D true; int rc; =20 - if ( !cpu_has_cx16 ) - { - /* - * Cannot atomically update the IRTE entry: mask the IO-APIC pin to - * avoid interrupts seeing an inconsistent IRTE entry. - */ - old_rte =3D __ioapic_read_entry(apic, pin, true); - if ( !old_rte.mask ) - { - masked =3D false; - old_rte.mask =3D 1; - __ioapic_write_entry(apic, pin, true, old_rte); - } - } - /* Not the initializer, for old gcc to cope. */ new_rte.raw =3D rte; =20 diff --git a/xen/drivers/passthrough/vtd/iommu.c b/xen/drivers/passthrough/= vtd/iommu.c index 7c6bae0256..a1bd3c5ff6 100644 --- a/xen/drivers/passthrough/vtd/iommu.c +++ b/xen/drivers/passthrough/vtd/iommu.c @@ -2663,12 +2663,7 @@ static int __init cf_check vtd_setup(void) iommu_intremap =3D iommu_intremap_off; =20 #ifndef iommu_intpost - /* - * We cannot use posted interrupt if X86_FEATURE_CX16 is - * not supported, since we count on this feature to - * atomically update 16-byte IRTE in posted format. - */ - if ( !cap_intr_post(iommu->cap) || !iommu_intremap || !cpu_has_cx1= 6 ) + if ( !cap_intr_post(iommu->cap) || !iommu_intremap ) iommu_intpost =3D false; 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charset="utf-8" All hardware with AMD-Vi has CMPXCHG16 support. Check this at initialisati= on time, and remove the effectively-dead logic for the non-cx16 case. Suggested-by: Andrew Cooper Signed-off-by: Teddy Astie --- xen/drivers/passthrough/amd/iommu_intr.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/xen/drivers/passthrough/amd/iommu_intr.c b/xen/drivers/passthr= ough/amd/iommu_intr.c index 7fc796dec2..9ab7c68749 100644 --- a/xen/drivers/passthrough/amd/iommu_intr.c +++ b/xen/drivers/passthrough/amd/iommu_intr.c @@ -649,6 +649,12 @@ bool __init cf_check iov_supports_xt(void) if ( !iommu_enable || !iommu_intremap ) return false; =20 + if ( unlikely(!cpu_has_cx16) ) + { + AMD_IOMMU_WARN("CPU doesn't support CMPXCHG16B, disable interrupt = remapping\n"); + return false; + } + if ( amd_iommu_prepare(true) ) return false; =20 --=20 2.44.0 Teddy Astie | Vates XCP-ng Intern XCP-ng & Xen Orchestra - Vates solutions web: https://vates.tech