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Wed, 16 Aug 2023 03:20:15 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Bob Eshleman , Alistair Francis , Connor Davis Subject: [PATCH v1 01/57] xen/riscv:introduce asm/byteorder.h Date: Wed, 16 Aug 2023 13:19:11 +0300 Message-ID: <026edfc051aafb87ed23d68cf757f9513ad78d91.1692181079.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1692181249412100004 Content-Type: text/plain; charset="utf-8" Signed-off-by: Oleksii Kurochko --- xen/arch/riscv/include/asm/byteorder.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) create mode 100644 xen/arch/riscv/include/asm/byteorder.h diff --git a/xen/arch/riscv/include/asm/byteorder.h b/xen/arch/riscv/includ= e/asm/byteorder.h new file mode 100644 index 0000000000..320a03c88f --- /dev/null +++ b/xen/arch/riscv/include/asm/byteorder.h @@ -0,0 +1,16 @@ +#ifndef __ASM_RISCV_BYTEORDER_H__ +#define __ASM_RISCV_BYTEORDER_H__ + +#define __BYTEORDER_HAS_U64__ + +#include + +#endif /* __ASM_RISCV_BYTEORDER_H__ */ +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ --=20 2.41.0 From nobody Wed May 15 01:18:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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Wed, 16 Aug 2023 03:20:15 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Andrew Cooper , George Dunlap , Jan Beulich , Julien Grall , Stefano Stabellini , Wei Liu Subject: [PATCH v1 02/57] xen/riscv: add public arch-riscv.h Date: Wed, 16 Aug 2023 13:19:12 +0300 Message-ID: X-Mailer: git-send-email 2.41.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1692181247999100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Oleksii Kurochko --- xen/include/public/arch-riscv.h | 90 +++++++++++++++++++++++++++++++++ xen/include/public/xen.h | 2 + 2 files changed, 92 insertions(+) create mode 100644 xen/include/public/arch-riscv.h diff --git a/xen/include/public/arch-riscv.h b/xen/include/public/arch-risc= v.h new file mode 100644 index 0000000000..05f2c67f49 --- /dev/null +++ b/xen/include/public/arch-riscv.h @@ -0,0 +1,90 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Guest OS interface to RISC-V Xen. + * Initially based on the ARM implementation. + */ + +#ifndef __XEN_PUBLIC_ARCH_RISCV_H__ +#define __XEN_PUBLIC_ARCH_RISCV_H__ + +#define int64_aligned_t int64_t __attribute__((__aligned__(8))) +#define uint64_aligned_t uint64_t __attribute__((__aligned__(8))) + +#ifndef __ASSEMBLY__ +#define ___DEFINE_XEN_GUEST_HANDLE(name, type) \ + typedef union { type *p; unsigned long q; } \ + __guest_handle_ ## name; \ + typedef union { type *p; uint64_aligned_t q; } \ + __guest_handle_64_ ## name + +/* + * XEN_GUEST_HANDLE represents a guest pointer, when passed as a field + * in a struct in memory. On RISCV is always 8 bytes sizes and 8 bytes + * aligned. + * XEN_GUEST_HANDLE_PARAM represents a guest pointer, when passed as an + * hypercall argument. It is 4 bytes on aarch32 and 8 bytes on aarch64. + */ +#define __DEFINE_XEN_GUEST_HANDLE(name, type) \ + ___DEFINE_XEN_GUEST_HANDLE(name, type); \ + ___DEFINE_XEN_GUEST_HANDLE(const_##name, const type) +#define DEFINE_XEN_GUEST_HANDLE(name) __DEFINE_XEN_GUEST_HANDLE(name, na= me) +#define __XEN_GUEST_HANDLE(name) __guest_handle_64_ ## name +#define XEN_GUEST_HANDLE(name) __XEN_GUEST_HANDLE(name) +#define XEN_GUEST_HANDLE_PARAM(name) __guest_handle_ ## name +#define set_xen_guest_handle_raw(hnd, val) \ + do { \ + typeof(&(hnd)) _sxghr_tmp =3D &(hnd); \ + _sxghr_tmp->q =3D 0; \ + _sxghr_tmp->p =3D (val); \ + } while ( 0 ) +#define set_xen_guest_handle(hnd, val) set_xen_guest_handle_raw(hnd, val) + +typedef uint64_t xen_pfn_t; +#define PRI_xen_pfn PRIx64 +#define PRIu_xen_pfn PRIu64 + +typedef uint64_t xen_ulong_t; +#define PRI_xen_ulong PRIx64 + +#if defined(__XEN__) || defined(__XEN_TOOLS__) + +struct vcpu_guest_context { +}; +typedef struct vcpu_guest_context vcpu_guest_context_t; +DEFINE_XEN_GUEST_HANDLE(vcpu_guest_context_t); + +struct xen_arch_domainconfig { +}; + +#endif + +struct arch_vcpu_info { +}; +typedef struct arch_vcpu_info arch_vcpu_info_t; + +struct arch_shared_info { +}; +typedef struct arch_shared_info arch_shared_info_t; + +/* Maximum number of virtual CPUs in legacy multi-processor guests. */ +/* Only one. All other VCPUS must use VCPUOP_register_vcpu_info */ +#define XEN_LEGACY_MAX_VCPUS 1 + +#endif /* __ASSEMBLY__ */ + +#ifndef __ASSEMBLY__ +/* Stub definition of PMU structure */ +typedef struct xen_pmu_arch { uint8_t dummy; } xen_pmu_arch_t; +#endif + +#endif /* __XEN_PUBLIC_ARCH_RISCV_H__ */ + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * tab-width: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/include/public/xen.h b/xen/include/public/xen.h index 920567e006..8a07032796 100644 --- a/xen/include/public/xen.h +++ b/xen/include/public/xen.h @@ -16,6 +16,8 @@ #include "arch-x86/xen.h" #elif defined(__arm__) || defined (__aarch64__) #include "arch-arm.h" +#elif defined(__riscv) +#include "arch-riscv.h" #else #error "Unsupported architecture" #endif --=20 2.41.0 From nobody Wed May 15 01:18:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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Wed, 16 Aug 2023 03:20:16 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Bob Eshleman , Alistair Francis , Connor Davis Subject: [PATCH v1 03/57] xen/riscv: introduce spinlock.h Date: Wed, 16 Aug 2023 13:19:13 +0300 Message-ID: X-Mailer: git-send-email 2.41.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1692181289281100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Oleksii Kurochko --- xen/arch/riscv/include/asm/spinlock.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) create mode 100644 xen/arch/riscv/include/asm/spinlock.h diff --git a/xen/arch/riscv/include/asm/spinlock.h b/xen/arch/riscv/include= /asm/spinlock.h new file mode 100644 index 0000000000..8e61a88c3d --- /dev/null +++ b/xen/arch/riscv/include/asm/spinlock.h @@ -0,0 +1,13 @@ +#ifndef __ASM_RISCV_SPINLOCK_H +#define __ASM_RISCV_SPINLOCK_H + +#define arch_lock_acquire_barrier() smp_mb() +#define arch_lock_release_barrier() smp_mb() + +#define arch_lock_relax() cpu_relax() +#define arch_lock_signal() do { \ +} while(0) + +#define arch_lock_signal_wmb() arch_lock_signal() + +#endif /* __ASM_RISCV_SPINLOCK_H */ --=20 2.41.0 From nobody Wed May 15 01:18:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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Wed, 16 Aug 2023 03:20:17 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Bob Eshleman , Alistair Francis , Connor Davis Subject: [PATCH v1 04/57] xen/riscv: introduce fence.h Date: Wed, 16 Aug 2023 13:19:14 +0300 Message-ID: <3e3a0893da26eb534975c8c60f4cb3e0f2721610.1692181079.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1692181255729100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: Oleksii Kurochko --- xen/arch/riscv/include/asm/fence.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) create mode 100644 xen/arch/riscv/include/asm/fence.h diff --git a/xen/arch/riscv/include/asm/fence.h b/xen/arch/riscv/include/as= m/fence.h new file mode 100644 index 0000000000..2b443a3a48 --- /dev/null +++ b/xen/arch/riscv/include/asm/fence.h @@ -0,0 +1,12 @@ +#ifndef _ASM_RISCV_FENCE_H +#define _ASM_RISCV_FENCE_H + +#ifdef CONFIG_SMP +#define RISCV_ACQUIRE_BARRIER "\tfence r , rw\n" +#define RISCV_RELEASE_BARRIER "\tfence rw, w\n" +#else +#define RISCV_ACQUIRE_BARRIER +#define RISCV_RELEASE_BARRIER +#endif + +#endif /* _ASM_RISCV_FENCE_H */ --=20 2.41.0 From nobody Wed May 15 01:18:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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Wed, 16 Aug 2023 03:20:18 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Andrew Cooper , George Dunlap , Jan Beulich , Julien Grall , Stefano Stabellini , Wei Liu Subject: [PATCH v1 05/57] xen/riscv: introduce arch-riscv/hvm/save.h Date: Wed, 16 Aug 2023 13:19:15 +0300 Message-ID: <0f590ab9f08e4c5515cc93067f626f30e5f43172.1692181079.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1692181259214100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Oleksii Kurochko --- xen/include/public/arch-riscv/hvm/save.h | 22 ++++++++++++++++++++++ xen/include/public/hvm/save.h | 2 ++ 2 files changed, 24 insertions(+) create mode 100644 xen/include/public/arch-riscv/hvm/save.h diff --git a/xen/include/public/arch-riscv/hvm/save.h b/xen/include/public/= arch-riscv/hvm/save.h new file mode 100644 index 0000000000..b81e323848 --- /dev/null +++ b/xen/include/public/arch-riscv/hvm/save.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Structure definitions for HVM state that is held by Xen and must + * be saved along with the domain's memory and device-model state. + * + * Copyright (c) 2012 Citrix Systems Ltd. + */ + +#ifndef __XEN_PUBLIC_HVM_SAVE_RISCV_H__ +#define __XEN_PUBLIC_HVM_SAVE_RISCV_H__ + +#endif + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * tab-width: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/include/public/hvm/save.h b/xen/include/public/hvm/save.h index 464ebdb0da..902320abe8 100644 --- a/xen/include/public/hvm/save.h +++ b/xen/include/public/hvm/save.h @@ -89,6 +89,8 @@ DECLARE_HVM_SAVE_TYPE(END, 0, struct hvm_save_end); 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charset="utf-8" Signed-off-by: Oleksii Kurochko --- xen/arch/riscv/include/asm/paging.h | 7 +++++++ 1 file changed, 7 insertions(+) create mode 100644 xen/arch/riscv/include/asm/paging.h diff --git a/xen/arch/riscv/include/asm/paging.h b/xen/arch/riscv/include/a= sm/paging.h new file mode 100644 index 0000000000..73810e83d4 --- /dev/null +++ b/xen/arch/riscv/include/asm/paging.h @@ -0,0 +1,7 @@ +#ifndef __ASM_RISCV_PAGING_H__ +#define __ASM_RISCV_PAGING_H__ + +#define paging_mode_translate(d) (1) +#define paging_mode_external(d) (1) + +#endif /* __ASM_RISCV_PAGING_H__ */ \ No newline at end of file --=20 2.41.0 From nobody Wed May 15 01:18:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; 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Wed, 16 Aug 2023 03:20:19 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Bob Eshleman , Alistair Francis , Connor Davis Subject: [PATCH v1 07/57] xen/riscv: introduce asm/cpufeature.h Date: Wed, 16 Aug 2023 13:19:17 +0300 Message-ID: X-Mailer: git-send-email 2.41.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1692181249404100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: Oleksii Kurochko --- xen/arch/riscv/include/asm/cpufeature.h | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 xen/arch/riscv/include/asm/cpufeature.h diff --git a/xen/arch/riscv/include/asm/cpufeature.h b/xen/arch/riscv/inclu= de/asm/cpufeature.h new file mode 100644 index 0000000000..211827f816 --- /dev/null +++ b/xen/arch/riscv/include/asm/cpufeature.h @@ -0,0 +1,22 @@ +#ifndef __ASM_RISCV_CPUFEATURE_H +#define __ASM_RISCV_CPUFEATURE_H + +#ifndef __ASSEMBLY__ + +static inline int cpu_nr_siblings(unsigned int cpu) +{ + return 1; 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charset="utf-8" Signed-off-by: Oleksii Kurochko --- xen/arch/riscv/include/asm/device.h | 55 +++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) create mode 100644 xen/arch/riscv/include/asm/device.h diff --git a/xen/arch/riscv/include/asm/device.h b/xen/arch/riscv/include/a= sm/device.h new file mode 100644 index 0000000000..e58178517a --- /dev/null +++ b/xen/arch/riscv/include/asm/device.h @@ -0,0 +1,55 @@ +#ifndef __ASM_RISCV_DEVICE_H__ +#define __ASM_RISCV_DEVICE_H__ + +struct dt_device_node; + +enum device_type +{ + DEV_DT, + DEV_PCI, +}; + +struct device { + enum device_type type; +#ifdef CONFIG_HAS_DEVICE_TREE + struct dt_device_node *of_node; /* Used by drivers imported from Linux= */ +#endif +}; + +enum device_class +{ + DEVICE_SERIAL, + DEVICE_IOMMU, + DEVICE_GIC, + DEVICE_PCI_HOSTBRIDGE, + /* Use for error */ + DEVICE_UNKNOWN, +}; + +struct device_desc { + /* Device name */ + const char *name; + /* Device class */ + enum device_class class; + /* List of devices supported by this driver */ + const struct dt_device_match *dt_match; + /* + * Device initialization. + * + * -EAGAIN is used to indicate that device probing is deferred. + */ + int (*init)(struct dt_device_node *dev, const void *data); +}; + +typedef struct device device_t; + +#define DT_DEVICE_START(_name, _namestr, _class) \ +static const struct device_desc __dev_desc_##_name __used \ +__section(".dev.info") =3D { \ + .name =3D _namestr, \ + .class =3D _class, \ + +#define DT_DEVICE_END \ +}; + +#endif /* __ASM_RISCV_DEVICE_H__ */ \ No newline at end of file --=20 2.41.0 From nobody Wed May 15 01:18:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; 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Wed, 16 Aug 2023 03:20:21 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Bob Eshleman , Alistair Francis , Connor Davis Subject: [PATCH v1 09/57] xen/riscv: introduce asm/event.h Date: Wed, 16 Aug 2023 13:19:19 +0300 Message-ID: <8589c3816ae402d0770d2043c58065617aa73e7c.1692181079.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1692181311640100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Oleksii Kurochko --- xen/arch/riscv/include/asm/event.h | 34 ++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 xen/arch/riscv/include/asm/event.h diff --git a/xen/arch/riscv/include/asm/event.h b/xen/arch/riscv/include/as= m/event.h new file mode 100644 index 0000000000..48630c77b3 --- /dev/null +++ b/xen/arch/riscv/include/asm/event.h @@ -0,0 +1,34 @@ +#ifndef __ASM_RISCV_EVENT_H__ +#define __ASM_RISCV_EVENT_H__ + +void vcpu_mark_events_pending(struct vcpu *v); + +static inline int vcpu_event_delivery_is_enabled(struct vcpu *v) +{ + return 0; +} + +static inline int local_events_need_delivery(void) +{ + return 0; +} + +static inline void local_event_delivery_enable(void) +{ +} + +/* No arch specific virq definition now. Default to global. */ +static inline bool arch_virq_is_global(unsigned int virq) +{ + return true; +} + +#endif +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ --=20 2.41.0 From nobody Wed May 15 01:18:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1692181251; cv=none; d=zohomail.com; s=zohoarc; b=GPkA/O0PLGJ7Vg1qmgGYH9UgiVUu39lQM+Rhy2xF/j01EuTyiGqdeueZKcJrikSZO9y2lqc1jskB9NJVOlm86AvVMAjsJ9z9zyab0sEW9zNZD1eTYm9MZcV8Q408EAuKYrYOi+HKO3/LjxpfKI0bDe/Odncp2u9IuZq38c3Vo6o= ARC-Message-Signature: i=1; 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charset="utf-8" Signed-off-by: Oleksii Kurochko --- xen/arch/riscv/include/asm/grant_table.h | 4 ++++ 1 file changed, 4 insertions(+) create mode 100644 xen/arch/riscv/include/asm/grant_table.h diff --git a/xen/arch/riscv/include/asm/grant_table.h b/xen/arch/riscv/incl= ude/asm/grant_table.h new file mode 100644 index 0000000000..600fb10669 --- /dev/null +++ b/xen/arch/riscv/include/asm/grant_table.h @@ -0,0 +1,4 @@ +#ifndef __ASM_RISCV_GRANTTABLE_H__ +#define __ASM_RISCV_GRANTTABLE_H__ + +#endif /* __ASM_RISCV_GRANTTABLE_H__ */ \ No newline at end of file --=20 2.41.0 From nobody Wed May 15 01:18:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; 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Wed, 16 Aug 2023 03:20:23 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Bob Eshleman , Alistair Francis , Connor Davis Subject: [PATCH v1 11/57] xen/riscv: introduce asm/guest_atomics.h Date: Wed, 16 Aug 2023 13:19:21 +0300 Message-ID: <02e2850d01d0184b9a1f0c643de4879773c5ad49.1692181079.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1692181255529100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Oleksii Kurochko --- xen/arch/riscv/include/asm/guest_atomics.h | 49 ++++++++++++++++++++++ 1 file changed, 49 insertions(+) create mode 100644 xen/arch/riscv/include/asm/guest_atomics.h diff --git a/xen/arch/riscv/include/asm/guest_atomics.h b/xen/arch/riscv/in= clude/asm/guest_atomics.h new file mode 100644 index 0000000000..71b0b11a25 --- /dev/null +++ b/xen/arch/riscv/include/asm/guest_atomics.h @@ -0,0 +1,49 @@ +#ifndef __ASM_RISCV_GUEST_ATOMICS_H +#define __ASM_RISCV_GUEST_ATOMICS_H + +/* + * TODO: implement guest atomics + */ + +#define guest_testop(name) = \ +static inline int guest_##name(struct domain *d, int nr, volatile void *p)= \ +{ = \ + (void) d; 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Wed, 16 Aug 2023 03:20:24 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Bob Eshleman , Alistair Francis , Connor Davis Subject: [PATCH v1 12/57] xen/riscv: introduce asm/hypercall.h Date: Wed, 16 Aug 2023 13:19:22 +0300 Message-ID: <35b62b1741e585e2c617ee39ff807468ad39875b.1692181079.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1692181263702100013 Content-Type: text/plain; charset="utf-8" Signed-off-by: Oleksii Kurochko --- xen/arch/riscv/include/asm/hypercall.h | 4 ++++ 1 file changed, 4 insertions(+) create mode 100644 xen/arch/riscv/include/asm/hypercall.h diff --git a/xen/arch/riscv/include/asm/hypercall.h b/xen/arch/riscv/includ= e/asm/hypercall.h new file mode 100644 index 0000000000..f58c2f2761 --- /dev/null +++ b/xen/arch/riscv/include/asm/hypercall.h @@ -0,0 +1,4 @@ +#ifndef __ASM_RISCV_HYPERCALL_H__ +#define __ASM_RISCV_HYPERCALL_H__ + +#endif /* __ASM_RISCV_HYPERCALL_H__ */ \ No newline at end of file --=20 2.41.0 From nobody Wed May 15 01:18:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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Wed, 16 Aug 2023 03:20:24 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Bob Eshleman , Alistair Francis , Connor Davis Subject: [PATCH v1 13/57] xen/riscv: introduce asm/iocap.h Date: Wed, 16 Aug 2023 13:19:23 +0300 Message-ID: <6387a36bb349e88b5ee9da4271c87ec1a9889e65.1692181079.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1692181312803100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: Oleksii Kurochko --- xen/arch/riscv/include/asm/iocap.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) create mode 100644 xen/arch/riscv/include/asm/iocap.h diff --git a/xen/arch/riscv/include/asm/iocap.h b/xen/arch/riscv/include/as= m/iocap.h new file mode 100644 index 0000000000..c3147b1aed --- /dev/null +++ b/xen/arch/riscv/include/asm/iocap.h @@ -0,0 +1,16 @@ +#ifndef __ASM_RISCV_IOCAP_H__ +#define __ASM_RISCV_IOCAP_H__ + +#define cache_flush_permitted(d) \ + (!rangeset_is_empty((d)->iomem_caps)) + +#endif + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ --=20 2.41.0 From nobody Wed May 15 01:18:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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Wed, 16 Aug 2023 03:20:25 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Bob Eshleman , Alistair Francis , Connor Davis Subject: [PATCH v1 14/57] xen/riscv: introduce asm/iommu.h Date: Wed, 16 Aug 2023 13:19:24 +0300 Message-ID: <778623157380cf687de887fbce3d6667d9dde37e.1692181079.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1692181259702100005 Content-Type: text/plain; charset="utf-8" Signed-off-by: Oleksii Kurochko --- xen/arch/riscv/include/asm/iommu.h | 7 +++++++ 1 file changed, 7 insertions(+) create mode 100644 xen/arch/riscv/include/asm/iommu.h diff --git a/xen/arch/riscv/include/asm/iommu.h b/xen/arch/riscv/include/as= m/iommu.h new file mode 100644 index 0000000000..dd823e33ca --- /dev/null +++ b/xen/arch/riscv/include/asm/iommu.h @@ -0,0 +1,7 @@ +#ifndef __ASM_RISCV_IOMMU_H__ +#define __ASM_RISCV_IOMMU_H__ + +struct arch_iommu { +}; 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Wed, 16 Aug 2023 03:20:26 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Bob Eshleman , Alistair Francis , Connor Davis Subject: [PATCH v1 15/57] xen/riscv: introduce asm/mem_access.h Date: Wed, 16 Aug 2023 13:19:25 +0300 Message-ID: <3313d384bcc4d4f42388cb980d307283f4eeb18c.1692181079.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1692181263191100010 Content-Type: text/plain; charset="utf-8" Signed-off-by: Oleksii Kurochko --- xen/arch/riscv/include/asm/mem_access.h | 4 ++++ 1 file changed, 4 insertions(+) create mode 100644 xen/arch/riscv/include/asm/mem_access.h diff --git a/xen/arch/riscv/include/asm/mem_access.h b/xen/arch/riscv/inclu= de/asm/mem_access.h new file mode 100644 index 0000000000..8668c55a4a --- /dev/null +++ b/xen/arch/riscv/include/asm/mem_access.h @@ -0,0 +1,4 @@ +#ifndef __ASM_RISCV_MEM_ACCESS +#define __ASM_RISCV_MEM_ACCESS + +#endif \ No newline at end of file --=20 2.41.0 From nobody Wed May 15 01:18:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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Wed, 16 Aug 2023 03:20:27 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Bob Eshleman , Alistair Francis , Connor Davis Subject: [PATCH v1 16/57] xen/riscv: introduce asm/nospec.h Date: Wed, 16 Aug 2023 13:19:26 +0300 Message-ID: X-Mailer: git-send-email 2.41.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1692181263185100009 Content-Type: text/plain; charset="utf-8" Signed-off-by: Oleksii Kurochko --- xen/arch/riscv/include/asm/nospec.h | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 xen/arch/riscv/include/asm/nospec.h diff --git a/xen/arch/riscv/include/asm/nospec.h b/xen/arch/riscv/include/a= sm/nospec.h new file mode 100644 index 0000000000..55087fa831 --- /dev/null +++ b/xen/arch/riscv/include/asm/nospec.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright 2018 Amazon.com, Inc. or its affiliates. All Rights Reserved.= */ + +#ifndef _ASM_RISCV_NOSPEC_H +#define _ASM_RISCV_NOSPEC_H + +static inline bool evaluate_nospec(bool condition) +{ + return condition; +} + +static inline void block_speculation(void) +{ +} + +#endif /* _ASM_RISCV_NOSPEC_H */ + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ --=20 2.41.0 From nobody Wed May 15 01:18:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1692181261; cv=none; d=zohomail.com; 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Wed, 16 Aug 2023 03:20:27 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Bob Eshleman , Alistair Francis , Connor Davis Subject: [PATCH v1 17/57] xen/riscv: introduce asm/pci.h Date: Wed, 16 Aug 2023 13:19:27 +0300 Message-ID: <4eb79794a495bc5987a26e939599fbf47ad23113.1692181079.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1692181313291100005 Content-Type: text/plain; charset="utf-8" Signed-off-by: Oleksii Kurochko --- xen/arch/riscv/include/asm/pci.h | 7 +++++++ 1 file changed, 7 insertions(+) create mode 100644 xen/arch/riscv/include/asm/pci.h diff --git a/xen/arch/riscv/include/asm/pci.h b/xen/arch/riscv/include/asm/= pci.h new file mode 100644 index 0000000000..bd1fc54696 --- /dev/null +++ b/xen/arch/riscv/include/asm/pci.h @@ -0,0 +1,7 @@ +#ifndef __ASM_RISCV_PCI_H__ +#define __ASM_RISCV_PCI_H__ + +struct arch_pci_dev { +}; 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Wed, 16 Aug 2023 03:20:28 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Bob Eshleman , Alistair Francis , Connor Davis Subject: [PATCH v1 18/57] xen/riscv: introduce asm/random.h Date: Wed, 16 Aug 2023 13:19:28 +0300 Message-ID: <93fb3701ad107c4cb772eacad215e70016ebf348.1692181079.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1692181313405100006 Content-Type: text/plain; charset="utf-8" Signed-off-by: Oleksii Kurochko --- xen/arch/riscv/include/asm/random.h | 9 +++++++++ 1 file changed, 9 insertions(+) create mode 100644 xen/arch/riscv/include/asm/random.h diff --git a/xen/arch/riscv/include/asm/random.h b/xen/arch/riscv/include/a= sm/random.h new file mode 100644 index 0000000000..8d5df8a9b6 --- /dev/null +++ b/xen/arch/riscv/include/asm/random.h @@ -0,0 +1,9 @@ +#ifndef __ASM_RISCV_RANDOM_H__ +#define __ASM_RISCV_RANDOM_H__ + +static inline unsigned int arch_get_random(void) +{ + return 0; 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Wed, 16 Aug 2023 03:20:29 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Bob Eshleman , Alistair Francis , Connor Davis Subject: [PATCH v1 19/57] xen/riscv: introduce asm/setup.h Date: Wed, 16 Aug 2023 13:19:29 +0300 Message-ID: <20012803bf6a630f3dc2f78cfc8524b7a89e6ec4.1692181079.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1692181956489100005 Content-Type: text/plain; charset="utf-8" Signed-off-by: Oleksii Kurochko --- xen/arch/riscv/include/asm/setup.h | 6 ++++++ 1 file changed, 6 insertions(+) create mode 100644 xen/arch/riscv/include/asm/setup.h diff --git a/xen/arch/riscv/include/asm/setup.h b/xen/arch/riscv/include/as= m/setup.h new file mode 100644 index 0000000000..9b3f8c6416 --- /dev/null +++ b/xen/arch/riscv/include/asm/setup.h @@ -0,0 +1,6 @@ +#ifndef __ASM_RISCV_SETUP_H__ +#define __ASM_RISCV_SETUP_H__ + +#define max_init_domid (0) + +#endif /* __ASM_RISCV_SETUP_H__ */ \ No newline at end of file --=20 2.41.0 From nobody Wed May 15 01:18:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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Wed, 16 Aug 2023 03:20:30 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Bob Eshleman , Alistair Francis , Connor Davis Subject: [PATCH v1 20/57] xen/riscv: introduce asm/system.h Date: Wed, 16 Aug 2023 13:19:30 +0300 Message-ID: <6e6d1e322635fbab0625ceac65c7dac83c5ff036.1692181079.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1692181968031100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Oleksii Kurochko --- xen/arch/riscv/include/asm/system.h | 83 +++++++++++++++++++++++++++++ 1 file changed, 83 insertions(+) create mode 100644 xen/arch/riscv/include/asm/system.h diff --git a/xen/arch/riscv/include/asm/system.h b/xen/arch/riscv/include/a= sm/system.h new file mode 100644 index 0000000000..b1d9936594 --- /dev/null +++ b/xen/arch/riscv/include/asm/system.h @@ -0,0 +1,83 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef _ASM_RISCV_BARRIER_H +#define _ASM_RISCV_BARRIER_H + +#include +// #include + +#ifndef __ASSEMBLY__ + +#define RISCV_FENCE(p, s) \ + __asm__ __volatile__ ("fence " #p "," #s : : : "memory") + +/* These barriers need to enforce ordering on both devices or memory. */ +#define mb() RISCV_FENCE(iorw,iorw) +#define rmb() RISCV_FENCE(ir,ir) +#define wmb() RISCV_FENCE(ow,ow) + +/* These barriers do not need to enforce ordering on devices, just memory.= */ +#define smp_mb() RISCV_FENCE(rw,rw) +#define smp_rmb() RISCV_FENCE(r,r) +#define smp_wmb() RISCV_FENCE(w,w) +#define smp_mb__before_atomic() smp_mb() +#define smp_mb__after_atomic() smp_mb() + +/* +#define __smp_store_release(p, v) \ +do { \ + compiletime_assert_atomic_type(*p); \ + RISCV_FENCE(rw,w); \ + WRITE_ONCE(*p, v); \ +} while (0) + +#define __smp_load_acquire(p) \ +({ \ + typeof(*p) ___p1 =3D READ_ONCE(*p); \ + compiletime_assert_atomic_type(*p); \ + RISCV_FENCE(r,rw); \ + ___p1; \ +}) +*/ + +static inline unsigned long local_save_flags(void) +{ + return csr_read(sstatus); +} + +static inline void local_irq_enable(void) +{ + csr_set(sstatus, SSTATUS_SIE); +} + +static inline void local_irq_disable(void) +{ + csr_clear(sstatus, SSTATUS_SIE); +} + +#define local_irq_save(x) \ +({ \ + x =3D csr_read_clear(CSR_SSTATUS, SSTATUS_SIE); \ + local_irq_disable(); \ +}) + +static inline void local_irq_restore(unsigned long flags) +{ + csr_set(CSR_SSTATUS, flags & SSTATUS_SIE); +} + +static inline int local_irq_is_enabled(void) +{ + unsigned long flags =3D local_save_flags(); + + return flags & SSTATUS_SIE; +} + +#define arch_fetch_and_add(x, v) __sync_fetch_and_add(x, v) + +// extern struct vcpu *__context_switch(struct vcpu *prev, struct vcpu *ne= xt); + +#endif /* __ASSEMBLY__ */ + + +#endif /* _ASM_RISCV_BARRIER_H */ --=20 2.41.0 From nobody Wed May 15 01:18:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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Wed, 16 Aug 2023 03:20:30 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Bob Eshleman , Alistair Francis , Connor Davis Subject: [PATCH v1 21/57] xen/riscv: introduce asm/xenoprof.h Date: Wed, 16 Aug 2023 13:19:31 +0300 Message-ID: <79e1d38ed9245de51e3c3441ed464db61d3b95f9.1692181079.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1692181959927100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Oleksii Kurochko --- xen/arch/riscv/include/asm/xenoprof.h | 4 ++++ 1 file changed, 4 insertions(+) create mode 100644 xen/arch/riscv/include/asm/xenoprof.h diff --git a/xen/arch/riscv/include/asm/xenoprof.h b/xen/arch/riscv/include= /asm/xenoprof.h new file mode 100644 index 0000000000..e3fc625932 --- /dev/null +++ b/xen/arch/riscv/include/asm/xenoprof.h @@ -0,0 +1,4 @@ +#ifndef __ASM_RISCV_XENOPROF_H__ +#define __ASM_RISCV_XENOPROF_H__ + +#endif /* __ASM_RISCV_XENOPROF_H__ */ \ No newline at end of file --=20 2.41.0 From nobody Wed May 15 01:18:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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Wed, 16 Aug 2023 03:20:32 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Bob Eshleman , Alistair Francis , Connor Davis Subject: [PATCH v1 22/57] xen/riscv: introduce bitops.h Date: Wed, 16 Aug 2023 13:19:33 +0300 Message-ID: X-Mailer: git-send-email 2.41.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1692181835144100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: Oleksii Kurochko --- xen/arch/riscv/include/asm/bitops.h | 288 ++++++++++++++++++++++++++++ 1 file changed, 288 insertions(+) create mode 100644 xen/arch/riscv/include/asm/bitops.h diff --git a/xen/arch/riscv/include/asm/bitops.h b/xen/arch/riscv/include/a= sm/bitops.h new file mode 100644 index 0000000000..24a49c499b --- /dev/null +++ b/xen/arch/riscv/include/asm/bitops.h @@ -0,0 +1,288 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (C) 2012 Regents of the University of California */ + +#ifndef _ASM_RISCV_BITOPS_H +#define _ASM_RISCV_BITOPS_H + +#include + +#define BITOP_BITS_PER_WORD 32 +#define BITOP_MASK(nr) (1UL << ((nr) % BITOP_BITS_PER_WORD)) +#define BITOP_WORD(nr) ((nr) / BITOP_BITS_PER_WORD) +#define BITS_PER_BYTE 8 + +#define __set_bit(n,p) set_bit(n,p) +#define __clear_bit(n,p) clear_bit(n,p) + +#define __AMO(op) "amo" #op ".w" + +#define __test_and_op_bit_ord(op, mod, nr, addr, ord) \ +({ \ + unsigned long __res, __mask; \ + __mask =3D BITOP_MASK(nr); \ + __asm__ __volatile__ ( \ + __AMO(op) #ord " %0, %2, %1" \ + : "=3Dr" (__res), "+A" (addr[BITOP_WORD(nr)]) \ + : "r" (mod(__mask)) \ + : "memory"); \ + ((__res & __mask) !=3D 0); \ +}) + +#define __op_bit_ord(op, mod, nr, addr, ord) \ + __asm__ __volatile__ ( \ + __AMO(op) #ord " zero, %1, %0" \ + : "+A" (addr[BITOP_WORD(nr)]) \ + : "r" (mod(BITOP_MASK(nr))) \ + : "memory"); + +#define __test_and_op_bit(op, mod, nr, addr) \ + __test_and_op_bit_ord(op, mod, nr, addr, .aqrl) + +#define __op_bit(op, mod, nr, addr) \ + __op_bit_ord(op, mod, nr, addr, ) + +/* Bitmask modifiers */ +#define __NOP(x) (x) +#define __NOT(x) (~(x)) + +/** + * __test_and_set_bit - Set a bit and return its old value + * @nr: Bit to set + * @addr: Address to count from + * + * This operation may be reordered on other architectures than x86. + */ +static inline int __test_and_set_bit(int nr, volatile void *p) +{ + volatile uint32_t *addr =3D p; + + return __test_and_op_bit(or, __NOP, nr, addr); +} + +/** + * __test_and_clear_bit - Clear a bit and return its old value + * @nr: Bit to clear + * @addr: Address to count from + * + * This operation can be reordered on other architectures other than x86. + */ +static inline int __test_and_clear_bit(int nr, volatile void *p) +{ + volatile uint32_t *addr =3D p; + + return __test_and_op_bit(and, __NOT, nr, addr); +} + +/** + * set_bit - Atomically set a bit in memory + * @nr: the bit to set + * @addr: the address to start counting from + * + * Note: there are no guarantees that this function will not be reordered + * on non x86 architectures, so if you are writing portable code, + * make sure not to rely on its reordering guarantees. + * + * Note that @nr may be almost arbitrarily large; this function is not + * restricted to acting on a single-word quantity. + */ +static inline void set_bit(int nr, volatile void *p) +{ + volatile uint32_t *addr =3D p; + + __op_bit(or, __NOP, nr, addr); +} + +/** + * clear_bit - Clears a bit in memory + * @nr: Bit to clear + * @addr: Address to start counting from + * + * Note: there are no guarantees that this function will not be reordered + * on non x86 architectures, so if you are writing portable code, + * make sure not to rely on its reordering guarantees. + */ +static inline void clear_bit(int nr, volatile void *p) +{ + volatile uint32_t *addr =3D p; + + __op_bit(and, __NOT, nr, addr); +} + +static inline int test_bit(int nr, const volatile void *p) +{ + const volatile uint32_t *addr =3D (const volatile uint32_t *)p; + + return 1UL & (addr[BITOP_WORD(nr)] >> (nr & (BITOP_BITS_PER_WORD-1))); +} + +#undef __test_and_op_bit +#undef __op_bit +#undef __NOP +#undef __NOT +#undef __AMO + +static inline int fls(unsigned int x) +{ + return generic_fls(x); +} + +static inline int flsl(unsigned long x) +{ + return generic_flsl(x); +} + +#define test_and_set_bit __test_and_set_bit +#define test_and_clear_bit __test_and_clear_bit + +/* Based on linux/include/asm-generic/bitops/find.h */ + +#ifndef find_next_bit +/** + * find_next_bit - find the next set bit in a memory region + * @addr: The address to base the search on + * @offset: The bitnumber to start searching at + * @size: The bitmap size in bits + */ +extern unsigned long find_next_bit(const unsigned long *addr, unsigned long + size, unsigned long offset); +#endif + +#ifndef find_next_zero_bit +/** + * find_next_zero_bit - find the next cleared bit in a memory region + * @addr: The address to base the search on + * @offset: The bitnumber to start searching at + * @size: The bitmap size in bits + */ +extern unsigned long find_next_zero_bit(const unsigned long *addr, unsigned + long size, unsigned long offset); +#endif + +/** + * find_first_bit - find the first set bit in a memory region + * @addr: The address to start the search at + * @size: The maximum size to search + * + * Returns the bit number of the first set bit. + */ +extern unsigned long find_first_bit(const unsigned long *addr, + unsigned long size); + +/** + * find_first_zero_bit - find the first cleared bit in a memory region + * @addr: The address to start the search at + * @size: The maximum size to search + * + * Returns the bit number of the first cleared bit. + */ +extern unsigned long find_first_zero_bit(const unsigned long *addr, + unsigned long size); + +#define ffs(x) ({ unsigned int __t =3D (x); fls(__t & -__t); }) + +/** + * ffs - find first bit in word. + * @word: The word to search + * + * Returns 0 if no bit exists, otherwise returns 1-indexed bit location. + */ +static inline unsigned long __ffs(unsigned long word) +{ + int num =3D 0; + +#if BITS_PER_LONG =3D=3D 64 + if ((word & 0xffffffff) =3D=3D 0) { + num +=3D 32; + word >>=3D 32; + } +#endif + if ((word & 0xffff) =3D=3D 0) { + num +=3D 16; + word >>=3D 16; + } + if ((word & 0xff) =3D=3D 0) { + num +=3D 8; + word >>=3D 8; + } + if ((word & 0xf) =3D=3D 0) { + num +=3D 4; + word >>=3D 4; + } + if ((word & 0x3) =3D=3D 0) { + num +=3D 2; + word >>=3D 2; + } + if ((word & 0x1) =3D=3D 0) + num +=3D 1; + return num; +} + +/** + * ffsl - find first bit in long. + * @word: The word to search + * + * Returns 0 if no bit exists, otherwise returns 1-indexed bit location. + */ +static inline unsigned int ffsl(unsigned long word) +{ + int num =3D 1; + + if (!word) + return 0; + +#if BITS_PER_LONG =3D=3D 64 + if ((word & 0xffffffff) =3D=3D 0) { + num +=3D 32; + word >>=3D 32; + } +#endif + if ((word & 0xffff) =3D=3D 0) { + num +=3D 16; + word >>=3D 16; + } + if ((word & 0xff) =3D=3D 0) { + num +=3D 8; + word >>=3D 8; + } + if ((word & 0xf) =3D=3D 0) { + num +=3D 4; + word >>=3D 4; + } + if ((word & 0x3) =3D=3D 0) { + num +=3D 2; + word >>=3D 2; + } + if ((word & 0x1) =3D=3D 0) + num +=3D 1; + return num; +} + +/* + * ffz - find first zero in word. + * @word: The word to search + * + * Undefined if no zero exists, so code should check against ~0UL first. + */ +#define ffz(x) __ffs(~(x)) + +/** + * find_first_set_bit - find the first set bit in @word + * @word: the word to search + * + * Returns the bit-number of the first set bit (first bit being 0). + * The input must *not* be zero. + */ +static inline unsigned int find_first_set_bit(unsigned long word) +{ + return ffsl(word) - 1; +} + +/** + * hweightN - returns the hamming weight of a N-bit word + * @x: the word to weigh + * + * The Hamming Weight of a number is the total number of bits set in it. + */ +#define hweight64(x) generic_hweight64(x) + +#endif /* _ASM_RISCV_BITOPS_H */ --=20 2.41.0 From nobody Wed May 15 01:18:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; 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Wed, 16 Aug 2023 03:20:33 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Bob Eshleman , Alistair Francis , Connor Davis Subject: [PATCH v1 23/57] xen/riscv: introduce flushtlb.h Date: Wed, 16 Aug 2023 13:19:34 +0300 Message-ID: X-Mailer: git-send-email 2.41.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1692181964500100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: Oleksii Kurochko --- xen/arch/riscv/include/asm/flushtlb.h | 31 +++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) create mode 100644 xen/arch/riscv/include/asm/flushtlb.h diff --git a/xen/arch/riscv/include/asm/flushtlb.h b/xen/arch/riscv/include= /asm/flushtlb.h new file mode 100644 index 0000000000..7059a53823 --- /dev/null +++ b/xen/arch/riscv/include/asm/flushtlb.h @@ -0,0 +1,31 @@ +#ifndef __ASM_RISCV_FLUSHTLB_H__ +#define __ASM_RISCV_FLUSHTLB_H__ + +#include + +/* + * Filter the given set of CPUs, removing those that definitely flushed th= eir + * TLB since @page_timestamp. + */ +/* XXX lazy implementation just doesn't clear anything.... */ +static inline void tlbflush_filter(cpumask_t *mask, uint32_t page_timestam= p) {} + +#define tlbflush_current_time() (0) + +static inline void page_set_tlbflush_timestamp(struct page_info *page) +{ + BUG(); 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charset="utf-8" Signed-off-by: Oleksii Kurochko --- xen/arch/riscv/include/asm/percpu.h | 33 +++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) create mode 100644 xen/arch/riscv/include/asm/percpu.h diff --git a/xen/arch/riscv/include/asm/percpu.h b/xen/arch/riscv/include/a= sm/percpu.h new file mode 100644 index 0000000000..6b317a28fd --- /dev/null +++ b/xen/arch/riscv/include/asm/percpu.h @@ -0,0 +1,33 @@ +#ifndef __ASM_RISCV_PERCPU_H__ +#define __ASM_RISCV_PERCPU_H__ + +#ifndef __ASSEMBLY__ + +#include + +extern char __per_cpu_start[], __per_cpu_data_end[]; +extern unsigned long __per_cpu_offset[NR_CPUS]; +void percpu_init_areas(void); + +#define per_cpu(var, cpu) \ + (*RELOC_HIDE(&per_cpu__##var, __per_cpu_offset[cpu])) + +#define this_cpu(var) \ + (*RELOC_HIDE(&per_cpu__##var, __per_cpu_offset[get_processor_id()])) + +#define per_cpu_ptr(var, cpu) \ + (*RELOC_HIDE(var, __per_cpu_offset[cpu])) +#define this_cpu_ptr(var) \ + (*RELOC_HIDE(var, get_processor_id())) + +#endif + +#endif /* __ASM_RISCV_PERCPU_H__ */ +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ --=20 2.41.0 From nobody Wed May 15 01:18:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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Wed, 16 Aug 2023 03:20:35 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Bob Eshleman , Alistair Francis , Connor Davis Subject: [PATCH v1 25/57] xen/riscv: introduce asm/smp.h Date: Wed, 16 Aug 2023 13:19:36 +0300 Message-ID: <3231fdcdd23bd97aab9769f97a78eaf2e718599a.1692181079.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1692181968550100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: Oleksii Kurochko --- xen/arch/riscv/include/asm/smp.h | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) create mode 100644 xen/arch/riscv/include/asm/smp.h diff --git a/xen/arch/riscv/include/asm/smp.h b/xen/arch/riscv/include/asm/= smp.h new file mode 100644 index 0000000000..cc8dd18254 --- /dev/null +++ b/xen/arch/riscv/include/asm/smp.h @@ -0,0 +1,20 @@ +#ifndef __ASM_RISCV_SMP_H +#define __ASM_RISCV_SMP_H + +#ifndef __ASSEMBLY__ +#include +#include +#endif + +DECLARE_PER_CPU(cpumask_var_t, cpu_sibling_mask); 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charset="utf-8" Signed-off-by: Oleksii Kurochko --- xen/arch/riscv/include/asm/atomic.h | 375 ++++++++++++++++++++++++++++ 1 file changed, 375 insertions(+) create mode 100644 xen/arch/riscv/include/asm/atomic.h diff --git a/xen/arch/riscv/include/asm/atomic.h b/xen/arch/riscv/include/a= sm/atomic.h new file mode 100644 index 0000000000..d4849cf282 --- /dev/null +++ b/xen/arch/riscv/include/asm/atomic.h @@ -0,0 +1,375 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Taken and modified from Linux. + *=20 + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * Copyright (C) 2012 Regents of the University of California + * Copyright (C) 2017 SiFive + * Copyright (C) 2021 Vates SAS + */ + +#ifndef _ASM_RISCV_ATOMIC_H +#define _ASM_RISCV_ATOMIC_H + +#include +#include +#include +#include +#include + +void __bad_atomic_size(void); + +static always_inline void read_atomic_size(const volatile void *p, + void *res, + unsigned int size) +{ + switch ( size ) { + case 1: *(uint8_t *)res =3D readb((uint8_t *)p); break; + case 2: *(uint16_t *)res =3D readw((uint16_t *)p); break; + case 4: *(uint32_t *)res =3D readl((uint32_t *)p); break; + case 8: *(uint32_t *)res =3D readq((uint64_t *)p); break; + default: __bad_atomic_size(); break; + } +} + +#define read_atomic(p) ({ \ + union { typeof(*p) val; char c[0]; } x_; \ + read_atomic_size(p, x_.c, sizeof(*p)); \ + x_.val; \ +}) + + +#define write_atomic(p, x) ({ \ + typeof(*p) __x =3D (x); \ + switch ( sizeof(*p) ) { \ + case 1: writeb((uint8_t)__x, (uint8_t *) p); break; \ + case 2: writew((uint16_t)__x, (uint16_t *) p); break; \ + case 4: writel((uint32_t)__x, (uint32_t *) p); break; \ + case 8: writeq((uint64_t)__x, (uint64_t *) p); break; \ + default: __bad_atomic_size(); break; \ + } \ + __x; \ +}) + +/* TODO: Fix this */ +#define add_sized(p, x) ({ \ + typeof(*(p)) __x =3D (x); \ + switch ( sizeof(*(p)) ) \ + { \ + case 1: writeb(read_atomic(p) + __x, (uint8_t *)(p)); break; \ + case 2: writew(read_atomic(p) + __x, (uint16_t *)(p)); break; \ + case 4: writel(read_atomic(p) + __x, (uint32_t *)(p)); break; \ + default: __bad_atomic_size(); break; \ + } \ +}) + +/* + * __unqual_scalar_typeof(x) - Declare an unqualified scalar type, leaving + * non-scalar types unchanged. + * + * Prefer C11 _Generic for better compile-times and simpler code. Note: 'c= har' + * is not type-compatible with 'signed char', and we define a separate cas= e. + */ +#define __scalar_type_to_expr_cases(type) \ + unsigned type: (unsigned type)0, \ + signed type: (signed type)0 + +#define __unqual_scalar_typeof(x) typeof( \ + _Generic((x), \ + char: (char)0, \ + __scalar_type_to_expr_cases(char), \ + __scalar_type_to_expr_cases(short), \ + __scalar_type_to_expr_cases(int), \ + __scalar_type_to_expr_cases(long), \ + __scalar_type_to_expr_cases(long long), \ + default: (x))) + +#define READ_ONCE(x) (*(const volatile __unqual_scalar_typeof(x) *)&(x)) +#define WRITE_ONCE(x, val) \ + do { \ + *(volatile typeof(x) *)&(x) =3D (val); \ + } while (0) + +#define __atomic_acquire_fence() \ + __asm__ __volatile__(RISCV_ACQUIRE_BARRIER "" ::: "memory") + +#define __atomic_release_fence() \ + __asm__ __volatile__(RISCV_RELEASE_BARRIER "" ::: "memory"); + +static inline int atomic_read(const atomic_t *v) +{ + return READ_ONCE(v->counter); +} + +static inline int _atomic_read(atomic_t v) +{ + return v.counter; +} + +static inline void atomic_set(atomic_t *v, int i) +{ + WRITE_ONCE(v->counter, i); +} + +static inline void _atomic_set(atomic_t *v, int i) +{ + v->counter =3D i; +} + +static inline int atomic_sub_and_test(int i, atomic_t *v) +{ + return atomic_sub_return(i, v) =3D=3D 0; +} + +static inline void atomic_inc(atomic_t *v) +{ + atomic_add(1, v); +} + +static inline int atomic_inc_return(atomic_t *v) +{ + return atomic_add_return(1, v); +} + +static inline void atomic_dec(atomic_t *v) +{ + atomic_sub(1, v); +} + +static inline int atomic_dec_return(atomic_t *v) +{ + return atomic_sub_return(1, v); +} + + +static inline int atomic_dec_and_test(atomic_t *v) +{ + return atomic_sub_return(1, v) =3D=3D 0; +} + +static inline int atomic_add_negative(int i, atomic_t *v) +{ + return atomic_add_return(i, v) < 0; +} + +static inline int atomic_inc_and_test(atomic_t *v) +{ + return atomic_add_return(1, v) =3D=3D 0; +} + +/* + * First, the atomic ops that have no ordering constraints and therefor do= n't + * have the AQ or RL bits set. These don't return anything, so there's on= ly + * one version to worry about. + */ +#define ATOMIC_OP(op, asm_op, I, asm_type, c_type, prefix) \ +static inline \ +void atomic##prefix##_##op(c_type i, atomic##prefix##_t *v) \ +{ \ + __asm__ __volatile__ ( \ + " amo" #asm_op "." #asm_type " zero, %1, %0" \ + : "+A" (v->counter) \ + : "r" (I) \ + : "memory"); \ +} \ + +#define ATOMIC_OPS(op, asm_op, I) \ + ATOMIC_OP (op, asm_op, I, w, int, ) + +ATOMIC_OPS(add, add, i) +ATOMIC_OPS(sub, add, -i) +ATOMIC_OPS(and, and, i) +ATOMIC_OPS( or, or, i) +ATOMIC_OPS(xor, xor, i) + +#undef ATOMIC_OP +#undef ATOMIC_OPS + +/* + * Atomic ops that have ordered, relaxed, acquire, and release variants. + * There's two flavors of these: the arithmatic ops have both fetch and re= turn + * versions, while the logical ops only have fetch versions. + */ +#define ATOMIC_FETCH_OP(op, asm_op, I, asm_type, c_type, prefix) \ +static inline \ +c_type atomic##prefix##_fetch_##op##_relaxed(c_type i, \ + atomic##prefix##_t *v) \ +{ \ + register c_type ret; \ + __asm__ __volatile__ ( \ + " amo" #asm_op "." #asm_type " %1, %2, %0" \ + : "+A" (v->counter), "=3Dr" (ret) \ + : "r" (I) \ + : "memory"); \ + return ret; \ +} \ +static inline \ +c_type atomic##prefix##_fetch_##op(c_type i, atomic##prefix##_t *v) \ +{ \ + register c_type ret; \ + __asm__ __volatile__ ( \ + " amo" #asm_op "." #asm_type ".aqrl %1, %2, %0" \ + : "+A" (v->counter), "=3Dr" (ret) \ + : "r" (I) \ + : "memory"); \ + return ret; \ +} + +#define ATOMIC_OP_RETURN(op, asm_op, c_op, I, asm_type, c_type, prefix) \ +static inline \ +c_type atomic##prefix##_##op##_return_relaxed(c_type i, \ + atomic##prefix##_t *v) \ +{ \ + return atomic##prefix##_fetch_##op##_relaxed(i, v) c_op I; \ +} \ +static inline \ +c_type atomic##prefix##_##op##_return(c_type i, atomic##prefix##_t *v) \ +{ \ + return atomic##prefix##_fetch_##op(i, v) c_op I; \ +} + +#define ATOMIC_OPS(op, asm_op, c_op, I) \ + ATOMIC_FETCH_OP( op, asm_op, I, w, int, ) \ + ATOMIC_OP_RETURN(op, asm_op, c_op, I, w, int, ) + +ATOMIC_OPS(add, add, +, i) +ATOMIC_OPS(sub, add, +, -i) + +#define atomic_add_return_relaxed atomic_add_return_relaxed +#define atomic_sub_return_relaxed atomic_sub_return_relaxed +#define atomic_add_return atomic_add_return +#define atomic_sub_return atomic_sub_return + +#define atomic_fetch_add_relaxed atomic_fetch_add_relaxed +#define atomic_fetch_sub_relaxed atomic_fetch_sub_relaxed +#define atomic_fetch_add atomic_fetch_add +#define atomic_fetch_sub atomic_fetch_sub + +#undef ATOMIC_OPS + +#define ATOMIC_OPS(op, asm_op, I) \ + ATOMIC_FETCH_OP(op, asm_op, I, w, int, ) + +ATOMIC_OPS(and, and, i) +ATOMIC_OPS( or, or, i) +ATOMIC_OPS(xor, xor, i) + +#define atomic_fetch_and_relaxed atomic_fetch_and_relaxed +#define atomic_fetch_or_relaxed atomic_fetch_or_relaxed +#define atomic_fetch_xor_relaxed atomic_fetch_xor_relaxed +#define atomic_fetch_and atomic_fetch_and +#define atomic_fetch_or atomic_fetch_or +#define atomic_fetch_xor atomic_fetch_xor + +#undef ATOMIC_OPS + +#undef ATOMIC_FETCH_OP +#undef ATOMIC_OP_RETURN + +/* This is required to provide a full barrier on success. */ +static inline int atomic_add_unless(atomic_t *v, int a, int u) +{ + int prev, rc; + + __asm__ __volatile__ ( + "0: lr.w %[p], %[c]\n" + " beq %[p], %[u], 1f\n" + " add %[rc], %[p], %[a]\n" + " sc.w.rl %[rc], %[rc], %[c]\n" + " bnez %[rc], 0b\n" + " fence rw, rw\n" + "1:\n" + : [p]"=3D&r" (prev), [rc]"=3D&r" (rc), [c]"+A" (v->counter) + : [a]"r" (a), [u]"r" (u) + : "memory"); + return prev; +} +#define atomic_fetch_add_unless atomic_fetch_add_unless + +/* + * atomic_{cmp,}xchg is required to have exactly the same ordering semanti= cs as + * {cmp,}xchg and the operations that return, so they need a full barrier. + */ +#define ATOMIC_OP(c_t, prefix, size) \ +static inline \ +c_t atomic##prefix##_xchg_relaxed(atomic##prefix##_t *v, c_t n) \ +{ \ + return __xchg_relaxed(&(v->counter), n, size); \ +} \ +static inline \ +c_t atomic##prefix##_xchg_acquire(atomic##prefix##_t *v, c_t n) \ +{ \ + return __xchg_acquire(&(v->counter), n, size); \ +} \ +static inline \ +c_t atomic##prefix##_xchg_release(atomic##prefix##_t *v, c_t n) \ +{ \ + return __xchg_release(&(v->counter), n, size); \ +} \ +static inline \ +c_t atomic##prefix##_xchg(atomic##prefix##_t *v, c_t n) \ +{ \ + return __xchg(&(v->counter), n, size); \ +} \ +static inline \ +c_t atomic##prefix##_cmpxchg_relaxed(atomic##prefix##_t *v, \ + c_t o, c_t n) \ +{ \ + return __cmpxchg_relaxed(&(v->counter), o, n, size); \ +} \ +static inline \ +c_t atomic##prefix##_cmpxchg_acquire(atomic##prefix##_t *v, \ + c_t o, c_t n) \ +{ \ + return __cmpxchg_acquire(&(v->counter), o, n, size); \ +} \ +static inline \ +c_t atomic##prefix##_cmpxchg_release(atomic##prefix##_t *v, \ + c_t o, c_t n) \ +{ \ + return __cmpxchg_release(&(v->counter), o, n, size); \ +} \ +static inline \ +c_t atomic##prefix##_cmpxchg(atomic##prefix##_t *v, c_t o, c_t n) \ +{ \ + return __cmpxchg(&(v->counter), o, n, size); \ +} + +#define ATOMIC_OPS() \ + ATOMIC_OP(int, , 4) + +ATOMIC_OPS() + +#define atomic_xchg_relaxed atomic_xchg_relaxed +#define atomic_xchg_acquire atomic_xchg_acquire +#define atomic_xchg_release atomic_xchg_release +#define atomic_xchg atomic_xchg +#define atomic_cmpxchg_relaxed atomic_cmpxchg_relaxed +#define atomic_cmpxchg_acquire atomic_cmpxchg_acquire +#define atomic_cmpxchg_release atomic_cmpxchg_release +#define atomic_cmpxchg atomic_cmpxchg + +#undef ATOMIC_OPS +#undef ATOMIC_OP + +static inline int atomic_sub_if_positive(atomic_t *v, int offset) +{ + int prev, rc; + + __asm__ __volatile__ ( + "0: lr.w %[p], %[c]\n" + " sub %[rc], %[p], %[o]\n" + " bltz %[rc], 1f\n" + " sc.w.rl %[rc], %[rc], %[c]\n" + " bnez %[rc], 0b\n" + " fence rw, rw\n" + "1:\n" + : [p]"=3D&r" (prev), [rc]"=3D&r" (rc), [c]"+A" (v->counter) + : [o]"r" (offset) + : "memory"); + return prev - offset; +} + +#define atomic_dec_if_positive(v) atomic_sub_if_positive(v, 1) + +#endif /* _ASM_RISCV_ATOMIC_H */ --=20 2.41.0 From nobody Wed May 15 01:18:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; 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Wed, 16 Aug 2023 03:20:36 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Bob Eshleman , Alistair Francis , Connor Davis Subject: [PATCH v1 27/57] xen/riscv: introduce cmpxchg.h Date: Wed, 16 Aug 2023 13:19:38 +0300 Message-ID: <40b81d8e401e375bc3723657e6b41f6b8d256490.1692181079.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1692181868514100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Oleksii Kurochko --- xen/arch/riscv/include/asm/cmpxchg.h | 373 +++++++++++++++++++++++++++ 1 file changed, 373 insertions(+) create mode 100644 xen/arch/riscv/include/asm/cmpxchg.h diff --git a/xen/arch/riscv/include/asm/cmpxchg.h b/xen/arch/riscv/include/= asm/cmpxchg.h new file mode 100644 index 0000000000..8660ecd287 --- /dev/null +++ b/xen/arch/riscv/include/asm/cmpxchg.h @@ -0,0 +1,373 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (C) 2014 Regents of the University of California */ + +#ifndef _ASM_RISCV_CMPXCHG_H +#define _ASM_RISCV_CMPXCHG_H + +#include +#include +#include + +#define __xchg_relaxed(ptr, new, size) \ +({ \ + __typeof__(ptr) __ptr =3D (ptr); \ + __typeof__(new) __new =3D (new); \ + __typeof__(*(ptr)) __ret; \ + switch (size) { \ + case 4: \ + __asm__ __volatile__ ( \ + " amoswap.w %0, %2, %1\n" \ + : "=3Dr" (__ret), "+A" (*__ptr) \ + : "r" (__new) \ + : "memory"); \ + break; \ + case 8: \ + __asm__ __volatile__ ( \ + " amoswap.d %0, %2, %1\n" \ + : "=3Dr" (__ret), "+A" (*__ptr) \ + : "r" (__new) \ + : "memory"); \ + break; \ + default: \ + ASSERT_UNREACHABLE(); \ + } \ + __ret; \ +}) + +#define xchg_relaxed(ptr, x) \ +({ \ + __typeof__(*(ptr)) _x_ =3D (x); \ + (__typeof__(*(ptr))) __xchg_relaxed((ptr), \ + _x_, sizeof(*(ptr))); \ +}) + +#define __xchg_acquire(ptr, new, size) \ +({ \ + __typeof__(ptr) __ptr =3D (ptr); \ + __typeof__(new) __new =3D (new); \ + __typeof__(*(ptr)) __ret; \ + switch (size) { \ + case 4: \ + __asm__ __volatile__ ( \ + " amoswap.w %0, %2, %1\n" \ + RISCV_ACQUIRE_BARRIER \ + : "=3Dr" (__ret), "+A" (*__ptr) \ + : "r" (__new) \ + : "memory"); \ + break; \ + case 8: \ + __asm__ __volatile__ ( \ + " amoswap.d %0, %2, %1\n" \ + RISCV_ACQUIRE_BARRIER \ + : "=3Dr" (__ret), "+A" (*__ptr) \ + : "r" (__new) \ + : "memory"); \ + break; \ + default: \ + ASSERT_UNREACHABLE(); \ + } \ + __ret; \ +}) + +#define xchg_acquire(ptr, x) \ +({ \ + __typeof__(*(ptr)) _x_ =3D (x); \ + (__typeof__(*(ptr))) __xchg_acquire((ptr), \ + _x_, sizeof(*(ptr))); \ +}) + +#define __xchg_release(ptr, new, size) \ +({ \ + __typeof__(ptr) __ptr =3D (ptr); \ + __typeof__(new) __new =3D (new); \ + __typeof__(*(ptr)) __ret; \ + switch (size) { \ + case 4: \ + __asm__ __volatile__ ( \ + RISCV_RELEASE_BARRIER \ + " amoswap.w %0, %2, %1\n" \ + : "=3Dr" (__ret), "+A" (*__ptr) \ + : "r" (__new) \ + : "memory"); \ + break; \ + case 8: \ + __asm__ __volatile__ ( \ + RISCV_RELEASE_BARRIER \ + " amoswap.d %0, %2, %1\n" \ + : "=3Dr" (__ret), "+A" (*__ptr) \ + : "r" (__new) \ + : "memory"); \ + break; \ + default: \ + ASSERT_UNREACHABLE(); \ + } \ + __ret; \ +}) + +#define xchg_release(ptr, x) \ +({ \ + __typeof__(*(ptr)) _x_ =3D (x); \ + (__typeof__(*(ptr))) __xchg_release((ptr), \ + _x_, sizeof(*(ptr))); \ +}) + +#define __xchg(ptr, new, size) \ +({ \ + __typeof__(ptr) __ptr =3D (ptr); \ + __typeof__(new) __new =3D (new); \ + __typeof__(*(ptr)) __ret; \ + switch (size) { \ + case 4: \ + __asm__ __volatile__ ( \ + " amoswap.w.aqrl %0, %2, %1\n" \ + : "=3Dr" (__ret), "+A" (*__ptr) \ + : "r" (__new) \ + : "memory"); \ + break; \ + case 8: \ + __asm__ __volatile__ ( \ + " amoswap.d.aqrl %0, %2, %1\n" \ + : "=3Dr" (__ret), "+A" (*__ptr) \ + : "r" (__new) \ + : "memory"); \ + break; \ + default: \ + __ret =3D 0; \ + ASSERT_UNREACHABLE(); \ + } \ + __ret; \ +}) + +#define xchg(ptr, x) \ +({ \ + __typeof__(*(ptr)) _x_ =3D (x); \ + (__typeof__(*(ptr))) __xchg((ptr), _x_, sizeof(*(ptr))); \ +}) + +#define xchg32(ptr, x) \ +({ \ + BUILD_BUG_ON(sizeof(*(ptr)) !=3D 4); \ + xchg((ptr), (x)); \ +}) + +#define xchg64(ptr, x) \ +({ \ + BUILD_BUG_ON(sizeof(*(ptr)) !=3D 8); \ + xchg((ptr), (x)); \ +}) + +/* + * Atomic compare and exchange. Compare OLD with MEM, if identical, + * store NEW in MEM. Return the initial value in MEM. Success is + * indicated by comparing RETURN with OLD. + */ +#define __cmpxchg_relaxed(ptr, old, new, size) \ +({ \ + __typeof__(ptr) __ptr =3D (ptr); \ + __typeof__(*(ptr)) __old =3D (old); \ + __typeof__(*(ptr)) __new =3D (new); \ + __typeof__(*(ptr)) __ret; \ + register unsigned int __rc; \ + switch (size) { \ + case 4: \ + __asm__ __volatile__ ( \ + "0: lr.w %0, %2\n" \ + " bne %0, %z3, 1f\n" \ + " sc.w %1, %z4, %2\n" \ + " bnez %1, 0b\n" \ + "1:\n" \ + : "=3D&r" (__ret), "=3D&r" (__rc), "+A" (*__ptr) \ + : "rJ" (__old), "rJ" (__new) \ + : "memory"); \ + break; \ + case 8: \ + __asm__ __volatile__ ( \ + "0: lr.d %0, %2\n" \ + " bne %0, %z3, 1f\n" \ + " sc.d %1, %z4, %2\n" \ + " bnez %1, 0b\n" \ + "1:\n" \ + : "=3D&r" (__ret), "=3D&r" (__rc), "+A" (*__ptr) \ + : "rJ" (__old), "rJ" (__new) \ + : "memory"); \ + break; \ + default: \ + ASSERT_UNREACHABLE(); \ + } \ + __ret; \ +}) + +#define cmpxchg_relaxed(ptr, o, n) \ +({ \ + __typeof__(*(ptr)) _o_ =3D (o); \ + __typeof__(*(ptr)) _n_ =3D (n); \ + (__typeof__(*(ptr))) __cmpxchg_relaxed((ptr), \ + _o_, _n_, sizeof(*(ptr))); \ +}) + +#define __cmpxchg_acquire(ptr, old, new, size) \ +({ \ + __typeof__(ptr) __ptr =3D (ptr); \ + __typeof__(*(ptr)) __old =3D (old); \ + __typeof__(*(ptr)) __new =3D (new); \ + __typeof__(*(ptr)) __ret; \ + register unsigned int __rc; \ + switch (size) { \ + case 4: \ + __asm__ __volatile__ ( \ + "0: lr.w %0, %2\n" \ + " bne %0, %z3, 1f\n" \ + " sc.w %1, %z4, %2\n" \ + " bnez %1, 0b\n" \ + RISCV_ACQUIRE_BARRIER \ + "1:\n" \ + : "=3D&r" (__ret), "=3D&r" (__rc), "+A" (*__ptr) \ + : "rJ" (__old), "rJ" (__new) \ + : "memory"); \ + break; \ + case 8: \ + __asm__ __volatile__ ( \ + "0: lr.d %0, %2\n" \ + " bne %0, %z3, 1f\n" \ + " sc.d %1, %z4, %2\n" \ + " bnez %1, 0b\n" \ + RISCV_ACQUIRE_BARRIER \ + "1:\n" \ + : "=3D&r" (__ret), "=3D&r" (__rc), "+A" (*__ptr) \ + : "rJ" (__old), "rJ" (__new) \ + : "memory"); \ + break; \ + default: \ + ASSERT_UNREACHABLE(); \ + } \ + __ret; \ +}) + +#define cmpxchg_acquire(ptr, o, n) \ +({ \ + __typeof__(*(ptr)) _o_ =3D (o); \ + __typeof__(*(ptr)) _n_ =3D (n); \ + (__typeof__(*(ptr))) __cmpxchg_acquire((ptr), \ + _o_, _n_, sizeof(*(ptr))); \ +}) + +#define __cmpxchg_release(ptr, old, new, size) \ +({ \ + __typeof__(ptr) __ptr =3D (ptr); \ + __typeof__(*(ptr)) __old =3D (old); \ + __typeof__(*(ptr)) __new =3D (new); \ + __typeof__(*(ptr)) __ret; \ + register unsigned int __rc; \ + switch (size) { \ + case 4: \ + __asm__ __volatile__ ( \ + RISCV_RELEASE_BARRIER \ + "0: lr.w %0, %2\n" \ + " bne %0, %z3, 1f\n" \ + " sc.w %1, %z4, %2\n" \ + " bnez %1, 0b\n" \ + "1:\n" \ + : "=3D&r" (__ret), "=3D&r" (__rc), "+A" (*__ptr) \ + : "rJ" (__old), "rJ" (__new) \ + : "memory"); \ + break; \ + case 8: \ + __asm__ __volatile__ ( \ + RISCV_RELEASE_BARRIER \ + "0: lr.d %0, %2\n" \ + " bne %0, %z3, 1f\n" \ + " sc.d %1, %z4, %2\n" \ + " bnez %1, 0b\n" \ + "1:\n" \ + : "=3D&r" (__ret), "=3D&r" (__rc), "+A" (*__ptr) \ + : "rJ" (__old), "rJ" (__new) \ + : "memory"); \ + break; \ + default: \ + ASSERT_UNREACHABLE(); \ + } \ + __ret; \ +}) + +#define cmpxchg_release(ptr, o, n) \ +({ \ + __typeof__(*(ptr)) _o_ =3D (o); \ + __typeof__(*(ptr)) _n_ =3D (n); \ + (__typeof__(*(ptr))) __cmpxchg_release((ptr), \ + _o_, _n_, sizeof(*(ptr))); \ +}) + +#define __cmpxchg(ptr, old, new, size) \ +({ \ + __typeof__(ptr) __ptr =3D (ptr); \ + __typeof__(*(ptr)) __old =3D (__typeof__(*(ptr)))(old); \ + __typeof__(*(ptr)) __new =3D (__typeof__(*(ptr)))(new); \ + __typeof__(*(ptr)) __ret; \ + register unsigned int __rc; \ + switch (size) { \ + case 4: \ + __asm__ __volatile__ ( \ + "0: lr.w %0, %2\n" \ + " bne %0, %z3, 1f\n" \ + " sc.w.rl %1, %z4, %2\n" \ + " bnez %1, 0b\n" \ + " fence rw, rw\n" \ + "1:\n" \ + : "=3D&r" (__ret), "=3D&r" (__rc), "+A" (*__ptr) \ + : "rJ" (__old), "rJ" (__new) \ + : "memory"); \ + break; \ + case 8: \ + __asm__ __volatile__ ( \ + "0: lr.d %0, %2\n" \ + " bne %0, %z3, 1f\n" \ + " sc.d.rl %1, %z4, %2\n" \ + " bnez %1, 0b\n" \ + " fence rw, rw\n" \ + "1:\n" \ + : "=3D&r" (__ret), "=3D&r" (__rc), "+A" (*__ptr) \ + : "rJ" (__old), "rJ" (__new) \ + : "memory"); \ + break; \ + default: \ + ASSERT_UNREACHABLE(); \ + } \ + __ret; \ +}) + +#define cmpxchg(ptr, o, n) \ +({ \ + __typeof__(*(ptr)) _o_ =3D (o); \ + __typeof__(*(ptr)) _n_ =3D (n); \ + (__typeof__(*(ptr))) __cmpxchg((ptr), \ + _o_, _n_, sizeof(*(ptr))); \ +}) + +#define cmpxchg_local(ptr, o, n) \ + (__cmpxchg_relaxed((ptr), (o), (n), sizeof(*(ptr)))) + +#define cmpxchg32(ptr, o, n) \ +({ \ + BUILD_BUG_ON(sizeof(*(ptr)) !=3D 4); \ + cmpxchg((ptr), (o), (n)); \ +}) + +#define cmpxchg32_local(ptr, o, n) \ +({ \ + BUILD_BUG_ON(sizeof(*(ptr)) !=3D 4); \ + cmpxchg_relaxed((ptr), (o), (n)) \ +}) + +#define cmpxchg64(ptr, o, n) \ +({ \ + BUILD_BUG_ON(sizeof(*(ptr)) !=3D 8); \ + cmpxchg((ptr), (o), (n)); \ +}) + +#define cmpxchg64_local(ptr, o, n) \ +({ \ + BUILD_BUG_ON(sizeof(*(ptr)) !=3D 8); \ + cmpxchg_relaxed((ptr), (o), (n)); \ +}) + +#endif /* _ASM_RISCV_CMPXCHG_H */ --=20 2.41.0 From nobody Wed May 15 01:18:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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Wed, 16 Aug 2023 03:20:37 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Bob Eshleman , Alistair Francis , Connor Davis Subject: [PATCH v1 28/57] xen/riscv: introduce asm/io.h Date: Wed, 16 Aug 2023 13:19:39 +0300 Message-ID: <39827b08ffe34621e572daabb1830b51e566fc5b.1692181079.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1692181916798100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Oleksii Kurochko --- xen/arch/riscv/include/asm/io.h | 132 ++++++++++++++++++++++++++++++++ 1 file changed, 132 insertions(+) create mode 100644 xen/arch/riscv/include/asm/io.h diff --git a/xen/arch/riscv/include/asm/io.h b/xen/arch/riscv/include/asm/i= o.h new file mode 100644 index 0000000000..8c83c9689b --- /dev/null +++ b/xen/arch/riscv/include/asm/io.h @@ -0,0 +1,132 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * {read,write}{b,w,l,q} based on arch/arm64/include/asm/io.h + * which was based on arch/arm/include/io.h + * + * Copyright (C) 1996-2000 Russell King + * Copyright (C) 2012 ARM Ltd. + * Copyright (C) 2014 Regents of the University of California + */ + +#ifndef _ASM_RISCV_IO_H +#define _ASM_RISCV_IO_H + +#include + +/* + * The RISC-V ISA doesn't yet specify how to query or modify PMAs, so we c= an't + * change the properties of memory regions. This should be fixed by the + * upcoming platform spec. + */ +#define ioremap_nocache(addr, size) ioremap((addr), (size)) +#define ioremap_wc(addr, size) ioremap((addr), (size)) +#define ioremap_wt(addr, size) ioremap((addr), (size)) + +/* Generic IO read/write. These perform native-endian accesses. */ +#define __raw_writeb __raw_writeb +static inline void __raw_writeb(u8 val, volatile void __iomem *addr) +{ + asm volatile("sb %0, 0(%1)" : : "r" (val), "r" (addr)); +} + +#define __raw_writew __raw_writew +static inline void __raw_writew(u16 val, volatile void __iomem *addr) +{ + asm volatile("sh %0, 0(%1)" : : "r" (val), "r" (addr)); +} + +#define __raw_writel __raw_writel +static inline void __raw_writel(u32 val, volatile void __iomem *addr) +{ + asm volatile("sw %0, 0(%1)" : : "r" (val), "r" (addr)); +} + +#ifdef CONFIG_64BIT +#define __raw_writeq __raw_writeq +static inline void __raw_writeq(u64 val, volatile void __iomem *addr) +{ + asm volatile("sd %0, 0(%1)" : : "r" (val), "r" (addr)); +} +#endif + +#define __raw_readb __raw_readb +static inline u8 __raw_readb(const volatile void __iomem *addr) +{ + u8 val; + + asm volatile("lb %0, 0(%1)" : "=3Dr" (val) : "r" (addr)); + return val; +} + +#define __raw_readw __raw_readw +static inline u16 __raw_readw(const volatile void __iomem *addr) +{ + u16 val; + + asm volatile("lh %0, 0(%1)" : "=3Dr" (val) : "r" (addr)); + return val; +} + +#define __raw_readl __raw_readl +static inline u32 __raw_readl(const volatile void __iomem *addr) +{ + u32 val; + + asm volatile("lw %0, 0(%1)" : "=3Dr" (val) : "r" (addr)); + return val; +} + +#ifdef CONFIG_64BIT +#define __raw_readq __raw_readq +static inline u64 __raw_readq(const volatile void __iomem *addr) +{ + u64 val; + + asm volatile("ld %0, 0(%1)" : "=3Dr" (val) : "r" (addr)); + return val; +} +#endif + +/* + * Unordered I/O memory access primitives. These are even more relaxed th= an + * the relaxed versions, as they don't even order accesses between success= ive + * operations to the I/O regions. + */ +#define readb_cpu(c) ({ u8 __r =3D __raw_readb(c); __r; }) +#define readw_cpu(c) ({ u16 __r =3D le16_to_cpu((__force __le16)__raw_rea= dw(c)); __r; }) +#define readl_cpu(c) ({ u32 __r =3D le32_to_cpu((__force __le32)__raw_rea= dl(c)); __r; }) + +#define writeb_cpu(v,c) ((void)__raw_writeb((v),(c))) +#define writew_cpu(v,c) ((void)__raw_writew((__force u16)cpu_to_le16(v),(= c))) +#define writel_cpu(v,c) ((void)__raw_writel((__force u32)cpu_to_le32(v),(= c))) + +#ifdef CONFIG_64BIT +#define readq_cpu(c) ({ u64 __r =3D le64_to_cpu((__force __le64)__raw_rea= dq(c)); __r; }) +#define writeq_cpu(v,c) ((void)__raw_writeq((__force u64)cpu_to_le64(v),(= c))) +#endif + +/* + * I/O memory access primitives. Reads are ordered relative to any + * following Normal memory access. Writes are ordered relative to any prior + * Normal memory access. The memory barriers here are necessary as RISC-V + * doesn't define any ordering between the memory space and the I/O space. + */ +#define __io_br() do {} while (0) +#define __io_ar(v) __asm__ __volatile__ ("fence i,r" : : : "memory"); +#define __io_bw() __asm__ __volatile__ ("fence w,o" : : : "memory"); +#define __io_aw() do { } while (0) + +#define readb(c) ({ u8 __v; __io_br(); __v =3D readb_cpu(c); __io_ar(__v)= ; __v; }) +#define readw(c) ({ u16 __v; __io_br(); __v =3D readw_cpu(c); __io_ar(__v)= ; __v; }) +#define readl(c) ({ u32 __v; __io_br(); __v =3D readl_cpu(c); __io_ar(__v)= ; __v; }) + +#define writeb(v,c) ({ __io_bw(); writeb_cpu((v),(c)); __io_aw(); }) +#define writew(v,c) ({ __io_bw(); writew_cpu((v),(c)); __io_aw(); }) +#define writel(v,c) ({ __io_bw(); writel_cpu((v),(c)); __io_aw(); }) + +#ifdef CONFIG_64BIT +#define readq(c) ({ u64 __v; __io_br(); __v =3D readq_cpu(c); __io_ar(__v)= ; __v; }) +#define writeq(v,c) ({ __io_bw(); writeq_cpu((v),(c)); __io_aw(); }) +#endif + +#endif /* _ASM_RISCV_IO_H */ --=20 2.41.0 From nobody Wed May 15 01:18:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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Wed, 16 Aug 2023 03:20:38 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Bob Eshleman , Alistair Francis , Connor Davis Subject: [PATCH v1 29/57] xen/riscv: introduce asm/hardirq.h Date: Wed, 16 Aug 2023 13:19:40 +0300 Message-ID: X-Mailer: git-send-email 2.41.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1692181913523100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: Oleksii Kurochko --- xen/arch/riscv/include/asm/hardirq.h | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 xen/arch/riscv/include/asm/hardirq.h diff --git a/xen/arch/riscv/include/asm/hardirq.h b/xen/arch/riscv/include/= asm/hardirq.h new file mode 100644 index 0000000000..467421849a --- /dev/null +++ b/xen/arch/riscv/include/asm/hardirq.h @@ -0,0 +1,26 @@ +#ifndef __ASM_RISCV_HARDIRQ_H +#define __ASM_RISCV_HARDIRQ_H + +#include + +typedef struct { + unsigned long __softirq_pending; + unsigned int __local_irq_count; +} __cacheline_aligned irq_cpustat_t; + +#include /* Standard mappings for irq_cpustat_t abo= ve */ + +#define in_irq() (local_irq_count(smp_processor_id()) !=3D 0) + +#define irq_enter() (local_irq_count(smp_processor_id())++) +#define irq_exit() (local_irq_count(smp_processor_id())--) + +#endif /* __ASM_RISCV_HARDIRQ_H */ +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ --=20 2.41.0 From nobody Wed May 15 01:18:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; 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Wed, 16 Aug 2023 03:20:39 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Bob Eshleman , Alistair Francis , Connor Davis Subject: [PATCH v1 30/57] xen/riscv: introduce div64.h Date: Wed, 16 Aug 2023 13:19:42 +0300 Message-ID: <167762fc457a89f284dc4e90408ed8e37fa25fdf.1692181079.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1692181963218100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Oleksii Kurochko --- xen/arch/riscv/include/asm/div64.h | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 xen/arch/riscv/include/asm/div64.h diff --git a/xen/arch/riscv/include/asm/div64.h b/xen/arch/riscv/include/as= m/div64.h new file mode 100644 index 0000000000..212dfe4e8a --- /dev/null +++ b/xen/arch/riscv/include/asm/div64.h @@ -0,0 +1,22 @@ +#ifndef __ASM_RISCV_DIV64 +#define __ASM_RISCV_DIV64 + +#include + +# define do_div(n,base) ({ \ + uint32_t __base =3D (base); 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charset="utf-8" Signed-off-by: Oleksii Kurochko --- xen/arch/riscv/xen.lds.S | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/xen/arch/riscv/xen.lds.S b/xen/arch/riscv/xen.lds.S index 9064852173..aa42d3d17b 100644 --- a/xen/arch/riscv/xen.lds.S +++ b/xen/arch/riscv/xen.lds.S @@ -40,6 +40,16 @@ SECTIONS . =3D ALIGN(PAGE_SIZE); .rodata : { _srodata =3D .; /* Read-only data */ + /* Bug frames table */ + __start_bug_frames =3D .; + *(.bug_frames.0) + __stop_bug_frames_0 =3D .; + *(.bug_frames.1) + __stop_bug_frames_1 =3D .; + *(.bug_frames.2) + __stop_bug_frames_2 =3D .; + *(.bug_frames.3) + __stop_bug_frames_3 =3D .; *(.rodata) *(.rodata.*) *(.data.rel.ro) --=20 2.41.0 From nobody Wed May 15 01:18:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; 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Wed, 16 Aug 2023 03:20:41 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Bob Eshleman , Alistair Francis , Connor Davis Subject: [PATCH v1 32/57] xen/riscv: introduce bit operations Date: Wed, 16 Aug 2023 13:19:44 +0300 Message-ID: X-Mailer: git-send-email 2.41.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1692182002844100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Oleksii Kurochko --- xen/arch/riscv/Makefile | 1 + xen/arch/riscv/lib/Makefile | 1 + xen/arch/riscv/lib/find_next_bit.c | 278 +++++++++++++++++++++++++++++ 3 files changed, 280 insertions(+) create mode 100644 xen/arch/riscv/lib/Makefile create mode 100644 xen/arch/riscv/lib/find_next_bit.c diff --git a/xen/arch/riscv/Makefile b/xen/arch/riscv/Makefile index 2fefe14e7c..b08048948f 100644 --- a/xen/arch/riscv/Makefile +++ b/xen/arch/riscv/Makefile @@ -1,5 +1,6 @@ obj-$(CONFIG_EARLY_PRINTK) +=3D early_printk.o obj-y +=3D entry.o +obj-y +=3D lib/ obj-y +=3D mm.o obj-$(CONFIG_RISCV_64) +=3D riscv64/ obj-y +=3D sbi.o diff --git a/xen/arch/riscv/lib/Makefile b/xen/arch/riscv/lib/Makefile new file mode 100644 index 0000000000..6fae6a1f10 --- /dev/null +++ b/xen/arch/riscv/lib/Makefile @@ -0,0 +1 @@ +obj-y +=3D find_next_bit.o diff --git a/xen/arch/riscv/lib/find_next_bit.c b/xen/arch/riscv/lib/find_n= ext_bit.c new file mode 100644 index 0000000000..ac5a4687e3 --- /dev/null +++ b/xen/arch/riscv/lib/find_next_bit.c @@ -0,0 +1,278 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * find_next_bit.c: fallback find next bit implementation + * + * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + */ +#include +#include +#include + +#ifndef find_next_bit +/* + * Find the next set bit in a memory region. + */ +unsigned long find_next_bit(const unsigned long *addr, unsigned long size, + unsigned long offset) +{ + const unsigned long *p =3D addr + BIT_WORD(offset); + unsigned long result =3D offset & ~(BITS_PER_LONG-1); + unsigned long tmp; + + if (offset >=3D size) + return size; + size -=3D result; + offset %=3D BITS_PER_LONG; + if (offset) { + tmp =3D *(p++); + tmp &=3D (~0UL << offset); + if (size < BITS_PER_LONG) + goto found_first; + if (tmp) + goto found_middle; + size -=3D BITS_PER_LONG; + result +=3D BITS_PER_LONG; + } + while (size & ~(BITS_PER_LONG-1)) { + if ((tmp =3D *(p++))) + goto found_middle; + result +=3D BITS_PER_LONG; + size -=3D BITS_PER_LONG; + } + if (!size) + return result; + tmp =3D *p; + +found_first: + tmp &=3D (~0UL >> (BITS_PER_LONG - size)); + if (tmp =3D=3D 0UL) /* Are any bits set? */ + return result + size; /* Nope. */ +found_middle: + return result + __ffs(tmp); +} +EXPORT_SYMBOL(find_next_bit); +#endif + +#ifndef find_next_zero_bit +/* + * This implementation of find_{first,next}_zero_bit was stolen from + * Linus' asm-alpha/bitops.h. + */ +unsigned long find_next_zero_bit(const unsigned long *addr, unsigned long = size, + unsigned long offset) +{ + const unsigned long *p =3D addr + BIT_WORD(offset); + unsigned long result =3D offset & ~(BITS_PER_LONG-1); + unsigned long tmp; + + if (offset >=3D size) + return size; + size -=3D result; + offset %=3D BITS_PER_LONG; + if (offset) { + tmp =3D *(p++); + tmp |=3D ~0UL >> (BITS_PER_LONG - offset); + if (size < BITS_PER_LONG) + goto found_first; + if (~tmp) + goto found_middle; + size -=3D BITS_PER_LONG; + result +=3D BITS_PER_LONG; + } + while (size & ~(BITS_PER_LONG-1)) { + if (~(tmp =3D *(p++))) + goto found_middle; + result +=3D BITS_PER_LONG; + size -=3D BITS_PER_LONG; + } + if (!size) + return result; + tmp =3D *p; + +found_first: + tmp |=3D ~0UL << size; + if (tmp =3D=3D ~0UL) /* Are any bits zero? */ + return result + size; /* Nope. */ +found_middle: + return result + ffz(tmp); +} +EXPORT_SYMBOL(find_next_zero_bit); +#endif + +#ifndef find_first_bit +/* + * Find the first set bit in a memory region. + */ +unsigned long find_first_bit(const unsigned long *addr, unsigned long size) +{ + const unsigned long *p =3D addr; + unsigned long result =3D 0; + unsigned long tmp; + + while (size & ~(BITS_PER_LONG-1)) { + if ((tmp =3D *(p++))) + goto found; + result +=3D BITS_PER_LONG; + size -=3D BITS_PER_LONG; + } + if (!size) + return result; + + tmp =3D (*p) & (~0UL >> (BITS_PER_LONG - size)); + if (tmp =3D=3D 0UL) /* Are any bits set? */ + return result + size; /* Nope. */ +found: + return result + __ffs(tmp); +} +EXPORT_SYMBOL(find_first_bit); +#endif + +#ifndef find_first_zero_bit +/* + * Find the first cleared bit in a memory region. + */ +unsigned long find_first_zero_bit(const unsigned long *addr, unsigned long= size) +{ + const unsigned long *p =3D addr; + unsigned long result =3D 0; + unsigned long tmp; + + while (size & ~(BITS_PER_LONG-1)) { + if (~(tmp =3D *(p++))) + goto found; + result +=3D BITS_PER_LONG; + size -=3D BITS_PER_LONG; + } + if (!size) + return result; + + tmp =3D (*p) | (~0UL << size); + if (tmp =3D=3D ~0UL) /* Are any bits zero? */ + return result + size; /* Nope. */ +found: + return result + ffz(tmp); +} +EXPORT_SYMBOL(find_first_zero_bit); +#endif + +#ifdef __BIG_ENDIAN + +/* include/linux/byteorder does not support "unsigned long" type */ +static inline unsigned long ext2_swabp(const unsigned long * x) +{ +#if BITS_PER_LONG =3D=3D 64 + return (unsigned long) __swab64p((u64 *) x); +#elif BITS_PER_LONG =3D=3D 32 + return (unsigned long) __swab32p((u32 *) x); +#else +#error BITS_PER_LONG not defined +#endif +} + +/* include/linux/byteorder doesn't support "unsigned long" type */ +static inline unsigned long ext2_swab(const unsigned long y) +{ +#if BITS_PER_LONG =3D=3D 64 + return (unsigned long) __swab64((u64) y); +#elif BITS_PER_LONG =3D=3D 32 + return (unsigned long) __swab32((u32) y); +#else +#error BITS_PER_LONG not defined +#endif +} + +#ifndef find_next_zero_bit_le +unsigned long find_next_zero_bit_le(const void *addr, unsigned + long size, unsigned long offset) +{ + const unsigned long *p =3D addr; + unsigned long result =3D offset & ~(BITS_PER_LONG - 1); + unsigned long tmp; + + if (offset >=3D size) + return size; + p +=3D BIT_WORD(offset); + size -=3D result; + offset &=3D (BITS_PER_LONG - 1UL); + if (offset) { + tmp =3D ext2_swabp(p++); + tmp |=3D (~0UL >> (BITS_PER_LONG - offset)); + if (size < BITS_PER_LONG) + goto found_first; + if (~tmp) + goto found_middle; + size -=3D BITS_PER_LONG; + result +=3D BITS_PER_LONG; + } + + while (size & ~(BITS_PER_LONG - 1)) { + if (~(tmp =3D *(p++))) + goto found_middle_swap; + result +=3D BITS_PER_LONG; + size -=3D BITS_PER_LONG; + } + if (!size) + return result; + tmp =3D ext2_swabp(p); +found_first: + tmp |=3D ~0UL << size; + if (tmp =3D=3D ~0UL) /* Are any bits zero? */ + return result + size; /* Nope. Skip ffz */ +found_middle: + return result + ffz(tmp); + +found_middle_swap: + return result + ffz(ext2_swab(tmp)); +} +EXPORT_SYMBOL(find_next_zero_bit_le); +#endif + +#ifndef find_next_bit_le +unsigned long find_next_bit_le(const void *addr, unsigned + long size, unsigned long offset) +{ + const unsigned long *p =3D addr; + unsigned long result =3D offset & ~(BITS_PER_LONG - 1); + unsigned long tmp; + + if (offset >=3D size) + return size; + p +=3D BIT_WORD(offset); + size -=3D result; + offset &=3D (BITS_PER_LONG - 1UL); + if (offset) { + tmp =3D ext2_swabp(p++); + tmp &=3D (~0UL << offset); + if (size < BITS_PER_LONG) + goto found_first; + if (tmp) + goto found_middle; + size -=3D BITS_PER_LONG; + result +=3D BITS_PER_LONG; + } + + while (size & ~(BITS_PER_LONG - 1)) { + tmp =3D *(p++); + if (tmp) + goto found_middle_swap; + result +=3D BITS_PER_LONG; + size -=3D BITS_PER_LONG; + } + if (!size) + return result; + tmp =3D ext2_swabp(p); +found_first: + tmp &=3D (~0UL >> (BITS_PER_LONG - size)); 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charset="utf-8" Signed-off-by: Oleksii Kurochko --- xen/arch/riscv/include/asm/altp2m.h | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 xen/arch/riscv/include/asm/altp2m.h diff --git a/xen/arch/riscv/include/asm/altp2m.h b/xen/arch/riscv/include/a= sm/altp2m.h new file mode 100644 index 0000000000..dc72a624f6 --- /dev/null +++ b/xen/arch/riscv/include/asm/altp2m.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Alternate p2m + * + * Copyright (c) 2014, Intel Corporation. + */ + +#ifndef __ASM_RISCV_ALTP2M_H +#define __ASM_RISCV_ALTP2M_H + +#include + +/* Alternate p2m on/off per domain */ +static inline bool altp2m_active(const struct domain *d) +{ + /* Not implemented on RISCV. */ + return false; +} + +/* Alternate p2m VCPU */ +static inline uint16_t altp2m_vcpu_idx(const struct vcpu *v) +{ + /* Not implemented on RISCV, should not be reached. */ + BUG(); + return 0; +} + +#endif /* __ASM_RISCV_ALTP2M_H */ --=20 2.41.0 From nobody Wed May 15 01:18:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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Wed, 16 Aug 2023 03:20:42 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Bob Eshleman , Alistair Francis , Connor Davis Subject: [PATCH v1 34/57] xen/riscv: introduce asm/delay.h Date: Wed, 16 Aug 2023 13:19:46 +0300 Message-ID: <02c9ae872feb85cf3d384f0504c6af7040f97c7e.1692181079.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1692181922860100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: Oleksii Kurochko --- xen/arch/riscv/include/asm/delay.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 xen/arch/riscv/include/asm/delay.h diff --git a/xen/arch/riscv/include/asm/delay.h b/xen/arch/riscv/include/as= m/delay.h new file mode 100644 index 0000000000..40370e381a --- /dev/null +++ b/xen/arch/riscv/include/asm/delay.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2009 Chen Liqin + * Copyright (C) 2016 Regents of the University of California + */ + +#ifndef _ASM_RISCV_DELAY_H +#define _ASM_RISCV_DELAY_H + +#include + +static inline void udelay(unsigned long usecs) +{ + BUG(); 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Wed, 16 Aug 2023 03:20:43 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Bob Eshleman , Alistair Francis , Connor Davis Subject: [PATCH v1 35/57] xen/riscv: introduce asm/domain.h Date: Wed, 16 Aug 2023 13:19:47 +0300 Message-ID: X-Mailer: git-send-email 2.41.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1692181830308100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Oleksii Kurochko --- xen/arch/riscv/include/asm/domain.h | 43 +++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) create mode 100644 xen/arch/riscv/include/asm/domain.h diff --git a/xen/arch/riscv/include/asm/domain.h b/xen/arch/riscv/include/a= sm/domain.h new file mode 100644 index 0000000000..680c357d4d --- /dev/null +++ b/xen/arch/riscv/include/asm/domain.h @@ -0,0 +1,43 @@ +#ifndef __ASM_RISCV_DOMAIN_H__ +#define __ASM_RISCV_DOMAIN_H__ + +#include +#include + +struct hvm_domain +{ + uint64_t params[HVM_NR_PARAMS]; +}; + +#define is_domain_direct_mapped(d) ((void)(d), 0) + +struct arch_vcpu_io { +}; + +struct arch_vcpu { +}; + +struct arch_domain { + struct hvm_domain hvm; +}; + +#include + +static inline struct vcpu_guest_context *alloc_vcpu_guest_context(void) +{ + return xmalloc(struct vcpu_guest_context); +} + +static inline void free_vcpu_guest_context(struct vcpu_guest_context *vgc) +{ + xfree(vgc); +} + +struct guest_memory_policy {}; +static inline void update_guest_memory_policy(struct vcpu *v, + struct guest_memory_policy *= gmp) +{} + +static inline void arch_vcpu_block(struct vcpu *v) {} + +#endif /* __ASM_RISCV_DOMAIN_H__ */ \ No newline at end of file --=20 2.41.0 From nobody Wed May 15 01:18:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; 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Wed, 16 Aug 2023 03:20:44 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Bob Eshleman , Alistair Francis , Connor Davis Subject: [PATCH v1 36/57] xen/riscv: introduce asm/guest_access.h Date: Wed, 16 Aug 2023 13:19:48 +0300 Message-ID: X-Mailer: git-send-email 2.41.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1692181884406100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: Oleksii Kurochko --- xen/arch/riscv/include/asm/guest_access.h | 29 +++++++++++++++++++++++ 1 file changed, 29 insertions(+) create mode 100644 xen/arch/riscv/include/asm/guest_access.h diff --git a/xen/arch/riscv/include/asm/guest_access.h b/xen/arch/riscv/inc= lude/asm/guest_access.h new file mode 100644 index 0000000000..7be5c4509d --- /dev/null +++ b/xen/arch/riscv/include/asm/guest_access.h @@ -0,0 +1,29 @@ +#ifndef __ASM_RISCV_GUEST_ACCESS_H__ +#define __ASM_RISCV_GUEST_ACCESS_H__ + +#include + +unsigned long raw_copy_to_guest(void *to, const void *from, unsigned len); +unsigned long raw_copy_from_guest(void *to, const void *from, unsigned len= ); + +#define __raw_copy_to_guest raw_copy_to_guest +#define __raw_copy_from_guest raw_copy_from_guest + +#define guest_handle_okay(hnd, nr) (1) +#define guest_handle_subrange_okay(hnd, first, last) (1) + +struct domain; +unsigned long copy_to_guest_phys(struct domain *d, + paddr_t gpa, + void *buf, + unsigned int len); + +#endif /* __ASM_RISCV_GUEST_ACCESS_H__ */ +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ --=20 2.41.0 From nobody Wed May 15 01:18:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; 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Wed, 16 Aug 2023 03:20:45 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Bob Eshleman , Alistair Francis , Connor Davis Subject: [PATCH v1 37/57] xen/riscv: introduce asm/irq.h Date: Wed, 16 Aug 2023 13:19:49 +0300 Message-ID: <9c083a58f7371c1c8da92556ab5ae7f47e650b3d.1692181079.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1692182008849100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Oleksii Kurochko --- xen/arch/riscv/include/asm/irq.h | 34 ++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 xen/arch/riscv/include/asm/irq.h diff --git a/xen/arch/riscv/include/asm/irq.h b/xen/arch/riscv/include/asm/= irq.h new file mode 100644 index 0000000000..7b08785f3f --- /dev/null +++ b/xen/arch/riscv/include/asm/irq.h @@ -0,0 +1,34 @@ +#ifndef __ASM_RISCV_IRQ_H__ +#define __ASM_RISCV_IRQ_H__ + +#include +#include +#include + +/* TODO */ +#define nr_irqs 0U +#define nr_static_irqs 0 +#define arch_hwdom_irqs(domid) 0U + +#define domain_pirq_to_irq(d, pirq) (pirq) + +#define arch_evtchn_bind_pirq(d, pirq) ((void)((d) + (pirq))) + +struct arch_pirq { +}; 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charset="utf-8" Signed-off-by: Oleksii Kurochko --- xen/arch/riscv/include/asm/monitor.h | 53 ++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) create mode 100644 xen/arch/riscv/include/asm/monitor.h diff --git a/xen/arch/riscv/include/asm/monitor.h b/xen/arch/riscv/include/= asm/monitor.h new file mode 100644 index 0000000000..fb7ef6639d --- /dev/null +++ b/xen/arch/riscv/include/asm/monitor.h @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * include/asm-RISCV/monitor.h + * + * Arch-specific monitor_op domctl handler. + * + * Copyright (c) 2015 Tamas K Lengyel (tamas@tklengyel.com) + * Copyright (c) 2016, Bitdefender S.R.L. + * + */ + +#ifndef __ASM_RISCV_MONITOR_H__ +#define __ASM_RISCV_MONITOR_H__ + +#include +#include + +static inline +void arch_monitor_allow_userspace(struct domain *d, bool allow_userspace) +{ +} + +static inline +int arch_monitor_domctl_op(struct domain *d, struct xen_domctl_monitor_op = *mop) +{ + /* No arch-specific monitor ops on RISCV. */ + return -EOPNOTSUPP; +} + +int arch_monitor_domctl_event(struct domain *d, + struct xen_domctl_monitor_op *mop); + +static inline +int arch_monitor_init_domain(struct domain *d) +{ + /* No arch-specific domain initialization on RISCV. */ + return 0; +} + +static inline +void arch_monitor_cleanup_domain(struct domain *d) +{ + /* No arch-specific domain cleanup on RISCV. */ +} + +static inline uint32_t arch_monitor_get_capabilities(struct domain *d) +{ + uint32_t capabilities =3D 0; + + return capabilities; +} + +#endif /* __ASM_RISCV_MONITOR_H__ */ --=20 2.41.0 From nobody Wed May 15 01:18:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; 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Wed, 16 Aug 2023 03:20:46 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Bob Eshleman , Alistair Francis , Connor Davis Subject: [PATCH v1 39/57] xen/riscv: introduce asm/numa.h Date: Wed, 16 Aug 2023 13:19:51 +0300 Message-ID: X-Mailer: git-send-email 2.41.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1692181971224100007 Content-Type: text/plain; charset="utf-8" Signed-off-by: Oleksii Kurochko --- xen/arch/riscv/include/asm/numa.h | 38 +++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100644 xen/arch/riscv/include/asm/numa.h diff --git a/xen/arch/riscv/include/asm/numa.h b/xen/arch/riscv/include/asm= /numa.h new file mode 100644 index 0000000000..0cfeeed38a --- /dev/null +++ b/xen/arch/riscv/include/asm/numa.h @@ -0,0 +1,38 @@ +#ifndef __ARCH_RISCV_NUMA_H +#define __ARCH_RISCV_NUMA_H + +#include + +typedef u8 nodeid_t; + +/* Fake one node for now. See also node_online_map. */ +#define cpu_to_node(cpu) 0 +#define node_to_cpumask(node) (cpu_online_map) + +/* + * TODO: make first_valid_mfn static when NUMA is supported on RISCV, this + * is required because the dummy helpers are using it. + */ +extern mfn_t first_valid_mfn; + +/* XXX: implement NUMA support */ +#define node_spanned_pages(nid) (max_page - mfn_x(first_valid_mfn)) +#define node_start_pfn(nid) (mfn_x(first_valid_mfn)) +#define __node_distance(a, b) (20) + +static inline unsigned int arch_get_dma_bitsize(void) +{ + return 32; +} + +#define arch_want_default_dmazone() (false) + +#endif /* __ARCH_RISCV_NUMA_H */ +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ --=20 2.41.0 From nobody Wed May 15 01:18:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; 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Wed, 16 Aug 2023 03:20:47 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Bob Eshleman , Alistair Francis , Connor Davis Subject: [PATCH v1 40/57] xen/riscv: introduce asm/p2m.h Date: Wed, 16 Aug 2023 13:19:52 +0300 Message-ID: <7c1a1083ac3577c26071de14459f7a3ba7316a27.1692181079.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1692181869577100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: Oleksii Kurochko --- xen/arch/riscv/include/asm/p2m.h | 105 +++++++++++++++++++++++++++++++ 1 file changed, 105 insertions(+) create mode 100644 xen/arch/riscv/include/asm/p2m.h diff --git a/xen/arch/riscv/include/asm/p2m.h b/xen/arch/riscv/include/asm/= p2m.h new file mode 100644 index 0000000000..993aec6d2c --- /dev/null +++ b/xen/arch/riscv/include/asm/p2m.h @@ -0,0 +1,105 @@ +#ifndef __ASM_RISCV_P2M_H__ +#define __ASM_RISCV_P2M_H__ + +#include + +#define paddr_bits PADDR_BITS + +/* + * List of possible type for each page in the p2m entry. + * The number of available bit per page in the pte for this purpose is 4 b= its. + * So it's possible to only have 16 fields. If we run out of value in the + * future, it's possible to use higher value for pseudo-type and don't sto= re + * them in the p2m entry. + */ +typedef enum { + p2m_invalid =3D 0, /* Nothing mapped here */ + p2m_ram_rw, /* Normal read/write guest RAM */ + p2m_ram_ro, /* Read-only; writes are silently dropped */ + p2m_mmio_direct_dev,/* Read/write mapping of genuine Device MMIO area = */ + p2m_mmio_direct_nc, /* Read/write mapping of genuine MMIO area non-cac= heable */ + p2m_mmio_direct_c, /* Read/write mapping of genuine MMIO area cacheab= le */ + p2m_map_foreign_rw, /* Read/write RAM pages from foreign domain */ + p2m_map_foreign_ro, /* Read-only RAM pages from foreign domain */ + p2m_grant_map_rw, /* Read/write grant mapping */ + p2m_grant_map_ro, /* Read-only grant mapping */ + /* The types below are only used to decide the page attribute in the P= 2M */ + p2m_iommu_map_rw, /* Read/write iommu mapping */ + p2m_iommu_map_ro, /* Read-only iommu mapping */ + p2m_max_real_type, /* Types after this won't be store in the p2m */ +} p2m_type_t; + +#include + +static inline int get_page_and_type(struct page_info *page, + struct domain *domain, + unsigned long type) +{ + BUG(); + return 1; +} + +/* Look up a GFN and take a reference count on the backing page. */ +typedef unsigned int p2m_query_t; +#define P2M_ALLOC (1u<<0) /* Populate PoD and paged-out entries */ +#define P2M_UNSHARE (1u<<1) /* Break CoW sharing */ + +static inline struct page_info *get_page_from_gfn( + struct domain *d, unsigned long gfn, p2m_type_t *t, p2m_query_t q) +{ + BUG(); + return NULL; +} + +static inline void memory_type_changed(struct domain *d) +{ + BUG(); +} + + +static inline int guest_physmap_mark_populate_on_demand(struct domain *d, = unsigned long gfn, + unsigned int order) +{ + BUG(); + return 1; +} + +static inline int guest_physmap_add_entry(struct domain *d, + gfn_t gfn, + mfn_t mfn, + unsigned long page_order, + p2m_type_t t) +{ + BUG(); + return 1; +} + +/* Untyped version for RAM only, for compatibility */ +static inline int __must_check +guest_physmap_add_page(struct domain *d, gfn_t gfn, mfn_t mfn, + unsigned int page_order) +{ + return guest_physmap_add_entry(d, gfn, mfn, page_order, p2m_ram_rw); +} + +static inline mfn_t gfn_to_mfn(struct domain *d, gfn_t gfn) +{ + BUG(); + return _mfn(0); +} + +static inline bool arch_acquire_resource_check(struct domain *d) +{ + /* + * The reference counting of foreign entries in set_foreign_p2m_entry() + * is supported on RISCV. + */ + return true; +} + +static inline void p2m_altp2m_check(struct vcpu *v, uint16_t idx) +{ + /* Not supported on RISCV. */ +} + +#endif /* __ASM_RISCV_P2M_H__ */ \ No newline at end of file --=20 2.41.0 From nobody Wed May 15 01:18:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; 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Wed, 16 Aug 2023 03:20:48 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Bob Eshleman , Alistair Francis , Connor Davis Subject: [PATCH v1 41/57] xen/riscv: introduce asm/regs.h Date: Wed, 16 Aug 2023 13:19:53 +0300 Message-ID: X-Mailer: git-send-email 2.41.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1692181880353100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Oleksii Kurochko --- xen/arch/riscv/include/asm/regs.h | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) create mode 100644 xen/arch/riscv/include/asm/regs.h diff --git a/xen/arch/riscv/include/asm/regs.h b/xen/arch/riscv/include/asm= /regs.h new file mode 100644 index 0000000000..33ae759a3e --- /dev/null +++ b/xen/arch/riscv/include/asm/regs.h @@ -0,0 +1,27 @@ +#ifndef __ARM_RISCV_REGS_H__ +#define __ARM_RISCV_REGS_H__ + +#ifndef __ASSEMBLY__ + +#include +#include + +#define hyp_mode(r) (0) + +static inline bool guest_mode(const struct cpu_user_regs *r) +{ + BUG(); +} + +#endif + + +#endif /* __ARM_RISCV_REGS_H__ */ +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ --=20 2.41.0 From nobody Wed May 15 01:18:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1692181976; cv=none; d=zohomail.com; s=zohoarc; b=Lv6sFf1moj4392mQZw7xjHNAW8pUavaebQvjIr5fnqxhhVc5aVfpmSilGTsQeIvb16uVaiLDeIbb8ojlmjDoUO7pWRJKFaSKJryN+xFvf/KwAPI/pn29JnwtpT2A8F89i66wQ07k9t65bGxAGIJawDoY8gsMEprgehvD/Xk+u5k= ARC-Message-Signature: i=1; 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charset="utf-8" Signed-off-by: Oleksii Kurochko --- xen/arch/riscv/include/asm/softirq.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) create mode 100644 xen/arch/riscv/include/asm/softirq.h diff --git a/xen/arch/riscv/include/asm/softirq.h b/xen/arch/riscv/include/= asm/softirq.h new file mode 100644 index 0000000000..8364aa2810 --- /dev/null +++ b/xen/arch/riscv/include/asm/softirq.h @@ -0,0 +1,16 @@ +#ifndef __ASM_RISCV_SOFTIRQ_H__ +#define __ASM_RISCV_SOFTIRQ_H__ + +#define NR_ARCH_SOFTIRQS 0 + +#define arch_skip_send_event_check(cpu) 0 + +#endif /* __ASM_RISCV_SOFTIRQ_H__ */ +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ --=20 2.41.0 From nobody Wed May 15 01:18:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; 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Wed, 16 Aug 2023 03:20:50 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Bob Eshleman , Alistair Francis , Connor Davis Subject: [PATCH v1 43/57] xen/riscv: introduce asm/time.h Date: Wed, 16 Aug 2023 13:19:56 +0300 Message-ID: <0b92dfba18dd8de27e2e65ab072c491ffd17cb5d.1692181079.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1692181955879100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: Oleksii Kurochko --- xen/arch/riscv/include/asm/time.h | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) create mode 100644 xen/arch/riscv/include/asm/time.h diff --git a/xen/arch/riscv/include/asm/time.h b/xen/arch/riscv/include/asm= /time.h new file mode 100644 index 0000000000..d0571cdf32 --- /dev/null +++ b/xen/arch/riscv/include/asm/time.h @@ -0,0 +1,20 @@ +#ifndef __ASM_RISCV_TIME_H__ +#define __ASM_RISCV_TIME_H__ + +#include +#include +#include + +struct vcpu; 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charset="utf-8" Signed-off-by: Oleksii Kurochko --- xen/arch/riscv/include/asm/vm_event.h | 52 +++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) create mode 100644 xen/arch/riscv/include/asm/vm_event.h diff --git a/xen/arch/riscv/include/asm/vm_event.h b/xen/arch/riscv/include= /asm/vm_event.h new file mode 100644 index 0000000000..4cae80840a --- /dev/null +++ b/xen/arch/riscv/include/asm/vm_event.h @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * vm_event.h: architecture specific vm_event handling routines + * + * Copyright (c) 2015 Tamas K Lengyel (tamas@tklengyel.com) + */ + +#ifndef __ASM_RISCV_VM_EVENT_H__ +#define __ASM_RISCV_VM_EVENT_H__ + +#include +#include +#include + +static inline int vm_event_init_domain(struct domain *d) +{ + /* Nothing to do. */ + return 0; +} + +static inline void vm_event_cleanup_domain(struct domain *d) +{ + memset(&d->monitor, 0, sizeof(d->monitor)); +} + +static inline void vm_event_toggle_singlestep(struct domain *d, struct vcp= u *v, + vm_event_response_t *rsp) +{ + /* Not supported on RISCV. */ +} + +static inline +void vm_event_register_write_resume(struct vcpu *v, vm_event_response_t *r= sp) +{ + /* Not supported on RISCV. */ +} + +static inline +void vm_event_emulate_check(struct vcpu *v, vm_event_response_t *rsp) +{ + /* Not supported on RISCV. */ +} + +static inline +void vm_event_sync_event(struct vcpu *v, bool value) +{ + /* Not supported on RISCV. */ +} + +void vm_event_reset_vmtrace(struct vcpu *v); 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Wed, 16 Aug 2023 03:20:52 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Bob Eshleman , Alistair Francis , Connor Davis Subject: [PATCH v1 45/57] xen/riscv: add definition of __read_mostly Date: Wed, 16 Aug 2023 13:19:58 +0300 Message-ID: X-Mailer: git-send-email 2.41.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1692181985324100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Oleksii Kurochko --- xen/arch/riscv/include/asm/cache.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/xen/arch/riscv/include/asm/cache.h b/xen/arch/riscv/include/as= m/cache.h index 69573eb051..94bd94db53 100644 --- a/xen/arch/riscv/include/asm/cache.h +++ b/xen/arch/riscv/include/asm/cache.h @@ -3,4 +3,6 @@ #ifndef _ASM_RISCV_CACHE_H #define _ASM_RISCV_CACHE_H =20 +#define __read_mostly __section(".data.read_mostly") + #endif /* _ASM_RISCV_CACHE_H */ --=20 2.41.0 From nobody Wed May 15 01:18:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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Wed, 16 Aug 2023 03:20:52 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Bob Eshleman , Alistair Francis , Connor Davis Subject: [PATCH v1 46/57] xen/riscv: define an address of frame table Date: Wed, 16 Aug 2023 13:19:59 +0300 Message-ID: <8d3a615afbcff9681aa0ba8e2272d7e7e26251d1.1692181079.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1692181975245100001 Content-Type: text/plain; charset="utf-8" Also the patchs adds some helpful macros. Signed-off-by: Oleksii Kurochko --- xen/arch/riscv/include/asm/config.h | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/xen/arch/riscv/include/asm/config.h b/xen/arch/riscv/include/a= sm/config.h index fa90ae0898..63ddcae1f9 100644 --- a/xen/arch/riscv/include/asm/config.h +++ b/xen/arch/riscv/include/asm/config.h @@ -77,12 +77,31 @@ name: #endif =20 +#define VPN_BITS (9) +#define OFFSET_BITS (12) + #ifdef CONFIG_RISCV_64 + +#define SLOTN_ENTRY_BITS (HYP_PT_ROOT_LEVEL * VPN_BITS + OFFSET_BIT= S) +#define SLOTN(slot) (_AT(vaddr_t,slot) << SLOTN_ENTRY_BITS) +#define SLOTN_ENTRY_SIZE SLOTN(1) + #define XEN_VIRT_START 0xFFFFFFFFC0000000 /* (_AC(-1, UL) + 1 - GB(1)) */ + +#define FRAMETABLE_VIRT_START SLOTN(196) +#define FRAMETABLE_SIZE GB(3) +#define FRAMETABLE_NR (FRAMETABLE_SIZE / sizeof(*frame_table)) +#define FRAMETABLE_VIRT_END (FRAMETABLE_VIRT_START + FRAMETABLE_SIZE -= 1) + +#define VMAP_VIRT_START SLOTN(194) +#define VMAP_VIRT_SIZE GB(1) + #else #error "RV32 isn't supported" #endif =20 +#define HYPERVISOR_VIRT_START XEN_VIRT_START + #define SMP_CACHE_BYTES (1 << 6) =20 #define STACK_SIZE PAGE_SIZE @@ -95,6 +114,8 @@ #define RV_STAGE1_MODE SATP_MODE_SV32 #endif =20 +#define HYP_PT_ROOT_LEVEL (CONFIG_PAGING_LEVELS - 1) + #endif /* __RISCV_CONFIG_H__ */ /* * Local variables: --=20 2.41.0 From nobody Wed May 15 01:18:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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Wed, 16 Aug 2023 03:20:53 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Bob Eshleman , Alistair Francis , Connor Davis Subject: [PATCH v1 47/57] xen/riscv: add required things to asm/current.h Date: Wed, 16 Aug 2023 13:20:00 +0300 Message-ID: X-Mailer: git-send-email 2.41.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1692181886611100001 Content-Type: text/plain; charset="utf-8" Add minimal requied things to be able to build full Xen. Signed-off-by: Oleksii Kurochko --- xen/arch/riscv/include/asm/current.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/xen/arch/riscv/include/asm/current.h b/xen/arch/riscv/include/= asm/current.h index d84f15dc50..d03d172f14 100644 --- a/xen/arch/riscv/include/asm/current.h +++ b/xen/arch/riscv/include/asm/current.h @@ -3,6 +3,21 @@ #ifndef __ASM_CURRENT_H #define __ASM_CURRENT_H =20 +#include + +#ifndef __ASSEMBLY__ + +struct vcpu; + +/* Which VCPU is "current" on this PCPU. */ +DECLARE_PER_CPU(struct vcpu *, curr_vcpu); + +#define current (this_cpu(curr_vcpu)) +#define set_current(vcpu) do { current =3D (vcpu); } while (0) +#define get_cpu_current(cpu) (per_cpu(curr_vcpu, cpu)) + +#define guest_cpu_user_regs() (0) + #define switch_stack_and_jump(stack, fn) do { \ asm volatile ( \ "mv sp, %0\n" \ @@ -10,4 +25,6 @@ unreachable(); \ } while ( false ) =20 +#endif /* __ASSEMBLY__ */ + #endif /* __ASM_CURRENT_H */ --=20 2.41.0 From nobody Wed May 15 01:18:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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Wed, 16 Aug 2023 03:20:54 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Bob Eshleman , Alistair Francis , Connor Davis Subject: [PATCH v1 48/57] xen/riscv: add minimal stuff to asm/page.h to build full Xen Date: Wed, 16 Aug 2023 13:20:01 +0300 Message-ID: <6337d25f0df323dc26c747ce8d07b77ccee07f2f.1692181079.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1692181850474100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Oleksii Kurochko --- xen/arch/riscv/include/asm/page.h | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/xen/arch/riscv/include/asm/page.h b/xen/arch/riscv/include/asm= /page.h index 95074e29b3..abbae75aaf 100644 --- a/xen/arch/riscv/include/asm/page.h +++ b/xen/arch/riscv/include/asm/page.h @@ -6,6 +6,7 @@ #ifndef __ASSEMBLY__ =20 #include +#include #include =20 #include @@ -32,6 +33,9 @@ #define PTE_LEAF_DEFAULT (PTE_VALID | PTE_READABLE | PTE_WRITAB= LE) #define PTE_TABLE (PTE_VALID) =20 +/* TODO */ +#define PAGE_HYPERVISOR 0 + /* Calculate the offsets into the pagetables for a given VA */ #define pt_linear_offset(lvl, va) ((va) >> XEN_PT_LEVEL_SHIFT(lvl)) =20 @@ -46,6 +50,9 @@ typedef struct { #endif } pte_t; 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Wed, 16 Aug 2023 03:20:55 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Bob Eshleman , Alistair Francis , Connor Davis Subject: [PATCH v1 49/57] xen/riscv: add minimal stuff to asm/processor.h to build full Xen Date: Wed, 16 Aug 2023 13:20:02 +0300 Message-ID: <49fc04992808963a17321e4f34b8310a4b3077fb.1692181079.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1692181889428100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Oleksii Kurochko --- xen/arch/riscv/include/asm/processor.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/xen/arch/riscv/include/asm/processor.h b/xen/arch/riscv/includ= e/asm/processor.h index 6db681d805..b6218a00a7 100644 --- a/xen/arch/riscv/include/asm/processor.h +++ b/xen/arch/riscv/include/asm/processor.h @@ -12,6 +12,9 @@ =20 #ifndef __ASSEMBLY__ =20 +/* TODO: need to be implemeted */ +#define get_processor_id() 0 + /* On stack VCPU state */ struct cpu_user_regs { @@ -53,6 +56,18 @@ struct cpu_user_regs unsigned long pregs; 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Wed, 16 Aug 2023 03:20:56 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Bob Eshleman , Alistair Francis , Connor Davis Subject: [PATCH v1 50/57] xen/riscv: add minimal stuff to asm/smp.h to build full Xen Date: Wed, 16 Aug 2023 13:20:03 +0300 Message-ID: <5df4e523937312bd6240acf0be9ad29273545fc6.1692181079.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1692181882436100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Oleksii Kurochko --- xen/arch/riscv/include/asm/smp.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/xen/arch/riscv/include/asm/smp.h b/xen/arch/riscv/include/asm/= smp.h index cc8dd18254..a7b4f94ce4 100644 --- a/xen/arch/riscv/include/asm/smp.h +++ b/xen/arch/riscv/include/asm/smp.h @@ -17,4 +17,7 @@ DECLARE_PER_CPU(cpumask_var_t, cpu_core_mask); */ #define park_offline_cpus false =20 +/* TODO: need to be implemeted */ +#define smp_processor_id() (0) + #endif \ No newline at end of file --=20 2.41.0 From nobody Wed May 15 01:18:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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Wed, 16 Aug 2023 03:20:56 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Andrew Cooper , George Dunlap , Jan Beulich , Julien Grall , Stefano Stabellini , Wei Liu Subject: [PATCH v1 51/57] xen: add RISCV support for pmu.h Date: Wed, 16 Aug 2023 13:20:04 +0300 Message-ID: <2506a46733cf4a7dc1d021b83437165d61921563.1692181079.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1692181912743100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Oleksii Kurochko --- xen/include/public/pmu.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/xen/include/public/pmu.h b/xen/include/public/pmu.h index eb87a81e7b..801912900b 100644 --- a/xen/include/public/pmu.h +++ b/xen/include/public/pmu.h @@ -11,6 +11,8 @@ #include "arch-x86/pmu.h" #elif defined (__arm__) || defined (__aarch64__) #include "arch-arm.h" +#elif defined(__riscv) +#include "arch-riscv.h" #else #error "Unsupported architecture" #endif --=20 2.41.0 From nobody Wed May 15 01:18:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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Wed, 16 Aug 2023 03:20:58 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Andrew Cooper , George Dunlap , Jan Beulich , Julien Grall , Stefano Stabellini , Wei Liu , Paul Durrant , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Subject: [PATCH v1 52/57] xen: add necessary headers to common to build full Xen for RISC-V Date: Wed, 16 Aug 2023 13:20:05 +0300 Message-ID: <8a0ba03485f42ad3fdfaaaa8eb06caf63f4205ec.1692181079.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1692181834468100001 Content-Type: text/plain; charset="utf-8" Mostly patch was taken from the PPC patch series so can be skipped during review: https://lore.kernel.org/xen-devel/2c9eb4fc175a1bdd21293f2e2611d8e21991636d.= 1691016993.git.sanastasio@raptorengineering.com/#Z31xen:common:symbols.c Signed-off-by: Oleksii Kurochko --- xen/common/memory.c | 1 + xen/common/symbols.c | 1 + xen/include/xen/domain.h | 1 + xen/include/xen/iommu.h | 1 + xen/include/xen/sched.h | 1 + 5 files changed, 5 insertions(+) diff --git a/xen/common/memory.c b/xen/common/memory.c index b1dcbaf551..fa165ebc14 100644 --- a/xen/common/memory.c +++ b/xen/common/memory.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include =20 diff --git a/xen/common/symbols.c b/xen/common/symbols.c index 9377f41424..691e617925 100644 --- a/xen/common/symbols.c +++ b/xen/common/symbols.c @@ -19,6 +19,7 @@ #include #include #include +#include =20 #ifdef SYMBOLS_ORIGIN extern const unsigned int symbols_offsets[]; diff --git a/xen/include/xen/domain.h b/xen/include/xen/domain.h index d35af34841..767127b440 100644 --- a/xen/include/xen/domain.h +++ b/xen/include/xen/domain.h @@ -4,6 +4,7 @@ =20 #include =20 +#include #include #include #include diff --git a/xen/include/xen/iommu.h b/xen/include/xen/iommu.h index 110693c59f..7368df9138 100644 --- a/xen/include/xen/iommu.h +++ b/xen/include/xen/iommu.h @@ -24,6 +24,7 @@ #include #include #include +#include #include #include #include diff --git a/xen/include/xen/sched.h b/xen/include/xen/sched.h index b4f43cd410..d8c8dd85a6 100644 --- a/xen/include/xen/sched.h +++ b/xen/include/xen/sched.h @@ -21,6 +21,7 @@ #include #include #include +#include #include #include #include --=20 2.41.0 From nobody Wed May 15 01:18:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; 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Wed, 16 Aug 2023 03:20:58 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Bob Eshleman , Alistair Francis , Connor Davis Subject: [PATCH v1 53/57] xen/riscv: add minimal stuff to asm/mm.h to build full Xen Date: Wed, 16 Aug 2023 13:20:06 +0300 Message-ID: <8d1ccfe520eb4ddcbeef677df3859bd0ed145419.1692181079.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1692181970606100005 Content-Type: text/plain; charset="utf-8" Signed-off-by: Oleksii Kurochko --- xen/arch/riscv/include/asm/mm.h | 265 +++++++++++++++++++++++++++++++- 1 file changed, 263 insertions(+), 2 deletions(-) diff --git a/xen/arch/riscv/include/asm/mm.h b/xen/arch/riscv/include/asm/m= m.h index 5e3ac5cde3..1d464afec9 100644 --- a/xen/arch/riscv/include/asm/mm.h +++ b/xen/arch/riscv/include/asm/mm.h @@ -3,10 +3,271 @@ #ifndef _ASM_RISCV_MM_H #define _ASM_RISCV_MM_H =20 +#include +#include +#include + +#include #include =20 -#define pfn_to_paddr(pfn) ((paddr_t)(pfn) << PAGE_SHIFT) -#define paddr_to_pfn(pa) ((unsigned long)((pa) >> PAGE_SHIFT)) +#define paddr_to_pdx(pa) mfn_to_pdx(maddr_to_mfn(pa)) +#define gfn_to_gaddr(gfn) pfn_to_paddr(gfn_x(gfn)) +#define gaddr_to_gfn(ga) _gfn(paddr_to_pfn(ga)) +#define mfn_to_maddr(mfn) pfn_to_paddr(mfn_x(mfn)) +#define maddr_to_mfn(ma) _mfn(paddr_to_pfn(ma)) +#define vmap_to_mfn(va) maddr_to_mfn(virt_to_maddr((vaddr_t)va)) +#define vmap_to_page(va) mfn_to_page(vmap_to_mfn(va)) +#define paddr_to_pdx(pa) mfn_to_pdx(maddr_to_mfn(pa)) +#define gfn_to_gaddr(gfn) pfn_to_paddr(gfn_x(gfn)) +#define gaddr_to_gfn(ga) _gfn(paddr_to_pfn(ga)) +#define mfn_to_maddr(mfn) pfn_to_paddr(mfn_x(mfn)) +#define maddr_to_mfn(ma) _mfn(paddr_to_pfn(ma)) +#define vmap_to_mfn(va) maddr_to_mfn(virt_to_maddr((vaddr_t)va)) +#define vmap_to_page(va) mfn_to_page(vmap_to_mfn(va)) + +#define virt_to_maddr(va) ((paddr_t)((vaddr_t)(va) & PADDR_MASK)) +#define maddr_to_virt(pa) ((void *)((paddr_t)(pa) | XEN_VIRT_START)) + +/* Convert between Xen-heap virtual addresses and machine frame numbers. */ +#define __virt_to_mfn(va) (virt_to_maddr(va) >> PAGE_SHIFT) +#define __mfn_to_virt(mfn) (maddr_to_virt((paddr_t)(mfn) << PAGE_SHIFT)) + +/* Convert between Xen-heap virtual addresses and page-info structures. */ +static inline struct page_info *virt_to_page(const void *v) +{ + BUG(); + return NULL; +} + +/* + * We define non-underscored wrappers for above conversion functions. + * These are overriden in various source files while underscored version + * remain intact. + */ +#define virt_to_mfn(va) __virt_to_mfn(va) +#define mfn_to_virt(mfn) __mfn_to_virt(mfn) + +struct page_info +{ + /* Each frame can be threaded onto a doubly-linked list. */ + struct page_list_entry list; + + /* Reference count and various PGC_xxx flags and fields. */ + unsigned long count_info; + + /* Context-dependent fields follow... */ + union { + /* Page is in use: ((count_info & PGC_count_mask) !=3D 0). */ + struct { + /* Type reference count and various PGT_xxx flags and fields. = */ + unsigned long type_info; + } inuse; + /* Page is on a free list: ((count_info & PGC_count_mask) =3D=3D 0= ). */ + union { + struct { + /* + * Index of the first *possibly* unscrubbed page in the bu= ddy. + * One more bit than maximum possible order to accommodate + * INVALID_DIRTY_IDX. + */ +#define INVALID_DIRTY_IDX ((1UL << (MAX_ORDER + 1)) - 1) + unsigned long first_dirty:MAX_ORDER + 1; + + /* Do TLBs need flushing for safety before next page use? = */ + bool need_tlbflush:1; + +#define BUDDY_NOT_SCRUBBING 0 +#define BUDDY_SCRUBBING 1 +#define BUDDY_SCRUB_ABORT 2 + unsigned long scrub_state:2; + }; + + unsigned long val; + } free; + + } u; + + union { + /* Page is in use, but not as a shadow. */ + struct { + /* Owner of this page (zero if page is anonymous). */ + struct domain *domain; + } inuse; + + /* Page is on a free list. */ + struct { + /* Order-size of the free chunk this page is the head of. */ + unsigned int order; + } free; + + } v; + + union { + /* + * Timestamp from 'TLB clock', used to avoid extra safety flushes. + * Only valid for: a) free pages, and b) pages with zero type count + */ + u32 tlbflush_timestamp; + }; + u64 pad; +}; + +#define frame_table ((struct page_info *)FRAMETABLE_VIRT_START) + +/* PDX of the first page in the frame table. */ +extern unsigned long frametable_base_pdx; + +/* Convert between machine frame numbers and page-info structures. */ +#define mfn_to_page(mfn) \ + (frame_table + (mfn_to_pdx(mfn) - frametable_base_pdx)) +#define page_to_mfn(pg) \ + pdx_to_mfn((unsigned long)((pg) - frame_table) + frametable_base_pdx) + +static inline void *page_to_virt(const struct page_info *pg) +{ + return mfn_to_virt(mfn_x(page_to_mfn(pg))); +} + +/* + * Common code requires get_page_type and put_page_type. + * We don't care about typecounts so we just do the minimum to make it + * happy. + */ +static inline int get_page_type(struct page_info *page, unsigned long type) +{ + return 1; +} + +static inline void put_page_type(struct page_info *page) +{ + return; +} + +/* TODO */ +static inline bool get_page_nr(struct page_info *page, const struct domain= *domain, + unsigned long nr) +{ + BUG(); +} +static inline void put_page_nr(struct page_info *page, unsigned long nr) +{ + BUG(); +} + +static inline void put_page_and_type(struct page_info *page) +{ + put_page_type(page); + put_page(page); +} + +/* + * RISCV does not have an M2P, but common code expects a handful of + * M2P-related defines and functions. Provide dummy versions of these. + */ +#define INVALID_M2P_ENTRY (~0UL) +#define SHARED_M2P_ENTRY (~0UL - 1UL) +#define SHARED_M2P(_e) ((_e) =3D=3D SHARED_M2P_ENTRY) + +/* Xen always owns P2M on PPC */ +#define set_gpfn_from_mfn(mfn, pfn) do { (void) (mfn), (void)(pfn); } whil= e (0) +#define mfn_to_gfn(d, mfn) ((void)(d), _gfn(mfn_x(mfn))) + +#define PDX_GROUP_SHIFT (16 + 5) + +static inline unsigned long domain_get_maximum_gpfn(struct domain *d) +{ + BUG(); + return 0; +} + +static inline long arch_memory_op(int op, XEN_GUEST_HANDLE_PARAM(void) arg) +{ + BUG(); + return 0; +} + +/* + * On RISCV, all the RAM is currently direct mapped in Xen. + * Hence return always true. + */ +static inline bool arch_mfns_in_directmap(unsigned long mfn, unsigned long= nr) +{ + return true; +} + +#define PG_shift(idx) (BITS_PER_LONG - (idx)) +#define PG_mask(x, idx) (x ## UL << PG_shift(idx)) + +#define PGT_none PG_mask(0, 1) /* no special uses of this page = */ +#define PGT_writable_page PG_mask(1, 1) /* has writable mappings? = */ +#define PGT_type_mask PG_mask(1, 1) /* Bits 31 or 63. = */ + + /* Count of uses of this frame as its current type. */ +#define PGT_count_width PG_shift(2) +#define PGT_count_mask ((1UL<count_info&PGC_state) =3D=3D PGC_= state_##st) + +/* Count of references to this frame. */ +#define PGC_count_width PG_shift(9) +#define PGC_count_mask ((1UL<count_info&PGC_state) =3D=3D PGC_sta= te_##st) + +#define _PGC_extra PG_shift(10) +#define PGC_extra PG_mask(1, 10) + +#define is_xen_heap_page(page) ((page)->count_info & PGC_xen_heap) +#define is_xen_heap_mfn(mfn) \ + (mfn_valid(mfn) && is_xen_heap_page(mfn_to_page(mfn))) + +#define is_xen_fixed_mfn(mfn) \ + ((mfn_to_maddr(mfn) >=3D virt_to_maddr(&_start)) && \ + (mfn_to_maddr(mfn) <=3D virt_to_maddr((vaddr_t)_end - 1))) + +#define page_get_owner(_p) (_p)->v.inuse.domain +#define page_set_owner(_p,_d) ((_p)->v.inuse.domain =3D (_d)) + +/* TODO: implement */ +#define mfn_valid(mfn) ({ (void) (mfn); 0; }) +// #define max_page (0UL) + +#define mfn_to_gfn(d, mfn) ((void)(d), _gfn(mfn_x(mfn))) + +#define domain_set_alloc_bitsize(d) ((void)0) +#define domain_clamp_alloc_bitsize(d, b) (b) + +#define PFN_ORDER(_pfn) ((_pfn)->v.free.order) =20 extern unsigned char cpu0_boot_stack[]; =20 --=20 2.41.0 From nobody Wed May 15 01:18:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1692181852; cv=none; d=zohomail.com; s=zohoarc; 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<5946097b08b3ba98a6e78e853ce6cf89b1d8abc3.1692181079.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1692181854569100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Oleksii Kurochko --- xen/arch/riscv/Kconfig | 1 + xen/arch/riscv/Makefile | 1 + xen/arch/riscv/early_printk.c | 168 ------------- xen/arch/riscv/mm.c | 52 +++- xen/arch/riscv/setup.c | 9 +- xen/arch/riscv/stubs.c | 437 ++++++++++++++++++++++++++++++++++ xen/arch/riscv/traps.c | 25 ++ 7 files changed, 523 insertions(+), 170 deletions(-) create mode 100644 xen/arch/riscv/stubs.c diff --git a/xen/arch/riscv/Kconfig b/xen/arch/riscv/Kconfig index f382b36f6c..64caaa2750 100644 --- a/xen/arch/riscv/Kconfig +++ b/xen/arch/riscv/Kconfig @@ -4,6 +4,7 @@ config RISCV config RISCV_64 def_bool y select 64BIT + select HAS_PDX =20 config ARCH_DEFCONFIG string diff --git a/xen/arch/riscv/Makefile b/xen/arch/riscv/Makefile index b08048948f..50c09469a0 100644 --- a/xen/arch/riscv/Makefile +++ b/xen/arch/riscv/Makefile @@ -5,6 +5,7 @@ obj-y +=3D mm.o obj-$(CONFIG_RISCV_64) +=3D riscv64/ obj-y +=3D sbi.o obj-y +=3D setup.o +obj-y +=3D stubs.o obj-y +=3D traps.o =20 $(TARGET): $(TARGET)-syms diff --git a/xen/arch/riscv/early_printk.c b/xen/arch/riscv/early_printk.c index 60742a042d..610c814f54 100644 --- a/xen/arch/riscv/early_printk.c +++ b/xen/arch/riscv/early_printk.c @@ -40,171 +40,3 @@ void early_printk(const char *str) str++; } } - -/* - * The following #if 1 ... #endif should be removed after printk - * and related stuff are ready. - */ -#if 1 - -#include -#include - -/** - * strlen - Find the length of a string - * @s: The string to be sized - */ -size_t (strlen)(const char * s) -{ - const char *sc; - - for (sc =3D s; *sc !=3D '\0'; ++sc) - /* nothing */; - return sc - s; -} - -/** - * memcpy - Copy one area of memory to another - * @dest: Where to copy to - * @src: Where to copy from - * @count: The size of the area. - * - * You should not use this function to access IO space, use memcpy_toio() - * or memcpy_fromio() instead. - */ -void *(memcpy)(void *dest, const void *src, size_t count) -{ - char *tmp =3D (char *) dest, *s =3D (char *) src; - - while (count--) - *tmp++ =3D *s++; - - return dest; -} - -int vsnprintf(char* str, size_t size, const char* format, va_list args) -{ - size_t i =3D 0; /* Current position in the output string */ - size_t written =3D 0; /* Total number of characters written */ - char* dest =3D str; - - while ( format[i] !=3D '\0' && written < size - 1 ) - { - if ( format[i] =3D=3D '%' ) - { - i++; - - if ( format[i] =3D=3D '\0' ) - break; - - if ( format[i] =3D=3D '%' ) - { - if ( written < size - 1 ) - { - dest[written] =3D '%'; - written++; - } - i++; - continue; - } - - /* - * Handle format specifiers. - * For simplicity, only %s and %d are implemented here. - */ - - if ( format[i] =3D=3D 's' ) - { - char* arg =3D va_arg(args, char*); - size_t arglen =3D strlen(arg); - - size_t remaining =3D size - written - 1; - - if ( arglen > remaining ) - arglen =3D remaining; - - memcpy(dest + written, arg, arglen); - - written +=3D arglen; - i++; - } - else if ( format[i] =3D=3D 'd' ) - { - int arg =3D va_arg(args, int); - - /* Convert the integer to string representation */ - char numstr[32]; /* Assumes a maximum of 32 digits */ - int numlen =3D 0; - int num =3D arg; - size_t remaining; - - if ( arg < 0 ) - { - if ( written < size - 1 ) - { - dest[written] =3D '-'; - written++; - } - - num =3D -arg; - } - - do - { - numstr[numlen] =3D '0' + num % 10; - num =3D num / 10; - numlen++; - } while ( num > 0 ); - - /* Reverse the string */ - for (int j =3D 0; j < numlen / 2; j++) - { - char tmp =3D numstr[j]; - numstr[j] =3D numstr[numlen - 1 - j]; - numstr[numlen - 1 - j] =3D tmp; - } - - remaining =3D size - written - 1; - - if ( numlen > remaining ) - numlen =3D remaining; - - memcpy(dest + written, numstr, numlen); - - written +=3D numlen; - i++; - } - } - else - { - if ( written < size - 1 ) - { - dest[written] =3D format[i]; - written++; - } - i++; - } - } - - if ( size > 0 ) - dest[written] =3D '\0'; - - return written; -} - -void printk(const char *format, ...) -{ - static char buf[1024]; - - va_list args; - va_start(args, format); - - (void)vsnprintf(buf, sizeof(buf), format, args); - - early_printk(buf); - - va_end(args); -} - -#endif - diff --git a/xen/arch/riscv/mm.c b/xen/arch/riscv/mm.c index 99ed5e9623..0f40641db7 100644 --- a/xen/arch/riscv/mm.c +++ b/xen/arch/riscv/mm.c @@ -3,15 +3,19 @@ #include #include #include +#include +#include #include =20 #include #include #include -#include #include #include =20 +unsigned long frametable_base_pdx __read_mostly; +unsigned long frametable_virt_end __read_mostly; + struct mmu_desc { unsigned int num_levels; unsigned int pgtbl_count; @@ -273,3 +277,49 @@ void __init noreturn noinline enable_mmu() switch_stack_and_jump((unsigned long)cpu0_boot_stack + STACK_SIZE, cont_after_mmu_is_enabled); } + +void put_page(struct page_info *page) +{ + assert_failed(__func__); +} + +unsigned long get_upper_mfn_bound(void) +{ + /* No memory hotplug yet, so current memory limit is the final one. */ + return max_page - 1; +} + +void arch_dump_shared_mem_info(void) +{ + WARN(); +} + +int populate_pt_range(unsigned long virt, unsigned long nr_mfns) +{ + assert_failed(__func__); + return -1; +} + +int xenmem_add_to_physmap_one(struct domain *d, unsigned int space, + union add_to_physmap_extra extra, + unsigned long idx, gfn_t gfn) +{ + WARN(); + + return 0; +} + +int destroy_xen_mappings(unsigned long s, unsigned long e) +{ + assert_failed(__func__); + return -1; +} + +int map_pages_to_xen(unsigned long virt, + mfn_t mfn, + unsigned long nr_mfns, + unsigned int flags) +{ + assert_failed(__func__); + return -1; +} diff --git a/xen/arch/riscv/setup.c b/xen/arch/riscv/setup.c index dde8fb898b..b44ce41d22 100644 --- a/xen/arch/riscv/setup.c +++ b/xen/arch/riscv/setup.c @@ -2,9 +2,16 @@ =20 #include #include +#include + +#include =20 #include -#include + +void arch_get_xen_caps(xen_capabilities_info_t *info) +{ + assert_failed("need to be implemented"); +} =20 /* Xen stack for bringing up the first CPU. */ unsigned char __initdata cpu0_boot_stack[STACK_SIZE] diff --git a/xen/arch/riscv/stubs.c b/xen/arch/riscv/stubs.c new file mode 100644 index 0000000000..3232039bc2 --- /dev/null +++ b/xen/arch/riscv/stubs.c @@ -0,0 +1,437 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#include +#include +#include +#include +#include +#include +#include + +#include + +/* smpboot.c */ + +cpumask_t cpu_online_map; +cpumask_t cpu_present_map; +cpumask_t cpu_possible_map; + +/* ID of the PCPU we're running on */ +DEFINE_PER_CPU(unsigned int, cpu_id); +/* XXX these seem awfully x86ish... */ +/* representing HT siblings of each logical CPU */ +DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_mask); +/* representing HT and core siblings of each logical CPU */ +DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_mask); + +nodemask_t __read_mostly node_online_map =3D { { [0] =3D 1UL } }; + +/* time.c */ + +unsigned long __read_mostly cpu_khz; /* CPU clock frequency in kHz. */ + +s_time_t get_s_time(void) +{ + BUG(); +} + +int reprogram_timer(s_time_t timeout) +{ + BUG(); +} + +void send_timer_event(struct vcpu *v) +{ + BUG(); +} + +void domain_set_time_offset(struct domain *d, int64_t time_offset_seconds) +{ + BUG(); +} + +/* shutdown.c */ + +void machine_restart(unsigned int delay_millisecs) +{ + BUG(); +} + +void machine_halt(void) +{ + BUG(); +} + +/* vm_event.c */ + +void vm_event_fill_regs(vm_event_request_t *req) +{ + BUG(); +} + +void vm_event_set_registers(struct vcpu *v, vm_event_response_t *rsp) +{ + BUG(); +} + +void vm_event_monitor_next_interrupt(struct vcpu *v) +{ + /* Not supported on RISCV. */ +} + +void vm_event_reset_vmtrace(struct vcpu *v) +{ + /* Not supported on RISCV. */ +} + +/* domctl.c */ + +long arch_do_domctl(struct xen_domctl *domctl, struct domain *d, + XEN_GUEST_HANDLE_PARAM(xen_domctl_t) u_domctl) +{ + BUG(); +} + +void arch_get_domain_info(const struct domain *d, + struct xen_domctl_getdomaininfo *info) +{ + BUG(); +} + +void arch_get_info_guest(struct vcpu *v, vcpu_guest_context_u c) +{ + BUG(); +} + +/* monitor.c */ + +int arch_monitor_domctl_event(struct domain *d, + struct xen_domctl_monitor_op *mop) +{ + BUG(); +} + +/* smp.c */ + +void arch_flush_tlb_mask(const cpumask_t *mask) +{ + BUG(); +} + +void smp_send_event_check_mask(const cpumask_t *mask) +{ + BUG(); +} + +void smp_send_call_function_mask(const cpumask_t *mask) +{ + BUG(); +} + +/* irq.c */ + +struct pirq *alloc_pirq_struct(struct domain *d) +{ + BUG(); +} + +int pirq_guest_bind(struct vcpu *v, struct pirq *pirq, int will_share) +{ + BUG(); +} + +void pirq_guest_unbind(struct domain *d, struct pirq *pirq) +{ + BUG(); +} + +void pirq_set_affinity(struct domain *d, int pirq, const cpumask_t *mask) +{ + BUG(); +} + +static void ack_none(struct irq_desc *irq) +{ + BUG(); +} + +static void end_none(struct irq_desc *irq) +{ + BUG(); +} + +hw_irq_controller no_irq_type =3D { + .typename =3D "none", + .startup =3D irq_startup_none, + .shutdown =3D irq_shutdown_none, + .enable =3D irq_enable_none, + .disable =3D irq_disable_none, + .ack =3D ack_none, + .end =3D end_none +}; + +int arch_init_one_irq_desc(struct irq_desc *desc) +{ + BUG(); +} + +void smp_send_state_dump(unsigned int cpu) +{ + BUG(); +} + +/* domain.c */ + +DEFINE_PER_CPU(struct vcpu *, curr_vcpu); +unsigned long __per_cpu_offset[NR_CPUS]; + +void context_switch(struct vcpu *prev, struct vcpu *next) +{ + BUG(); +} + +void continue_running(struct vcpu *same) +{ + BUG(); +} + +void sync_local_execstate(void) +{ + BUG(); +} + +void sync_vcpu_execstate(struct vcpu *v) +{ + BUG(); +} + +void startup_cpu_idle_loop(void) +{ + BUG(); +} + +void free_domain_struct(struct domain *d) +{ + BUG(); +} + +void dump_pageframe_info(struct domain *d) +{ + BUG(); +} + +void free_vcpu_struct(struct vcpu *v) +{ + BUG(); +} + +int arch_vcpu_create(struct vcpu *v) +{ + BUG(); +} + +void arch_vcpu_destroy(struct vcpu *v) +{ + BUG(); +} + +void vcpu_switch_to_aarch64_mode(struct vcpu *v) +{ + BUG(); +} + +int arch_sanitise_domain_config(struct xen_domctl_createdomain *config) +{ + BUG(); +} + +int arch_domain_create(struct domain *d, + struct xen_domctl_createdomain *config, + unsigned int flags) +{ + BUG(); +} + +int arch_domain_teardown(struct domain *d) +{ + BUG(); +} + +void arch_domain_destroy(struct domain *d) +{ + BUG(); +} + +void arch_domain_shutdown(struct domain *d) +{ + BUG(); +} + +void arch_domain_pause(struct domain *d) +{ + BUG(); +} + +void arch_domain_unpause(struct domain *d) +{ + BUG(); +} + +int arch_domain_soft_reset(struct domain *d) +{ + BUG(); +} + +void arch_domain_creation_finished(struct domain *d) +{ + BUG(); +} + +int arch_set_info_guest(struct vcpu *v, vcpu_guest_context_u c) +{ + BUG(); +} + +int arch_initialise_vcpu(struct vcpu *v, XEN_GUEST_HANDLE_PARAM(void) arg) +{ + BUG(); +} + +int arch_vcpu_reset(struct vcpu *v) +{ + BUG(); +} + +int domain_relinquish_resources(struct domain *d) +{ + BUG(); +} + +void arch_dump_domain_info(struct domain *d) +{ + BUG(); +} + +void arch_dump_vcpu_info(struct vcpu *v) +{ + BUG(); +} + +void vcpu_mark_events_pending(struct vcpu *v) +{ + BUG(); +} + +void vcpu_update_evtchn_irq(struct vcpu *v) +{ + BUG(); +} + +void vcpu_block_unless_event_pending(struct vcpu *v) +{ + BUG(); +} + +void vcpu_kick(struct vcpu *v) +{ + BUG(); +} + +struct domain *alloc_domain_struct(void) +{ + BUG(); +} + +struct vcpu *alloc_vcpu_struct(const struct domain *d) +{ + BUG(); +} + +unsigned long +hypercall_create_continuation(unsigned int op, const char *format, ...) +{ + BUG(); +} + +int __init parse_arch_dom0_param(const char *s, const char *e) +{ + BUG(); +} + +/* guestcopy.c */ + +unsigned long raw_copy_to_guest(void *to, const void *from, unsigned int l= en) +{ + BUG(); +} + +unsigned long raw_copy_from_guest(void *to, const void __user *from, + unsigned int len) +{ + BUG(); +} + +/* sysctl.c */ + +long arch_do_sysctl(struct xen_sysctl *sysctl, + XEN_GUEST_HANDLE_PARAM(xen_sysctl_t) u_sysctl) +{ + BUG(); +} + +void arch_do_physinfo(struct xen_sysctl_physinfo *pi) +{ + BUG(); +} + +/* p2m.c */ + +int arch_set_paging_mempool_size(struct domain *d, uint64_t size) +{ + BUG(); +} + +int unmap_mmio_regions(struct domain *d, + gfn_t start_gfn, + unsigned long nr, + mfn_t mfn) +{ + BUG(); +} + +int map_mmio_regions(struct domain *d, + gfn_t start_gfn, + unsigned long nr, + mfn_t mfn) +{ + BUG(); +} + +int set_foreign_p2m_entry(struct domain *d, const struct domain *fd, + unsigned long gfn, mfn_t mfn) +{ + BUG(); +} + +/* Return the size of the pool, in bytes. */ +int arch_get_paging_mempool_size(struct domain *d, uint64_t *size) +{ + BUG(); +} + +/* need for build until common code starts be buildable */ +unsigned long __read_mostly max_page; + +void printk(const char *fmt, ...) +{ + BUG(); +} + +void cf_check irq_actor_none(struct irq_desc *desc) +{ + BUG(); +} + +unsigned int cf_check irq_startup_none(struct irq_desc *desc) +{ + return 0; +} \ No newline at end of file diff --git a/xen/arch/riscv/traps.c b/xen/arch/riscv/traps.c index ccd3593f5a..ca56df75d8 100644 --- a/xen/arch/riscv/traps.c +++ b/xen/arch/riscv/traps.c @@ -4,6 +4,10 @@ * * RISC-V Trap handlers */ + +#include +#include + #include #include =20 @@ -11,3 +15,24 @@ void do_trap(struct cpu_user_regs *cpu_regs) { die(); } + +void vcpu_show_execution_state(struct vcpu *v) +{ + assert_failed("need to be implented"); +} + +void show_execution_state(const struct cpu_user_regs *regs) +{ + printk("implement show_execution_state(regs)\n"); +} + +void arch_hypercall_tasklet_result(struct vcpu *v, long res) +{ + assert_failed("need to be implented"); +} + +enum mc_disposition arch_do_multicall_call(struct mc_state *state) +{ + assert_failed("need to be implented"); + return mc_continue; +} --=20 2.41.0 From nobody Wed May 15 01:18:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1692181918; cv=none; d=zohomail.com; s=zohoarc; b=Aw5UrK8PG9Ru5H8GCJauGniyTMzsp09WNKFmizoVLq2VuY+CM0U3PDNwQA97/CvZWz8qeLm/6v6rXNTn0mFbJ2ml1ia5dAXze/rDCWejklYR15YEvEDY0HlJXd/3Iw7FWiJiiIQD7P1IyNDhtZC1A11drjA2C+fsc5OaKj/sMTc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; 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text/plain; charset="utf-8" Signed-off-by: Oleksii Kurochko --- xen/arch/riscv/Makefile | 16 +++++++++++++++- xen/arch/riscv/arch.mk | 4 ---- xen/arch/riscv/configs/tiny64_defconfig | 19 ++++++++++++++++++- xen/arch/riscv/stubs.c | 18 ------------------ 4 files changed, 33 insertions(+), 24 deletions(-) diff --git a/xen/arch/riscv/Makefile b/xen/arch/riscv/Makefile index 50c09469a0..9c02cb0ccf 100644 --- a/xen/arch/riscv/Makefile +++ b/xen/arch/riscv/Makefile @@ -12,10 +12,24 @@ $(TARGET): $(TARGET)-syms $(OBJCOPY) -O binary -S $< $@ =20 $(TARGET)-syms: $(objtree)/prelink.o $(obj)/xen.lds - $(LD) $(XEN_LDFLAGS) -T $(obj)/xen.lds -N $< $(build_id_linker) -o $@ + $(LD) $(XEN_LDFLAGS) -T $(obj)/xen.lds -N $< \ + $(objtree)/common/symbols-dummy.o -o $(dot-target).0 + $(NM) -pa --format=3Dsysv $(dot-target).0 \ + | $(objtree)/tools/symbols $(all_symbols) --sysv --sort \ + > $(dot-target).0.S + $(MAKE) $(build)=3D$(@D) $(dot-target).0.o + $(LD) $(XEN_LDFLAGS) -T $(obj)/xen.lds -N $< \ + $(dot-target).0.o -o $(dot-target).1 + $(NM) -pa --format=3Dsysv $(dot-target).1 \ + | $(objtree)/tools/symbols $(all_symbols) --sysv --sort \ + > $(dot-target).1.S + $(MAKE) $(build)=3D$(@D) $(dot-target).1.o + $(LD) $(XEN_LDFLAGS) -T $(obj)/xen.lds -N $< $(build_id_linker) \ + $(dot-target).1.o -o $@ $(NM) -pa --format=3Dsysv $@ \ | $(objtree)/tools/symbols --all-symbols --xensyms --sysv --sort \ > $@.map + rm -f $(@D)/.$(@F).[0-9]* =20 $(obj)/xen.lds: $(src)/xen.lds.S FORCE $(call if_changed_dep,cpp_lds_S) diff --git a/xen/arch/riscv/arch.mk b/xen/arch/riscv/arch.mk index 8403f96b6f..12b1673fae 100644 --- a/xen/arch/riscv/arch.mk +++ b/xen/arch/riscv/arch.mk @@ -13,7 +13,3 @@ riscv-march-$(CONFIG_RISCV_ISA_C) :=3D $(riscv-marc= h-y)c # -mcmodel=3Dmedlow would force Xen into the lower half. =20 CFLAGS +=3D -march=3D$(riscv-march-y) -mstrict-align -mcmodel=3Dmedany - -# TODO: Drop override when more of the build is working -override ALL_OBJS-y =3D arch/$(SRCARCH)/built_in.o -override ALL_LIBS-y =3D diff --git a/xen/arch/riscv/configs/tiny64_defconfig b/xen/arch/riscv/confi= gs/tiny64_defconfig index 3c9a2ff941..4b488180ae 100644 --- a/xen/arch/riscv/configs/tiny64_defconfig +++ b/xen/arch/riscv/configs/tiny64_defconfig @@ -6,7 +6,24 @@ # CONFIG_HYPFS is not set # CONFIG_GRANT_TABLE is not set # CONFIG_SPECULATIVE_HARDEN_ARRAY is not set - +# CONFIG_ARGO is not set +# CONFIG_HYPFS_CONFIG is not set +# CONFIG_CORE_PARKING is not set +# CONFIG_DEBUG_TRACE is not set +# CONFIG_IOREQ_SERVER is not set +# CONFIG_CRASH_DEBUG is not setz +# CONFIG_KEXEC is not set +# CONFIG_LIVEPATCH is not set +# CONFIG_MEM_ACCESS is not set +# CONFIG_NUMA is not set +# CONFIG_PERF_COUNTERS is not set +# CONFIG_HAS_PMAP is not set +# CONFIG_TRACEBUFFER is not set +# CONFIG_XENOPROF is not set +# CONFIG_COMPAT is not set +# CONFIG_COVERAGE is not set +# CONFIG_UBSAN is not set +# CONFIG_NEEDS_LIBELF is not set CONFIG_RISCV_64=3Dy CONFIG_DEBUG=3Dy CONFIG_DEBUG_INFO=3Dy diff --git a/xen/arch/riscv/stubs.c b/xen/arch/riscv/stubs.c index 3232039bc2..5f3040965e 100644 --- a/xen/arch/riscv/stubs.c +++ b/xen/arch/riscv/stubs.c @@ -417,21 +417,3 @@ int arch_get_paging_mempool_size(struct domain *d, uin= t64_t *size) { BUG(); } - -/* need for build until common code starts be buildable */ -unsigned long __read_mostly max_page; - -void printk(const char *fmt, ...) -{ - BUG(); -} - -void cf_check irq_actor_none(struct irq_desc *desc) -{ - BUG(); -} - -unsigned int cf_check irq_startup_none(struct irq_desc *desc) -{ - return 0; -} \ No newline at end of file --=20 2.41.0 From nobody Wed May 15 01:18:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org 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Subject: [PATCH v1 56/57] test only riscv Date: Wed, 16 Aug 2023 13:20:09 +0300 Message-ID: X-Mailer: git-send-email 2.41.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1692181978275100007 Content-Type: text/plain; charset="utf-8" Signed-off-by: Oleksii Kurochko --- automation/gitlab-ci/analyze.yaml | 16 - automation/gitlab-ci/build.yaml | 544 ------------------------------ automation/gitlab-ci/test.yaml | 308 ----------------- 3 files changed, 868 deletions(-) diff --git a/automation/gitlab-ci/analyze.yaml b/automation/gitlab-ci/analy= ze.yaml index 4aa4abe2ee..89cef96771 100644 --- a/automation/gitlab-ci/analyze.yaml +++ b/automation/gitlab-ci/analyze.yaml @@ -20,22 +20,6 @@ codequality: gl-code-quality-report.json needs: [] =20 -eclair-x86_64: - extends: .eclair-analysis - variables: - LOGFILE: "eclair-x86_64.log" - VARIANT: "X86_64" - RULESET: "Set1" - allow_failure: true - -eclair-ARM64: - extends: .eclair-analysis - variables: - LOGFILE: "eclair-ARM64.log" - VARIANT: "ARM64" - RULESET: "Set1" - allow_failure: true - .eclair-analysis:on-schedule: extends: .eclair-analysis rules: diff --git a/automation/gitlab-ci/build.yaml b/automation/gitlab-ci/build.y= aml index 173613567c..210f7da264 100644 --- a/automation/gitlab-ci/build.yaml +++ b/automation/gitlab-ci/build.yaml @@ -271,247 +271,6 @@ needs: [] except: !reference [.test-jobs-common, except] =20 -# Arm test artifacts - -alpine-3.18-arm64-rootfs-export: - extends: .test-jobs-artifact-common - image: registry.gitlab.com/xen-project/xen/tests-artifacts/alpine:3.18-a= rm64v8 - script: - - mkdir binaries && cp /initrd.tar.gz binaries/initrd.tar.gz - artifacts: - paths: - - binaries/initrd.tar.gz - tags: - - arm64 - -kernel-5.19-arm64-export: - extends: .test-jobs-artifact-common - image: registry.gitlab.com/xen-project/xen/tests-artifacts/kernel:5.19-a= rm64v8 - script: - - mkdir binaries && cp /Image binaries/Image - artifacts: - paths: - - binaries/Image - tags: - - arm64 - -qemu-system-aarch64-6.0.0-arm64-export: - extends: .test-jobs-artifact-common - image: registry.gitlab.com/xen-project/xen/tests-artifacts/qemu-system-a= arch64:6.0.0-arm64v8 - script: - - mkdir binaries && cp /qemu-system-aarch64 binaries/qemu-system-aarch= 64 - artifacts: - paths: - - binaries/qemu-system-aarch64 - tags: - - arm64 - -qemu-system-aarch64-6.0.0-arm32-export: - extends: .test-jobs-artifact-common - image: registry.gitlab.com/xen-project/xen/tests-artifacts/qemu-system-a= arch64:6.0.0-arm64v8 - script: - - mkdir binaries && cp /qemu-system-arm binaries/qemu-system-arm - artifacts: - paths: - - binaries/qemu-system-arm - tags: - - arm64 - -# x86_64 test artifacts - -alpine-3.18-rootfs-export: - extends: .test-jobs-artifact-common - image: registry.gitlab.com/xen-project/xen/tests-artifacts/alpine:3.18 - script: - - mkdir binaries && cp /initrd.tar.gz binaries/initrd.tar.gz - artifacts: - paths: - - binaries/initrd.tar.gz - tags: - - x86_64 - -kernel-6.1.19-export: - extends: .test-jobs-artifact-common - image: registry.gitlab.com/xen-project/xen/tests-artifacts/kernel:6.1.19 - script: - - mkdir binaries && cp /bzImage binaries/bzImage - artifacts: - paths: - - binaries/bzImage - tags: - - x86_64 - -# Jobs below this line - -# Build jobs needed for tests - -alpine-3.18-gcc: - extends: .gcc-x86-64-build - variables: - CONTAINER: alpine:3.18 - -alpine-3.18-gcc-debug: - extends: .gcc-x86-64-build-debug - variables: - CONTAINER: alpine:3.18 - -debian-stretch-gcc-debug: - extends: .gcc-x86-64-build-debug - variables: - CONTAINER: debian:stretch - -debian-unstable-clang-debug: - extends: .clang-x86-64-build-debug - variables: - CONTAINER: debian:unstable - -# Arm32 cross-build - -debian-unstable-gcc-arm32: - extends: .gcc-arm32-cross-build - variables: - CONTAINER: debian:unstable-arm64v8-arm32-gcc - HYPERVISOR_ONLY: y - -debian-unstable-gcc-arm32-debug: - extends: .gcc-arm32-cross-build-debug - variables: - CONTAINER: debian:unstable-arm64v8-arm32-gcc - HYPERVISOR_ONLY: y - -debian-unstable-gcc-arm32-randconfig: - extends: .gcc-arm32-cross-build - variables: - CONTAINER: debian:unstable-arm64v8-arm32-gcc - HYPERVISOR_ONLY: y - RANDCONFIG: y - -debian-unstable-gcc-arm32-debug-randconfig: - extends: .gcc-arm32-cross-build-debug - variables: - CONTAINER: debian:unstable-arm64v8-arm32-gcc - HYPERVISOR_ONLY: y - RANDCONFIG: y - -debian-unstable-gcc-arm32-staticmem: - extends: .gcc-arm32-cross-build - variables: - CONTAINER: debian:unstable-arm64v8-arm32-gcc - HYPERVISOR_ONLY: y - EXTRA_XEN_CONFIG: | - CONFIG_EXPERT=3Dy - CONFIG_UNSUPPORTED=3Dy - CONFIG_STATIC_MEMORY=3Dy - -debian-unstable-gcc-arm32-debug-staticmem: - extends: .gcc-arm32-cross-build-debug - variables: - CONTAINER: debian:unstable-arm64v8-arm32-gcc - HYPERVISOR_ONLY: y - EXTRA_XEN_CONFIG: | - CONFIG_EXPERT=3Dy - CONFIG_UNSUPPORTED=3Dy - CONFIG_STATIC_MEMORY=3Dy - -# Arm builds - -debian-unstable-gcc-arm64: - extends: .gcc-arm64-build - variables: - CONTAINER: debian:unstable-arm64v8 - -debian-unstable-gcc-debug-arm64: - extends: .gcc-arm64-build-debug - variables: - CONTAINER: debian:unstable-arm64v8 - -debian-unstable-gcc-arm64-randconfig: - extends: .gcc-arm64-build - variables: - CONTAINER: debian:unstable-arm64v8 - RANDCONFIG: y - -debian-unstable-gcc-debug-arm64-randconfig: - extends: .gcc-arm64-build-debug - variables: - CONTAINER: debian:unstable-arm64v8 - RANDCONFIG: y - -alpine-3.18-gcc-arm64: - extends: .gcc-arm64-build - variables: - CONTAINER: alpine:3.18-arm64v8 - -alpine-3.18-gcc-debug-arm64: - extends: .gcc-arm64-build-debug - variables: - CONTAINER: alpine:3.18-arm64v8 - -alpine-3.18-gcc-arm64-randconfig: - extends: .gcc-arm64-build - variables: - CONTAINER: alpine:3.18-arm64v8 - RANDCONFIG: y - -alpine-3.18-gcc-debug-arm64-randconfig: - extends: .gcc-arm64-build-debug - variables: - CONTAINER: alpine:3.18-arm64v8 - RANDCONFIG: y - -alpine-3.18-gcc-arm64-staticmem: - extends: .gcc-arm64-build - variables: - CONTAINER: alpine:3.18-arm64v8 - EXTRA_XEN_CONFIG: | - CONFIG_EXPERT=3Dy - CONFIG_UNSUPPORTED=3Dy - CONFIG_STATIC_MEMORY=3Dy - -alpine-3.18-gcc-debug-arm64-staticmem: - extends: .gcc-arm64-build-debug - variables: - CONTAINER: alpine:3.18-arm64v8 - EXTRA_XEN_CONFIG: | - CONFIG_EXPERT=3Dy - CONFIG_UNSUPPORTED=3Dy - CONFIG_STATIC_MEMORY=3Dy - -alpine-3.18-gcc-arm64-static-shared-mem: - extends: .gcc-arm64-build - variables: - CONTAINER: alpine:3.18-arm64v8 - EXTRA_XEN_CONFIG: | - CONFIG_UNSUPPORTED=3Dy - CONFIG_STATIC_MEMORY=3Dy - CONFIG_STATIC_SHM=3Dy - -alpine-3.18-gcc-debug-arm64-static-shared-mem: - extends: .gcc-arm64-build-debug - variables: - CONTAINER: alpine:3.18-arm64v8 - EXTRA_XEN_CONFIG: | - CONFIG_UNSUPPORTED=3Dy - CONFIG_STATIC_MEMORY=3Dy - CONFIG_STATIC_SHM=3Dy - -alpine-3.18-gcc-arm64-boot-cpupools: - extends: .gcc-arm64-build - variables: - CONTAINER: alpine:3.18-arm64v8 - EXTRA_XEN_CONFIG: | - CONFIG_EXPERT=3Dy - CONFIG_UNSUPPORTED=3Dy - CONFIG_SCHED_NULL=3Dy - CONFIG_BOOT_TIME_CPUPOOLS=3Dy - -alpine-3.18-gcc-debug-arm64-boot-cpupools: - extends: .gcc-arm64-build-debug - variables: - CONTAINER: alpine:3.18-arm64v8 - EXTRA_XEN_CONFIG: | - CONFIG_BOOT_TIME_CPUPOOLS=3Dy - # RISC-V 64 cross-build archlinux-current-gcc-riscv64: extends: .gcc-riscv64-cross-build @@ -544,306 +303,3 @@ archlinux-current-gcc-riscv64-debug-randconfig: RANDCONFIG: y EXTRA_FIXED_RANDCONFIG: CONFIG_COVERAGE=3Dn - -# Power cross-build -debian-bullseye-gcc-ppc64le: - extends: .gcc-ppc64le-cross-build - variables: - CONTAINER: debian:bullseye-ppc64le - KBUILD_DEFCONFIG: ppc64_defconfig - HYPERVISOR_ONLY: y - -debian-bullseye-gcc-ppc64le-debug: - extends: .gcc-ppc64le-cross-build-debug - variables: - CONTAINER: debian:bullseye-ppc64le - KBUILD_DEFCONFIG: ppc64_defconfig - HYPERVISOR_ONLY: y - -debian-bullseye-gcc-ppc64le-randconfig: - extends: .gcc-ppc64le-cross-build - variables: - CONTAINER: debian:bullseye-ppc64le - KBUILD_DEFCONFIG: ppc64_defconfig - RANDCONFIG: y - EXTRA_FIXED_RANDCONFIG: - CONFIG_COVERAGE=3Dn - -debian-bullseye-gcc-ppc64le-debug-randconfig: - extends: .gcc-ppc64le-cross-build-debug - variables: - CONTAINER: debian:bullseye-ppc64le - KBUILD_DEFCONFIG: ppc64_defconfig - RANDCONFIG: y - EXTRA_FIXED_RANDCONFIG: - CONFIG_COVERAGE=3Dn - -# Yocto test jobs -yocto-qemuarm64: - extends: .yocto-test-arm64 - variables: - YOCTO_BOARD: qemuarm64 - -yocto-qemuarm: - extends: .yocto-test-arm64 - variables: - YOCTO_BOARD: qemuarm - YOCTO_OUTPUT: --copy-output - -yocto-qemux86-64: - extends: .yocto-test-arm64 - variables: - YOCTO_BOARD: qemux86-64 - -# Cppcheck analysis jobs - -debian-unstable-gcc-cppcheck: - extends: .gcc-x86-64-cross-build - variables: - CONTAINER: debian:unstable-cppcheck - CROSS_COMPILE: /usr/bin/x86_64-linux-gnu- - CPPCHECK: y - HYPERVISOR_ONLY: y - -debian-unstable-gcc-arm32-cppcheck: - extends: .gcc-arm32-cross-build - variables: - CONTAINER: debian:unstable-cppcheck - CROSS_COMPILE: /usr/bin/arm-linux-gnueabihf- - CPPCHECK: y - HYPERVISOR_ONLY: y - -debian-unstable-gcc-arm64-cppcheck: - extends: .gcc-arm64-build - variables: - CONTAINER: debian:unstable-cppcheck - CPPCHECK: y - HYPERVISOR_ONLY: y - -# Build jobs not needed for tests - -alpine-3.18-clang: - extends: .clang-x86-64-build - variables: - CONTAINER: alpine:3.18 - -alpine-3.18-clang-debug: - extends: .clang-x86-64-build-debug - variables: - CONTAINER: alpine:3.18 - -archlinux-gcc: - extends: .gcc-x86-64-build - variables: - CONTAINER: archlinux:current - -archlinux-gcc-debug: - extends: .gcc-x86-64-build-debug - variables: - CONTAINER: archlinux:current - -centos-7-gcc: - extends: .gcc-x86-64-build - variables: - CONTAINER: centos:7 - -centos-7-gcc-debug: - extends: .gcc-x86-64-build-debug - variables: - CONTAINER: centos:7 - -debian-stretch-gcc: - extends: .gcc-x86-64-build - variables: - CONTAINER: debian:stretch - -debian-stretch-clang: - extends: .clang-x86-64-build - variables: - CONTAINER: debian:stretch - -debian-stretch-clang-debug: - extends: .clang-x86-64-build-debug - variables: - CONTAINER: debian:stretch - -debian-stretch-32-clang-debug: - extends: .clang-x86-32-build-debug - variables: - CONTAINER: debian:stretch-i386 - -debian-stretch-32-gcc-debug: - extends: .gcc-x86-32-build-debug - variables: - CONTAINER: debian:stretch-i386 - -debian-buster-gcc-ibt: - extends: .gcc-x86-64-build - variables: - CONTAINER: debian:buster-gcc-ibt - RANDCONFIG: y - EXTRA_FIXED_RANDCONFIG: | - CONFIG_XEN_IBT=3Dy - -debian-unstable-clang: - extends: .clang-x86-64-build - variables: - CONTAINER: debian:unstable - -debian-unstable-gcc: - extends: .gcc-x86-64-build - variables: - CONTAINER: debian:unstable - -debian-unstable-gcc-debug: - extends: .gcc-x86-64-build-debug - variables: - CONTAINER: debian:unstable - -debian-unstable-gcc-randconfig: - extends: .gcc-x86-64-build - variables: - CONTAINER: debian:unstable - RANDCONFIG: y - -debian-unstable-gcc-debug-randconfig: - extends: .gcc-x86-64-build-debug - variables: - CONTAINER: debian:unstable - RANDCONFIG: y - -debian-unstable-32-clang-debug: - extends: .clang-x86-32-build-debug - variables: - CONTAINER: debian:unstable-i386 - -debian-unstable-32-gcc-debug: - extends: .gcc-x86-32-build-debug - variables: - CONTAINER: debian:unstable-i386 - -fedora-gcc: - extends: .gcc-x86-64-build - variables: - CONTAINER: fedora:29 - -fedora-gcc-debug: - extends: .gcc-x86-64-build-debug - variables: - CONTAINER: fedora:29 - -# Ubuntu Trusty's Clang is 3.4 while Xen requires 3.5 - -ubuntu-trusty-gcc: - extends: .gcc-x86-64-build - variables: - CONTAINER: ubuntu:trusty - -ubuntu-trusty-gcc-debug: - extends: .gcc-x86-64-build-debug - variables: - CONTAINER: ubuntu:trusty - -ubuntu-xenial-clang: - extends: .clang-x86-64-build - variables: - CONTAINER: ubuntu:xenial - -ubuntu-xenial-clang-debug: - extends: .clang-x86-64-build-debug - variables: - CONTAINER: ubuntu:xenial - -ubuntu-xenial-gcc: - extends: .gcc-x86-64-build - variables: - CONTAINER: ubuntu:xenial - -ubuntu-xenial-gcc-debug: - extends: .gcc-x86-64-build-debug - variables: - CONTAINER: ubuntu:xenial - -ubuntu-bionic-clang: - extends: .clang-x86-64-build - variables: - CONTAINER: ubuntu:bionic - -ubuntu-bionic-clang-debug: - extends: .clang-x86-64-build-debug - variables: - CONTAINER: ubuntu:bionic - -ubuntu-bionic-gcc: - extends: .gcc-x86-64-build - variables: - CONTAINER: ubuntu:bionic - -ubuntu-bionic-gcc-debug: - extends: .gcc-x86-64-build-debug - variables: - CONTAINER: ubuntu:bionic - -ubuntu-focal-gcc: - extends: .gcc-x86-64-build - variables: - CONTAINER: ubuntu:focal - -ubuntu-focal-gcc-debug: - extends: .gcc-x86-64-build-debug - variables: - CONTAINER: ubuntu:focal - -ubuntu-focal-clang: - extends: .clang-x86-64-build - variables: - CONTAINER: ubuntu:focal - -ubuntu-focal-clang-debug: - extends: .clang-x86-64-build-debug - variables: - CONTAINER: ubuntu:focal - -opensuse-leap-clang: - extends: .clang-x86-64-build - variables: - CONTAINER: suse:opensuse-leap - -opensuse-leap-clang-debug: - extends: .clang-x86-64-build-debug - variables: - CONTAINER: suse:opensuse-leap - -opensuse-leap-gcc: - extends: .gcc-x86-64-build - variables: - CONTAINER: suse:opensuse-leap - -opensuse-leap-gcc-debug: - extends: .gcc-x86-64-build-debug - variables: - CONTAINER: suse:opensuse-leap - -opensuse-tumbleweed-clang: - extends: .clang-x86-64-build - variables: - CONTAINER: suse:opensuse-tumbleweed - allow_failure: true - -opensuse-tumbleweed-clang-debug: - extends: .clang-x86-64-build-debug - variables: - CONTAINER: suse:opensuse-tumbleweed - allow_failure: true - -opensuse-tumbleweed-gcc: - extends: .gcc-x86-64-build - variables: - CONTAINER: suse:opensuse-tumbleweed - allow_failure: true - -opensuse-tumbleweed-gcc-debug: - extends: .gcc-x86-64-build-debug - variables: - CONTAINER: suse:opensuse-tumbleweed - allow_failure: true diff --git a/automation/gitlab-ci/test.yaml b/automation/gitlab-ci/test.yaml index 8ccce1fe26..869fe8cd9f 100644 --- a/automation/gitlab-ci/test.yaml +++ b/automation/gitlab-ci/test.yaml @@ -149,308 +149,6 @@ build-each-commit-gcc: tags: - x86_64 =20 -xilinx-smoke-dom0less-arm64-gcc: - extends: .xilinx-arm64 - script: - - ./automation/scripts/xilinx-smoke-dom0less-arm64.sh 2>&1 | tee ${LOG= FILE} - needs: - - *arm64-test-needs - - alpine-3.18-gcc-arm64 - -xilinx-smoke-dom0less-arm64-gcc-gem-passthrough: - extends: .xilinx-arm64 - script: - - ./automation/scripts/xilinx-smoke-dom0less-arm64.sh gem-passthrough = 2>&1 | tee ${LOGFILE} - needs: - - *arm64-test-needs - - alpine-3.18-gcc-arm64 - -adl-smoke-x86-64-gcc-debug: - extends: .adl-x86-64 - script: - - ./automation/scripts/qubes-x86-64.sh 2>&1 | tee ${LOGFILE} - needs: - - *x86-64-test-needs - - alpine-3.18-gcc-debug - -adl-smoke-x86-64-dom0pvh-gcc-debug: - extends: .adl-x86-64 - script: - - ./automation/scripts/qubes-x86-64.sh dom0pvh 2>&1 | tee ${LOGFILE} - needs: - - *x86-64-test-needs - - alpine-3.18-gcc-debug - -adl-suspend-x86-64-gcc-debug: - extends: .adl-x86-64 - script: - - ./automation/scripts/qubes-x86-64.sh s3 2>&1 | tee ${LOGFILE} - needs: - - *x86-64-test-needs - - alpine-3.18-gcc-debug - -adl-pci-pv-x86-64-gcc-debug: - extends: .adl-x86-64 - script: - - ./automation/scripts/qubes-x86-64.sh pci-pv 2>&1 | tee ${LOGFILE} - needs: - - *x86-64-test-needs - - alpine-3.18-gcc-debug - -adl-pci-hvm-x86-64-gcc-debug: - extends: .adl-x86-64 - variables: - PCIDEV_INTR: "MSI" - script: - - ./automation/scripts/qubes-x86-64.sh pci-hvm 2>&1 | tee ${LOGFILE} - needs: - - *x86-64-test-needs - - alpine-3.18-gcc-debug - -zen3p-smoke-x86-64-gcc-debug: - extends: .zen3p-x86-64 - script: - - ./automation/scripts/qubes-x86-64.sh 2>&1 | tee ${LOGFILE} - needs: - - *x86-64-test-needs - - alpine-3.18-gcc-debug - -zen3p-smoke-x86-64-dom0pvh-gcc-debug: - extends: .zen3p-x86-64 - script: - - ./automation/scripts/qubes-x86-64.sh dom0pvh 2>&1 | tee ${LOGFILE} - needs: - - *x86-64-test-needs - - alpine-3.18-gcc-debug - -zen3p-pci-hvm-x86-64-gcc-debug: - extends: .zen3p-x86-64 - script: - - ./automation/scripts/qubes-x86-64.sh pci-hvm 2>&1 | tee ${LOGFILE} - needs: - - *x86-64-test-needs - - alpine-3.18-gcc-debug - -qemu-smoke-dom0-arm64-gcc: - extends: .qemu-arm64 - script: - - ./automation/scripts/qemu-smoke-dom0-arm64.sh 2>&1 | tee ${LOGFILE} - needs: - - *arm64-test-needs - - alpine-3.18-gcc-arm64 - -qemu-smoke-dom0-arm64-gcc-debug: - extends: .qemu-arm64 - script: - - ./automation/scripts/qemu-smoke-dom0-arm64.sh 2>&1 | tee ${LOGFILE} - needs: - - *arm64-test-needs - - alpine-3.18-gcc-debug-arm64 - -qemu-smoke-dom0less-arm64-gcc: - extends: .qemu-arm64 - script: - - ./automation/scripts/qemu-smoke-dom0less-arm64.sh 2>&1 | tee ${LOGFI= LE} - needs: - - *arm64-test-needs - - alpine-3.18-gcc-arm64 - -qemu-smoke-dom0less-arm64-gcc-debug: - extends: .qemu-arm64 - script: - - ./automation/scripts/qemu-smoke-dom0less-arm64.sh 2>&1 | tee ${LOGFI= LE} - needs: - - *arm64-test-needs - - alpine-3.18-gcc-debug-arm64 - -qemu-smoke-dom0less-arm64-gcc-staticmem: - extends: .qemu-arm64 - script: - - ./automation/scripts/qemu-smoke-dom0less-arm64.sh static-mem 2>&1 | = tee ${LOGFILE} - needs: - - *arm64-test-needs - - alpine-3.18-gcc-arm64-staticmem - -qemu-smoke-dom0less-arm64-gcc-debug-staticmem: - extends: .qemu-arm64 - script: - - ./automation/scripts/qemu-smoke-dom0less-arm64.sh static-mem 2>&1 | = tee ${LOGFILE} - needs: - - *arm64-test-needs - - alpine-3.18-gcc-debug-arm64-staticmem - -qemu-smoke-dom0less-arm64-gcc-staticheap: - extends: .qemu-arm64 - script: - - ./automation/scripts/qemu-smoke-dom0less-arm64.sh static-heap 2>&1 | = tee ${LOGFILE} - needs: - - *arm64-test-needs - - alpine-3.18-gcc-arm64 - -qemu-smoke-dom0less-arm64-gcc-debug-staticheap: - extends: .qemu-arm64 - script: - - ./automation/scripts/qemu-smoke-dom0less-arm64.sh static-heap 2>&1 | = tee ${LOGFILE} - needs: - - *arm64-test-needs - - alpine-3.18-gcc-debug-arm64 - -qemu-smoke-dom0less-arm64-gcc-static-shared-mem: - extends: .qemu-arm64 - script: - - ./automation/scripts/qemu-smoke-dom0less-arm64.sh static-shared-mem = 2>&1 | tee ${LOGFILE} - needs: - - *arm64-test-needs - - alpine-3.18-gcc-arm64-static-shared-mem - -qemu-smoke-dom0less-arm64-gcc-debug-static-shared-mem: - extends: .qemu-arm64 - script: - - ./automation/scripts/qemu-smoke-dom0less-arm64.sh static-shared-mem = 2>&1 | tee ${LOGFILE} - needs: - - *arm64-test-needs - - alpine-3.18-gcc-debug-arm64-static-shared-mem - -qemu-smoke-dom0less-arm64-gcc-boot-cpupools: - extends: .qemu-arm64 - script: - - ./automation/scripts/qemu-smoke-dom0less-arm64.sh boot-cpupools 2>&1= | tee ${LOGFILE} - needs: - - *arm64-test-needs - - alpine-3.18-gcc-arm64-boot-cpupools - -qemu-smoke-dom0less-arm64-gcc-debug-boot-cpupools: - extends: .qemu-arm64 - script: - - ./automation/scripts/qemu-smoke-dom0less-arm64.sh boot-cpupools 2>&1= | tee ${LOGFILE} - needs: - - *arm64-test-needs - - alpine-3.18-gcc-debug-arm64-boot-cpupools - -qemu-xtf-dom0less-arm64-gcc-hyp-xen-version: - extends: .qemu-arm64 - script: - - ./automation/scripts/qemu-xtf-dom0less-arm64.sh hyp-xen-version 2>&1= | tee ${LOGFILE} - needs: - - alpine-3.18-gcc-arm64 - - qemu-system-aarch64-6.0.0-arm64-export - -qemu-xtf-dom0less-arm64-gcc-debug-hyp-xen-version: - extends: .qemu-arm64 - script: - - ./automation/scripts/qemu-xtf-dom0less-arm64.sh hyp-xen-version 2>&1= | tee ${LOGFILE} - needs: - - alpine-3.18-gcc-debug-arm64 - - qemu-system-aarch64-6.0.0-arm64-export - -qemu-smoke-dom0-arm32-gcc: - extends: .qemu-arm32 - script: - - ./automation/scripts/qemu-smoke-dom0-arm32.sh 2>&1 | tee ${LOGFILE} - needs: - - *arm32-test-needs - - yocto-qemuarm - -qemu-smoke-dom0less-arm32-gcc: - extends: .qemu-arm32 - script: - - ./automation/scripts/qemu-smoke-dom0less-arm32.sh 2>&1 | tee ${LOGFI= LE} - needs: - - *arm32-test-needs - - debian-unstable-gcc-arm32 - -qemu-smoke-dom0less-arm32-gcc-debug: - extends: .qemu-arm32 - script: - - ./automation/scripts/qemu-smoke-dom0less-arm32.sh 2>&1 | tee ${LOGFI= LE} - needs: - - *arm32-test-needs - - debian-unstable-gcc-arm32-debug - -qemu-smoke-dom0less-arm32-gcc-staticmem: - extends: .qemu-arm32 - script: - - ./automation/scripts/qemu-smoke-dom0less-arm32.sh static-mem 2>&1 | = tee ${LOGFILE} - needs: - - *arm32-test-needs - - debian-unstable-gcc-arm32-staticmem - -qemu-smoke-dom0less-arm32-gcc-debug-staticmem: - extends: .qemu-arm32 - script: - - ./automation/scripts/qemu-smoke-dom0less-arm32.sh static-mem 2>&1 | = tee ${LOGFILE} - needs: - - *arm32-test-needs - - debian-unstable-gcc-arm32-debug-staticmem - -qemu-smoke-dom0less-arm32-gcc-gzip: - extends: .qemu-arm32 - script: - - ./automation/scripts/qemu-smoke-dom0less-arm32.sh gzip 2>&1 | tee ${= LOGFILE} - needs: - - *arm32-test-needs - - debian-unstable-gcc-arm32 - -qemu-smoke-dom0less-arm32-gcc-debug-gzip: - extends: .qemu-arm32 - script: - - ./automation/scripts/qemu-smoke-dom0less-arm32.sh gzip 2>&1 | tee ${= LOGFILE} - needs: - - *arm32-test-needs - - debian-unstable-gcc-arm32-debug - -qemu-smoke-dom0less-arm32-gcc-without-dom0: - extends: .qemu-arm32 - script: - - ./automation/scripts/qemu-smoke-dom0less-arm32.sh without-dom0 2>&1 = | tee ${LOGFILE} - needs: - - *arm32-test-needs - - debian-unstable-gcc-arm32 - -qemu-smoke-dom0less-arm32-gcc-debug-without-dom0: - extends: .qemu-arm32 - script: - - ./automation/scripts/qemu-smoke-dom0less-arm32.sh without-dom0 2>&1 = | tee ${LOGFILE} - needs: - - *arm32-test-needs - - debian-unstable-gcc-arm32-debug - -qemu-alpine-x86_64-gcc: - extends: .qemu-x86-64 - script: - - ./automation/scripts/qemu-alpine-x86_64.sh 2>&1 | tee ${LOGFILE} - needs: - - *x86-64-test-needs - - alpine-3.18-gcc - -qemu-smoke-x86-64-gcc: - extends: .qemu-x86-64 - script: - - ./automation/scripts/qemu-smoke-x86-64.sh pv 2>&1 | tee ${LOGFILE} - needs: - - debian-stretch-gcc-debug - -qemu-smoke-x86-64-clang: - extends: .qemu-x86-64 - script: - - ./automation/scripts/qemu-smoke-x86-64.sh pv 2>&1 | tee ${LOGFILE} - needs: - - debian-unstable-clang-debug - -qemu-smoke-x86-64-gcc-pvh: - extends: .qemu-x86-64 - script: - - ./automation/scripts/qemu-smoke-x86-64.sh pvh 2>&1 | tee ${LOGFILE} - needs: - - debian-stretch-gcc-debug - -qemu-smoke-x86-64-clang-pvh: - extends: .qemu-x86-64 - script: - - ./automation/scripts/qemu-smoke-x86-64.sh pvh 2>&1 | tee ${LOGFILE} - needs: - - debian-unstable-clang-debug - qemu-smoke-riscv64-gcc: extends: .qemu-riscv64 script: @@ -458,9 +156,3 @@ qemu-smoke-riscv64-gcc: needs: - archlinux-current-gcc-riscv64-debug =20 -qemu-smoke-ppc64le-pseries-gcc: - extends: .qemu-ppc64le - script: - - ./automation/scripts/qemu-smoke-ppc64le.sh pseries-5.2 2>&1 | tee ${= LOGFILE} - needs: - - debian-bullseye-gcc-ppc64le-debug --=20 2.41.0 From nobody Wed May 15 01:18:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org 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2002:a5d:4dd1:0:b0:313:e735:6d23 with SMTP id f17-20020a5d4dd1000000b00313e7356d23mr1142481wru.22.1692181262260; Wed, 16 Aug 2023 03:21:02 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Bob Eshleman , Alistair Francis , Connor Davis , Konrad Rzeszutek Wilk , Ross Lagerwall Subject: [PATCH v1 57/57] xxxen/riscv: WIP ( need advise ) Date: Wed, 16 Aug 2023 13:20:10 +0300 Message-ID: <85c3008696e5f9568f6a6504c915a319ca326537.1692181079.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1692181976641100005 Content-Type: text/plain; charset="utf-8" These changes are needed only to make GitLab CI happy is it doesn't take into account tiny64_defconfig where unnecessary configs are disabled. I tried different approaches to deal with it: 1. Override EXTRA_XEN_CONFIG and EXTRA_FIXED_RANDCONFIG in the following wa= y: EXTRA_XEN_CONFIG: CONFIG_1=3Dn CONFIG_2=3Dn ... 2. Override in arch-specific KConfig: CONFIG_1: default n Each option doesn't work for me fully. Could you please suggest other options or more correct way? Signed-off-by: Oleksii Kurochko --- xen/arch/riscv/include/asm/asm_defns.h | 44 +++++++++++++++++ xen/arch/riscv/include/asm/grant_table.h | 57 ++++++++++++++++++++++ xen/arch/riscv/include/asm/guest_atomics.h | 16 +++++- xen/arch/riscv/include/asm/livepatch.h | 0 xen/arch/riscv/include/asm/mm.h | 5 ++ xen/arch/riscv/include/asm/p2m.h | 24 +++++++++ xen/arch/riscv/include/asm/page.h | 16 ++++++ xen/arch/riscv/include/asm/perfc_defn.h | 0 xen/arch/riscv/mm.c | 33 +++++++++++++ 9 files changed, 194 insertions(+), 1 deletion(-) create mode 100644 xen/arch/riscv/include/asm/asm_defns.h create mode 100644 xen/arch/riscv/include/asm/livepatch.h create mode 100644 xen/arch/riscv/include/asm/perfc_defn.h diff --git a/xen/arch/riscv/include/asm/asm_defns.h b/xen/arch/riscv/includ= e/asm/asm_defns.h new file mode 100644 index 0000000000..dd0511a9c6 --- /dev/null +++ b/xen/arch/riscv/include/asm/asm_defns.h @@ -0,0 +1,44 @@ +#ifndef __ARM_ASM_DEFNS_H__ +#define __ARM_ASM_DEFNS_H__ + +#ifndef COMPILE_OFFSETS +/* NB. Auto-generated from arch/.../asm-offsets.c */ +#include +#endif +#include + +/* Macros for generic assembly code */ +#if defined(CONFIG_RISCV_32) +# define __OP32 +# define ASM_REG(index) asm("r" # index) +#elif defined(CONFIG_RISCV_64) +# define __OP32 "w" +/* + * Clang < 8.0 doesn't support register alllocation using the syntax rN. + * See https://reviews.llvm.org/rL328829. + */ +# define ASM_REG(index) asm("x" # index) +#else +# error "unknown ARM variant" +#endif + +#define RODATA_STR(label, msg) \ +.pushsection .rodata.str, "aMS", %progbits, 1 ; \ +label: .asciz msg; \ +.popsection + +#define ASM_INT(label, val) \ + .p2align 2; \ +label: .long (val); \ + .size label, . - label; \ + .type label, %object + +#endif /* __ARM_ASM_DEFNS_H__ */ +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/riscv/include/asm/grant_table.h b/xen/arch/riscv/incl= ude/asm/grant_table.h index 600fb10669..8b7880d3ed 100644 --- a/xen/arch/riscv/include/asm/grant_table.h +++ b/xen/arch/riscv/include/asm/grant_table.h @@ -1,4 +1,61 @@ #ifndef __ASM_RISCV_GRANTTABLE_H__ #define __ASM_RISCV_GRANTTABLE_H__ =20 +#define INITIAL_NR_GRANT_FRAMES 1U + +#define gnttab_shared_page(t, i) virt_to_page((t)->shared_raw[i]) + +#define gnttab_status_page(t, i) virt_to_page((t)->status[i]) + +#define gnttab_shared_gfn(d, t, i) \ + page_get_xenheap_gfn(gnttab_shared_page(t, i)) + +#define gnttab_status_gfn(d, t, i) \ + page_get_xenheap_gfn(gnttab_status_page(t, i)) + +#define gnttab_set_frame_gfn(gt, st, idx, gfn, mfn) \ + (gfn_eq(gfn, INVALID_GFN) \ + ? guest_physmap_remove_page((gt)->domain, \ + gnttab_get_frame_gfn(gt, st, idx), \ + mfn, 0) \ + : 0) + +#define gnttab_get_frame_gfn(gt, st, idx) ({ \ + (st) ? gnttab_status_gfn(NULL, gt, idx) \ + : gnttab_shared_gfn(NULL, gt, idx); \ +}) + +#define gnttab_need_iommu_mapping(d) \ + (is_domain_direct_mapped(d) && is_iommu_enabled(d)) + +static inline bool gnttab_release_host_mappings(const struct domain *d) +{ + BUG(); +} + +static inline void gnttab_mark_dirty(struct domain *d, mfn_t mfn) +{ +#ifndef NDEBUG + printk_once(XENLOG_G_WARNING "gnttab_mark_dirty not implemented yet\n"= ); +#endif +} + +static inline void gnttab_clear_flags(struct domain *d, + unsigned int mask, uint16_t *addr) +{ + BUG(); +} + +static inline bool gnttab_host_mapping_get_page_type(bool ro, + const struct domain *= ld, + const struct domain *= rd) +{ + return false; +} + +int create_grant_host_mapping(uint64_t gpaddr, mfn_t frame, + unsigned int flags, unsigned int cache_flags= ); +int replace_grant_host_mapping(uint64_t gpaddr, mfn_t frame, + uint64_t new_gpaddr, unsigned int flags); + #endif /* __ASM_RISCV_GRANTTABLE_H__ */ \ No newline at end of file diff --git a/xen/arch/riscv/include/asm/guest_atomics.h b/xen/arch/riscv/in= clude/asm/guest_atomics.h index 71b0b11a25..8c8fd647d6 100644 --- a/xen/arch/riscv/include/asm/guest_atomics.h +++ b/xen/arch/riscv/include/asm/guest_atomics.h @@ -35,9 +35,23 @@ guest_testop(test_and_change_bit) =20 #undef guest_testop =20 - #define guest_test_bit(d, nr, p) ((void)(d), test_bit(nr, p)) =20 +#define guest_cmpxchg(d, ptr, o, n) \ + ((__typeof__(*(ptr)))__guest_cmpxchg(d, ptr, \ + (unsigned long)(o),\ + (unsigned long)(n),\ + sizeof (*(ptr)))) + +static always_inline unsigned long __guest_cmpxchg(struct domain *d, + volatile void *ptr, + unsigned long old, + unsigned long new, + unsigned int size) +{ + BUG(); +} + #endif /* __ASM_RISCV_GUEST_ATOMICS_H */ /* * Local variables: diff --git a/xen/arch/riscv/include/asm/livepatch.h b/xen/arch/riscv/includ= e/asm/livepatch.h new file mode 100644 index 0000000000..e69de29bb2 diff --git a/xen/arch/riscv/include/asm/mm.h b/xen/arch/riscv/include/asm/m= m.h index 1d464afec9..37916f9be7 100644 --- a/xen/arch/riscv/include/asm/mm.h +++ b/xen/arch/riscv/include/asm/mm.h @@ -276,4 +276,9 @@ void setup_initial_pagetables(void); void enable_mmu(void); void cont_after_mmu_is_enabled(void); =20 +static inline gfn_t page_get_xenheap_gfn(const struct page_info *p) +{ + BUG(); +} + #endif /* _ASM_RISCV_MM_H */ diff --git a/xen/arch/riscv/include/asm/p2m.h b/xen/arch/riscv/include/asm/= p2m.h index 993aec6d2c..8537ce12fd 100644 --- a/xen/arch/riscv/include/asm/p2m.h +++ b/xen/arch/riscv/include/asm/p2m.h @@ -29,6 +29,28 @@ typedef enum { p2m_max_real_type, /* Types after this won't be store in the p2m */ } p2m_type_t; =20 +/* We use bitmaps and mask to handle groups of types */ +#define p2m_to_mask(_t) (1UL << (_t)) + +/* RAM types, which map to real machine frames */ +#define P2M_RAM_TYPES (p2m_to_mask(p2m_ram_rw) | \ + p2m_to_mask(p2m_ram_ro)) + +/* Grant mapping types, which map to a real frame in another VM */ +#define P2M_GRANT_TYPES (p2m_to_mask(p2m_grant_map_rw) | \ + p2m_to_mask(p2m_grant_map_ro)) + +/* Foreign mappings types */ +#define P2M_FOREIGN_TYPES (p2m_to_mask(p2m_map_foreign_rw) | \ + p2m_to_mask(p2m_map_foreign_ro)) + +/* Useful predicates */ +#define p2m_is_ram(_t) (p2m_to_mask(_t) & P2M_RAM_TYPES) +#define p2m_is_foreign(_t) (p2m_to_mask(_t) & P2M_FOREIGN_TYPES) +#define p2m_is_any_ram(_t) (p2m_to_mask(_t) & \ + (P2M_RAM_TYPES | P2M_GRANT_TYPES | \ + P2M_FOREIGN_TYPES)) + #include =20 static inline int get_page_and_type(struct page_info *page, @@ -102,4 +124,6 @@ static inline void p2m_altp2m_check(struct vcpu *v, uin= t16_t idx) /* Not supported on RISCV. */ } =20 +bool is_iomem_page(mfn_t mfn); + #endif /* __ASM_RISCV_P2M_H__ */ \ No newline at end of file diff --git a/xen/arch/riscv/include/asm/page.h b/xen/arch/riscv/include/asm= /page.h index abbae75aaf..52eb517669 100644 --- a/xen/arch/riscv/include/asm/page.h +++ b/xen/arch/riscv/include/asm/page.h @@ -83,6 +83,22 @@ static inline void flush_page_to_ram(unsigned long mfn, = bool sync_icache) BUG(); } =20 +static inline int clean_dcache_va_range(const void *p, unsigned long size) +{ + BUG(); +} + +static inline int invalidate_dcache_va_range(const void *p, unsigned long = size) +{ + BUG(); +} + +static inline int clean_and_invalidate_dcache_va_range + (const void *p, unsigned long size) +{ + BUG(); +} + #endif /* __ASSEMBLY__ */ =20 #endif /* _ASM_RISCV_PAGE_H */ diff --git a/xen/arch/riscv/include/asm/perfc_defn.h b/xen/arch/riscv/inclu= de/asm/perfc_defn.h new file mode 100644 index 0000000000..e69de29bb2 diff --git a/xen/arch/riscv/mm.c b/xen/arch/riscv/mm.c index 0f40641db7..696a1e8448 100644 --- a/xen/arch/riscv/mm.c +++ b/xen/arch/riscv/mm.c @@ -323,3 +323,36 @@ int map_pages_to_xen(unsigned long virt, assert_failed(__func__); return -1; } + +bool is_iomem_page(mfn_t mfn) +{ + BUG(); +} + +int replace_grant_host_mapping(uint64_t gpaddr, mfn_t frame, + uint64_t new_gpaddr, unsigned int flags) +{ + BUG(); +} + +int create_grant_host_mapping(uint64_t gpaddr, mfn_t frame, + unsigned int flags, unsigned int cache_flags) +{ + BUG(); +} + +struct domain *page_get_owner_and_reference(struct page_info *page) +{ + BUG(); +} + +void share_xen_page_with_guest(struct page_info *page, struct domain *d, + enum XENSHARE_flags flags) +{ + BUG(); +} + +bool get_page(struct page_info *page, const struct domain *domain) +{ + BUG(); +} \ No newline at end of file --=20 2.41.0