Also it was added explanation about ignoring of top VA bits
Signed-off-by: Oleksii Kurochko <oleksii.kurochko@gmail.com>
---
Changes in V9:
- Update comment for VM layout description.
---
Changes in V8:
- Add "#ifdef RV_STAGE1_MODE == SATP_MODE_SV39" instead of "#ifdef SV39"
in the comment to VM layout description.
- Update the upper bound of direct map area in VM layout description.
---
Changes in V7:
- Fix range of frametable range in RV64 layout.
- Add ifdef SV39 to the RV64 layout comment to make it explicit that
description if for SV39 mode.
- Add missed row in the RV64 layout table.
---
Changes in V6:
- update comment above the RISCV-64 layout table
- add Slot column to the table with RISCV-64 Layout
- update RV-64 layout table.
---
Changes in V5:
* the patch was introduced in the current patch series.
---
xen/arch/riscv/include/asm/config.h | 36 +++++++++++++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/xen/arch/riscv/include/asm/config.h b/xen/arch/riscv/include/asm/config.h
index 763a922a04..9900d29dab 100644
--- a/xen/arch/riscv/include/asm/config.h
+++ b/xen/arch/riscv/include/asm/config.h
@@ -4,6 +4,42 @@
#include <xen/const.h>
#include <xen/page-size.h>
+/*
+ * RISC-V64 Layout:
+ *
+#if RV_STAGE1_MODE == SATP_MODE_SV39
+ *
+ * From the riscv-privileged doc:
+ * When mapping between narrower and wider addresses,
+ * RISC-V zero-extends a narrower physical address to a wider size.
+ * The mapping between 64-bit virtual addresses and the 39-bit usable
+ * address space of Sv39 is not based on zero-extension but instead
+ * follows an entrenched convention that allows an OS to use one or
+ * a few of the most-significant bits of a full-size (64-bit) virtual
+ * address to quickly distinguish user and supervisor address regions.
+ *
+ * It means that:
+ * top VA bits are simply ignored for the purpose of translating to PA.
+ *
+ * ============================================================================
+ * Start addr | End addr | Size | Slot |area description
+ * ============================================================================
+ * FFFFFFFFC0800000 | FFFFFFFFFFFFFFFF |1016 MB | L2 511 | Unused
+ * FFFFFFFFC0600000 | FFFFFFFFC0800000 | 2 MB | L2 511 | Fixmap
+ * FFFFFFFFC0200000 | FFFFFFFFC0600000 | 4 MB | L2 511 | FDT
+ * FFFFFFFFC0000000 | FFFFFFFFC0200000 | 2 MB | L2 511 | Xen
+ * ... | 1 GB | L2 510 | Unused
+ * 0000003200000000 | 0000007F80000000 | 309 GB | L2 200-509 | Direct map
+ * ... | 1 GB | L2 199 | Unused
+ * 0000003100000000 | 00000031C0000000 | 3 GB | L2 196-198 | Frametable
+ * ... | 1 GB | L2 195 | Unused
+ * 0000003080000000 | 00000030C0000000 | 1 GB | L2 194 | VMAP
+ * ... | 194 GB | L2 0 - 193 | Unused
+ * ============================================================================
+ *
+#endif
+ */
+
#if defined(CONFIG_RISCV_64)
# define LONG_BYTEORDER 3
# define ELFSIZE 64
--
2.40.1On Thu, May 25, 2023 at 06:28:14PM +0300, Oleksii Kurochko wrote: > Also it was added explanation about ignoring of top VA bits > > Signed-off-by: Oleksii Kurochko <oleksii.kurochko@gmail.com> > --- > Changes in V9: > - Update comment for VM layout description. > --- > Changes in V8: > - Add "#ifdef RV_STAGE1_MODE == SATP_MODE_SV39" instead of "#ifdef SV39" > in the comment to VM layout description. > - Update the upper bound of direct map area in VM layout description. > --- > Changes in V7: > - Fix range of frametable range in RV64 layout. > - Add ifdef SV39 to the RV64 layout comment to make it explicit that > description if for SV39 mode. > - Add missed row in the RV64 layout table. > --- > Changes in V6: > - update comment above the RISCV-64 layout table > - add Slot column to the table with RISCV-64 Layout > - update RV-64 layout table. > --- > Changes in V5: > * the patch was introduced in the current patch series. > --- > xen/arch/riscv/include/asm/config.h | 36 +++++++++++++++++++++++++++++ > 1 file changed, 36 insertions(+) > > diff --git a/xen/arch/riscv/include/asm/config.h b/xen/arch/riscv/include/asm/config.h > index 763a922a04..9900d29dab 100644 > --- a/xen/arch/riscv/include/asm/config.h > +++ b/xen/arch/riscv/include/asm/config.h > @@ -4,6 +4,42 @@ > #include <xen/const.h> > #include <xen/page-size.h> > > +/* > + * RISC-V64 Layout: > + * > +#if RV_STAGE1_MODE == SATP_MODE_SV39 > + * > + * From the riscv-privileged doc: > + * When mapping between narrower and wider addresses, > + * RISC-V zero-extends a narrower physical address to a wider size. > + * The mapping between 64-bit virtual addresses and the 39-bit usable > + * address space of Sv39 is not based on zero-extension but instead > + * follows an entrenched convention that allows an OS to use one or > + * a few of the most-significant bits of a full-size (64-bit) virtual > + * address to quickly distinguish user and supervisor address regions. > + * > + * It means that: > + * top VA bits are simply ignored for the purpose of translating to PA. > + * > + * ============================================================================ > + * Start addr | End addr | Size | Slot |area description > + * ============================================================================ > + * FFFFFFFFC0800000 | FFFFFFFFFFFFFFFF |1016 MB | L2 511 | Unused > + * FFFFFFFFC0600000 | FFFFFFFFC0800000 | 2 MB | L2 511 | Fixmap > + * FFFFFFFFC0200000 | FFFFFFFFC0600000 | 4 MB | L2 511 | FDT > + * FFFFFFFFC0000000 | FFFFFFFFC0200000 | 2 MB | L2 511 | Xen > + * ... | 1 GB | L2 510 | Unused > + * 0000003200000000 | 0000007F80000000 | 309 GB | L2 200-509 | Direct map > + * ... | 1 GB | L2 199 | Unused > + * 0000003100000000 | 00000031C0000000 | 3 GB | L2 196-198 | Frametable > + * ... | 1 GB | L2 195 | Unused > + * 0000003080000000 | 00000030C0000000 | 1 GB | L2 194 | VMAP > + * ... | 194 GB | L2 0 - 193 | Unused > + * ============================================================================ > + * > +#endif > + */ > + > #if defined(CONFIG_RISCV_64) > # define LONG_BYTEORDER 3 > # define ELFSIZE 64 > -- > 2.40.1 > > Acked-by: Bobby Eshleman <bobbyeshleman@gmail.com>
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