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charset="utf-8" Also it was added explanation about ignoring of top VA bits Signed-off-by: Oleksii Kurochko --- Changes in V5: * the patch was introduced in the current patch series. --- xen/arch/riscv/include/asm/config.h | 31 +++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/xen/arch/riscv/include/asm/config.h b/xen/arch/riscv/include/a= sm/config.h index 763a922a04..0c860e88ce 100644 --- a/xen/arch/riscv/include/asm/config.h +++ b/xen/arch/riscv/include/asm/config.h @@ -4,6 +4,37 @@ #include #include =20 +/* + * RISC-V64 Layout: + * + * From the riscv-privileged doc: + * When mapping between narrower and wider addresses, + * RISC-V zero-extends a narrower physical address to a wider size. + * The mapping between 64-bit virtual addresses and the 39-bit usable + * address space of Sv39 is not based on zero-extension but instead + * follows an entrenched convention that allows an OS to use one or + * a few of the most-significant bits of a full-size (64-bit) virtual + * address to quickly distinguish user and supervisor address regions. + * + * It means that: + * top VA bits are simply ignored for the purpose of translating to PA. + * + * The similar is true for other Sv{32, 39, 48, 57}. + * + * =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D + * Start addr | End addr | Size | VM area description + * =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D + * FFFFFFFFC0000000 | FFFFFFFFC0200000 | 2 MB | Xen + * FFFFFFFFC0200000 | FFFFFFFFC0600000 | 4 MB | FDT + * FFFFFFFFC0600000 | FFFFFFFFC0800000 | 2 MB | Fixmap + * .................. unused .................. + * 0000003200000000 | 0000007f40000000 | 331 GB | Direct map(L2 slot: 200= -509) + * 0000003100000000 | 0000003140000000 | 1 GB | Frametable(L2 slot: 196= -197) + * 0000003080000000 | 00000030c0000000 | 1 GB | VMAP (L2 slot: 194-195) + * .................. unused .................. + * =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D + */ + #if defined(CONFIG_RISCV_64) # define LONG_BYTEORDER 3 # define ELFSIZE 64 --=20 2.39.2 From nobody Tue May 14 02:03:37 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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([94.75.70.14]) by smtp.gmail.com with ESMTPSA id f3-20020a2e6a03000000b00298dc945e9bsm2945367ljc.125.2023.04.19.08.42.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Apr 2023 08:42:51 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: d89d7361-dec8-11ed-b21f-6b7b168915f2 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1681918972; x=1684510972; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=eU8aCTHu5cx3tQ+vk3d1bAbIO58Fbf4v0HDH4HjO7+4=; b=JiK7IdRj93qlr2R4RtSIXjyyYBe1t/jKa59RncxWQ6D+kFeEyuqzR0X9cglj1hO3we 8R3EzeWKoEBkhonxKgNTZ+wDaI394FgJIjYnEVXHz7iAn1XV21IwSL9jmwBP+qFwESXS VV+YaWeO7ia5fAqRMNXlUkbXvugaL67f5ANKmpMtMP+z3Xji3LT47YoU6NVHtWQ9uU2E VQ5XuVUhWcM96F74kbv/W6xg9xHsccuHwYbrYIs7tAYdGdLK3nrIQi+5VBKKIf6pNhWe 8Wkz74HKyMtZ/aIMRWwiencU2Vrp3Uimmv4YcCWOR3iegvfksLKAAeiLEuKZNb1/VBYe 9glQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681918972; x=1684510972; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=eU8aCTHu5cx3tQ+vk3d1bAbIO58Fbf4v0HDH4HjO7+4=; b=dX+B4TGVFM0yIfHsLD2MQMuOSkF3Mgzw8MGQW9/bYX/x6OLbLleF707l2b/URVsf0Z kCV/2tpf0BKylht3w90dwBx1mQDOJVyFU1L+BumjqGBMfi6T5aLGQVWOZSM3yovd7iff n/M2OzxaN9nrR+DGhzH97qodwDv6BdH9fE3qQdYI+NM8M/e4ovyL0kwyUUM4Q30s8vf7 clJWK3uBXM8xhkZWFBYGDOxIvF9wADqvTJA824OD9A+04XCbUuYoJFlv5eAZHmj2nD7Q wH3+2oFKmHOo9Sk3qubKgQpSH/IH3jlQPCPrQD4MW0nPXMhtQ9urIb7c40NvvaMbJJkE WGFw== X-Gm-Message-State: AAQBX9egf1ibuK573rOFWEEbplI/Q56YYsMV2Q5aU79TY/8dbGbnKFms K4CChcbQuE5KkOH9jh/JpTYPnAFNCIQ= X-Google-Smtp-Source: AKy350YOFdTDwM6B9aRXvknZa9os+TpNvP67EHugiVHuAhSKXhdw+/ohj5KMFR9SNi/rttLsGYJ68A== X-Received: by 2002:a2e:9209:0:b0:2a8:ea9c:116a with SMTP id k9-20020a2e9209000000b002a8ea9c116amr1200016ljg.42.1681918971946; Wed, 19 Apr 2023 08:42:51 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Julien Grall , Jan Beulich , Andrew Cooper , Stefano Stabellini , Gianluca Guida , Oleksii Kurochko , Bob Eshleman , Alistair Francis , Connor Davis Subject: [PATCH v5 2/4] xen/riscv: introduce setup_initial_pages Date: Wed, 19 Apr 2023 18:42:45 +0300 Message-Id: <5b27693bcdf6d64381314aeef72cfe03dee8d73a.1681918194.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1681919011742100002 Content-Type: text/plain; charset="utf-8" The idea was taken from xvisor but the following changes were done: * Use only a minimal part of the code enough to enable MMU * rename {_}setup_initial_pagetables functions * add an argument for setup_initial_mapping to have an opportunity to make set PTE flags. * update setup_initial_pagetables function to map sections with correct PTE flags. * Rewrite enable_mmu() to C. * map linker addresses range to load addresses range without 1:1 mapping. It will be 1:1 only in case when load_start_addr is equal to linker_start_addr. * add safety checks such as: * Xen size is less than page size * linker addresses range doesn't overlap load addresses range * Rework macros {THIRD,SECOND,FIRST,ZEROETH}_{SHIFT,MASK} * change PTE_LEAF_DEFAULT to RW instead of RWX. * Remove phys_offset as it is not used now * Remove alignment of {map, pa}_start &=3D XEN_PT_LEVEL_MAP_MASK(0); in setup_inital_mapping() as they should be already aligned. Make a check that {map_pa}_start are aligned. * Remove clear_pagetables() as initial pagetables will be zeroed during bss initialization * Remove __attribute__((section(".entry")) for setup_initial_pagetables() as there is no such section in xen.lds.S * Update the argument of pte_is_valid() to "const pte_t *p" * Add check that Xen's load address is aligned at 4k boundary * Refactor setup_initial_pagetables() so it is mapping linker address range to load address range. After setup needed permissions for specific section ( such as .text, .rodata, etc ) otherwise RW permission will be set by default. * Add function to check that requested SATP_MODE is supported Origin: git@github.com:xvisor/xvisor.git 9be2fdd7 Signed-off-by: Oleksii Kurochko --- Changes in V5: * Indent fields of pte_t struct * Rename addr_to_pte() and ppn_to_paddr() to match their content --- Changes in V4: * use GB() macros instead of defining SZ_1G * hardcode XEN_VIRT_START and add comment (ADDRESS_SPACE_END + 1 - GB(1)) * remove unnecessary 'asm' word at the end of #error * encapsulate pte_t definition in a struct * rename addr_to_ppn() to ppn_to_paddr(). * change type of paddr argument from const unsigned long to paddr_t * pte_to_paddr() update prototype. * calculate size of Xen binary based on an amount of page tables * use unsgined int instead of 'uint32_t' instead of uint32_t as their use isn't warranted. * remove extern of bss_{start,end} as they aren't used in mm.c anymore * fix code style * add argument for HANDLE_PGTBL macros instead of curr_lvl_num variable * make enable_mmu() as noinline to prevent under link-time optimization because of the nature of enable_mmu() * add function to check that SATP_MODE is supported. * update the commit message * update setup_initial_pagetables to set correct PTE flags in one pass instead of calling setup_pte_permissions after setup_initial_pagetables= () as setup_initial_pagetables() isn't used to change permission flags. --- Changes in V3: - update definition of pte_t structure to have a proper size of pte_t in case of RV32. - update asm/mm.h with new functions and remove unnecessary 'extern'. - remove LEVEL_* macros as only XEN_PT_LEVEL_* are enough. - update paddr_to_pte() to receive permissions as an argument. - add check that map_start & pa_start is properly aligned. - move defines PAGETABLE_ORDER, PAGETABLE_ENTRIES, PTE_PPN_SHIFT to - Rename PTE_SHIFT to PTE_PPN_SHIFT - refactor setup_initial_pagetables: map all LINK addresses to LOAD addres= ses and after setup PTEs permission for sections; update check that linker and load addresses don't overlap. - refactor setup_initial_mapping: allocate pagetable 'dynamically' if it is necessary. - rewrite enable_mmu in C; add the check that map_start and pa_start are aligned on 4k boundary. - update the comment for setup_initial_pagetable funcion - Add RV_STAGE1_MODE to support different MMU modes - set XEN_VIRT_START very high to not overlap with load address range - align bss section --- Changes in V2: * update the commit message: * Remove {ZEROETH,FIRST,...}_{SHIFT,MASK, SIZE,...} and introduce instead of them XEN_PT_LEVEL_*() and LEVEL_* * Rework pt_linear_offset() and pt_index based on XEN_PT_LEVEL_*() * Remove clear_pagetables() functions as pagetables were zeroed during .bss initialization * Rename _setup_initial_pagetables() to setup_initial_mapping() * Make PTE_DEFAULT equal to RX. * Update prototype of setup_initial_mapping(..., bool writable) ->=20 setup_initial_mapping(..., UL flags) =20 * Update calls of setup_initial_mapping according to new prototype * Remove unnecessary call of: _setup_initial_pagetables(..., load_addr_start, load_addr_end, load_addr= _start, ...) * Define index* in the loop of setup_initial_mapping * Remove attribute "__attribute__((section(".entry")))" for setup_initial_= pagetables() as we don't have such section * make arguments of paddr_to_pte() and pte_is_valid() as const. * make xen_second_pagetable static. * use instead of declaring extern unsigned long _stext, 0et= ext, _srodata, _erodata * update 'extern unsigned long __init_begin' to 'extern unsigned long __i= nit_begin[]' * use aligned() instead of "__attribute__((__aligned__(PAGE_SIZE)))" * set __section(".bss.page_aligned") for page tables arrays * fix identatations * Change '__attribute__((section(".entry")))' to '__init' * Remove phys_offset as it isn't used now. * Remove alignment of {map, pa}_start &=3D XEN_PT_LEVEL_MAP_MASK(0); in setup_inital_mapping() as they should be already aligned. * Remove clear_pagetables() as initial pagetables will be zeroed during bss initialization * Remove __attribute__((section(".entry")) for setup_initial_pagetables() as there is no such section in xen.lds.S * Update the argument of pte_is_valid() to "const pte_t *p" --- xen/arch/riscv/Makefile | 1 + xen/arch/riscv/include/asm/config.h | 12 +- xen/arch/riscv/include/asm/mm.h | 9 + xen/arch/riscv/include/asm/page-bits.h | 10 + xen/arch/riscv/include/asm/page.h | 63 +++++ xen/arch/riscv/mm.c | 319 +++++++++++++++++++++++++ xen/arch/riscv/riscv64/head.S | 2 + xen/arch/riscv/setup.c | 11 + xen/arch/riscv/xen.lds.S | 4 + 9 files changed, 430 insertions(+), 1 deletion(-) create mode 100644 xen/arch/riscv/include/asm/mm.h create mode 100644 xen/arch/riscv/include/asm/page.h create mode 100644 xen/arch/riscv/mm.c diff --git a/xen/arch/riscv/Makefile b/xen/arch/riscv/Makefile index 443f6bf15f..956ceb02df 100644 --- a/xen/arch/riscv/Makefile +++ b/xen/arch/riscv/Makefile @@ -1,5 +1,6 @@ obj-$(CONFIG_EARLY_PRINTK) +=3D early_printk.o obj-y +=3D entry.o +obj-y +=3D mm.o obj-$(CONFIG_RISCV_64) +=3D riscv64/ obj-y +=3D sbi.o obj-y +=3D setup.o diff --git a/xen/arch/riscv/include/asm/config.h b/xen/arch/riscv/include/a= sm/config.h index 0c860e88ce..4cd4f7a701 100644 --- a/xen/arch/riscv/include/asm/config.h +++ b/xen/arch/riscv/include/asm/config.h @@ -70,12 +70,22 @@ name: #endif =20 -#define XEN_VIRT_START _AT(UL, 0x80200000) +#ifdef CONFIG_RISCV_64 +#define XEN_VIRT_START 0xFFFFFFFFC0000000 /* (_AC(-1, UL) + 1 - GB(1)) */ +#else +#error "RV32 isn't supported" +#endif =20 #define SMP_CACHE_BYTES (1 << 6) =20 #define STACK_SIZE PAGE_SIZE =20 +#ifdef CONFIG_RISCV_64 +#define RV_STAGE1_MODE SATP_MODE_SV39 +#else +#define RV_STAGE1_MODE SATP_MODE_SV32 +#endif + #endif /* __RISCV_CONFIG_H__ */ /* * Local variables: diff --git a/xen/arch/riscv/include/asm/mm.h b/xen/arch/riscv/include/asm/m= m.h new file mode 100644 index 0000000000..e16ce66fae --- /dev/null +++ b/xen/arch/riscv/include/asm/mm.h @@ -0,0 +1,9 @@ +#ifndef _ASM_RISCV_MM_H +#define _ASM_RISCV_MM_H + +void setup_initial_pagetables(void); + +void enable_mmu(void); +void cont_after_mmu_is_enabled(void); + +#endif /* _ASM_RISCV_MM_H */ diff --git a/xen/arch/riscv/include/asm/page-bits.h b/xen/arch/riscv/includ= e/asm/page-bits.h index 1801820294..0879a527f2 100644 --- a/xen/arch/riscv/include/asm/page-bits.h +++ b/xen/arch/riscv/include/asm/page-bits.h @@ -1,6 +1,16 @@ #ifndef __RISCV_PAGE_BITS_H__ #define __RISCV_PAGE_BITS_H__ =20 +#ifdef CONFIG_RISCV_64 +#define PAGETABLE_ORDER (9) +#else /* CONFIG_RISCV_32 */ +#define PAGETABLE_ORDER (10) +#endif + +#define PAGETABLE_ENTRIES (1 << PAGETABLE_ORDER) + +#define PTE_PPN_SHIFT 10 + #define PAGE_SHIFT 12 /* 4 KiB Pages */ #define PADDR_BITS 56 /* 44-bit PPN */ =20 diff --git a/xen/arch/riscv/include/asm/page.h b/xen/arch/riscv/include/asm= /page.h new file mode 100644 index 0000000000..daa880558e --- /dev/null +++ b/xen/arch/riscv/include/asm/page.h @@ -0,0 +1,63 @@ +#ifndef _ASM_RISCV_PAGE_H +#define _ASM_RISCV_PAGE_H + +#include +#include + +#define VPN_MASK ((unsigned long)(PAGETABLE_ENTRIES - 1= )) + +#define XEN_PT_LEVEL_ORDER(lvl) ((lvl) * PAGETABLE_ORDER) +#define XEN_PT_LEVEL_SHIFT(lvl) (XEN_PT_LEVEL_ORDER(lvl) + PAGE_SHIFT) +#define XEN_PT_LEVEL_SIZE(lvl) (_AT(paddr_t, 1) << XEN_PT_LEVEL_SHIFT= (lvl)) +#define XEN_PT_LEVEL_MAP_MASK(lvl) (~(XEN_PT_LEVEL_SIZE(lvl) - 1)) +#define XEN_PT_LEVEL_MASK(lvl) (VPN_MASK << XEN_PT_LEVEL_SHIFT(lvl)) + +#define PTE_VALID BIT(0, UL) +#define PTE_READABLE BIT(1, UL) +#define PTE_WRITABLE BIT(2, UL) +#define PTE_EXECUTABLE BIT(3, UL) +#define PTE_USER BIT(4, UL) +#define PTE_GLOBAL BIT(5, UL) +#define PTE_ACCESSED BIT(6, UL) +#define PTE_DIRTY BIT(7, UL) +#define PTE_RSW (BIT(8, UL) | BIT(9, UL)) + +#define PTE_LEAF_DEFAULT (PTE_VALID | PTE_READABLE | PTE_WRITAB= LE) +#define PTE_TABLE (PTE_VALID) + +/* Calculate the offsets into the pagetables for a given VA */ +#define pt_linear_offset(lvl, va) ((va) >> XEN_PT_LEVEL_SHIFT(lvl)) + +#define pt_index(lvl, va) pt_linear_offset(lvl, (va) & XEN_PT_LEVEL_MASK(l= vl)) + +/* Page Table entry */ +typedef struct { +#ifdef CONFIG_RISCV_64 + uint64_t pte; +#else + uint32_t pte; +#endif +} pte_t; + +#define pte_to_addr(x) (((x) >> PTE_PPN_SHIFT) << PAGE_SHIFT) + +#define addr_to_pte(x) (((x) >> PAGE_SHIFT) << PTE_PPN_SHIFT) + +static inline pte_t paddr_to_pte(const paddr_t paddr, + const unsigned long permissions) +{ + unsigned long tmp =3D addr_to_pte(paddr); + return (pte_t) { .pte =3D tmp | permissions }; +} + +static inline paddr_t pte_to_paddr(const pte_t pte) +{ + return pte_to_addr(pte.pte); +} + +static inline bool pte_is_valid(const pte_t p) +{ + return p.pte & PTE_VALID; +} + +#endif /* _ASM_RISCV_PAGE_H */ diff --git a/xen/arch/riscv/mm.c b/xen/arch/riscv/mm.c new file mode 100644 index 0000000000..43b7181c33 --- /dev/null +++ b/xen/arch/riscv/mm.c @@ -0,0 +1,319 @@ +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +struct mmu_desc { + unsigned long num_levels; + unsigned int pgtbl_count; + pte_t *next_pgtbl; + pte_t *pgtbl_base; +}; + +extern unsigned char cpu0_boot_stack[STACK_SIZE]; + +#define PHYS_OFFSET ((unsigned long)_start - XEN_VIRT_START) +#define LOAD_TO_LINK(addr) ((addr) - PHYS_OFFSET) +#define LINK_TO_LOAD(addr) ((addr) + PHYS_OFFSET) + + +/* + * It is expected that Xen won't be more then 2 MB. + * The check in xen.lds.S guarantees that. + * At least 4 page (in case when Sv48 or Sv57 are used ) + * tables are needed to cover 2 MB. One for each page level + * table with PAGE_SIZE =3D 4 Kb + * + * One L0 page table can cover 2 MB + * (512 entries of one page table * PAGE_SIZE). + * + * It might be needed one more page table in case when + * Xen load address isn't 2 MB aligned. + * + */ +#define PGTBL_INITIAL_COUNT (5) + +#define PGTBL_ENTRY_AMOUNT (PAGE_SIZE / sizeof(pte_t)) + +pte_t __section(".bss.page_aligned") __aligned(PAGE_SIZE) +stage1_pgtbl_root[PGTBL_ENTRY_AMOUNT]; + +pte_t __section(".bss.page_aligned") __aligned(PAGE_SIZE) +stage1_pgtbl_nonroot[PGTBL_INITIAL_COUNT * PGTBL_ENTRY_AMOUNT]; + +#define HANDLE_PGTBL(curr_lvl_num) = \ + index =3D pt_index(curr_lvl_num, page_addr); = \ + if ( pte_is_valid(pgtbl[index]) ) = \ + { = \ + /* Find L{ 0-3 } table */ = \ + pgtbl =3D (pte_t *)pte_to_paddr(pgtbl[index]); = \ + } = \ + else = \ + { = \ + /* Allocate new L{0-3} page table */ = \ + if ( mmu_desc->pgtbl_count =3D=3D PGTBL_INITIAL_COUNT ) = \ + { = \ + early_printk("(XEN) No initial table available\n"); = \ + /* panic(), BUG() or ASSERT() aren't ready now. */ = \ + die(); = \ + } = \ + mmu_desc->pgtbl_count++; = \ + pgtbl[index] =3D paddr_to_pte((unsigned long)mmu_desc->next_pgtbl,= \ + PTE_VALID); = \ + pgtbl =3D mmu_desc->next_pgtbl; = \ + mmu_desc->next_pgtbl +=3D PGTBL_ENTRY_AMOUNT; = \ + } + +static void __init setup_initial_mapping(struct mmu_desc *mmu_desc, + unsigned long map_start, + unsigned long map_end, + unsigned long pa_start, + unsigned long permissions) +{ + unsigned int index; + pte_t *pgtbl; + unsigned long page_addr; + pte_t pte_to_be_written; + unsigned long paddr; + unsigned long tmp_permissions; + + if ( (unsigned long)_start % XEN_PT_LEVEL_SIZE(0) ) + { + early_printk("(XEN) Xen should be loaded at 4k boundary\n"); + die(); + } + + if ( map_start & ~XEN_PT_LEVEL_MAP_MASK(0) || + pa_start & ~XEN_PT_LEVEL_MAP_MASK(0) ) + { + early_printk("(XEN) map and pa start addresses should be aligned\n= "); + /* panic(), BUG() or ASSERT() aren't ready now. */ + die(); + } + + page_addr =3D map_start; + while ( page_addr < map_end ) + { + pgtbl =3D mmu_desc->pgtbl_base; + + switch (mmu_desc->num_levels) + { + case 4: /* Level 3 */ + HANDLE_PGTBL(3); + case 3: /* Level 2 */ + HANDLE_PGTBL(2); + case 2: /* Level 1 */ + HANDLE_PGTBL(1); + case 1: /* Level 0 */ + index =3D pt_index(0, page_addr); + paddr =3D (page_addr - map_start) + pa_start; + + tmp_permissions =3D permissions; + + if ( is_kernel_text(LINK_TO_LOAD(page_addr)) || + is_kernel_inittext(LINK_TO_LOAD(page_addr)) ) + tmp_permissions =3D + PTE_EXECUTABLE | PTE_READABLE | PTE_VALID; + + if ( is_kernel_rodata(LINK_TO_LOAD(page_addr)) ) + tmp_permissions =3D PTE_READABLE | PTE_VALID; + + pte_to_be_written =3D paddr_to_pte(paddr, tmp_permissions); + + if ( !pte_is_valid(pgtbl[index]) ) + pgtbl[index] =3D pte_to_be_written; + else + { + /* + * get an adresses of current pte and that one to + * be written without permission flags + */ + unsigned long curr_pte =3D + pgtbl[index].pte & ~((1 << PTE_PPN_SHIFT) - 1); + + pte_to_be_written.pte &=3D ~((1 << PTE_PPN_SHIFT) - 1); + + if ( curr_pte !=3D pte_to_be_written.pte ) + { + early_printk("PTE that is intended to write isn't = the" + "same that the once are overwriting\n"= ); + /* panic(), aren't ready now. */ + die(); + } + } + } + + /* Point to next page */ + page_addr +=3D XEN_PT_LEVEL_SIZE(0); + } +} + +static void __init calc_pgtbl_lvls_num(struct mmu_desc *mmu_desc) +{ + unsigned long satp_mode =3D RV_STAGE1_MODE; + + /* Number of page table levels */ + switch (satp_mode) + { + case SATP_MODE_SV32: + mmu_desc->num_levels =3D 2; + break; + case SATP_MODE_SV39: + mmu_desc->num_levels =3D 3; + break; + case SATP_MODE_SV48: + mmu_desc->num_levels =3D 4; + break; + default: + early_printk("(XEN) Unsupported SATP_MODE\n"); + die(); + } +} + +static bool __init check_pgtbl_mode_support(struct mmu_desc *mmu_desc, + unsigned long load_start, + unsigned long satp_mode) +{ + bool is_mode_supported =3D false; + unsigned int index; + unsigned int page_table_level =3D (mmu_desc->num_levels - 1); + unsigned level_map_mask =3D XEN_PT_LEVEL_MAP_MASK(page_table_level); + + unsigned long aligned_load_start =3D load_start & level_map_mask; + unsigned long aligned_page_size =3D XEN_PT_LEVEL_SIZE(page_table_level= ); + unsigned long xen_size =3D (unsigned long)(_end - start); + + if ( (load_start + xen_size) > (aligned_load_start + aligned_page_size= ) ) + { + early_printk("please place Xen to be in range of PAGE_SIZE " + "where PAGE_SIZE is XEN_PT_LEVEL_SIZE( {L3 | L2 | L1}= ) " + "depending on expected SATP_MODE \n" + "XEN_PT_LEVEL_SIZE is defined in \n"); + die(); + } + + index =3D pt_index(page_table_level, aligned_load_start); + stage1_pgtbl_root[index] =3D paddr_to_pte(aligned_load_start, + PTE_LEAF_DEFAULT | PTE_EXECUTA= BLE); + + asm volatile("sfence.vma"); + csr_write(CSR_SATP, + ((unsigned long)stage1_pgtbl_root >> PAGE_SHIFT) | + satp_mode << SATP_MODE_SHIFT); + + if ( (csr_read(CSR_SATP) >> SATP_MODE_SHIFT) =3D=3D satp_mode ) + is_mode_supported =3D true; + + /* Clean MMU root page table and disable MMU */ + stage1_pgtbl_root[index] =3D paddr_to_pte(0x0, 0x0); + + csr_write(CSR_SATP, 0); + asm volatile("sfence.vma"); + + return is_mode_supported; +} + +/* + * setup_initial_pagetables: + * + * Build the page tables for Xen that map the following: + * 1. Calculate page table's level numbers. + * 2. Init mmu description structure. + * 3. Check that linker addresses range doesn't overlap + * with load addresses range + * 4. Map all linker addresses and load addresses ( it shouldn't + * be 1:1 mapped and will be 1:1 mapped only in case if + * linker address is equal to load address ) with + * RW permissions by default. + * 5. Setup proper PTE permissions for each section. + */ +void __init setup_initial_pagetables(void) +{ + struct mmu_desc mmu_desc =3D { 0, 0, NULL, 0 }; + + /* + * Access to _{stard, end } is always PC-relative + * thereby when access them we will get load adresses + * of start and end of Xen + * To get linker addresses LOAD_TO_LINK() is required + * to use + */ + unsigned long load_start =3D (unsigned long)_start; + unsigned long load_end =3D (unsigned long)_end; + unsigned long linker_start =3D LOAD_TO_LINK(load_start); + unsigned long linker_end =3D LOAD_TO_LINK(load_end); + + if ( (linker_start !=3D load_start) && + (linker_start <=3D load_end) && (load_start <=3D linker_end) ) { + early_printk("(XEN) linker and load address ranges overlap\n"); + die(); + } + + calc_pgtbl_lvls_num(&mmu_desc); + + if ( !check_pgtbl_mode_support(&mmu_desc, load_start, RV_STAGE1_MODE) ) + { + early_printk("requested MMU mode isn't supported by CPU\n" + "Please choose different in \n"); + die(); + } + + mmu_desc.pgtbl_base =3D stage1_pgtbl_root; + mmu_desc.next_pgtbl =3D stage1_pgtbl_nonroot; + + setup_initial_mapping(&mmu_desc, + linker_start, + linker_end, + load_start, + PTE_LEAF_DEFAULT); +} + +void __init noinline enable_mmu() +{ + /* + * Calculate a linker time address of the mmu_is_enabled + * label and update CSR_STVEC with it. + * MMU is configured in a way where linker addresses are mapped + * on load addresses so in a case when linker addresses are not equal + * to load addresses, after MMU is enabled, it will cause + * an exception and jump to linker time addresses. + * Otherwise if load addresses are equal to linker addresses the code + * after mmu_is_enabled label will be executed without exception. + */ + csr_write(CSR_STVEC, LOAD_TO_LINK((unsigned long)&&mmu_is_enabled)); + + /* Ensure page table writes precede loading the SATP */ + asm volatile("sfence.vma"); + + /* Enable the MMU and load the new pagetable for Xen */ + csr_write(CSR_SATP, + ((unsigned long)stage1_pgtbl_root >> PAGE_SHIFT) | + RV_STAGE1_MODE << SATP_MODE_SHIFT); + + asm volatile(".align 2"); + mmu_is_enabled: + /* + * Stack should be re-inited as: + * 1. Right now an address of the stack is relative to load time + * addresses what will cause an issue in case of load start address + * isn't equal to linker start address. + * 2. Addresses in stack are all load time relative which can be an + * issue in case when load start address isn't equal to linker + * start address. + */ + asm volatile ("mv sp, %0" : : "r"((unsigned long)cpu0_boot_stack + STA= CK_SIZE)); + + /* + * We can't return to the caller because the stack was reseted + * and it may have stash some variable on the stack. + * Jump to a brand new function as the stack was reseted + */ + cont_after_mmu_is_enabled(); +} + diff --git a/xen/arch/riscv/riscv64/head.S b/xen/arch/riscv/riscv64/head.S index 8887f0cbd4..b3309d902c 100644 --- a/xen/arch/riscv/riscv64/head.S +++ b/xen/arch/riscv/riscv64/head.S @@ -1,4 +1,5 @@ #include +#include #include =20 .section .text.header, "ax", %progbits @@ -32,3 +33,4 @@ ENTRY(start) add sp, sp, t0 =20 tail start_xen + diff --git a/xen/arch/riscv/setup.c b/xen/arch/riscv/setup.c index 3786f337e0..315804aa87 100644 --- a/xen/arch/riscv/setup.c +++ b/xen/arch/riscv/setup.c @@ -2,6 +2,7 @@ #include =20 #include +#include =20 /* Xen stack for bringing up the first CPU. */ unsigned char __initdata cpu0_boot_stack[STACK_SIZE] @@ -26,3 +27,13 @@ void __init noreturn start_xen(unsigned long bootcpu_id, =20 unreachable(); } + +void __init noreturn cont_after_mmu_is_enabled(void) +{ + early_printk("All set up\n"); + + for ( ;; ) + asm volatile ("wfi"); + + unreachable(); +} diff --git a/xen/arch/riscv/xen.lds.S b/xen/arch/riscv/xen.lds.S index 31e0d3576c..2f7f76bee6 100644 --- a/xen/arch/riscv/xen.lds.S +++ b/xen/arch/riscv/xen.lds.S @@ -136,6 +136,7 @@ SECTIONS . =3D ALIGN(POINTER_ALIGN); __init_end =3D .; =20 + . =3D ALIGN(PAGE_SIZE); .bss : { /* BSS */ __bss_start =3D .; *(.bss.stack_aligned) @@ -172,3 +173,6 @@ ASSERT(IS_ALIGNED(__bss_end, POINTER_ALIGN), "__= bss_end is misaligned") =20 ASSERT(!SIZEOF(.got), ".got non-empty") ASSERT(!SIZEOF(.got.plt), ".got.plt non-empty") + +ASSERT(_end - _start <=3D MB(2), "Xen too large for early-boot assumptions= ") + --=20 2.39.2 From nobody Tue May 14 02:03:37 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1681919010; cv=none; d=zohomail.com; s=zohoarc; b=Yr8YJ2qHCleMmjli2oom+gSuOzWE8EWXpCfyjU9KL2Cb64sOoo43byb2ysLbDkXxSAe+CrN1tJdW8v4kDOJtVbknGBmmJEi8zSa9AjXonFWLaEG9tHRAg/8IjZr57/xybjbbUWpSw0PRV+xHM498ZATsi4yDZFVGr5oAUddEU3E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1681919010; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=sK6lOiJmrrx8EIkDgF6+ULo+pkwl5Br6n5iUV/9+gh0=; b=b5KrdO5vXWrD4WzHuGLtCcSv5CMVjva7MzlsVGP6J+bm79XH0gTnT4O1fYXRxPZrLZ9vypW+i0sofMtHca+7k7rkb2WU/jxFyx1qXNYOVjnbRtg7gW7Pz8YgOD0954nSdqtj6jKqktXsmPMIur8qy270Fh3SJsSKKFlb2CSLEPg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1681919010219286.6645496714856; Wed, 19 Apr 2023 08:43:30 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.523579.813782 (Exim 4.92) (envelope-from ) id 1pp9xQ-0002J5-Ii; Wed, 19 Apr 2023 15:42:56 +0000 Received: by outflank-mailman (output) from mailman id 523579.813782; Wed, 19 Apr 2023 15:42:56 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1pp9xQ-0002Eg-D3; Wed, 19 Apr 2023 15:42:56 +0000 Received: by outflank-mailman (input) for mailman id 523579; Wed, 19 Apr 2023 15:42:55 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1pp9xO-0001fS-WB for xen-devel@lists.xenproject.org; Wed, 19 Apr 2023 15:42:54 +0000 Received: from mail-lj1-x22c.google.com (mail-lj1-x22c.google.com [2a00:1450:4864:20::22c]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id d9091f47-dec8-11ed-8611-37d641c3527e; Wed, 19 Apr 2023 17:42:53 +0200 (CEST) Received: by mail-lj1-x22c.google.com with SMTP id y24so6980342ljm.6 for ; Wed, 19 Apr 2023 08:42:53 -0700 (PDT) Received: from fedora.. ([94.75.70.14]) by smtp.gmail.com with ESMTPSA id f3-20020a2e6a03000000b00298dc945e9bsm2945367ljc.125.2023.04.19.08.42.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Apr 2023 08:42:52 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: d9091f47-dec8-11ed-8611-37d641c3527e DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1681918973; x=1684510973; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=sK6lOiJmrrx8EIkDgF6+ULo+pkwl5Br6n5iUV/9+gh0=; b=JY3+kb4x2B3fIW868V/DEQbhu+mTCUCi1tY01W+zSiNxgxm9xuR3y8tCW4kOQViPIK /RCkVPNQUc4KfL2ShZuG+bT0+PNuDRLZkhIw1xQaVaOqDGdiXJGeXQzLyxqhFM+YkbxK qXw/4BuAUE90ea2JDSeWo1ujNpatGO1FPLbx7I885L15uACE2DjzA20Vx/JgFwWFkpYr g7tUR/jB7BuCYhb2qv2dGuiu00lF+rT70xuwZNAn5zlX7yzWNVNtOfJfWKf2Q9ts9UIe hJM1vfO42IUk4/UFJYhcfHeAILiMpvr/Pye9uTf9k2kCtLPzVjZiAhNV+BDZS04nu383 wqEw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681918973; x=1684510973; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=sK6lOiJmrrx8EIkDgF6+ULo+pkwl5Br6n5iUV/9+gh0=; b=SKQ3xIjjGIxoOQ79mLsmDqmEF338cowCVNKrO/N0GxJoRmkyrGWdegi9nGpBFKMLnG SNMaw/6FBogIvluuCB1U1zQ4U/DoQoHOEimIO2pgRBQXeR2tSrKsZHb2QbQCR2HbN98g cwQK9JxzUKQvPnQvQAnsBOuW8oaIG4ScE9j1rUvxDpxUf5lHZ4Ywr0N0K0fL4mYeIObK oJpQWsf8NGnhvj/iWimSzLk9xNckWSILM5PfsLF7GrK2npUif3js7tfL5bKS7uAHBdXG apnp5+4nFlHep7RiuSk1jdY1J4cRNSxcLVLFevl3mm6XrgSzXx8y+3mGEBLkCIaHhTLx 6kEA== X-Gm-Message-State: AAQBX9cS4HA7z9IjdGEHIPojyUFuk38tvLLVNbu8f8BWZyqX5mnJRyMf OxzEjAgFqwCJLOrUEMCelkc2Sv5bs+M= X-Google-Smtp-Source: AKy350bGcPFjMvPqoJslalD3B9AiEdsxHV+y7m279vTxSFKXJbRv+mXVwElB34h0bTjwCmFPzOHvNw== X-Received: by 2002:a2e:b041:0:b0:2a8:ea22:28b5 with SMTP id d1-20020a2eb041000000b002a8ea2228b5mr1253128ljl.4.1681918972863; Wed, 19 Apr 2023 08:42:52 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Julien Grall , Jan Beulich , Andrew Cooper , Stefano Stabellini , Gianluca Guida , Oleksii Kurochko , Bob Eshleman , Alistair Francis , Connor Davis Subject: [PATCH v5 3/4] xen/riscv: setup initial pagetables Date: Wed, 19 Apr 2023 18:42:46 +0300 Message-Id: X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1681919011646100001 Content-Type: text/plain; charset="utf-8" The patch does two thing: 1. Setup initial pagetables. 2. Enable MMU which end up with code in cont_after_mmu_is_enabled() Signed-off-by: Oleksii Kurochko --- Changes in V5: - Nothing changed. Only rebase --- Changes in V4: - Nothing changed. Only rebase --- Changes in V3: - update the commit message that MMU is also enabled here - remove early_printk("All set up\n") as it was moved to cont_after_mmu_is_enabled() function after MMU is enabled. --- Changes in V2: * Update the commit message --- xen/arch/riscv/setup.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/xen/arch/riscv/setup.c b/xen/arch/riscv/setup.c index 315804aa87..cf5dc5824e 100644 --- a/xen/arch/riscv/setup.c +++ b/xen/arch/riscv/setup.c @@ -21,7 +21,10 @@ void __init noreturn start_xen(unsigned long bootcpu_id, { early_printk("Hello from C env\n"); =20 - early_printk("All set up\n"); + setup_initial_pagetables(); + + enable_mmu(); + for ( ;; ) asm volatile ("wfi"); =20 --=20 2.39.2 From nobody Tue May 14 02:03:37 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1681919008; cv=none; d=zohomail.com; s=zohoarc; b=PUGR11AOTtoH/zCroNj+KsFH3/+7owb+6ch0phthLhGXbE64hcfXWIUBjYSMQRlwZX5OkbiP0w+6EITArnYlow3GRTOqaABog/y06uNpyMqgDrk/C4QtSiBMHZecwQAuh6ZeCxx757RH9aVgm8SZmffTYAcZgOkE+zMC37EAPpY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1681919008; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=d6nuZqH4BFpdEi3VMqbbjTAjUlawv3o6/WP+NDuHGao=; b=E38CCY8ylH9g6wfWG/L81j3GiB3EstpgfAUXN6O2Q2f9BbN+ke7BzMXVYxLA0dA7ep9qUycz+OUuHTeJFA6M0nUsy2bR+XrGQjjcQg7UD+b1nKj5KrKRl0JOplwjRzO/5TKO0O0a7VYSE14/gJ38p8L1xf65PkJkZSze7pvx5BI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 168191900838048.76003311007128; Wed, 19 Apr 2023 08:43:28 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.523578.813774 (Exim 4.92) (envelope-from ) id 1pp9xQ-00025C-0F; Wed, 19 Apr 2023 15:42:56 +0000 Received: by outflank-mailman (output) from mailman id 523578.813774; Wed, 19 Apr 2023 15:42:55 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1pp9xP-00023t-QR; Wed, 19 Apr 2023 15:42:55 +0000 Received: by outflank-mailman (input) for mailman id 523578; Wed, 19 Apr 2023 15:42:54 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1pp9xO-0001fK-QX for xen-devel@lists.xenproject.org; Wed, 19 Apr 2023 15:42:54 +0000 Received: from mail-lj1-x232.google.com (mail-lj1-x232.google.com [2a00:1450:4864:20::232]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id d9981225-dec8-11ed-b21f-6b7b168915f2; Wed, 19 Apr 2023 17:42:54 +0200 (CEST) Received: by mail-lj1-x232.google.com with SMTP id r9so21017386ljp.9 for ; Wed, 19 Apr 2023 08:42:54 -0700 (PDT) Received: from fedora.. ([94.75.70.14]) by smtp.gmail.com with ESMTPSA id f3-20020a2e6a03000000b00298dc945e9bsm2945367ljc.125.2023.04.19.08.42.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Apr 2023 08:42:53 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: d9981225-dec8-11ed-b21f-6b7b168915f2 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1681918974; x=1684510974; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=d6nuZqH4BFpdEi3VMqbbjTAjUlawv3o6/WP+NDuHGao=; b=FTQsPdb4VZ4U8RE3yeFfHXGlvbgFa0QGfqVFr+jC6kl6lxCZtsLyajUUqYQLMgURWb J4uGmuFYPY0pjFG3CvgZXBQ+DQSwKkx3aLHi8JiMlqqwFM7VZfY8qLUXuH8hNbaooToh oUl8JWcg6/dqqTOISasLH4ArbdoYMv/7qTsrk21lipm8TZ0o+iGKtQcaitVK3NT7LnHh cHUofTY6cexuLNRmw8QblHcS8LmQhx8wUSQySx0lMZFd0Mvb9N4HS1X65zhUQf+nG5lT 3cGIRqrrWfhy8kgYqFl1kyHbNncTpe5lX859YIwTjvJeyWa/XSb9WXw3PXjXypHssGbH H7Zw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681918974; x=1684510974; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=d6nuZqH4BFpdEi3VMqbbjTAjUlawv3o6/WP+NDuHGao=; b=Ny8H3Ypi0tTbfRCZjJONA1mxkFCo4dXZGZAIfjCIQUdMSRHwCuiuqtLj7XlgQFYRZf LNHavrN3fJFflEYEFhkzyeUmj41cOPfCUzh/QeL+MfjXLJpnklR7x1XVbrIZTVQ+n2+r 86XrsWL9/suZQ1qbxV3RUK/T93AdrAPID+LQYPDCqKVCVGrlTEx+LnAZIKEJGD61zurU 1Itm8jscpnXvw60SeI++RWUkS7ZpdcWC3MMCPhCWNx687HDyrgTKXcJr+q2P3hgtZSl8 gUDZT0TCSU3qIzJ9pjgAQuUxuNEh5XKGZh66Q+mxlBzQzPF9I0BKWQAzYYIFRTWSXYb0 r86w== X-Gm-Message-State: AAQBX9eqqFzqLlj6udxAlu3mgBWrAH7AnwjX67eCRhQTpbgtYzvJYFxq tylnPSnqEXv4+PBZItEM5Sza+JBaq4M= X-Google-Smtp-Source: AKy350b0B/kQEXWANRl+Ln8SJiVSd3pvv9i8HvVi4kbbG70yeWrmbVGwKZQAs+lqgOodMZ12n2+Y5w== X-Received: by 2002:a05:651c:cb:b0:2a7:79e6:1625 with SMTP id 11-20020a05651c00cb00b002a779e61625mr1987538ljr.37.1681918973693; Wed, 19 Apr 2023 08:42:53 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Julien Grall , Jan Beulich , Andrew Cooper , Stefano Stabellini , Gianluca Guida , Oleksii Kurochko , Bob Eshleman , Alistair Francis , Connor Davis Subject: [PATCH v5 4/4] xen/riscv: remove dummy_bss variable Date: Wed, 19 Apr 2023 18:42:47 +0300 Message-Id: <6b56f750edc5d8f3ed41769896c865e3ea89c68f.1681918194.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1681919008918100001 Content-Type: text/plain; charset="utf-8" After introduction of initial pagetables there is no any sense in dummy_bss variable as bss section will not be empty anymore. Signed-off-by: Oleksii Kurochko --- Changes in V5: - Nothing changed. Only rebase --- Changes in V4: - Nothing changed. Only rebase --- Changes in V3: * patch was introduced in the current one patch series (v3). --- Changes in V2: * patch was introduced in the current one patch series (v2). --- xen/arch/riscv/setup.c | 8 -------- 1 file changed, 8 deletions(-) diff --git a/xen/arch/riscv/setup.c b/xen/arch/riscv/setup.c index cf5dc5824e..845d18d86f 100644 --- a/xen/arch/riscv/setup.c +++ b/xen/arch/riscv/setup.c @@ -8,14 +8,6 @@ unsigned char __initdata cpu0_boot_stack[STACK_SIZE] __aligned(STACK_SIZE); =20 -/* =20 - * To be sure that .bss isn't zero. It will simplify code of - * .bss initialization. - * TODO: - * To be deleted when the first real .bss user appears - */ -int dummy_bss __attribute__((unused)); - void __init noreturn start_xen(unsigned long bootcpu_id, paddr_t dtb_addr) { --=20 2.39.2