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[46.204.108.92]) by smtp.gmail.com with ESMTPSA id a25-20020a05651c031900b00295a8d1ecc7sm50489ljp.18.2023.02.24.03.35.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Feb 2023 03:35:11 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 4ca96701-b437-11ed-88bb-e56d68cac8db DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=LEV0XXkwftLh/YYhu2PWBtw6xma6pefn5J7iR2uA1b8=; b=L3mCGaEwgUnEZk8uJDMAAGvHR0buasQ8IhDhO15TIhAmXamcOJV1NS2r9Zk6dO4XT2 Oq4KS5euJxgy/5Tx4G0ojC4iNMUWGbsczmHfURnPCFpt5HoNV4FQGf8tVtqsphK2Tgvd SmrCr3pkR+SgHdSDq8GzYEKqiKMhs7/Fm80v56SdOpxB02rGtbYkHeqcW29yOBZAxbam k5I+G3/3n7KEgtLDeKTwCPQv+URHCgzU//eqbbfyH/oztfsiz12ONrftYxpR7urg/wSC eaT3+GejRSw7IBaSaOhELaiF9rL1mxTqC8dVpb+ok0GtYXT7klBA1NTEpnRBi7My/70u l1HQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=LEV0XXkwftLh/YYhu2PWBtw6xma6pefn5J7iR2uA1b8=; b=a1oDHuTjNaD3tXi+hgPhL1j0HpZFtPekojYA/G2/+SyS9MkpEQKdJ9l680sCRayGcf Az78IZY334bCeCM6zz4wtzPEaflniZfGwYHOGvAywfM8HC/5h1dohC5y1agqXv/nb7ov DHSNhz/7D9PGYRLckr+j1ZfSOHlDCKgXClIylqfJ6hpn8pPr/eHHWwBz0qus4C53X3fH MXTaXx45/UzahPXYtZfx+Jn2L0btm56f0ZrW2Jg5xXDxR86B7h76/whetCsDKYuJrowD OjhUW13sNS9+sbo9wmmg2Is2OqZ+A5uCHuGlqqczwWe8xPbLpoN6YYASetiubE3KRyfH JMKw== X-Gm-Message-State: AO0yUKWmODUfkcYxoGmJrSniJogHnflkLV3pkUqMglhfAum+czxTFJTJ 7JF1dgOpcBPy99z5LGpM3EyBRiCXBdE= X-Google-Smtp-Source: AK7set+4UsiLENwc9Yu3xAUF6hHU3jFibegHt+1QqE3NwHASdq0D9Wrbl2xtm0BO70wAZ2lAdhQRvw== X-Received: by 2002:a05:651c:a0e:b0:293:4cfe:ad31 with SMTP id k14-20020a05651c0a0e00b002934cfead31mr9704967ljq.14.1677238511687; Fri, 24 Feb 2023 03:35:11 -0800 (PST) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Julien Grall , Jan Beulich , Andrew Cooper , Stefano Stabellini , Gianluca Guida , Oleksii Kurochko , Bob Eshleman , Alistair Francis , Connor Davis Subject: [PATCH v4 1/5] xen/riscv: introduce decode_cause() stuff Date: Fri, 24 Feb 2023 13:35:01 +0200 Message-Id: <397e6741438a8b125dc53945a74a58246fac4faf.1677237653.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1677238540557100001 Content-Type: text/plain; charset="utf-8" The patch introduces stuff needed to decode a reason of an exception. Signed-off-by: Oleksii Kurochko --- Changes in V4: - fix string in decode_reserved_interrupt_cause() --- Changes in V3: - Nothing changed --- Changes in V2: - Make decode_trap_cause() more optimization friendly. - Merge the pathc which introduces do_unexpected_trap() to the current on= e. --- xen/arch/riscv/traps.c | 87 +++++++++++++++++++++++++++++++++++++++++- 1 file changed, 86 insertions(+), 1 deletion(-) diff --git a/xen/arch/riscv/traps.c b/xen/arch/riscv/traps.c index ccd3593f5a..29b1a0dfae 100644 --- a/xen/arch/riscv/traps.c +++ b/xen/arch/riscv/traps.c @@ -4,10 +4,95 @@ * * RISC-V Trap handlers */ + +#include +#include + +#include +#include #include #include =20 -void do_trap(struct cpu_user_regs *cpu_regs) +static const char *decode_trap_cause(unsigned long cause) +{ + static const char *const trap_causes[] =3D { + [CAUSE_MISALIGNED_FETCH] =3D "Instruction Address Misaligned", + [CAUSE_FETCH_ACCESS] =3D "Instruction Access Fault", + [CAUSE_ILLEGAL_INSTRUCTION] =3D "Illegal Instruction", + [CAUSE_BREAKPOINT] =3D "Breakpoint", + [CAUSE_MISALIGNED_LOAD] =3D "Load Address Misaligned", + [CAUSE_LOAD_ACCESS] =3D "Load Access Fault", + [CAUSE_MISALIGNED_STORE] =3D "Store/AMO Address Misaligned", + [CAUSE_STORE_ACCESS] =3D "Store/AMO Access Fault", + [CAUSE_USER_ECALL] =3D "Environment Call from U-Mode", + [CAUSE_SUPERVISOR_ECALL] =3D "Environment Call from S-Mode", + [CAUSE_MACHINE_ECALL] =3D "Environment Call from M-Mode", + [CAUSE_FETCH_PAGE_FAULT] =3D "Instruction Page Fault", + [CAUSE_LOAD_PAGE_FAULT] =3D "Load Page Fault", + [CAUSE_STORE_PAGE_FAULT] =3D "Store/AMO Page Fault", + [CAUSE_FETCH_GUEST_PAGE_FAULT] =3D "Instruction Guest Page Fault", + [CAUSE_LOAD_GUEST_PAGE_FAULT] =3D "Load Guest Page Fault", + [CAUSE_VIRTUAL_INST_FAULT] =3D "Virtualized Instruction Fault", + [CAUSE_STORE_GUEST_PAGE_FAULT] =3D "Guest Store/AMO Page Fault", + }; + + if ( cause < ARRAY_SIZE(trap_causes) && trap_causes[cause] ) + return trap_causes[cause]; + return "UNKNOWN"; +} + +const char *decode_reserved_interrupt_cause(unsigned long irq_cause) +{ + switch ( irq_cause ) + { + case IRQ_M_SOFT: + return "M-mode Software Interrupt"; + case IRQ_M_TIMER: + return "M-mode TIMER Interrupt"; + case IRQ_M_EXT: + return "M-mode External Interrupt"; + default: + return "UNKNOWN IRQ type"; + } +} + +const char *decode_interrupt_cause(unsigned long cause) +{ + unsigned long irq_cause =3D cause & ~CAUSE_IRQ_FLAG; + + switch ( irq_cause ) + { + case IRQ_S_SOFT: + return "Supervisor Software Interrupt"; + case IRQ_S_TIMER: + return "Supervisor Timer Interrupt"; + case IRQ_S_EXT: + return "Supervisor External Interrupt"; + default: + return decode_reserved_interrupt_cause(irq_cause); + } +} + +const char *decode_cause(unsigned long cause) +{ + if ( cause & CAUSE_IRQ_FLAG ) + return decode_interrupt_cause(cause); + + return decode_trap_cause(cause); +} + +static void do_unexpected_trap(const struct cpu_user_regs *regs) { + unsigned long cause =3D csr_read(CSR_SCAUSE); + + early_printk("Unhandled exception: "); + early_printk(decode_cause(cause)); + early_printk("\n"); + die(); } + +void do_trap(struct cpu_user_regs *cpu_regs) +{ + do_unexpected_trap(cpu_regs); +} --=20 2.39.0 From nobody Wed May 15 07:41:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1677238533; cv=none; d=zohomail.com; s=zohoarc; b=csgAAh+Td5sijxIwoCWVrVYRpRVxj+aCP/78Srq0vtSfoDk4qxCWLOSBoOsddmImgNMMg7+xlYtqR5O5P7sSasB/BPy65rLcl9GpGADkcz8E14VqgNhM+ZgXOJLbyYWIscElO9WAooBz3nUTFTXGDivEQhAmn+X/8+wbVY/KklE= ARC-Message-Signature: i=1; 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charset="utf-8" Signed-off-by: Oleksii Kurochko Reviewed-by: Alistair Francis --- Changes in V4: - Nothing changed --- Changes in V3: - Nothing changed --- Changes in V2: - Rename setup_trap_handler() to trap_init(). - Add Reviewed-by to the commit message. --- xen/arch/riscv/include/asm/traps.h | 1 + xen/arch/riscv/setup.c | 4 ++++ xen/arch/riscv/traps.c | 7 +++++++ 3 files changed, 12 insertions(+) diff --git a/xen/arch/riscv/include/asm/traps.h b/xen/arch/riscv/include/as= m/traps.h index f3fb6b25d1..f1879294ef 100644 --- a/xen/arch/riscv/include/asm/traps.h +++ b/xen/arch/riscv/include/asm/traps.h @@ -7,6 +7,7 @@ =20 void do_trap(struct cpu_user_regs *cpu_regs); void handle_trap(void); +void trap_init(void); =20 #endif /* __ASSEMBLY__ */ =20 diff --git a/xen/arch/riscv/setup.c b/xen/arch/riscv/setup.c index d09ffe1454..c8513ca4f8 100644 --- a/xen/arch/riscv/setup.c +++ b/xen/arch/riscv/setup.c @@ -1,7 +1,9 @@ #include #include =20 +#include #include +#include =20 /* Xen stack for bringing up the first CPU. */ unsigned char __initdata cpu0_boot_stack[STACK_SIZE] @@ -11,6 +13,8 @@ void __init noreturn start_xen(void) { early_printk("Hello from C env\n"); =20 + trap_init(); + for ( ;; ) asm volatile ("wfi"); =20 diff --git a/xen/arch/riscv/traps.c b/xen/arch/riscv/traps.c index 29b1a0dfae..ad7311f269 100644 --- a/xen/arch/riscv/traps.c +++ b/xen/arch/riscv/traps.c @@ -13,6 +13,13 @@ #include #include =20 +void trap_init(void) +{ + unsigned long addr =3D (unsigned long)&handle_trap; + + csr_write(CSR_STVEC, addr); +} + static const char *decode_trap_cause(unsigned long cause) { static const char *const trap_causes[] =3D { --=20 2.39.0 From nobody Wed May 15 07:41:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; 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[46.204.108.92]) by smtp.gmail.com with ESMTPSA id a25-20020a05651c031900b00295a8d1ecc7sm50489ljp.18.2023.02.24.03.35.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Feb 2023 03:35:14 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 4e97e729-b437-11ed-a82a-c9ca1d2f71af DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=51X9MeY84AeI86UksVCXFvV/ywJXDcqY/IRT+9++n+0=; b=Cm3iRbMNcUp94s2Ne+koA/IZarQkv+AuXuJQGinD3yoETGZxCS5ZTTBkWfUwQbTUDV +U0Omhk1NpXJlMZgGbmGgEktbRg0ISL7W5jRcyHCXR+DxUnpIsiYymmRqxahcTTF6xJt LzPoaiP69oL2FQmuu4J/Kcai1W8LGjDvFtxXHI3kZ3SRppYbcArl//S6cJElWlfbiwxS O83FiFSbyyzpAUmZhEfKcj4b9ycFlTQN98CdpLGO4JUKGg6BtqmRSET2Ysy04TS6s3Rf FZriy3YtvdXg/uWv6aX3M0cOP0gscdZlcDEQef+NAfpyO2VkLqZxkY5bY8FRE5OJQn/o mRPw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=51X9MeY84AeI86UksVCXFvV/ywJXDcqY/IRT+9++n+0=; b=ObOGbBgfFxVdrRTNSfXbz7xfaJams4uxJe1M5xmMA/jfnRaFVZx1FtFhusBIWDpGOx ALU44CYodzCes7xW+FdZMIv9GsoYu0t2Sd5SG7TRPhyvH96TVBasBJm8pUnwAdhr/sRx 7Ts4e9rhf2NKk0s2+KF4OTAD7u1ENTylu9GFsFJI9kPOqjz/7/7aROr78GY2+uh2dad5 r/HXfwwtGlVCy7DgG2O7fQ7XHOG3T9QDJUtnbHrXh1aNRJJjlId5W0G8gSM2uqIrOLVq RsZcQ1LMLWvMp7kLipGrbh331E78JaVH9hSbe0HIaKVVHwf1ci+StJ0jEh5xrtDPRrAF skew== X-Gm-Message-State: AO0yUKWzXP0zcYRN6knVS7eaYjy5IKJ3EClH5odZU9nwnEs4XOgCoPHB ZoPfl2Eg8HuTvOPyL0PP6zAwpPX+Xyg= X-Google-Smtp-Source: AK7set+oZ+AFDYIcbDmMMFFIbxZwMRNFhQH6aO+qx8QQaR//6vlQ2TEWysdF5xvyqn4sb4oxguCajg== X-Received: by 2002:ac2:5927:0:b0:4dd:9a38:fcc with SMTP id v7-20020ac25927000000b004dd9a380fccmr3430648lfi.63.1677238514815; Fri, 24 Feb 2023 03:35:14 -0800 (PST) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Julien Grall , Jan Beulich , Andrew Cooper , Stefano Stabellini , Gianluca Guida , Oleksii Kurochko , Bob Eshleman , Alistair Francis , Connor Davis Subject: [PATCH v4 3/5] xen/riscv: introduce an implementation of macros from Date: Fri, 24 Feb 2023 13:35:03 +0200 Message-Id: X-Mailer: git-send-email 2.39.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1677238544787100001 Content-Type: text/plain; charset="utf-8" The patch introduces macros: BUG(), WARN(), run_in_exception(), assert_failed. The implementation uses "ebreak" instruction in combination with diffrent bug frame tables (for each type) which contains useful information. Signed-off-by: Oleksii Kurochko --- Changes in V4: - Updates in RISC-V's : * Add explanatory comment about why there is only defined for 32-bits l= ength instructions and 16/32-bits BUG_INSN_{16,32}. * Change 'unsigned long' to 'unsigned int' inside GET_INSN_LENGTH(). * Update declaration of is_valid_bugaddr(): switch return type from int= to bool and the argument from 'unsigned int' to 'vaddr'. - Updates in RISC-V's traps.c: * replace /xen and /asm includes=20 * update definition of is_valid_bugaddr():switch return type from int t= o bool and the argument from 'unsigned int' to 'vaddr'. Code style inside fu= nction was updated too. * do_bug_frame() refactoring: * local variables start and bug became 'const struct bug_frame' * bug_frames[] array became 'static const struct bug_frame[] =3D ...' * remove all casts * remove unneeded comments and add an explanatory comment that the do= _bug_frame() will be switched to a generic one. * do_trap() refactoring: * read 16-bits value instead of 32-bits as compressed instruction can be used and it might happen than only 16-bits may be accessible. * code style updates * re-use instr variable instead of re-reading instruction. - Updates in setup.c: * add blank line between xen/ and asm/ includes. --- Changes in V3: - Rebase the patch "xen/riscv: introduce an implementation of macros from " on top of patch series [introduce generic implementat= ion of macros from bug.h] --- Changes in V2: - Remove __ in define namings - Update run_in_exception_handler() with register void *fn_ asm(__stringify(BUG_FN_REG)) =3D (fn); - Remove bug_instr_t type and change it's usage to uint32_t --- xen/arch/riscv/include/asm/bug.h | 48 ++++++++++ xen/arch/riscv/include/asm/processor.h | 2 + xen/arch/riscv/setup.c | 1 + xen/arch/riscv/traps.c | 125 +++++++++++++++++++++++++ xen/arch/riscv/xen.lds.S | 10 ++ 5 files changed, 186 insertions(+) create mode 100644 xen/arch/riscv/include/asm/bug.h diff --git a/xen/arch/riscv/include/asm/bug.h b/xen/arch/riscv/include/asm/= bug.h new file mode 100644 index 0000000000..67ade6f895 --- /dev/null +++ b/xen/arch/riscv/include/asm/bug.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2012 Regents of the University of California + * Copyright (C) 2021-2023 Vates + * + */ +#ifndef _ASM_RISCV_BUG_H +#define _ASM_RISCV_BUG_H + +#include + +#ifndef __ASSEMBLY__ + +#define BUG_INSTR "ebreak" + +/* + * The base instruction set has a fixed length of 32-bit naturally aligned + * instructions. + * + * There are extensions of variable length ( where each instruction can be + * any number of 16-bit parcels in length ) but they aren't used in Xen + * and Linux kernel ( where these definitions were taken from ). + * + * Compressed ISA is used now where the instruction length is 16 bit and + * 'ebreak' instruction, in this case, can be either 16 or 32 bit ( + * depending on if compressed ISA is used or not ) + */ +#define INSN_LENGTH_MASK _UL(0x3) +#define INSN_LENGTH_32 _UL(0x3) + +#define BUG_INSN_32 _UL(0x00100073) /* ebreak */ +#define BUG_INSN_16 _UL(0x9002) /* c.ebreak */ +#define COMPRESSED_INSN_MASK _UL(0xffff) + +#define GET_INSN_LENGTH(insn) \ +({ \ + unsigned int len; \ + len =3D ((insn & INSN_LENGTH_MASK) =3D=3D INSN_LENGTH_32) ? \ + 4UL : 2UL; \ + len; \ +}) + +/* These are defined by the architecture */ +bool is_valid_bugaddr(vaddr_t addr); + +#endif /* !__ASSEMBLY__ */ + +#endif /* _ASM_RISCV_BUG_H */ diff --git a/xen/arch/riscv/include/asm/processor.h b/xen/arch/riscv/includ= e/asm/processor.h index a71448e02e..ef23d9589e 100644 --- a/xen/arch/riscv/include/asm/processor.h +++ b/xen/arch/riscv/include/asm/processor.h @@ -69,6 +69,8 @@ static inline void die(void) wfi(); } =20 +void show_execution_state(const struct cpu_user_regs *regs); + #endif /* __ASSEMBLY__ */ =20 #endif /* _ASM_RISCV_PROCESSOR_H */ diff --git a/xen/arch/riscv/setup.c b/xen/arch/riscv/setup.c index c8513ca4f8..73b9a82883 100644 --- a/xen/arch/riscv/setup.c +++ b/xen/arch/riscv/setup.c @@ -1,3 +1,4 @@ +#include #include #include =20 diff --git a/xen/arch/riscv/traps.c b/xen/arch/riscv/traps.c index ad7311f269..d87a9cfd2c 100644 --- a/xen/arch/riscv/traps.c +++ b/xen/arch/riscv/traps.c @@ -5,6 +5,7 @@ * RISC-V Trap handlers */ =20 +#include #include #include =20 @@ -99,7 +100,131 @@ static void do_unexpected_trap(const struct cpu_user_r= egs *regs) die(); } =20 +void show_execution_state(const struct cpu_user_regs *regs) +{ + early_printk("implement show_execution_state(regs)\n"); +} + +/* + * TODO: change early_printk's function to early_printk with format + * when s(n)printf() will be added. + * + * Probably the TODO won't be needed as generic do_bug_frame() (at + * least, for ARM and RISC-V) has been introduced and current + * implementation will be replaced with generic one when panic(), + * printk() and find_text_region() (virtual memory?) will be + * ready/merged + */ +int do_bug_frame(const struct cpu_user_regs *regs, vaddr_t pc) +{ + const struct bug_frame *start, *end; + const struct bug_frame *bug =3D NULL; + unsigned int id =3D 0; + const char *filename, *predicate; + int lineno; + + static const struct bug_frame* bug_frames[] =3D { + &__start_bug_frames[0], + &__stop_bug_frames_0[0], + &__stop_bug_frames_1[0], + &__stop_bug_frames_2[0], + &__stop_bug_frames_3[0], + }; + + for ( id =3D 0; id < BUGFRAME_NR; id++ ) + { + start =3D bug_frames[id]; + end =3D bug_frames[id + 1]; + + while ( start !=3D end ) + { + if ( (vaddr_t)bug_loc(start) =3D=3D pc ) + { + bug =3D start; + goto found; + } + + start++; + } + } + + found: + if ( bug =3D=3D NULL ) + return -ENOENT; + + if ( id =3D=3D BUGFRAME_run_fn ) + { + void (*fn)(const struct cpu_user_regs *) =3D bug_ptr(bug); + + fn(regs); + + goto end; + } + + /* WARN, BUG or ASSERT: decode the filename pointer and line number. */ + filename =3D bug_ptr(bug); + lineno =3D bug_line(bug); + + switch ( id ) + { + case BUGFRAME_warn: + early_printk("Xen WARN at "); + early_printk(filename); + early_printk("\n"); + + show_execution_state(regs); + + goto end; + + case BUGFRAME_bug: + early_printk("Xen BUG at "); + early_printk(filename); + early_printk("\n"); + + show_execution_state(regs); + early_printk("change wait_for_interrupt to panic() when common is = available\n"); + die(); + + case BUGFRAME_assert: + /* ASSERT: decode the predicate string pointer. */ + predicate =3D bug_msg(bug); + + early_printk("Assertion \'"); + early_printk(predicate); + early_printk("\' failed at "); + early_printk(filename); + early_printk("\n"); + + show_execution_state(regs); + early_printk("change wait_for_interrupt to panic() when common is = available\n"); + die(); + } + + return -EINVAL; + + end: + return 0; +} + +bool is_valid_bugaddr(vaddr_t insn) +{ + if ( (insn & INSN_LENGTH_MASK) =3D=3D INSN_LENGTH_32 ) + return ( insn =3D=3D BUG_INSN_32 ); + else + return ( (insn & COMPRESSED_INSN_MASK) =3D=3D BUG_INSN_16 ); +} + void do_trap(struct cpu_user_regs *cpu_regs) { + register_t pc =3D cpu_regs->sepc; + uint16_t instr =3D *(uint16_t *)pc; + + if ( is_valid_bugaddr(instr) ) { + if ( !do_bug_frame(cpu_regs, cpu_regs->sepc) ) { + cpu_regs->sepc +=3D GET_INSN_LENGTH(instr); + return; + } + } + do_unexpected_trap(cpu_regs); } diff --git a/xen/arch/riscv/xen.lds.S b/xen/arch/riscv/xen.lds.S index ca57cce75c..139e2d04cb 100644 --- a/xen/arch/riscv/xen.lds.S +++ b/xen/arch/riscv/xen.lds.S @@ -39,6 +39,16 @@ SECTIONS . =3D ALIGN(PAGE_SIZE); .rodata : { _srodata =3D .; /* Read-only data */ + /* Bug frames table */ + __start_bug_frames =3D .; + *(.bug_frames.0) + __stop_bug_frames_0 =3D .; + *(.bug_frames.1) + __stop_bug_frames_1 =3D .; + *(.bug_frames.2) + __stop_bug_frames_2 =3D .; + *(.bug_frames.3) + __stop_bug_frames_3 =3D .; *(.rodata) *(.rodata.*) *(.data.rel.ro) --=20 2.39.0 From nobody Wed May 15 07:41:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1677238541; cv=none; d=zohomail.com; s=zohoarc; b=I3BJORfkYW5JgNPfdIfcuTulbwhisg2q8GFg0HfUTGIAqNjhCgzc9Smo/imlbwn4nLQiEs6iizv37Qj23XRMFqPXFFP2J175682qB5q9XvhZjpwz+IlFPh9f8q04ODZplbJ/1/lrD8enuRNCeQVwkMqRO07AcmObNwvo0iN6XE8= ARC-Message-Signature: i=1; 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charset="utf-8" Signed-off-by: Oleksii Kurochko Acked-by: Alistair Francis --- Changes in V4: - Add Acked-by: Alistair Francis --- Changes in V3: - Nothing changed --- Changes in V2: - Nothing changed --- xen/arch/riscv/setup.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/xen/arch/riscv/setup.c b/xen/arch/riscv/setup.c index 73b9a82883..b3f8b10f71 100644 --- a/xen/arch/riscv/setup.c +++ b/xen/arch/riscv/setup.c @@ -10,12 +10,28 @@ unsigned char __initdata cpu0_boot_stack[STACK_SIZE] __aligned(STACK_SIZE); =20 +static void test_run_in_exception(struct cpu_user_regs *regs) +{ + early_printk("If you see this message, "); + early_printk("run_in_exception_handler is most likely working\n"); +} + +static void test_macros_from_bug_h(void) +{ + run_in_exception_handler(test_run_in_exception); + WARN(); + early_printk("If you see this message, "); + early_printk("WARN is most likely working\n"); +} + void __init noreturn start_xen(void) { early_printk("Hello from C env\n"); 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Signed-off-by: Oleksii Kurochko Reviewed-by: Alistair Francis Acked-by: Stefano Stabellini --- Changes in V4: - Add Reviewed-by: Alistair Francis and Acked-by: Stefano Stabellini --- Changes in V3: - Update commit message --- Changes in V2: - Leave only the latest "grep ..." --- automation/scripts/qemu-smoke-riscv64.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/automation/scripts/qemu-smoke-riscv64.sh b/automation/scripts/= qemu-smoke-riscv64.sh index e0f06360bc..02fc66be03 100755 --- a/automation/scripts/qemu-smoke-riscv64.sh +++ b/automation/scripts/qemu-smoke-riscv64.sh @@ -16,5 +16,5 @@ qemu-system-riscv64 \ |& tee smoke.serial =20 set -e -(grep -q "Hello from C env" smoke.serial) || exit 1 +(grep -q "WARN is most likely working" smoke.serial) || exit 1 exit 0 --=20 2.39.0