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charset="utf-8" get_page_from_l1e() relied on Xen's choice of PAT, which is brittle in the face of future PAT changes. Use the proper _PAGE_* constants instead. Also, treat the two unused cases as if they are cacheable, as future changes may make them cacheable. Signed-off-by: Demi Marie Obenour --- xen/arch/x86/mm.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/xen/arch/x86/mm.c b/xen/arch/x86/mm.c index 78b1972e4170cacccc9c37c6e64e76e66a7da87f..b73cb29327ba49703673886d09d= 79f2f8928a6c0 100644 --- a/xen/arch/x86/mm.c +++ b/xen/arch/x86/mm.c @@ -959,14 +959,19 @@ get_page_from_l1e( flip =3D _PAGE_RW; } =20 + /* Force cacheable memtypes to UC */ switch ( l1f & PAGE_CACHE_ATTRS ) { - case 0: /* WB */ - flip |=3D _PAGE_PWT | _PAGE_PCD; + case _PAGE_UC: + case _PAGE_UCM: + case _PAGE_WC: + /* not cached */ break; - case _PAGE_PWT: /* WT */ - case _PAGE_PWT | _PAGE_PAT: /* WP */ - flip |=3D _PAGE_PCD | (l1f & _PAGE_PAT); + case _PAGE_WB: + case _PAGE_WT: + case _PAGE_WP: + default: + flip |=3D (l1f & PAGE_CACHE_ATTRS) ^ _PAGE_UC; break; } =20 --=20 Sincerely, Demi Marie Obenour (she/her/hers) Invisible Things Lab From nobody Fri Nov 1 00:05:37 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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charset="utf-8" This makes the code much easier to understand. No functional change intended. As per Andrew Cooper, the existing logic is questionable, but this does not make it any worse. Signed-off-by: Demi Marie Obenour Acked-by: Jan Beulich --- xen/arch/x86/mm/p2m-pt.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/xen/arch/x86/mm/p2m-pt.c b/xen/arch/x86/mm/p2m-pt.c index eaba2b0fb4e6830f52b7d112fba8175dfe6d2770..cd1af33b6772ab1016e8d4c3284= a6bc5d282869d 100644 --- a/xen/arch/x86/mm/p2m-pt.c +++ b/xen/arch/x86/mm/p2m-pt.c @@ -99,13 +99,13 @@ static unsigned long p2m_type_to_flags(const struct p2m= _domain *p2m, return flags | P2M_BASE_FLAGS | _PAGE_RW | _PAGE_NX_BIT; case p2m_mmio_direct: if ( !rangeset_contains_singleton(mmio_ro_ranges, mfn_x(mfn)) ) - flags |=3D _PAGE_RW; + flags |=3D _PAGE_RW | _PAGE_UCM; else { - flags |=3D _PAGE_PWT; + flags |=3D _PAGE_UC; ASSERT(!level); } - return flags | P2M_BASE_FLAGS | _PAGE_PCD; + return flags | P2M_BASE_FLAGS; } } =20 --=20 Sincerely, Demi Marie Obenour (she/her/hers) Invisible Things Lab From nobody Fri Nov 1 00:05:37 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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charset="utf-8" This makes the code much easier to understand, and avoids problems if Xen's PAT ever changes in the future. Signed-off-by: Demi Marie Obenour Reviewed-by: Jan Beulich --- xen/common/efi/boot.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/xen/common/efi/boot.c b/xen/common/efi/boot.c index d521b47bc6d9513ca6e65c3170abb94881a71910..e1248d63e7f99d598a6b1df04e3= 4ed34ed0b6910 100644 --- a/xen/common/efi/boot.c +++ b/xen/common/efi/boot.c @@ -1748,23 +1748,23 @@ void __init efi_init_memory(void) emfn =3D PFN_UP(desc->PhysicalStart + len); =20 if ( desc->Attribute & EFI_MEMORY_WB ) - /* nothing */; + prot |=3D _PAGE_WB; else if ( desc->Attribute & EFI_MEMORY_WT ) - prot |=3D _PAGE_PWT | MAP_SMALL_PAGES; + prot |=3D _PAGE_WT | MAP_SMALL_PAGES; else if ( desc->Attribute & EFI_MEMORY_WC ) - prot |=3D _PAGE_PAT | MAP_SMALL_PAGES; + prot |=3D _PAGE_WC | MAP_SMALL_PAGES; else if ( desc->Attribute & (EFI_MEMORY_UC | EFI_MEMORY_UCE) ) - prot |=3D _PAGE_PWT | _PAGE_PCD | MAP_SMALL_PAGES; + prot |=3D _PAGE_UC | MAP_SMALL_PAGES; else if ( efi_bs_revision >=3D EFI_REVISION(2, 5) && (desc->Attribute & EFI_MEMORY_WP) ) - prot |=3D _PAGE_PAT | _PAGE_PWT | MAP_SMALL_PAGES; + prot |=3D _PAGE_WP | MAP_SMALL_PAGES; else { printk(XENLOG_ERR "Unknown cachability for MFNs %#lx-%#lx%s\n", smfn, emfn - 1, efi_map_uc ? ", assuming UC" : ""); if ( !efi_map_uc ) continue; - prot |=3D _PAGE_PWT | _PAGE_PCD | MAP_SMALL_PAGES; + prot |=3D _PAGE_UC | MAP_SMALL_PAGES; } =20 if ( desc->Attribute & (efi_bs_revision < EFI_REVISION(2, 5) --=20 Sincerely, Demi Marie Obenour (she/her/hers) Invisible Things Lab From nobody Fri Nov 1 00:05:37 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1671059588801523.3232614083965; Wed, 14 Dec 2022 15:13:08 -0800 (PST) Received: from list by lists.xenproject.org with outflank-mailman.462664.720862 (Exim 4.92) (envelope-from ) id 1p5avh-0001RY-84; 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charset="utf-8" These are not currently used, so there is no functional change. Future patches will use these constants. Suggested-by: Andrew Cooper Signed-off-by: Demi Marie Obenour --- Changes since v2: - Avoid using _AC where not required. - Define reserved memory types inline --- xen/arch/x86/include/asm/x86-defns.h | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/xen/arch/x86/include/asm/x86-defns.h b/xen/arch/x86/include/as= m/x86-defns.h index 28628807cb9897cf6fa8e266f71f5f220813984d..6380b8197c3b16a5d95286097d2= 37579d3d55bd2 100644 --- a/xen/arch/x86/include/asm/x86-defns.h +++ b/xen/arch/x86/include/asm/x86-defns.h @@ -153,4 +153,15 @@ (1u << X86_EXC_AC) | (1u << X86_EXC_CP) | \ (1u << X86_EXC_VC) | (1u << X86_EXC_SX)) =20 +/* Memory types */ +#define X86_MT_UC 0x00 /* uncachable */ +#define X86_MT_WC 0x01 /* write-combined */ +#define X86_MT_RESERVED_1 0x02 /* reserved */ +#define X86_MT_RESERVED_2 0x03 /* reserved */ +#define X86_MT_WT 0x04 /* write-through */ +#define X86_MT_WP 0x05 /* write-protect */ +#define X86_MT_WB 0x06 /* write-back */ +#define X86_MT_UCM 0x07 /* UC- */ +#define X86_NUM_MT 0x08 + #endif /* __XEN_X86_DEFNS_H__ */ --=20 Sincerely, Demi Marie Obenour (she/her/hers) Invisible Things Lab From nobody Fri Nov 1 00:05:37 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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charset="utf-8" This allows eliminating the former. Suggested-by: Andrew Cooper Signed-off-by: Demi Marie Obenour Reviewed-by: Jan Beulich --- Changes since v2: Style adjustments --- xen/arch/x86/hvm/hvm.c | 12 ++++---- xen/arch/x86/hvm/mtrr.c | 52 ++++++++++++++++----------------- xen/arch/x86/hvm/vmx/vmx.c | 16 +++++----- xen/arch/x86/include/asm/mtrr.h | 12 +------- xen/arch/x86/mm/p2m-ept.c | 4 +-- xen/arch/x86/mm/shadow/multi.c | 4 +-- 6 files changed, 45 insertions(+), 55 deletions(-) diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c index ae4368ec4b338cf8c6cb14d383f612c91c98e800..00b3fa56e25e2934e2870e11fd1= 9b120daff2715 100644 --- a/xen/arch/x86/hvm/hvm.c +++ b/xen/arch/x86/hvm/hvm.c @@ -307,12 +307,12 @@ int hvm_set_guest_pat(struct vcpu *v, uint64_t guest_= pat) for ( i =3D 0, tmp =3D guest_pat; i < 8; i++, tmp >>=3D 8 ) switch ( tmp & 0xff ) { - case PAT_TYPE_UC_MINUS: - case PAT_TYPE_UNCACHABLE: - case PAT_TYPE_WRBACK: - case PAT_TYPE_WRCOMB: - case PAT_TYPE_WRPROT: - case PAT_TYPE_WRTHROUGH: + case X86_MT_UCM: + case X86_MT_UC: + case X86_MT_WB: + case X86_MT_WC: + case X86_MT_WP: + case X86_MT_WT: break; default: return 0; diff --git a/xen/arch/x86/hvm/mtrr.c b/xen/arch/x86/hvm/mtrr.c index 4d2aa6def86de45aeeaade7a1a7815c5ef2b3d7a..242623f3c239ee18a44f882ecb3= 910a00c615825 100644 --- a/xen/arch/x86/hvm/mtrr.c +++ b/xen/arch/x86/hvm/mtrr.c @@ -37,7 +37,7 @@ static const uint8_t pat_entry_2_pte_flags[8] =3D { _PAGE_PAT | _PAGE_PCD, _PAGE_PAT | _PAGE_PCD | _PAGE_PWT }; =20 /* Effective mm type lookup table, according to MTRR and PAT. */ -static const uint8_t mm_type_tbl[MTRR_NUM_TYPES][PAT_TYPE_NUMS] =3D { +static const uint8_t mm_type_tbl[MTRR_NUM_TYPES][X86_NUM_MT] =3D { #define RS MEMORY_NUM_TYPES #define UC MTRR_TYPE_UNCACHABLE #define WB MTRR_TYPE_WRBACK @@ -72,8 +72,8 @@ static uint8_t __read_mostly mtrr_epat_tbl[MTRR_NUM_TYPES= ][MEMORY_NUM_TYPES] =3D }; =20 /* Lookup table for PAT entry of a given PAT value in host PAT. */ -static uint8_t __read_mostly pat_entry_tbl[PAT_TYPE_NUMS] =3D - { [0 ... PAT_TYPE_NUMS-1] =3D INVALID_MEM_TYPE }; +static uint8_t __read_mostly pat_entry_tbl[X86_NUM_MT] =3D + { [0 ... X86_NUM_MT - 1] =3D INVALID_MEM_TYPE }; =20 static int __init cf_check hvm_mtrr_pat_init(void) { @@ -81,7 +81,7 @@ static int __init cf_check hvm_mtrr_pat_init(void) =20 for ( i =3D 0; i < MTRR_NUM_TYPES; i++ ) { - for ( j =3D 0; j < PAT_TYPE_NUMS; j++ ) + for ( j =3D 0; j < X86_NUM_MT; j++ ) { unsigned int tmp =3D mm_type_tbl[i][j]; =20 @@ -90,9 +90,9 @@ static int __init cf_check hvm_mtrr_pat_init(void) } } =20 - for ( i =3D 0; i < PAT_TYPE_NUMS; i++ ) + for ( i =3D 0; i < X86_NUM_MT; i++ ) { - for ( j =3D 0; j < PAT_TYPE_NUMS; j++ ) + for ( j =3D 0; j < X86_NUM_MT; j++ ) { if ( pat_cr_2_paf(XEN_MSR_PAT, j) =3D=3D i ) { @@ -115,7 +115,7 @@ uint8_t pat_type_2_pte_flags(uint8_t pat_type) * given pat_type. If host PAT covers all the PAT types, it can't happ= en. */ if ( unlikely(pat_entry =3D=3D INVALID_MEM_TYPE) ) - pat_entry =3D pat_entry_tbl[PAT_TYPE_UNCACHABLE]; + pat_entry =3D pat_entry_tbl[X86_MT_UC]; =20 return pat_entry_2_pte_flags[pat_entry]; } @@ -145,14 +145,14 @@ int hvm_vcpu_cacheattr_init(struct vcpu *v) m->mtrr_cap =3D (1u << 10) | (1u << 8) | num_var_ranges; =20 v->arch.hvm.pat_cr =3D - ((uint64_t)PAT_TYPE_WRBACK) | /* PAT0: WB */ - ((uint64_t)PAT_TYPE_WRTHROUGH << 8) | /* PAT1: WT */ - ((uint64_t)PAT_TYPE_UC_MINUS << 16) | /* PAT2: UC- */ - ((uint64_t)PAT_TYPE_UNCACHABLE << 24) | /* PAT3: UC */ - ((uint64_t)PAT_TYPE_WRBACK << 32) | /* PAT4: WB */ - ((uint64_t)PAT_TYPE_WRTHROUGH << 40) | /* PAT5: WT */ - ((uint64_t)PAT_TYPE_UC_MINUS << 48) | /* PAT6: UC- */ - ((uint64_t)PAT_TYPE_UNCACHABLE << 56); /* PAT7: UC */ + ((uint64_t)X86_MT_WB) | /* PAT0: WB */ + ((uint64_t)X86_MT_WT << 8) | /* PAT1: WT */ + ((uint64_t)X86_MT_UCM << 16) | /* PAT2: UC- */ + ((uint64_t)X86_MT_UC << 24) | /* PAT3: UC */ + ((uint64_t)X86_MT_WB << 32) | /* PAT4: WB */ + ((uint64_t)X86_MT_WT << 40) | /* PAT5: WT */ + ((uint64_t)X86_MT_UCM << 48) | /* PAT6: UC- */ + ((uint64_t)X86_MT_UC << 56); /* PAT7: UC */ =20 if ( is_hardware_domain(v->domain) ) { @@ -356,7 +356,7 @@ uint32_t get_pat_flags(struct vcpu *v, */ pat_entry_value =3D mtrr_epat_tbl[shadow_mtrr_type][guest_eff_mm_type]; /* If conflit occurs(e.g host MTRR is UC, guest memory type is - * WB),set UC as effective memory. Here, returning PAT_TYPE_UNCACHABLE= will + * WB), set UC as effective memory. Here, returning X86_MT_UC will * always set effective memory as UC. */ if ( pat_entry_value =3D=3D INVALID_MEM_TYPE ) @@ -371,7 +371,7 @@ uint32_t get_pat_flags(struct vcpu *v, "because the host mtrr type is:%d\n", gl1e_flags, (uint64_t)gpaddr, guest_eff_mm_type, shadow_mtrr_type); - pat_entry_value =3D PAT_TYPE_UNCACHABLE; + pat_entry_value =3D X86_MT_UC; } /* 4. Get the pte flags */ return pat_type_2_pte_flags(pat_entry_value); @@ -620,13 +620,13 @@ int hvm_set_mem_pinned_cacheattr(struct domain *d, ui= nt64_t gfn_start, p2m_memory_type_changed(d); switch ( type ) { - case PAT_TYPE_UC_MINUS: + case X86_MT_UCM: /* * For EPT we can also avoid the flush in this case; * see epte_get_entry_emt(). */ if ( hap_enabled(d) && cpu_has_vmx ) - case PAT_TYPE_UNCACHABLE: + case X86_MT_UC: break; /* fall through */ default: @@ -638,12 +638,12 @@ int hvm_set_mem_pinned_cacheattr(struct domain *d, ui= nt64_t gfn_start, rcu_read_unlock(&pinned_cacheattr_rcu_lock); return -ENOENT; =20 - case PAT_TYPE_UC_MINUS: - case PAT_TYPE_UNCACHABLE: - case PAT_TYPE_WRBACK: - case PAT_TYPE_WRCOMB: - case PAT_TYPE_WRPROT: - case PAT_TYPE_WRTHROUGH: + case X86_MT_UCM: + case X86_MT_UC: + case X86_MT_WB: + case X86_MT_WC: + case X86_MT_WP: + case X86_MT_WT: break; =20 default: @@ -681,7 +681,7 @@ int hvm_set_mem_pinned_cacheattr(struct domain *d, uint= 64_t gfn_start, =20 list_add_rcu(&range->list, &d->arch.hvm.pinned_cacheattr_ranges); p2m_memory_type_changed(d); - if ( type !=3D PAT_TYPE_WRBACK ) + if ( type !=3D X86_MT_WB ) flush_all(FLUSH_CACHE); =20 return 0; diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c index 7c81b80710f99e08fe8291d3e413c449322b777d..b543c3983d77ae807e8bd973306= 91a79d8d39bae 100644 --- a/xen/arch/x86/hvm/vmx/vmx.c +++ b/xen/arch/x86/hvm/vmx/vmx.c @@ -1231,14 +1231,14 @@ static void cf_check vmx_handle_cd(struct vcpu *v, = unsigned long value) * memory type are all UC. */ u64 uc_pat =3D - ((uint64_t)PAT_TYPE_UNCACHABLE) | /* PAT0 */ - ((uint64_t)PAT_TYPE_UNCACHABLE << 8) | /* PAT1 */ - ((uint64_t)PAT_TYPE_UNCACHABLE << 16) | /* PAT2 */ - ((uint64_t)PAT_TYPE_UNCACHABLE << 24) | /* PAT3 */ - ((uint64_t)PAT_TYPE_UNCACHABLE << 32) | /* PAT4 */ - ((uint64_t)PAT_TYPE_UNCACHABLE << 40) | /* PAT5 */ - ((uint64_t)PAT_TYPE_UNCACHABLE << 48) | /* PAT6 */ - ((uint64_t)PAT_TYPE_UNCACHABLE << 56); /* PAT7 */ + ((uint64_t)X86_MT_UC) | /* PAT0 */ + ((uint64_t)X86_MT_UC << 8) | /* PAT1 */ + ((uint64_t)X86_MT_UC << 16) | /* PAT2 */ + ((uint64_t)X86_MT_UC << 24) | /* PAT3 */ + ((uint64_t)X86_MT_UC << 32) | /* PAT4 */ + ((uint64_t)X86_MT_UC << 40) | /* PAT5 */ + ((uint64_t)X86_MT_UC << 48) | /* PAT6 */ + ((uint64_t)X86_MT_UC << 56); /* PAT7 */ =20 vmx_get_guest_pat(v, pat); vmx_set_guest_pat(v, uc_pat); diff --git a/xen/arch/x86/include/asm/mtrr.h b/xen/arch/x86/include/asm/mtr= r.h index 7733800b798fc2c72ba87e4ce6500e4183553d04..92fc930c692039b6c709d6a04f6= 553593f40aa55 100644 --- a/xen/arch/x86/include/asm/mtrr.h +++ b/xen/arch/x86/include/asm/mtrr.h @@ -16,17 +16,7 @@ #define NORMAL_CACHE_MODE 0 #define NO_FILL_CACHE_MODE 2 =20 -enum { - PAT_TYPE_UNCACHABLE=3D0, - PAT_TYPE_WRCOMB=3D1, - PAT_TYPE_WRTHROUGH=3D4, - PAT_TYPE_WRPROT=3D5, - PAT_TYPE_WRBACK=3D6, - PAT_TYPE_UC_MINUS=3D7, - PAT_TYPE_NUMS -}; - -#define INVALID_MEM_TYPE PAT_TYPE_NUMS +#define INVALID_MEM_TYPE X86_NUM_MT =20 /* In the Intel processor's MTRR interface, the MTRR type is always held in an 8 bit field: */ diff --git a/xen/arch/x86/mm/p2m-ept.c b/xen/arch/x86/mm/p2m-ept.c index d61d66c20e4180f8cbe21bcd97b568519e0b738e..126437285d8a9f222fca6a7b6ff= 4434b60637847 100644 --- a/xen/arch/x86/mm/p2m-ept.c +++ b/xen/arch/x86/mm/p2m-ept.c @@ -573,8 +573,8 @@ int epte_get_entry_emt(struct domain *d, gfn_t gfn, mfn= _t mfn, if ( gmtrr_mtype >=3D 0 ) { *ipat =3D true; - return gmtrr_mtype !=3D PAT_TYPE_UC_MINUS ? gmtrr_mtype - : MTRR_TYPE_UNCACHABLE; + return gmtrr_mtype !=3D X86_MT_UCM ? gmtrr_mtype + : MTRR_TYPE_UNCACHABLE; } if ( gmtrr_mtype =3D=3D -EADDRNOTAVAIL ) return -1; diff --git a/xen/arch/x86/mm/shadow/multi.c b/xen/arch/x86/mm/shadow/multi.c index 6bb564b0145285afc93b72a60b7797fcfe8696dc..b64bba70fc17906236872a017ad= 48ce91fd30803 100644 --- a/xen/arch/x86/mm/shadow/multi.c +++ b/xen/arch/x86/mm/shadow/multi.c @@ -561,7 +561,7 @@ _sh_propagate(struct vcpu *v, (type =3D hvm_get_mem_pinned_cacheattr(d, target_gfn, 0)) >= =3D 0 ) sflags |=3D pat_type_2_pte_flags(type); else if ( d->arch.hvm.is_in_uc_mode ) - sflags |=3D pat_type_2_pte_flags(PAT_TYPE_UNCACHABLE); + sflags |=3D pat_type_2_pte_flags(X86_MT_UC); else if ( iomem_access_permitted(d, mfn_x(target_mfn), mfn_x(target= _mfn)) ) { @@ -572,7 +572,7 @@ _sh_propagate(struct vcpu *v, mfn_to_maddr(target_mfn), MTRR_TYPE_UNCACHABLE); else if ( iommu_snoop ) - sflags |=3D pat_type_2_pte_flags(PAT_TYPE_WRBACK); + sflags |=3D pat_type_2_pte_flags(X86_MT_WB); else sflags |=3D get_pat_flags(v, gflags, --=20 Sincerely, Demi Marie Obenour (she/her/hers) Invisible Things Lab From nobody Fri Nov 1 00:05:37 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1671059598975899.3633054596095; Wed, 14 Dec 2022 15:13:18 -0800 (PST) Received: from list by lists.xenproject.org with outflank-mailman.462676.720895 (Exim 4.92) (envelope-from ) id 1p5avp-0002UP-E0; Wed, 14 Dec 2022 23:12:57 +0000 Received: by outflank-mailman (output) from mailman id 462676.720895; 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charset="utf-8" This allows eliminating of the former, with the exception of MTRR_NUM_TYPES. MTRR_NUM_TYPES is kept, as due to a quirk of the x86 architecture X86_MT_UCM (7) is not valid in an MTRR. Suggested-by: Andrew Cooper Signed-off-by: Demi Marie Obenour Reviewed-by: Jan Beulich --- Changes since v2: - Improve commit message - Do not replace MTRR_NUM_TYPES with X86_MT_UCM - State explicitly that MTRR_NUM_TYPES is kept --- xen/arch/x86/cpu/mtrr/generic.c | 10 ++--- xen/arch/x86/cpu/mtrr/main.c | 26 ++++++------- xen/arch/x86/e820.c | 4 +- xen/arch/x86/hvm/mtrr.c | 30 +++++++-------- xen/arch/x86/hvm/vmx/vmcs.c | 2 +- xen/arch/x86/hvm/vmx/vmx.c | 2 +- xen/arch/x86/include/asm/hvm/vmx/vmcs.h | 2 +- xen/arch/x86/include/asm/mtrr.h | 10 +---- xen/arch/x86/mm/p2m-ept.c | 51 ++++++++++++------------- xen/arch/x86/mm/shadow/multi.c | 2 +- 10 files changed, 66 insertions(+), 73 deletions(-) diff --git a/xen/arch/x86/cpu/mtrr/generic.c b/xen/arch/x86/cpu/mtrr/generi= c.c index 47aaf76226e0a8a0712b7211ed339a4a032ab3f3..660ae26c2350b3436a471155fc0= 426699ba8ac1d 100644 --- a/xen/arch/x86/cpu/mtrr/generic.c +++ b/xen/arch/x86/cpu/mtrr/generic.c @@ -127,11 +127,11 @@ static const char *__init mtrr_attrib_to_str(mtrr_typ= e x) { static const char __initconst strings[MTRR_NUM_TYPES][16] =3D { - [MTRR_TYPE_UNCACHABLE] =3D "uncachable", - [MTRR_TYPE_WRCOMB] =3D "write-combining", - [MTRR_TYPE_WRTHROUGH] =3D "write-through", - [MTRR_TYPE_WRPROT] =3D "write-protect", - [MTRR_TYPE_WRBACK] =3D "write-back", + [X86_MT_UC] =3D "uncachable", + [X86_MT_WC] =3D "write-combining", + [X86_MT_WT] =3D "write-through", + [X86_MT_WP] =3D "write-protect", + [X86_MT_WB] =3D "write-back", }; =20 return (x < ARRAY_SIZE(strings) && strings[x][0]) ? strings[x] : "?"; diff --git a/xen/arch/x86/cpu/mtrr/main.c b/xen/arch/x86/cpu/mtrr/main.c index 4e01c8d6f9df6562b94438f265d79a0a6fca8de6..2946003b84938f3b83c98b62dfa= a3ace90822983 100644 --- a/xen/arch/x86/cpu/mtrr/main.c +++ b/xen/arch/x86/cpu/mtrr/main.c @@ -163,10 +163,10 @@ static void cf_check ipi_handler(void *info) } =20 static inline int types_compatible(mtrr_type type1, mtrr_type type2) { - return type1 =3D=3D MTRR_TYPE_UNCACHABLE || - type2 =3D=3D MTRR_TYPE_UNCACHABLE || - (type1 =3D=3D MTRR_TYPE_WRTHROUGH && type2 =3D=3D MTRR_TYPE_WRBACK= ) || - (type1 =3D=3D MTRR_TYPE_WRBACK && type2 =3D=3D MTRR_TYPE_WRTHROUGH= ); + return type1 =3D=3D X86_MT_UC || + type2 =3D=3D X86_MT_UC || + (type1 =3D=3D X86_MT_WT && type2 =3D=3D X86_MT_WB) || + (type1 =3D=3D X86_MT_WB && type2 =3D=3D X86_MT_WT); } =20 /** @@ -297,13 +297,13 @@ static void set_mtrr(unsigned int reg, unsigned long = base, * * The available types are * - * %MTRR_TYPE_UNCACHABLE - No caching + * %X86_MT_UC - No caching * - * %MTRR_TYPE_WRBACK - Write data back in bursts whenever + * %X86_MT_WB - Write data back in bursts whenever * - * %MTRR_TYPE_WRCOMB - Write data back soon but allow bursts + * %X86_MT_WC - Write data back soon but allow bursts * - * %MTRR_TYPE_WRTHROUGH - Cache reads but not writes + * %X86_MT_WT - Cache reads but not writes * * BUGS: Needs a quiet flag for the cases where drivers do not mind * failures and do not wish system log messages to be sent. @@ -328,7 +328,7 @@ int mtrr_add_page(unsigned long base, unsigned long siz= e, } =20 /* If the type is WC, check that this processor supports it */ - if ((type =3D=3D MTRR_TYPE_WRCOMB) && !have_wrcomb()) { + if ((type =3D=3D X86_MT_WC) && !have_wrcomb()) { printk(KERN_WARNING "mtrr: your processor doesn't support write-combining\n"); return -EOPNOTSUPP; @@ -442,13 +442,13 @@ static int mtrr_check(unsigned long base, unsigned lo= ng size) * * The available types are * - * %MTRR_TYPE_UNCACHABLE - No caching + * %X86_MT_UC - No caching * - * %MTRR_TYPE_WRBACK - Write data back in bursts whenever + * %X86_MT_WB - Write data back in bursts whenever * - * %MTRR_TYPE_WRCOMB - Write data back soon but allow bursts + * %X86_MT_WC - Write data back soon but allow bursts * - * %MTRR_TYPE_WRTHROUGH - Cache reads but not writes + * %X86_MT_WT - Cache reads but not writes * * BUGS: Needs a quiet flag for the cases where drivers do not mind * failures and do not wish system log messages to be sent. diff --git a/xen/arch/x86/e820.c b/xen/arch/x86/e820.c index b653a19c93afb98c2d64330384cb4fa7b4d2e1ec..c5911cf48dc4a281c03ddef35f2= 3b19bc7af42eb 100644 --- a/xen/arch/x86/e820.c +++ b/xen/arch/x86/e820.c @@ -459,7 +459,7 @@ static uint64_t __init mtrr_top_of_ram(void) printk(" MTRR cap: %"PRIx64" type: %"PRIx64"\n", mtrr_cap, mtrr_de= f); =20 /* MTRRs enabled, and default memory type is not writeback? */ - if ( !test_bit(11, &mtrr_def) || ((uint8_t)mtrr_def =3D=3D MTRR_TYPE_W= RBACK) ) + if ( !test_bit(11, &mtrr_def) || ((uint8_t)mtrr_def =3D=3D X86_MT_WB) ) return 0; =20 /* @@ -476,7 +476,7 @@ static uint64_t __init mtrr_top_of_ram(void) printk(" MTRR[%d]: base %"PRIx64" mask %"PRIx64"\n", i, base, mask); =20 - if ( !test_bit(11, &mask) || ((uint8_t)base !=3D MTRR_TYPE_WRBACK)= ) + if ( !test_bit(11, &mask) || ((uint8_t)base !=3D X86_MT_WB) ) continue; base &=3D addr_mask; mask &=3D addr_mask; diff --git a/xen/arch/x86/hvm/mtrr.c b/xen/arch/x86/hvm/mtrr.c index 242623f3c239ee18a44f882ecb3910a00c615825..093103f6c768cf64f880d1b20e1= c14f5918c1250 100644 --- a/xen/arch/x86/hvm/mtrr.c +++ b/xen/arch/x86/hvm/mtrr.c @@ -39,11 +39,11 @@ static const uint8_t pat_entry_2_pte_flags[8] =3D { /* Effective mm type lookup table, according to MTRR and PAT. */ static const uint8_t mm_type_tbl[MTRR_NUM_TYPES][X86_NUM_MT] =3D { #define RS MEMORY_NUM_TYPES -#define UC MTRR_TYPE_UNCACHABLE -#define WB MTRR_TYPE_WRBACK -#define WC MTRR_TYPE_WRCOMB -#define WP MTRR_TYPE_WRPROT -#define WT MTRR_TYPE_WRTHROUGH +#define UC X86_MT_UC +#define WB X86_MT_WB +#define WC X86_MT_WC +#define WP X86_MT_WP +#define WT X86_MT_WT =20 /* PAT(UC, WC, RS, RS, WT, WP, WB, UC-) */ /* MTRR(UC) */ {UC, WC, RS, RS, UC, UC, UC, UC}, @@ -202,7 +202,7 @@ int mtrr_get_type(const struct mtrr_state *m, paddr_t p= a, unsigned int order) unsigned int seg, num_var_ranges =3D MASK_EXTR(m->mtrr_cap, MTRRcap_VCN= T); =20 if ( unlikely(!m->enabled) ) - return MTRR_TYPE_UNCACHABLE; + return X86_MT_UC; =20 pa &=3D mask; if ( (pa < 0x100000) && m->fixed_enabled ) @@ -277,13 +277,13 @@ int mtrr_get_type(const struct mtrr_state *m, paddr_t= pa, unsigned int order) return -1; =20 /* Two or more matches, one being UC? */ - if ( overlap_mtrr & (1 << MTRR_TYPE_UNCACHABLE) ) - return MTRR_TYPE_UNCACHABLE; + if ( overlap_mtrr & (1 << X86_MT_UC) ) + return X86_MT_UC; =20 /* Two or more matches, all of them WT and WB? */ if ( overlap_mtrr =3D=3D - ((1 << MTRR_TYPE_WRTHROUGH) | (1 << MTRR_TYPE_WRBACK)) ) - return MTRR_TYPE_WRTHROUGH; + ((1 << X86_MT_WT) | (1 << X86_MT_WB)) ) + return X86_MT_WT; =20 /* Behaviour is undefined, but return the last overlapped type. */ return overlap_mtrr_pos; @@ -381,11 +381,11 @@ static inline bool_t valid_mtrr_type(uint8_t type) { switch ( type ) { - case MTRR_TYPE_UNCACHABLE: - case MTRR_TYPE_WRBACK: - case MTRR_TYPE_WRCOMB: - case MTRR_TYPE_WRPROT: - case MTRR_TYPE_WRTHROUGH: + case X86_MT_UC: + case X86_MT_WB: + case X86_MT_WC: + case X86_MT_WP: + case X86_MT_WT: return 1; } return 0; diff --git a/xen/arch/x86/hvm/vmx/vmcs.c b/xen/arch/x86/hvm/vmx/vmcs.c index 84dbb88d33b76111833a37339186199f8bc03b5e..f0825216d722d978f221bb34a79= 7d8de5505cb80 100644 --- a/xen/arch/x86/hvm/vmx/vmcs.c +++ b/xen/arch/x86/hvm/vmx/vmcs.c @@ -555,7 +555,7 @@ static int vmx_init_vmcs_config(bool bsp) /* Require Write-Back (WB) memory type for VMCS accesses. */ opt =3D (vmx_basic_msr_high & (VMX_BASIC_MEMORY_TYPE_MASK >> 32)) / ((VMX_BASIC_MEMORY_TYPE_MASK & -VMX_BASIC_MEMORY_TYPE_MASK) >> 3= 2); - if ( opt !=3D MTRR_TYPE_WRBACK ) + if ( opt !=3D X86_MT_WB ) { printk("VMX: CPU%d has unexpected VMCS access type %u\n", smp_processor_id(), opt); diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c index b543c3983d77ae807e8bd97330691a79d8d39bae..4ae7dd56c9981d32ac545d6e7b7= c126b15f68969 100644 --- a/xen/arch/x86/hvm/vmx/vmx.c +++ b/xen/arch/x86/hvm/vmx/vmx.c @@ -434,7 +434,7 @@ static void cf_check domain_creation_finished(struct do= main *d) return; =20 ASSERT(epte_get_entry_emt(d, gfn, apic_access_mfn, 0, &ipat, - p2m_mmio_direct) =3D=3D MTRR_TYPE_WRBACK); + p2m_mmio_direct) =3D=3D X86_MT_WB); ASSERT(ipat); =20 if ( set_mmio_p2m_entry(d, gfn, apic_access_mfn, PAGE_ORDER_4K) ) diff --git a/xen/arch/x86/include/asm/hvm/vmx/vmcs.h b/xen/arch/x86/include= /asm/hvm/vmx/vmcs.h index 75f9928abfad28e3895fe3dd4058b2b0a6e145c3..65e9e27b5437adff59abc46976f= 73a9f2cc587da 100644 --- a/xen/arch/x86/include/asm/hvm/vmx/vmcs.h +++ b/xen/arch/x86/include/asm/hvm/vmx/vmcs.h @@ -38,7 +38,7 @@ struct vmx_msr_entry { u64 data; }; =20 -#define EPT_DEFAULT_MT MTRR_TYPE_WRBACK +#define EPT_DEFAULT_MT X86_MT_WB =20 struct ept_data { union { diff --git a/xen/arch/x86/include/asm/mtrr.h b/xen/arch/x86/include/asm/mtr= r.h index 92fc930c692039b6c709d6a04f6553593f40aa55..e4f6ca6048334b2094a1836cc2f= 298453641232f 100644 --- a/xen/arch/x86/include/asm/mtrr.h +++ b/xen/arch/x86/include/asm/mtrr.h @@ -3,15 +3,9 @@ =20 #include =20 -/* These are the region types. They match the architectural specification.= */ -#define MTRR_TYPE_UNCACHABLE 0 -#define MTRR_TYPE_WRCOMB 1 -#define MTRR_TYPE_WRTHROUGH 4 -#define MTRR_TYPE_WRPROT 5 -#define MTRR_TYPE_WRBACK 6 -#define MTRR_NUM_TYPES 7 +#define MTRR_NUM_TYPES X86_MT_UCM #define MEMORY_NUM_TYPES MTRR_NUM_TYPES -#define NO_HARDCODE_MEM_TYPE MTRR_NUM_TYPES +#define NO_HARDCODE_MEM_TYPE MTRR_NUM_TYPES =20 #define NORMAL_CACHE_MODE 0 #define NO_FILL_CACHE_MODE 2 diff --git a/xen/arch/x86/mm/p2m-ept.c b/xen/arch/x86/mm/p2m-ept.c index 126437285d8a9f222fca6a7b6ff4434b60637847..bb143c6c42c69db4e054b9156aa= d9a18ea0b2378 100644 --- a/xen/arch/x86/mm/p2m-ept.c +++ b/xen/arch/x86/mm/p2m-ept.c @@ -506,7 +506,7 @@ int epte_get_entry_emt(struct domain *d, gfn_t gfn, mfn= _t mfn, mfn_x(mfn) | ((1UL << order= ) - 1)) ) { *ipat =3D true; - return MTRR_TYPE_UNCACHABLE; + return X86_MT_UC; } /* Force invalid memory type so resolve_misconfig() will split it = */ return -1; @@ -515,7 +515,7 @@ int epte_get_entry_emt(struct domain *d, gfn_t gfn, mfn= _t mfn, if ( !mfn_valid(mfn) ) { *ipat =3D true; - return MTRR_TYPE_UNCACHABLE; + return X86_MT_UC; } =20 /* @@ -526,7 +526,7 @@ int epte_get_entry_emt(struct domain *d, gfn_t gfn, mfn= _t mfn, !cache_flush_permitted(d) ) { *ipat =3D true; - return MTRR_TYPE_WRBACK; + return X86_MT_WB; } =20 for ( special_pgs =3D i =3D 0; i < (1ul << order); i++ ) @@ -539,13 +539,13 @@ int epte_get_entry_emt(struct domain *d, gfn_t gfn, m= fn_t mfn, return -1; =20 *ipat =3D true; - return MTRR_TYPE_WRBACK; + return X86_MT_WB; } =20 switch ( type ) { case p2m_mmio_direct: - return MTRR_TYPE_UNCACHABLE; + return X86_MT_UC; =20 case p2m_grant_map_ro: case p2m_grant_map_rw: @@ -563,7 +563,7 @@ int epte_get_entry_emt(struct domain *d, gfn_t gfn, mfn= _t mfn, * diverges. See p2m_type_to_flags for the AMD attributes. */ *ipat =3D true; - return MTRR_TYPE_WRBACK; + return X86_MT_WB; =20 default: break; @@ -573,15 +573,14 @@ int epte_get_entry_emt(struct domain *d, gfn_t gfn, m= fn_t mfn, if ( gmtrr_mtype >=3D 0 ) { *ipat =3D true; - return gmtrr_mtype !=3D X86_MT_UCM ? gmtrr_mtype - : MTRR_TYPE_UNCACHABLE; + return gmtrr_mtype !=3D X86_MT_UCM ? gmtrr_mtype : X86_MT_UC; } if ( gmtrr_mtype =3D=3D -EADDRNOTAVAIL ) return -1; =20 gmtrr_mtype =3D v ? mtrr_get_type(&v->arch.hvm.mtrr, gfn_x(gfn) << PAGE_SHIFT, order) - : MTRR_TYPE_WRBACK; + : X86_MT_WB; hmtrr_mtype =3D mtrr_get_type(&mtrr_state, mfn_x(mfn) << PAGE_SHIFT, order); if ( gmtrr_mtype < 0 || hmtrr_mtype < 0 ) @@ -592,14 +591,14 @@ int epte_get_entry_emt(struct domain *d, gfn_t gfn, m= fn_t mfn, return hmtrr_mtype; =20 /* If either type is UC, we have to go with that one. */ - if ( gmtrr_mtype =3D=3D MTRR_TYPE_UNCACHABLE || - hmtrr_mtype =3D=3D MTRR_TYPE_UNCACHABLE ) - return MTRR_TYPE_UNCACHABLE; + if ( gmtrr_mtype =3D=3D X86_MT_UC || + hmtrr_mtype =3D=3D X86_MT_UC ) + return X86_MT_UC; =20 /* If either type is WB, we have to go with the other one. */ - if ( gmtrr_mtype =3D=3D MTRR_TYPE_WRBACK ) + if ( gmtrr_mtype =3D=3D X86_MT_WB ) return hmtrr_mtype; - if ( hmtrr_mtype =3D=3D MTRR_TYPE_WRBACK ) + if ( hmtrr_mtype =3D=3D X86_MT_WB ) return gmtrr_mtype; =20 /* @@ -610,13 +609,13 @@ int epte_get_entry_emt(struct domain *d, gfn_t gfn, m= fn_t mfn, * permit this), while WT and WP require writes to go straight to memo= ry * (WC can buffer them). */ - if ( (gmtrr_mtype =3D=3D MTRR_TYPE_WRTHROUGH && - hmtrr_mtype =3D=3D MTRR_TYPE_WRPROT) || - (gmtrr_mtype =3D=3D MTRR_TYPE_WRPROT && - hmtrr_mtype =3D=3D MTRR_TYPE_WRTHROUGH) ) - return MTRR_TYPE_WRPROT; + if ( (gmtrr_mtype =3D=3D X86_MT_WT && + hmtrr_mtype =3D=3D X86_MT_WP) || + (gmtrr_mtype =3D=3D X86_MT_WP && + hmtrr_mtype =3D=3D X86_MT_WT) ) + return X86_MT_WP; =20 - return MTRR_TYPE_UNCACHABLE; + return X86_MT_UC; } =20 /* @@ -1426,12 +1425,12 @@ void ept_p2m_uninit(struct p2m_domain *p2m) static const char *memory_type_to_str(unsigned int x) { static const char memory_types[8][3] =3D { - [MTRR_TYPE_UNCACHABLE] =3D "UC", - [MTRR_TYPE_WRCOMB] =3D "WC", - [MTRR_TYPE_WRTHROUGH] =3D "WT", - [MTRR_TYPE_WRPROT] =3D "WP", - [MTRR_TYPE_WRBACK] =3D "WB", - [MTRR_NUM_TYPES] =3D "??" + [X86_MT_UC] =3D "UC", + [X86_MT_WC] =3D "WC", + [X86_MT_WT] =3D "WT", + [X86_MT_WP] =3D "WP", + [X86_MT_WB] =3D "WB", + [MTRR_NUM_TYPES] =3D "??", }; =20 ASSERT(x < ARRAY_SIZE(memory_types)); diff --git a/xen/arch/x86/mm/shadow/multi.c b/xen/arch/x86/mm/shadow/multi.c index b64bba70fc17906236872a017ad48ce91fd30803..f5f7ff021bd9e057c5b6f6329de= 7acb5ef05d58f 100644 --- a/xen/arch/x86/mm/shadow/multi.c +++ b/xen/arch/x86/mm/shadow/multi.c @@ -570,7 +570,7 @@ _sh_propagate(struct vcpu *v, gflags, gfn_to_paddr(target_gfn), mfn_to_maddr(target_mfn), - MTRR_TYPE_UNCACHABLE); + X86_MT_UC); else if ( iommu_snoop ) sflags |=3D pat_type_2_pte_flags(X86_MT_WB); else --=20 Sincerely, Demi Marie Obenour (she/her/hers) Invisible Things Lab From nobody Fri Nov 1 00:05:37 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1671059599372838.2563245647867; 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charset="utf-8" This allows eliminating the former. No functional change intended. Suggested-by: Andrew Cooper Signed-off-by: Demi Marie Obenour --- xen/arch/x86/include/asm/hvm/vmx/vmx.h | 9 --------- xen/arch/x86/mm/hap/nested_ept.c | 4 ++-- 2 files changed, 2 insertions(+), 11 deletions(-) diff --git a/xen/arch/x86/include/asm/hvm/vmx/vmx.h b/xen/arch/x86/include/= asm/hvm/vmx/vmx.h index 8eedf59155e01ec1ca84dcc6b30961f9c884cb3b..49fe9822fac5eae15b67f0cfd3d= 0cb96347dc7ed 100644 --- a/xen/arch/x86/include/asm/hvm/vmx/vmx.h +++ b/xen/arch/x86/include/asm/hvm/vmx/vmx.h @@ -80,15 +80,6 @@ typedef enum { #define EPTE_RWX_MASK 0x7 #define EPTE_FLAG_MASK 0x7f =20 -#define EPT_EMT_UC 0 -#define EPT_EMT_WC 1 -#define EPT_EMT_RSV0 2 -#define EPT_EMT_RSV1 3 -#define EPT_EMT_WT 4 -#define EPT_EMT_WP 5 -#define EPT_EMT_WB 6 -#define EPT_EMT_RSV2 7 - #define PI_xAPIC_NDST_MASK 0xFF00 =20 void vmx_asm_vmexit_handler(struct cpu_user_regs); diff --git a/xen/arch/x86/mm/hap/nested_ept.c b/xen/arch/x86/mm/hap/nested_= ept.c index 1cb7fefc37091bf7d92a277203e652add5611871..84fdec024ad216f2c9b333ac65d= 46b55cf90dada 100644 --- a/xen/arch/x86/mm/hap/nested_ept.c +++ b/xen/arch/x86/mm/hap/nested_ept.c @@ -84,8 +84,8 @@ static bool_t nept_emt_bits_check(ept_entry_t e, uint32_t= level) { if ( e.sp || level =3D=3D 1 ) { - if ( e.emt =3D=3D EPT_EMT_RSV0 || e.emt =3D=3D EPT_EMT_RSV1 || - e.emt =3D=3D EPT_EMT_RSV2 ) + if ( e.emt =3D=3D X86_MT_RESERVED_1 || e.emt =3D=3D X86_MT_RESERVE= D_2 || + e.emt =3D=3D X86_MT_UCM ) return 1; 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charset="utf-8" No functional change intended. Signed-off-by: Demi Marie Obenour --- Changes since v2: - Keep MTRR_NUM_TYPES and adjust commit message accordingly --- xen/arch/x86/hvm/mtrr.c | 18 +++++++++--------- xen/arch/x86/include/asm/mtrr.h | 2 -- xen/arch/x86/mm/shadow/multi.c | 2 +- 3 files changed, 10 insertions(+), 12 deletions(-) diff --git a/xen/arch/x86/hvm/mtrr.c b/xen/arch/x86/hvm/mtrr.c index 093103f6c768cf64f880d1b20e1c14f5918c1250..05e978041d62fd0d559462de181= a04bef8a5bca9 100644 --- a/xen/arch/x86/hvm/mtrr.c +++ b/xen/arch/x86/hvm/mtrr.c @@ -38,7 +38,7 @@ static const uint8_t pat_entry_2_pte_flags[8] =3D { =20 /* Effective mm type lookup table, according to MTRR and PAT. */ static const uint8_t mm_type_tbl[MTRR_NUM_TYPES][X86_NUM_MT] =3D { -#define RS MEMORY_NUM_TYPES +#define RS MTRR_NUM_TYPES #define UC X86_MT_UC #define WB X86_MT_WB #define WC X86_MT_WC @@ -66,9 +66,9 @@ static const uint8_t mm_type_tbl[MTRR_NUM_TYPES][X86_NUM_= MT] =3D { * Reverse lookup table, to find a pat type according to MTRR and effective * memory type. This table is dynamically generated. */ -static uint8_t __read_mostly mtrr_epat_tbl[MTRR_NUM_TYPES][MEMORY_NUM_TYPE= S] =3D - { [0 ... MTRR_NUM_TYPES-1] =3D - { [0 ... MEMORY_NUM_TYPES-1] =3D INVALID_MEM_TYPE } +static uint8_t __read_mostly mtrr_epat_tbl[MTRR_NUM_TYPES][MTRR_NUM_TYPES]= =3D + { [0 ... MTRR_NUM_TYPES - 1] =3D + { [0 ... MTRR_NUM_TYPES - 1] =3D INVALID_MEM_TYPE } }; =20 /* Lookup table for PAT entry of a given PAT value in host PAT. */ @@ -85,7 +85,7 @@ static int __init cf_check hvm_mtrr_pat_init(void) { unsigned int tmp =3D mm_type_tbl[i][j]; =20 - if ( tmp < MEMORY_NUM_TYPES ) + if ( tmp < MTRR_NUM_TYPES ) mtrr_epat_tbl[i][tmp] =3D j; } } @@ -317,11 +317,11 @@ static uint8_t effective_mm_type(struct mtrr_state *m, uint8_t gmtrr_mtype) { uint8_t mtrr_mtype, pat_value; - =20 + /* if get_pat_flags() gives a dedicated MTRR type, * just use it - */=20 - if ( gmtrr_mtype =3D=3D NO_HARDCODE_MEM_TYPE ) + */ + if ( gmtrr_mtype =3D=3D MTRR_NUM_TYPES ) mtrr_mtype =3D mtrr_get_type(m, gpa, 0); else mtrr_mtype =3D gmtrr_mtype; @@ -346,7 +346,7 @@ uint32_t get_pat_flags(struct vcpu *v, /* 1. Get the effective memory type of guest physical address, * with the pair of guest MTRR and PAT */ - guest_eff_mm_type =3D effective_mm_type(g, pat, gpaddr,=20 + guest_eff_mm_type =3D effective_mm_type(g, pat, gpaddr, gl1e_flags, gmtrr_mtype); /* 2. Get the memory type of host physical address, with MTRR */ shadow_mtrr_type =3D mtrr_get_type(&mtrr_state, spaddr, 0); diff --git a/xen/arch/x86/include/asm/mtrr.h b/xen/arch/x86/include/asm/mtr= r.h index e4f6ca6048334b2094a1836cc2f298453641232f..4b7f840a965954cc4b59698327a= 37e47026893a4 100644 --- a/xen/arch/x86/include/asm/mtrr.h +++ b/xen/arch/x86/include/asm/mtrr.h @@ -4,8 +4,6 @@ #include =20 #define MTRR_NUM_TYPES X86_MT_UCM -#define MEMORY_NUM_TYPES MTRR_NUM_TYPES -#define NO_HARDCODE_MEM_TYPE MTRR_NUM_TYPES =20 #define NORMAL_CACHE_MODE 0 #define NO_FILL_CACHE_MODE 2 diff --git a/xen/arch/x86/mm/shadow/multi.c b/xen/arch/x86/mm/shadow/multi.c index f5f7ff021bd9e057c5b6f6329de7acb5ef05d58f..1faf9940db6b0afefc5977c00c0= 0fb6a39cd27d2 100644 --- a/xen/arch/x86/mm/shadow/multi.c +++ b/xen/arch/x86/mm/shadow/multi.c @@ -578,7 +578,7 @@ _sh_propagate(struct vcpu *v, gflags, gfn_to_paddr(target_gfn), mfn_to_maddr(target_mfn), - NO_HARDCODE_MEM_TYPE); + MTRR_NUM_TYPES); } } =20 --=20 Sincerely, Demi Marie Obenour (she/her/hers) Invisible Things Lab From nobody Fri Nov 1 00:05:37 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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charset="utf-8" This avoids it being a magic constant that is difficult for humans to decode. Use BUILD_BUG_ON to check that the old and new values are identical. Signed-off-by: Demi Marie Obenour --- xen/arch/x86/include/asm/processor.h | 10 +++++++++- xen/arch/x86/mm.c | 6 ++++++ 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/xen/arch/x86/include/asm/processor.h b/xen/arch/x86/include/as= m/processor.h index 8e2816fae9b97bd4e153a30cc3802971fe0355af..9535b1f7f49d75e6853365e6109= a33359c740f4f 100644 --- a/xen/arch/x86/include/asm/processor.h +++ b/xen/arch/x86/include/asm/processor.h @@ -96,7 +96,15 @@ * Host IA32_CR_PAT value to cover all memory types. This is not the defa= ult * MSR_PAT value, and is an ABI with PV guests. */ -#define XEN_MSR_PAT _AC(0x050100070406, ULL) +#define XEN_MSR_PAT (X86_MT_WB << 0x00 | \ + X86_MT_WT << 0x08 | \ + X86_MT_UCM << 0x10 | \ + X86_MT_UC << 0x18 | \ + X86_MT_WC << 0x20 | \ + X86_MT_WP << 0x28 | \ + X86_MT_UC << 0x30 | \ + X86_MT_UC << 0x38 | \ + 0) =20 #ifndef __ASSEMBLY__ =20 diff --git a/xen/arch/x86/mm.c b/xen/arch/x86/mm.c index b73cb29327ba49703673886d09d79f2f8928a6c0..a8def47aa3bf9770576c62a1900= 32d45d63dd86e 100644 --- a/xen/arch/x86/mm.c +++ b/xen/arch/x86/mm.c @@ -6355,6 +6355,12 @@ unsigned long get_upper_mfn_bound(void) return min(max_mfn, 1UL << (paddr_bits - PAGE_SHIFT)) - 1; } =20 +static void __init __maybe_unused build_assertions(void) +{ + BUILD_BUG_ON(XEN_MSR_PAT !=3D 0x050100070406ULL && + "wrong XEN_MSR_PAT breaks PV guests"); +} + /* * Local variables: * mode: C --=20 Sincerely, Demi Marie Obenour (she/her/hers) Invisible Things Lab From nobody Fri Nov 1 00:05:37 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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charset="utf-8" It may be desirable to change Xen's PAT for various reasons. This requires changes to several _PAGE_* macros as well. Add static assertions to check that XEN_MSR_PAT is consistent with the _PAGE_* macros, and that _PAGE_WB is 0 as required by Linux. Signed-off-by: Demi Marie Obenour --- xen/arch/x86/mm.c | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/xen/arch/x86/mm.c b/xen/arch/x86/mm.c index a8def47aa3bf9770576c62a190032d45d63dd86e..7fb1a0f91910952640378f316a6= 8096a08895b37 100644 --- a/xen/arch/x86/mm.c +++ b/xen/arch/x86/mm.c @@ -6357,8 +6357,44 @@ unsigned long get_upper_mfn_bound(void) =20 static void __init __maybe_unused build_assertions(void) { + /* A bunch of static assertions to check that the XEN_MSR_PAT is valid + * and consistent with the _PAGE_* macros */ BUILD_BUG_ON(XEN_MSR_PAT !=3D 0x050100070406ULL && "wrong XEN_MSR_PAT breaks PV guests"); + BUILD_BUG_ON(_PAGE_WB && "Linux requires _PAGE_WB to be 0"); +#define PAT_VALUE(v) (0xFF & (XEN_MSR_PAT >> (8 * (v)))) +#define BAD_VALUE(v) ((v) < 0 || (v) > 7 || = \ + (v) =3D=3D X86_MT_RESERVED_1 || (v) =3D=3D X86_MT_RE= SERVED_2) +#define BAD_PAT_VALUE(v) BUILD_BUG_ON(BAD_VALUE(PAT_VALUE(v))) + BAD_PAT_VALUE(0); + BAD_PAT_VALUE(1); + BAD_PAT_VALUE(2); + BAD_PAT_VALUE(3); + BAD_PAT_VALUE(4); + BAD_PAT_VALUE(5); + BAD_PAT_VALUE(6); + BAD_PAT_VALUE(7); +#undef BAD_PAT_VALUE +#undef BAD_VALUE +#define PAT_SHIFT(page_value) (((page_value) & _PAGE_PAT) >> 5 | = \ + ((page_value) & (_PAGE_PCD | _PAGE_PWT)) >>= 3) +#define CHECK_PAGE_VALUE(page_value) do { = \ + /* Check that the _PAGE_* macros only use bits from PAGE_CACHE_ATTRS *= / \ + BUILD_BUG_ON(((_PAGE_##page_value) & PAGE_CACHE_ATTRS) !=3D = \ + (_PAGE_##page_value)); = \ + /* Check that the _PAGE_* are consistent with XEN_MSR_PAT */ = \ + BUILD_BUG_ON(PAT_VALUE(PAT_SHIFT(_PAGE_##page_value)) !=3D = \ + (X86_MT_##page_value)); = \ +} while (0) + CHECK_PAGE_VALUE(WT); + CHECK_PAGE_VALUE(WB); + CHECK_PAGE_VALUE(WC); + CHECK_PAGE_VALUE(UC); + CHECK_PAGE_VALUE(UCM); + CHECK_PAGE_VALUE(WP); +#undef CHECK_PAGE_VALUE +#undef PAT_SHIFT +#undef PAT_VALUE } =20 /* --=20 Sincerely, Demi Marie Obenour (she/her/hers) Invisible Things Lab From nobody Fri Nov 1 00:05:37 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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charset="utf-8" Setting cacheability flags that are not ones specified by Xen is a bug in the guest. By default, inject #GP into any guest that does this. allow_invalid_cacheability can be used on the Xen command line to disable this check. Signed-off-by: Demi Marie Obenour --- xen/arch/x86/mm.c | 25 ++++++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/xen/arch/x86/mm.c b/xen/arch/x86/mm.c index 7fb1a0f91910952640378f316a68096a08895b37..a199bb05031e0fb1ea4c25ef1d6= 41afe71690d74 100644 --- a/xen/arch/x86/mm.c +++ b/xen/arch/x86/mm.c @@ -145,6 +145,8 @@ =20 #ifdef CONFIG_PV #include "pv/mm.h" +bool allow_invalid_cacheability; +boolean_param("allow_invalid_cacheability", allow_invalid_cacheability); #endif =20 /* Override macros from asm/page.h to make them work with mfn_t */ @@ -1346,7 +1348,28 @@ static int promote_l1_table(struct page_info *page) } else { - switch ( ret =3D get_page_from_l1e(pl1e[i], d, d) ) + l1_pgentry_t l1e =3D pl1e[i]; + + BUILD_BUG_ON(PAGE_CACHE_ATTRS > 0xffff); + if ( !allow_invalid_cacheability ) + { + switch ( l1e.l1 & PAGE_CACHE_ATTRS ) + { + case _PAGE_WB: + case _PAGE_UC: + case _PAGE_UCM: + case _PAGE_WC: + case _PAGE_WT: + case _PAGE_WP: + break; + default: + pv_inject_hw_exception(TRAP_gp_fault, 0); + ret =3D -EINVAL; + goto fail; + } + } + + switch ( ret =3D get_page_from_l1e(l1e, d, d) ) { default: goto fail; --=20 Sincerely, Demi Marie Obenour (she/her/hers) Invisible Things Lab From nobody Fri Nov 1 00:05:37 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1671059722212980.8963118694883; Wed, 14 Dec 2022 15:15:22 -0800 (PST) Received: from list by lists.xenproject.org with outflank-mailman.462737.720939 (Exim 4.92) (envelope-from ) id 1p5axq-00066V-W6; Wed, 14 Dec 2022 23:15:02 +0000 Received: by outflank-mailman (output) from mailman id 462737.720939; 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charset="utf-8" This is purely for testing, to see if it works around a bug in i915. It is not intended to be merged. NOT-signed-off-by: DO NOT MERGE --- xen/arch/x86/include/asm/page.h | 4 ++-- xen/arch/x86/include/asm/processor.h | 13 +++++-------- xen/arch/x86/mm.c | 2 -- 3 files changed, 7 insertions(+), 12 deletions(-) diff --git a/xen/arch/x86/include/asm/page.h b/xen/arch/x86/include/asm/pag= e.h index b585235d064a567082582c8e92a4e8283fd949ca..ab9b46f1d0901e50a83fd035ff2= 8d1bda0b781a2 100644 --- a/xen/arch/x86/include/asm/page.h +++ b/xen/arch/x86/include/asm/page.h @@ -333,11 +333,11 @@ void efi_update_l4_pgtable(unsigned int l4idx, l4_pge= ntry_t); =20 /* Memory types, encoded under Xen's choice of MSR_PAT. */ #define _PAGE_WB ( 0) -#define _PAGE_WT ( _PAGE_PWT) +#define _PAGE_WC ( _PAGE_PWT) #define _PAGE_UCM ( _PAGE_PCD ) #define _PAGE_UC ( _PAGE_PCD | _PAGE_PWT) -#define _PAGE_WC (_PAGE_PAT ) #define _PAGE_WP (_PAGE_PAT | _PAGE_PWT) +#define _PAGE_WT (_PAGE_PAT | _PAGE_PCD | _PAGE_PWT) =20 /* * Debug option: Ensure that granted mappings are not implicitly unmapped. diff --git a/xen/arch/x86/include/asm/processor.h b/xen/arch/x86/include/as= m/processor.h index 9535b1f7f49d75e6853365e6109a33359c740f4f..04e9674ea76ce11a2ac00fb7457= f3ce97db24d70 100644 --- a/xen/arch/x86/include/asm/processor.h +++ b/xen/arch/x86/include/asm/processor.h @@ -92,18 +92,15 @@ X86_EFLAGS_NT|X86_EFLAGS_DF|X86_EFLAGS_IF| \ X86_EFLAGS_TF) =20 -/* - * Host IA32_CR_PAT value to cover all memory types. This is not the defa= ult - * MSR_PAT value, and is an ABI with PV guests. - */ +/* Linux PAT, required by i915 driver */ #define XEN_MSR_PAT (X86_MT_WB << 0x00 | \ - X86_MT_WT << 0x08 | \ + X86_MT_WC << 0x08 | \ X86_MT_UCM << 0x10 | \ X86_MT_UC << 0x18 | \ - X86_MT_WC << 0x20 | \ + X86_MT_WB << 0x20 | \ X86_MT_WP << 0x28 | \ - X86_MT_UC << 0x30 | \ - X86_MT_UC << 0x38 | \ + X86_MT_UCM << 0x30 | \ + X86_MT_WT << 0x38 | \ 0) =20 #ifndef __ASSEMBLY__ diff --git a/xen/arch/x86/mm.c b/xen/arch/x86/mm.c index a199bb05031e0fb1ea4c25ef1d641afe71690d74..b844ff441d8ddd371bc69f4e43c= 796d03638cbb3 100644 --- a/xen/arch/x86/mm.c +++ b/xen/arch/x86/mm.c @@ -6382,8 +6382,6 @@ static void __init __maybe_unused build_assertions(vo= id) { /* A bunch of static assertions to check that the XEN_MSR_PAT is valid * and consistent with the _PAGE_* macros */ - BUILD_BUG_ON(XEN_MSR_PAT !=3D 0x050100070406ULL && - "wrong XEN_MSR_PAT breaks PV guests"); BUILD_BUG_ON(_PAGE_WB && "Linux requires _PAGE_WB to be 0"); #define PAT_VALUE(v) (0xFF & (XEN_MSR_PAT >> (8 * (v)))) #define BAD_VALUE(v) ((v) < 0 || (v) > 7 || = \ --=20 Sincerely, Demi Marie Obenour (she/her/hers) Invisible Things Lab