From nobody Sun May 12 23:32:47 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail(p=none dis=none) header.from=arm.com Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 16515707553671008.0915157210603; Tue, 3 May 2022 02:39:15 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.319342.539569 (Exim 4.92) (envelope-from ) id 1nlozT-0005mw-Es; Tue, 03 May 2022 09:38:43 +0000 Received: by outflank-mailman (output) from mailman id 319342.539569; Tue, 03 May 2022 09:38:43 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1nlozT-0005mo-Bd; Tue, 03 May 2022 09:38:43 +0000 Received: by outflank-mailman (input) for mailman id 319342; Tue, 03 May 2022 09:38:42 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1nlozS-0005X9-5c for xen-devel@lists.xenproject.org; Tue, 03 May 2022 09:38:42 +0000 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by se1-gles-flk1.inumbo.com (Halon) with ESMTP id d0d66aa9-cac4-11ec-8fc4-03012f2f19d4; Tue, 03 May 2022 11:38:41 +0200 (CEST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6145012FC; Tue, 3 May 2022 02:38:40 -0700 (PDT) Received: from e109506.cambridge.arm.com (e109506.cambridge.arm.com [10.1.199.62]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 8F0123F73D; Tue, 3 May 2022 02:38:39 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: d0d66aa9-cac4-11ec-8fc4-03012f2f19d4 From: Bertrand Marquis To: xen-devel@lists.xenproject.org Cc: Stefano Stabellini , Julien Grall , Volodymyr Babchuk Subject: [PATCH 1/3] xen/arm: Sync sysregs and cpuinfo with Linux 5.18-rc3 Date: Tue, 3 May 2022 10:38:29 +0100 Message-Id: <832955382caa4ced744ec7894282592b62e8cf61.1651570561.git.bertrand.marquis@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZM-MESSAGEID: 1651570757397100007 Content-Type: text/plain; charset="utf-8" Sync arm64 sysreg bit shift definitions with status of Linux kernel as of 5.18-rc3 version (linux commit b2d229d4ddb1). Sync ID registers sanitization with the status of Linux 5.18-rc3 and add sanitization of ISAR2 registers. Complete AA64ISAR2 and AA64MMFR1 with more fields. While there add a comment for MMFR bitfields as for other registers in the cpuinfo structure definition. Signed-off-by: Bertrand Marquis reviewed-by to the first patch with the changes from Linux. --- xen/arch/arm/arm64/cpufeature.c | 18 +++++- xen/arch/arm/include/asm/arm64/sysregs.h | 76 ++++++++++++++++++++---- xen/arch/arm/include/asm/cpufeature.h | 14 ++++- 3 files changed, 91 insertions(+), 17 deletions(-) diff --git a/xen/arch/arm/arm64/cpufeature.c b/xen/arch/arm/arm64/cpufeatur= e.c index 6e5d30dc7b..d9039d37b2 100644 --- a/xen/arch/arm/arm64/cpufeature.c +++ b/xen/arch/arm/arm64/cpufeature.c @@ -143,6 +143,16 @@ static const struct arm64_ftr_bits ftr_id_aa64isar1[] = =3D { ARM64_FTR_END, }; =20 +static const struct arm64_ftr_bits ftr_id_aa64isar2[] =3D { + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64ISAR2_CLEA= RBHB_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), + FTR_STRICT, FTR_EXACT, ID_AA64ISAR2_APA3_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), + FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_GPA3_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_R= PRES_SHIFT, 4, 0), + ARM64_FTR_END, +}; + static const struct arm64_ftr_bits ftr_id_aa64pfr0[] =3D { ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV= 3_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV= 2_SHIFT, 4, 0), @@ -158,8 +168,8 @@ static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = =3D { S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_= SHIFT, 4, ID_AA64PFR0_FP_NI), ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL3= _SHIFT, 4, 0), ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL2= _SHIFT, 4, 0), - ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1= _SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY), - ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL0= _SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY), + ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1= _SHIFT, 4, ID_AA64PFR0_ELx_64BIT_ONLY), + ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL0= _SHIFT, 4, ID_AA64PFR0_ELx_64BIT_ONLY), ARM64_FTR_END, }; =20 @@ -197,7 +207,7 @@ static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = =3D { }; =20 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] =3D { - ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ECV_S= HIFT, 4, 0), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ECV_= SHIFT, 4, 0), ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_FGT_S= HIFT, 4, 0), ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EXS_S= HIFT, 4, 0), /* @@ -243,6 +253,7 @@ static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = =3D { }; =20 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] =3D { + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_AFP_= SHIFT, 4, 0), ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_ETS_S= HIFT, 4, 0), ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_TWED_= SHIFT, 4, 0), ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_XNX_S= HIFT, 4, 0), @@ -588,6 +599,7 @@ void update_system_features(const struct cpuinfo_arm *n= ew) =20 SANITIZE_ID_REG(isa64, 0, aa64isar0); SANITIZE_ID_REG(isa64, 1, aa64isar1); + SANITIZE_ID_REG(isa64, 2, aa64isar2); =20 SANITIZE_ID_REG(zfr64, 0, aa64zfr0); =20 diff --git a/xen/arch/arm/include/asm/arm64/sysregs.h b/xen/arch/arm/includ= e/asm/arm64/sysregs.h index eac08ed33f..54670084c3 100644 --- a/xen/arch/arm/include/asm/arm64/sysregs.h +++ b/xen/arch/arm/include/asm/arm64/sysregs.h @@ -144,6 +144,30 @@ =20 /* id_aa64isar2 */ #define ID_AA64ISAR2_CLEARBHB_SHIFT 28 +#define ID_AA64ISAR2_APA3_SHIFT 12 +#define ID_AA64ISAR2_GPA3_SHIFT 8 +#define ID_AA64ISAR2_RPRES_SHIFT 4 +#define ID_AA64ISAR2_WFXT_SHIFT 0 + +#define ID_AA64ISAR2_RPRES_8BIT 0x0 +#define ID_AA64ISAR2_RPRES_12BIT 0x1 +/* + * Value 0x1 has been removed from the architecture, and is + * reserved, but has not yet been removed from the ARM ARM + * as of ARM DDI 0487G.b. + */ +#define ID_AA64ISAR2_WFXT_NI 0x0 +#define ID_AA64ISAR2_WFXT_SUPPORTED 0x2 + +#define ID_AA64ISAR2_APA3_NI 0x0 +#define ID_AA64ISAR2_APA3_ARCHITECTED 0x1 +#define ID_AA64ISAR2_APA3_ARCH_EPAC 0x2 +#define ID_AA64ISAR2_APA3_ARCH_EPAC2 0x3 +#define ID_AA64ISAR2_APA3_ARCH_EPAC2_FPAC 0x4 +#define ID_AA64ISAR2_APA3_ARCH_EPAC2_FPAC_CMB 0x5 + +#define ID_AA64ISAR2_GPA3_NI 0x0 +#define ID_AA64ISAR2_GPA3_ARCHITECTED 0x1 =20 /* id_aa64pfr0 */ #define ID_AA64PFR0_CSV3_SHIFT 60 @@ -165,14 +189,13 @@ #define ID_AA64PFR0_AMU 0x1 #define ID_AA64PFR0_SVE 0x1 #define ID_AA64PFR0_RAS_V1 0x1 +#define ID_AA64PFR0_RAS_V1P1 0x2 #define ID_AA64PFR0_FP_NI 0xf #define ID_AA64PFR0_FP_SUPPORTED 0x0 #define ID_AA64PFR0_ASIMD_NI 0xf #define ID_AA64PFR0_ASIMD_SUPPORTED 0x0 -#define ID_AA64PFR0_EL1_64BIT_ONLY 0x1 -#define ID_AA64PFR0_EL1_32BIT_64BIT 0x2 -#define ID_AA64PFR0_EL0_64BIT_ONLY 0x1 -#define ID_AA64PFR0_EL0_32BIT_64BIT 0x2 +#define ID_AA64PFR0_ELx_64BIT_ONLY 0x1 +#define ID_AA64PFR0_ELx_32BIT_64BIT 0x2 =20 /* id_aa64pfr1 */ #define ID_AA64PFR1_MPAMFRAC_SHIFT 16 @@ -189,6 +212,7 @@ #define ID_AA64PFR1_MTE_NI 0x0 #define ID_AA64PFR1_MTE_EL0 0x1 #define ID_AA64PFR1_MTE 0x2 +#define ID_AA64PFR1_MTE_ASYMM 0x3 =20 /* id_aa64zfr0 */ #define ID_AA64ZFR0_F64MM_SHIFT 56 @@ -228,17 +252,37 @@ #define ID_AA64MMFR0_ASID_SHIFT 4 #define ID_AA64MMFR0_PARANGE_SHIFT 0 =20 -#define ID_AA64MMFR0_TGRAN4_NI 0xf -#define ID_AA64MMFR0_TGRAN4_SUPPORTED 0x0 -#define ID_AA64MMFR0_TGRAN64_NI 0xf -#define ID_AA64MMFR0_TGRAN64_SUPPORTED 0x0 -#define ID_AA64MMFR0_TGRAN16_NI 0x0 -#define ID_AA64MMFR0_TGRAN16_SUPPORTED 0x1 +#define ID_AA64MMFR0_ASID_8 0x0 +#define ID_AA64MMFR0_ASID_16 0x2 + +#define ID_AA64MMFR0_TGRAN4_NI 0xf +#define ID_AA64MMFR0_TGRAN4_SUPPORTED_MIN 0x0 +#define ID_AA64MMFR0_TGRAN4_SUPPORTED_MAX 0x7 +#define ID_AA64MMFR0_TGRAN64_NI 0xf +#define ID_AA64MMFR0_TGRAN64_SUPPORTED_MIN 0x0 +#define ID_AA64MMFR0_TGRAN64_SUPPORTED_MAX 0x7 +#define ID_AA64MMFR0_TGRAN16_NI 0x0 +#define ID_AA64MMFR0_TGRAN16_SUPPORTED_MIN 0x1 +#define ID_AA64MMFR0_TGRAN16_SUPPORTED_MAX 0xf + +#define ID_AA64MMFR0_PARANGE_32 0x0 +#define ID_AA64MMFR0_PARANGE_36 0x1 +#define ID_AA64MMFR0_PARANGE_40 0x2 +#define ID_AA64MMFR0_PARANGE_42 0x3 +#define ID_AA64MMFR0_PARANGE_44 0x4 #define ID_AA64MMFR0_PARANGE_48 0x5 #define ID_AA64MMFR0_PARANGE_52 0x6 =20 +#define ARM64_MIN_PARANGE_BITS 32 + +#define ID_AA64MMFR0_TGRAN_2_SUPPORTED_DEFAULT 0x0 +#define ID_AA64MMFR0_TGRAN_2_SUPPORTED_NONE 0x1 +#define ID_AA64MMFR0_TGRAN_2_SUPPORTED_MIN 0x2 +#define ID_AA64MMFR0_TGRAN_2_SUPPORTED_MAX 0x7 + /* id_aa64mmfr1 */ #define ID_AA64MMFR1_ECBHB_SHIFT 60 +#define ID_AA64MMFR1_AFP_SHIFT 44 #define ID_AA64MMFR1_ETS_SHIFT 36 #define ID_AA64MMFR1_TWED_SHIFT 32 #define ID_AA64MMFR1_XNX_SHIFT 28 @@ -271,6 +315,9 @@ #define ID_AA64MMFR2_CNP_SHIFT 0 =20 /* id_aa64dfr0 */ +#define ID_AA64DFR0_MTPMU_SHIFT 48 +#define ID_AA64DFR0_TRBE_SHIFT 44 +#define ID_AA64DFR0_TRACE_FILT_SHIFT 40 #define ID_AA64DFR0_DOUBLELOCK_SHIFT 36 #define ID_AA64DFR0_PMSVER_SHIFT 32 #define ID_AA64DFR0_CTX_CMPS_SHIFT 28 @@ -284,11 +331,18 @@ #define ID_AA64DFR0_PMUVER_8_1 0x4 #define ID_AA64DFR0_PMUVER_8_4 0x5 #define ID_AA64DFR0_PMUVER_8_5 0x6 +#define ID_AA64DFR0_PMUVER_8_7 0x7 #define ID_AA64DFR0_PMUVER_IMP_DEF 0xf =20 +#define ID_AA64DFR0_PMSVER_8_2 0x1 +#define ID_AA64DFR0_PMSVER_8_3 0x2 + #define ID_DFR0_PERFMON_SHIFT 24 =20 -#define ID_DFR0_PERFMON_8_1 0x4 +#define ID_DFR0_PERFMON_8_0 0x3 +#define ID_DFR0_PERFMON_8_1 0x4 +#define ID_DFR0_PERFMON_8_4 0x5 +#define ID_DFR0_PERFMON_8_5 0x6 =20 #define ID_ISAR4_SWP_FRAC_SHIFT 28 #define ID_ISAR4_PSR_M_SHIFT 24 diff --git a/xen/arch/arm/include/asm/cpufeature.h b/xen/arch/arm/include/a= sm/cpufeature.h index f7368766c0..4719de47f3 100644 --- a/xen/arch/arm/include/asm/cpufeature.h +++ b/xen/arch/arm/include/asm/cpufeature.h @@ -230,6 +230,7 @@ struct cpuinfo_arm { union { register_t bits[3]; struct { + /* MMFR0 */ unsigned long pa_range:4; unsigned long asid_bits:4; unsigned long bigend:4; @@ -240,16 +241,21 @@ struct cpuinfo_arm { unsigned long tgranule_4K:4; unsigned long __res0:32; =20 + /* MMFR1 */ unsigned long hafdbs:4; unsigned long vmid_bits:4; unsigned long vh:4; unsigned long hpds:4; unsigned long lo:4; unsigned long pan:4; - unsigned long __res1:8; - unsigned long __res2:28; + unsigned long specsei:4; + unsigned long xnx:4; + unsigned long twed:4; + unsigned long ets:4; + unsigned long __res1:20; unsigned long ecbhb:4; =20 + /* MMFR2 */ unsigned long __res3:64; }; } mm64; @@ -293,7 +299,9 @@ struct cpuinfo_arm { unsigned long __res2:8; =20 /* ISAR2 */ - unsigned long __res3:28; + unsigned long wfxt:4; + unsigned long rpres:4; + unsigned long __res3:20; unsigned long clearbhb:4; =20 unsigned long __res4:32; --=20 2.25.1 From nobody Sun May 12 23:32:47 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail(p=none dis=none) header.from=arm.com Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1651570752247944.4826437419001; Tue, 3 May 2022 02:39:12 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.319343.539581 (Exim 4.92) (envelope-from ) id 1nlozU-00062a-N9; Tue, 03 May 2022 09:38:44 +0000 Received: by outflank-mailman (output) from mailman id 319343.539581; Tue, 03 May 2022 09:38:44 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1nlozU-00062T-JP; Tue, 03 May 2022 09:38:44 +0000 Received: by outflank-mailman (input) for mailman id 319343; Tue, 03 May 2022 09:38:43 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1nlozT-0005X9-5l for xen-devel@lists.xenproject.org; Tue, 03 May 2022 09:38:43 +0000 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by se1-gles-flk1.inumbo.com (Halon) with ESMTP id d159bfae-cac4-11ec-8fc4-03012f2f19d4; Tue, 03 May 2022 11:38:41 +0200 (CEST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4534E13D5; Tue, 3 May 2022 02:38:41 -0700 (PDT) Received: from e109506.cambridge.arm.com (e109506.cambridge.arm.com [10.1.199.62]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 8D5373F73D; Tue, 3 May 2022 02:38:40 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: d159bfae-cac4-11ec-8fc4-03012f2f19d4 From: Bertrand Marquis To: xen-devel@lists.xenproject.org Cc: Stefano Stabellini , Julien Grall , Volodymyr Babchuk Subject: [PATCH 2/3] xen/arm: Advertise workaround 1 if we apply 3 Date: Tue, 3 May 2022 10:38:30 +0100 Message-Id: <8119538cce93516f1e78d37d578996a195686f89.1651570561.git.bertrand.marquis@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZM-MESSAGEID: 1651570754090100001 Content-Type: text/plain; charset="utf-8" SMCC_WORKAROUND_3 is handling both Spectre v2 and spectre BHB. So when a guest is asking if we support workaround 1, tell yes if we apply workaround 3 on exception entry as it handles it. This will allow guests not supporting Spectre BHB but impacted by spectre v2 to still handle it correctly. The modified behaviour is coherent with what the Linux kernel does in KVM for guests. While there use ARM_SMCCC_SUCCESS instead of 0 for the return code value for workaround detection to be coherent with Workaround 2 handling. Signed-off-by: Bertrand Marquis Acked-by: Julien Grall --- xen/arch/arm/vsmc.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/xen/arch/arm/vsmc.c b/xen/arch/arm/vsmc.c index b633ff2fe8..676740ef15 100644 --- a/xen/arch/arm/vsmc.c +++ b/xen/arch/arm/vsmc.c @@ -104,8 +104,13 @@ static bool handle_arch(struct cpu_user_regs *regs) switch ( arch_func_id ) { case ARM_SMCCC_ARCH_WORKAROUND_1_FID: - if ( cpus_have_cap(ARM_HARDEN_BRANCH_PREDICTOR) ) - ret =3D 0; + /* + * Workaround 3 is also mitigating spectre v2 so advertise tha= t we + * support Workaround 1 if we do Workaround 3 on exception ent= ry. + */ + if ( cpus_have_cap(ARM_HARDEN_BRANCH_PREDICTOR) || + cpus_have_cap(ARM_WORKAROUND_BHB_SMCC_3) ) + ret =3D ARM_SMCCC_SUCCESS; break; case ARM_SMCCC_ARCH_WORKAROUND_2_FID: switch ( get_ssbd_state() ) @@ -126,7 +131,7 @@ static bool handle_arch(struct cpu_user_regs *regs) break; case ARM_SMCCC_ARCH_WORKAROUND_3_FID: if ( cpus_have_cap(ARM_WORKAROUND_BHB_SMCC_3) ) - ret =3D 0; + ret =3D ARM_SMCCC_SUCCESS; break; } =20 --=20 2.25.1 From nobody Sun May 12 23:32:47 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail(p=none dis=none) header.from=arm.com Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1651570754391618.428747123723; Tue, 3 May 2022 02:39:14 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.319344.539592 (Exim 4.92) (envelope-from ) id 1nlozV-0006Ii-Uy; Tue, 03 May 2022 09:38:45 +0000 Received: by outflank-mailman (output) from mailman id 319344.539592; Tue, 03 May 2022 09:38:45 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1nlozV-0006Ib-RV; Tue, 03 May 2022 09:38:45 +0000 Received: by outflank-mailman (input) for mailman id 319344; Tue, 03 May 2022 09:38:44 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1nlozU-0005vC-8H for xen-devel@lists.xenproject.org; Tue, 03 May 2022 09:38:44 +0000 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by se1-gles-sth1.inumbo.com (Halon) with ESMTP id d2048c21-cac4-11ec-a406-831a346695d4; Tue, 03 May 2022 11:38:43 +0200 (CEST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 29029143D; Tue, 3 May 2022 02:38:42 -0700 (PDT) Received: from e109506.cambridge.arm.com (e109506.cambridge.arm.com [10.1.199.62]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 71AB23F73D; Tue, 3 May 2022 02:38:41 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: d2048c21-cac4-11ec-a406-831a346695d4 From: Bertrand Marquis To: xen-devel@lists.xenproject.org Cc: Stefano Stabellini , Julien Grall , Volodymyr Babchuk Subject: [PATCH 3/3] xen/arm: Add sb instruction support Date: Tue, 3 May 2022 10:38:31 +0100 Message-Id: <24fd2364294345f103cb13bdab2ad0b706681071.1651570561.git.bertrand.marquis@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZM-MESSAGEID: 1651570755635100005 Content-Type: text/plain; charset="utf-8" This patch is adding sb instruction support when it is supported by a CPU on arm64. To achieve this, the "sb" macro is moved to sub-arch macros.h so that we can use sb instruction when available through alternative on arm64 and keep the current behaviour on arm32. A new cpuerrata capability is introduced to enable the alternative code for sb when the support is detected using isa64 coprocessor register. The sb instruction is encoded using its hexadecimal value. Signed-off-by: Bertrand Marquis --- xen/arch/arm/cpuerrata.c | 14 ++++++++++++++ xen/arch/arm/include/asm/arm32/macros.h | 8 ++++++++ xen/arch/arm/include/asm/arm64/macros.h | 18 ++++++++++++++++++ xen/arch/arm/include/asm/cpufeature.h | 3 ++- xen/arch/arm/include/asm/macros.h | 9 --------- 5 files changed, 42 insertions(+), 10 deletions(-) diff --git a/xen/arch/arm/cpuerrata.c b/xen/arch/arm/cpuerrata.c index ae649d16ef..e744abe800 100644 --- a/xen/arch/arm/cpuerrata.c +++ b/xen/arch/arm/cpuerrata.c @@ -458,6 +458,13 @@ static bool has_ssbd_mitigation(const struct arm_cpu_c= apabilities *entry) } #endif =20 +#ifdef CONFIG_ARM_64 +static bool has_sb_instruction(const struct arm_cpu_capabilities *entry) +{ + return system_cpuinfo.isa64.sb; +} +#endif + #define MIDR_RANGE(model, min, max) \ .matches =3D is_affected_midr_range, \ .midr_model =3D model, \ @@ -674,6 +681,13 @@ static const struct arm_cpu_capabilities arm_errata[] = =3D { .capability =3D ARM64_WORKAROUND_AT_SPECULATE, MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), }, +#ifdef CONFIG_ARM_64 + { + .desc =3D "Speculation barrier (SB)", + .capability =3D ARM64_HAS_SB, + .matches =3D has_sb_instruction, + }, +#endif {}, }; =20 diff --git a/xen/arch/arm/include/asm/arm32/macros.h b/xen/arch/arm/include= /asm/arm32/macros.h index a4e20aa520..cf0ddad52b 100644 --- a/xen/arch/arm/include/asm/arm32/macros.h +++ b/xen/arch/arm/include/asm/arm32/macros.h @@ -5,4 +5,12 @@ mov pc, lr .endm =20 + /* + * Speculative barrier + */ + .macro sb + dsb nsh + isb + .endm + #endif /* __ASM_ARM_ARM32_MACROS_H */ diff --git a/xen/arch/arm/include/asm/arm64/macros.h b/xen/arch/arm/include= /asm/arm64/macros.h index 140e223b4c..e639cec400 100644 --- a/xen/arch/arm/include/asm/arm64/macros.h +++ b/xen/arch/arm/include/asm/arm64/macros.h @@ -1,6 +1,24 @@ #ifndef __ASM_ARM_ARM64_MACROS_H #define __ASM_ARM_ARM64_MACROS_H =20 +#include + + /* + * Speculative barrier + */ + .macro sb +alternative_if_not ARM64_HAS_SB + dsb nsh + isb +alternative_else +/* + * SB encoding as given in chapter C6.2.264 of ARM ARM (DDI 0487H.a). + */ + .inst 0xd50330ff + nop +alternative_endif + .endm + /* * @dst: Result of get_cpu_info() */ diff --git a/xen/arch/arm/include/asm/cpufeature.h b/xen/arch/arm/include/a= sm/cpufeature.h index 4719de47f3..9370805900 100644 --- a/xen/arch/arm/include/asm/cpufeature.h +++ b/xen/arch/arm/include/asm/cpufeature.h @@ -67,8 +67,9 @@ #define ARM_WORKAROUND_BHB_LOOP_24 13 #define ARM_WORKAROUND_BHB_LOOP_32 14 #define ARM_WORKAROUND_BHB_SMCC_3 15 +#define ARM64_HAS_SB 16 =20 -#define ARM_NCAPS 16 +#define ARM_NCAPS 17 =20 #ifndef __ASSEMBLY__ =20 diff --git a/xen/arch/arm/include/asm/macros.h b/xen/arch/arm/include/asm/m= acros.h index 1aa373760f..91ea3505e4 100644 --- a/xen/arch/arm/include/asm/macros.h +++ b/xen/arch/arm/include/asm/macros.h @@ -5,15 +5,6 @@ # error "This file should only be included in assembly file" #endif =20 - /* - * Speculative barrier - * XXX: Add support for the 'sb' instruction - */ - .macro sb - dsb nsh - isb - .endm - #if defined (CONFIG_ARM_32) # include #elif defined(CONFIG_ARM_64) --=20 2.25.1