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[142.79.211.230]) by smtp.gmail.com with ESMTPSA id e29sm25287oiy.53.2021.06.02.08.09.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Jun 2021 08:09:01 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 02ad2af5-521b-4054-bc34-f33394e27e80 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=UpOeaMEF9ZtjJDEC63CsaCASXXXpK+CjdZ0eTjBgKHU=; b=WluB/sS6QKDAdVmEC8aMbwfgJHfOnvp+lHftJ84SREIvF8lL4iu030ifMdB4f/lEoE dJ/8KHPWiTnVJTk7oPqFzRTXlrqhp9zJ0SPtkuzxSdOj4/2dOOkXqsCRlfzaftoVR+BL 4Wn7ifq6m1d+hldFgMHMvmlHO3Ph01sc+CF11TqYqCicxsK6OqlMk3G0IrbZFAGsun7y CchjplKJYLefzisuOlJFb4eWTBAsWssxC+/jdJurq8c2gv+wH54pIOg/TBoDlu+cG5Zn N1tj9NBdSDlMvDPO3ImJpb2FlABGSJl/jd2/59in3SO3kmtVT168x/PIHpRBAfsV36qh aYPw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=UpOeaMEF9ZtjJDEC63CsaCASXXXpK+CjdZ0eTjBgKHU=; b=ip36EpCn4S1T/V4CZ4KSa0ItvhgSPYg51Uq4x3dVjovPHAOnAyBkvFUwV385emAnNN PvBL6k/bN0TDtb+haAr1EUfS6rRqZ06YpmG6UviZEtwj20e4E475h6ZaDzV//TCIE4yP vlb2oNb2WuZh+RsAEraCPNKRxCEBEHHwrf5LCeQxdnNeotS5gy3vhLBHZFjpO35erNyq scqwa+yb5hLXQnhBxRUSi//rICLwDs4uyq9K0P4TMyiEF057BvLzOgBkQGaLrk5ug4dB TdAzpk7tDq3mrD/jLowQbXmaBfHnnRcXRVkswwMSrC/sTnPwdihFFk+LXcAgx2DFROS3 JcLg== X-Gm-Message-State: AOAM530sp/23NekOeYykU7bnfixRiTV/tlzaEfc78M1Jk9U+I5xoLHcq 9u2ODmcl3e5X73P0PCMX+HhC2ExtDjaHxA== X-Google-Smtp-Source: ABdhPJwQ+WXaQFw7ZYh1xXrbG0Cfz68tGyEPXixc1hcXDRbGyg+YPQFZpit6zSv+QZpYBNL16XrjhQ== X-Received: by 2002:a05:6830:192:: with SMTP id q18mr27810801ota.79.1622646541846; Wed, 02 Jun 2021 08:09:01 -0700 (PDT) From: Connor Davis To: xen-devel@lists.xenproject.org Cc: Bobby Eshleman , Alistair Francis , Connor Davis , Andrew Cooper , George Dunlap , Ian Jackson , Jan Beulich , Julien Grall , Stefano Stabellini , Wei Liu Subject: [PATCH v5 1/2] xen/char: Default HAS_NS16550 to y only for X86 and ARM Date: Wed, 2 Jun 2021 09:08:27 -0600 Message-Id: <2c24cadace47e51e9e3fce6614e0f5e83db6c3af.1622645816.git.connojdavis@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Content-Type: text/plain; charset="utf-8" Defaulting to yes only for X86 and ARM reduces the requirements for a minimal build when porting new architectures. Signed-off-by: Connor Davis --- xen/drivers/char/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/xen/drivers/char/Kconfig b/xen/drivers/char/Kconfig index b572305657..2ff5b288e2 100644 --- a/xen/drivers/char/Kconfig +++ b/xen/drivers/char/Kconfig @@ -1,5 +1,6 @@ config HAS_NS16550 bool "NS16550 UART driver" if ARM + default n if RISCV default y help This selects the 16550-series UART support. For most systems, say Y. --=20 2.31.1 From nobody Sat Apr 27 18:44:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1622646570; cv=none; d=zohomail.com; s=zohoarc; b=WG/kKb+ZeP8FNH4abTDCAS4DwRquHwmQC+pYEEsXyL0XMElJ3ZWuYNbQFZ84iG7XzIPT8Al2igqFd9jMz/mXsTjpyJSjQbhrytLLifUQU/U1bcHJ1vBDDLdbO91Hq/wccVgT0utLV8/YVcVb2bw8NvE6geKih3nZr2GeRbDn0Kw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622646570; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=y7wXnoCWLDx7IQREahGv6BGDyqktjGf6yjBgrAWmplI=; b=XoXE1plONk96AhUGDsJjSmt5Cs/VbHcufNxTW4Mj3qhi0MREVm3fw2x+hwSWLo3ElO8t2utihYeYOU3kLrkx6BxraiENHR5FfolEBgKXokSfrfFPmUCOGLz3uTkh6D2OFfKIoRN13m9LphEEOM/rv5OhXY5c77B7qoIcWT4wFV4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1622646570513528.720979019181; Wed, 2 Jun 2021 08:09:30 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.136078.252501 (Exim 4.92) (envelope-from ) id 1loSUa-0002Sw-CK; Wed, 02 Jun 2021 15:09:12 +0000 Received: by outflank-mailman (output) from mailman id 136078.252501; Wed, 02 Jun 2021 15:09:12 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1loSUa-0002Sl-8t; Wed, 02 Jun 2021 15:09:12 +0000 Received: by outflank-mailman (input) for mailman id 136078; Wed, 02 Jun 2021 15:09:10 +0000 Received: from us1-rack-iad1.inumbo.com ([172.99.69.81]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1loSUY-0001oH-Mt for xen-devel@lists.xenproject.org; Wed, 02 Jun 2021 15:09:10 +0000 Received: from mail-ot1-x32c.google.com (unknown [2607:f8b0:4864:20::32c]) by us1-rack-iad1.inumbo.com (Halon) with ESMTPS id ebce3ce2-2b4a-473e-9997-11237b2b5212; Wed, 02 Jun 2021 15:09:04 +0000 (UTC) Received: by mail-ot1-x32c.google.com with SMTP id h19-20020a9d6f930000b02903c0c4560e99so2729671otq.1 for ; Wed, 02 Jun 2021 08:09:04 -0700 (PDT) Received: from localhost.localdomain (142-79-211-230.starry-inc.net. [142.79.211.230]) by smtp.gmail.com with ESMTPSA id e29sm25287oiy.53.2021.06.02.08.09.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Jun 2021 08:09:03 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: ebce3ce2-2b4a-473e-9997-11237b2b5212 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=y7wXnoCWLDx7IQREahGv6BGDyqktjGf6yjBgrAWmplI=; b=dFj4sTASo4fYEOIPGgyNyZzFb60dHRKTCym915IFPJc7+6zqJF8n3CWo3rb4FVdZYd x7vut7ldrlhsi/e/BBlPObmdUfoI17UvEcAil+i/VqulcmPuP2LNRSZ4JFAv4Asbqp1k pmfCenfqHaQduIS2MmVPytOJhTha9EmBDtFxv49gvGKQjCqRhdIlxqK6u6hw2eh5lfdd zzmPd0//+oPcb6TnolQn3PZw+kBH91RojWoo2omF1XGtCEfuJ3PeZ3Fzc98ev8j9ec1T I65oyujx7vmPQNSYqkyvROXL84kTdgnS0oHejFeutIJEldZyX4gDpwH71xs1UB7oEe7n urGg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=y7wXnoCWLDx7IQREahGv6BGDyqktjGf6yjBgrAWmplI=; b=T4WuUgSnXrRdgHB3SEw2ps3xIgmtPDB9KFttrbT8aGFMXIU4N0PwStO3p50ZXXDvyZ m/e1bycJbbf2b5e3ufoNUQwyubMb33O/LYzVL+PnMYvrUqRG2RkKML9QutfCeSq8rA9U Xe8JHuFBV5S2iEPiEtXAiTP2GsHM0LwilQVQ0+xMyIPSSDeQVfV0ZHcp9TolXdyDMp4E /1RlsUAsC9rkZkY0isamzcDQJjbC3kEwjyfUTz28DdLzCDfQFmd0/GAFYbljpJai2vuD xDt/O5TLPtGT8E/cTDZfOGbfEkZUYbGIKIYXWqAB1nZCcuRfqEZgdeS2NIgGQqDBo7ST gHsg== X-Gm-Message-State: AOAM533JQzgokL9nuSQoPc8C00lC89KCyqBIVpsOHSpQiy11i+ya8t6x RkNa15ketgKsuYjOVPHQNq8cLAWX8Kovow== X-Google-Smtp-Source: ABdhPJyzas22Hcmg5hLVbfL0rGAEcBh7pHsLWfn/TD//YITzbDc5sZbEfOvQW1B1p12JeK4xaRHG2w== X-Received: by 2002:a9d:6756:: with SMTP id w22mr14209050otm.369.1622646544071; Wed, 02 Jun 2021 08:09:04 -0700 (PDT) From: Connor Davis To: xen-devel@lists.xenproject.org Cc: Bobby Eshleman , Alistair Francis , Connor Davis , Andrew Cooper , George Dunlap , Ian Jackson , Jan Beulich , Julien Grall , Stefano Stabellini , Wei Liu Subject: [PATCH v5 2/2] xen: Add files needed for minimal riscv build Date: Wed, 2 Jun 2021 09:08:28 -0600 Message-Id: <97ae93649f0a4366d6957f3b56d43a522ac21685.1622645816.git.connojdavis@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Content-Type: text/plain; charset="utf-8" Add arch-specific makefiles and configs needed to build for riscv. Also add a minimal head.S that is a simple infinite loop. head.o can be built with $ make XEN_TARGET_ARCH=3Driscv64 SUBSYSTEMS=3Dxen -C xen tiny64_defconfig $ make XEN_TARGET_ARCH=3Driscv64 SUBSYSTEMS=3Dxen -C xen TARGET=3Driscv64/h= ead.o No other TARGET is supported at the moment. Signed-off-by: Connor Davis --- Bob: I moved back to XEN_TARGET_ARCH=3Driscv64 because supplying just XEN_TARGET_ARCH=3Driscv causes TARGET_ARCH =3D=3D TARGET_SUBARCH, and that broke the build after the recent commit b6ecd5c8bc "build: centralize / unify asm-offsets generation". It also deviates from how x86 and arm work now, so I think this change is for the best for now. That commit is also why the PHONY include target is added in the riscv/Makefile. --- MAINTAINERS | 8 +++++ config/riscv64.mk | 5 +++ xen/Makefile | 8 +++-- xen/arch/riscv/Kconfig | 47 +++++++++++++++++++++++++ xen/arch/riscv/Kconfig.debug | 0 xen/arch/riscv/Makefile | 2 ++ xen/arch/riscv/Rules.mk | 0 xen/arch/riscv/arch.mk | 14 ++++++++ xen/arch/riscv/configs/tiny64_defconfig | 13 +++++++ xen/arch/riscv/riscv64/asm-offsets.c | 0 xen/arch/riscv/riscv64/head.S | 6 ++++ xen/include/asm-riscv/config.h | 47 +++++++++++++++++++++++++ 12 files changed, 148 insertions(+), 2 deletions(-) create mode 100644 config/riscv64.mk create mode 100644 xen/arch/riscv/Kconfig create mode 100644 xen/arch/riscv/Kconfig.debug create mode 100644 xen/arch/riscv/Makefile create mode 100644 xen/arch/riscv/Rules.mk create mode 100644 xen/arch/riscv/arch.mk create mode 100644 xen/arch/riscv/configs/tiny64_defconfig create mode 100644 xen/arch/riscv/riscv64/asm-offsets.c create mode 100644 xen/arch/riscv/riscv64/head.S create mode 100644 xen/include/asm-riscv/config.h diff --git a/MAINTAINERS b/MAINTAINERS index d46b08a0d2..956e71220d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -456,6 +456,14 @@ F: tools/libs/light/libxl_nonetbuffer.c F: tools/hotplug/Linux/remus-netbuf-setup F: tools/hotplug/Linux/block-drbd-probe =20 +RISCV +M: Bob Eshleman +R: Connor Davis +S: Supported +F: config/riscv64.mk +F: xen/arch/riscv/ +F: xen/include/asm-riscv/ + RTDS SCHEDULER M: Dario Faggioli M: Meng Xu diff --git a/config/riscv64.mk b/config/riscv64.mk new file mode 100644 index 0000000000..a5a21e5fa2 --- /dev/null +++ b/config/riscv64.mk @@ -0,0 +1,5 @@ +CONFIG_RISCV :=3D y +CONFIG_RISCV_64 :=3D y +CONFIG_RISCV_$(XEN_OS) :=3D y + +CONFIG_XEN_INSTALL_SUFFIX :=3D diff --git a/xen/Makefile b/xen/Makefile index 7ce7692354..89879fad4c 100644 --- a/xen/Makefile +++ b/xen/Makefile @@ -26,7 +26,9 @@ MAKEFLAGS +=3D -rR EFI_MOUNTPOINT ?=3D $(BOOT_DIR)/efi =20 ARCH=3D$(XEN_TARGET_ARCH) -SRCARCH=3D$(shell echo $(ARCH) | sed -e 's/x86.*/x86/' -e s'/arm\(32\|64\)= /arm/g') +SRCARCH=3D$(shell echo $(ARCH) | \ + sed -e 's/x86.*/x86/' -e s'/arm\(32\|64\)/arm/g' \ + -e s'/riscv.*/riscv/g') =20 # Don't break if the build process wasn't called from the top level # we need XEN_TARGET_ARCH to generate the proper config @@ -35,7 +37,8 @@ include $(XEN_ROOT)/Config.mk # Set ARCH/SUBARCH appropriately. export TARGET_SUBARCH :=3D $(XEN_TARGET_ARCH) export TARGET_ARCH :=3D $(shell echo $(XEN_TARGET_ARCH) | \ - sed -e 's/x86.*/x86/' -e s'/arm\(32\|64\)/arm/= g') + sed -e 's/x86.*/x86/' -e s'/arm\(32\|64\)/arm/= g' \ + -e s'/riscv.*/riscv/g') =20 # Allow someone to change their config file export KCONFIG_CONFIG ?=3D .config @@ -335,6 +338,7 @@ _clean: delete-unfresh-files $(MAKE) $(clean) xsm $(MAKE) $(clean) crypto $(MAKE) $(clean) arch/arm + $(MAKE) $(clean) arch/riscv $(MAKE) $(clean) arch/x86 $(MAKE) $(clean) test $(MAKE) -f $(BASEDIR)/tools/kconfig/Makefile.kconfig ARCH=3D$(ARCH) SRCAR= CH=3D$(SRCARCH) clean diff --git a/xen/arch/riscv/Kconfig b/xen/arch/riscv/Kconfig new file mode 100644 index 0000000000..bd8381c5e0 --- /dev/null +++ b/xen/arch/riscv/Kconfig @@ -0,0 +1,47 @@ +config RISCV + def_bool y + +config RISCV_64 + def_bool y + select 64BIT + +config ARCH_DEFCONFIG + string + default "arch/riscv/configs/tiny64_defconfig" + +menu "Architecture Features" + +source "arch/Kconfig" + +endmenu + +menu "ISA Selection" + +choice + prompt "Base ISA" + default RISCV_ISA_RV64IMA if RISCV_64 + help + This selects the base ISA extensions that Xen will target. + +config RISCV_ISA_RV64IMA + bool "RV64IMA" + help + Use the RV64I base ISA, plus the "M" and "A" extensions + for integer multiply/divide and atomic instructions, respectively. + +endchoice + +config RISCV_ISA_C + bool "Compressed extension" + help + Add "C" to the ISA subsets that the toolchain is allowed to + emit when building Xen, which results in compressed instructions + in the Xen binary. + + If unsure, say N. + +endmenu + +source "common/Kconfig" + +source "drivers/Kconfig" diff --git a/xen/arch/riscv/Kconfig.debug b/xen/arch/riscv/Kconfig.debug new file mode 100644 index 0000000000..e69de29bb2 diff --git a/xen/arch/riscv/Makefile b/xen/arch/riscv/Makefile new file mode 100644 index 0000000000..942e4ffbc1 --- /dev/null +++ b/xen/arch/riscv/Makefile @@ -0,0 +1,2 @@ +.PHONY: include +include: diff --git a/xen/arch/riscv/Rules.mk b/xen/arch/riscv/Rules.mk new file mode 100644 index 0000000000..e69de29bb2 diff --git a/xen/arch/riscv/arch.mk b/xen/arch/riscv/arch.mk new file mode 100644 index 0000000000..53dadb8975 --- /dev/null +++ b/xen/arch/riscv/arch.mk @@ -0,0 +1,14 @@ +######################################## +# RISCV-specific definitions + +CFLAGS-$(CONFIG_RISCV_64) +=3D -mabi=3Dlp64 + +riscv-march-$(CONFIG_RISCV_ISA_RV64IMA) :=3D rv64ima +riscv-march-$(CONFIG_RISCV_ISA_C) :=3D $(riscv-march-y)c + +# Note that -mcmodel=3Dmedany is used so that Xen can be mapped +# into the upper half _or_ the lower half of the address space. +# -mcmodel=3Dmedlow would force Xen into the lower half. + +CFLAGS +=3D -march=3D$(riscv-march-y) -mstrict-align -mcmodel=3Dmedany +CFLAGS +=3D -I$(BASEDIR)/include diff --git a/xen/arch/riscv/configs/tiny64_defconfig b/xen/arch/riscv/confi= gs/tiny64_defconfig new file mode 100644 index 0000000000..3c9a2ff941 --- /dev/null +++ b/xen/arch/riscv/configs/tiny64_defconfig @@ -0,0 +1,13 @@ +# CONFIG_SCHED_CREDIT is not set +# CONFIG_SCHED_RTDS is not set +# CONFIG_SCHED_NULL is not set +# CONFIG_SCHED_ARINC653 is not set +# CONFIG_TRACEBUFFER is not set +# CONFIG_HYPFS is not set +# CONFIG_GRANT_TABLE is not set +# CONFIG_SPECULATIVE_HARDEN_ARRAY is not set + +CONFIG_RISCV_64=3Dy +CONFIG_DEBUG=3Dy +CONFIG_DEBUG_INFO=3Dy +CONFIG_EXPERT=3Dy diff --git a/xen/arch/riscv/riscv64/asm-offsets.c b/xen/arch/riscv/riscv64/= asm-offsets.c new file mode 100644 index 0000000000..e69de29bb2 diff --git a/xen/arch/riscv/riscv64/head.S b/xen/arch/riscv/riscv64/head.S new file mode 100644 index 0000000000..0dbc27ba75 --- /dev/null +++ b/xen/arch/riscv/riscv64/head.S @@ -0,0 +1,6 @@ +#include + + .text + +ENTRY(start) + j start diff --git a/xen/include/asm-riscv/config.h b/xen/include/asm-riscv/config.h new file mode 100644 index 0000000000..e2ae21de61 --- /dev/null +++ b/xen/include/asm-riscv/config.h @@ -0,0 +1,47 @@ +#ifndef __RISCV_CONFIG_H__ +#define __RISCV_CONFIG_H__ + +#if defined(CONFIG_RISCV_64) +# define LONG_BYTEORDER 3 +# define ELFSIZE 64 +# define MAX_VIRT_CPUS 128u +#else +# error "Unsupported RISCV variant" +#endif + +#define BYTES_PER_LONG (1 << LONG_BYTEORDER) +#define BITS_PER_LONG (BYTES_PER_LONG << 3) +#define POINTER_ALIGN BYTES_PER_LONG + +#define BITS_PER_LLONG 64 + +/* xen_ulong_t is always 64 bits */ +#define BITS_PER_XEN_ULONG 64 + +#define CONFIG_RISCV_L1_CACHE_SHIFT 6 +#define CONFIG_PAGEALLOC_MAX_ORDER 18 +#define CONFIG_DOMU_MAX_ORDER 9 +#define CONFIG_HWDOM_MAX_ORDER 10 + +#define OPT_CONSOLE_STR "dtuart" +#define INVALID_VCPU_ID MAX_VIRT_CPUS + +/* Linkage for RISCV */ +#ifdef __ASSEMBLY__ +#define ALIGN .align 2 + +#define ENTRY(name) \ + .globl name; \ + ALIGN; \ + name: +#endif + +#endif /* __RISCV_CONFIG_H__ */ +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ --=20 2.31.1