From nobody Wed May 8 20:21:36 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1608219771; cv=none; d=zohomail.com; s=zohoarc; b=igZN7fabKfeCmUpprgADsbceP6QXVN4V/aRToQwAas3i2/IZycvqD85Cis1z3N6uNNB8Z4TyVqL2dFPEqA5YsD4XO7GZ80czjNz/d9IgGcW5PJe0uuHJN+fhdUrk6cwyA+aRbnrvt4RdI20DM31uXFj3s1RmINdBibz0YIQAFXE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1608219771; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=rtZD5vfkim3VR1d3ktgdstpZBApPAWNx+MrSginiGGo=; b=L5LEPUTyKcUc3cx6pl2aV5dVl4juxWWA1dszNCJk5RSdN4yNsEKwQDuhBDHP03GwahKPOb09JRA6AgmxRlRK7DeJEeb/T6FMctsJZme0HiJQkixPRUNqt7dKluUsRvFSs85y71+7NU+JrAf7FKtCha+t9WgCwHdsdHWOTVx6eSY= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1608219770835855.2228543356176; Thu, 17 Dec 2020 07:42:50 -0800 (PST) Received: from list by lists.xenproject.org with outflank-mailman.55979.97664 (Exim 4.92) (envelope-from ) id 1kpvQI-0004GQ-8n; Thu, 17 Dec 2020 15:42:34 +0000 Received: by outflank-mailman (output) from mailman id 55979.97664; Thu, 17 Dec 2020 15:42:34 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1kpvQI-0004GJ-5W; Thu, 17 Dec 2020 15:42:34 +0000 Received: by outflank-mailman (input) for mailman id 55979; Thu, 17 Dec 2020 15:42:33 +0000 Received: from us1-rack-iad1.inumbo.com ([172.99.69.81]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1kpvQG-0004G9-Tk for xen-devel@lists.xenproject.org; Thu, 17 Dec 2020 15:42:32 +0000 Received: from foss.arm.com (unknown [217.140.110.172]) by us1-rack-iad1.inumbo.com (Halon) with ESMTP id 449d379c-d30f-49e2-98e8-9d1402156f8b; Thu, 17 Dec 2020 15:42:32 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id F37AE30E; Thu, 17 Dec 2020 07:42:31 -0800 (PST) Received: from e109506-lin.cambridge.arm.com (e109506-lin.cambridge.arm.com [10.1.199.1]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 3BC833F66B; Thu, 17 Dec 2020 07:42:31 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 449d379c-d30f-49e2-98e8-9d1402156f8b From: Bertrand Marquis To: xen-devel@lists.xenproject.org Cc: Stefano Stabellini , Julien Grall , Volodymyr Babchuk Subject: [PATCH v4 1/8] xen/arm: Use READ_SYSREG instead of 32/64 versions Date: Thu, 17 Dec 2020 15:38:01 +0000 Message-Id: <75ab5c84ed6ce1d004316ca4677735aa0543ecdc.1608214355.git.bertrand.marquis@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Modify identify_cpu function to use READ_SYSREG instead of READ_SYSREG32 or READ_SYSREG64. The aarch32 versions of the registers are 64bit on an aarch64 processor so it was wrong to access them as 32bit registers. Signed-off-by: Bertrand Marquis Reviewed-by: Bertrand Marquis Reviewed-by: Stefano Stabellini --- Change in V4: This patch was introduced in v4. --- xen/arch/arm/cpufeature.c | 50 +++++++++++++++++++-------------------- 1 file changed, 25 insertions(+), 25 deletions(-) diff --git a/xen/arch/arm/cpufeature.c b/xen/arch/arm/cpufeature.c index 44126dbf07..115e1b164d 100644 --- a/xen/arch/arm/cpufeature.c +++ b/xen/arch/arm/cpufeature.c @@ -99,44 +99,44 @@ int enable_nonboot_cpu_caps(const struct arm_cpu_capabi= lities *caps) =20 void identify_cpu(struct cpuinfo_arm *c) { - c->midr.bits =3D READ_SYSREG32(MIDR_EL1); + c->midr.bits =3D READ_SYSREG(MIDR_EL1); c->mpidr.bits =3D READ_SYSREG(MPIDR_EL1); =20 #ifdef CONFIG_ARM_64 - c->pfr64.bits[0] =3D READ_SYSREG64(ID_AA64PFR0_EL1); - c->pfr64.bits[1] =3D READ_SYSREG64(ID_AA64PFR1_EL1); + c->pfr64.bits[0] =3D READ_SYSREG(ID_AA64PFR0_EL1); + c->pfr64.bits[1] =3D READ_SYSREG(ID_AA64PFR1_EL1); =20 - c->dbg64.bits[0] =3D READ_SYSREG64(ID_AA64DFR0_EL1); - c->dbg64.bits[1] =3D READ_SYSREG64(ID_AA64DFR1_EL1); + c->dbg64.bits[0] =3D READ_SYSREG(ID_AA64DFR0_EL1); + c->dbg64.bits[1] =3D READ_SYSREG(ID_AA64DFR1_EL1); =20 - c->aux64.bits[0] =3D READ_SYSREG64(ID_AA64AFR0_EL1); - c->aux64.bits[1] =3D READ_SYSREG64(ID_AA64AFR1_EL1); + c->aux64.bits[0] =3D READ_SYSREG(ID_AA64AFR0_EL1); + c->aux64.bits[1] =3D READ_SYSREG(ID_AA64AFR1_EL1); =20 - c->mm64.bits[0] =3D READ_SYSREG64(ID_AA64MMFR0_EL1); - c->mm64.bits[1] =3D READ_SYSREG64(ID_AA64MMFR1_EL1); + c->mm64.bits[0] =3D READ_SYSREG(ID_AA64MMFR0_EL1); + c->mm64.bits[1] =3D READ_SYSREG(ID_AA64MMFR1_EL1); =20 - c->isa64.bits[0] =3D READ_SYSREG64(ID_AA64ISAR0_EL1); - c->isa64.bits[1] =3D READ_SYSREG64(ID_AA64ISAR1_EL1); + c->isa64.bits[0] =3D READ_SYSREG(ID_AA64ISAR0_EL1); + c->isa64.bits[1] =3D READ_SYSREG(ID_AA64ISAR1_EL1); #endif =20 - c->pfr32.bits[0] =3D READ_SYSREG32(ID_PFR0_EL1); - c->pfr32.bits[1] =3D READ_SYSREG32(ID_PFR1_EL1); + c->pfr32.bits[0] =3D READ_SYSREG(ID_PFR0_EL1); + c->pfr32.bits[1] =3D READ_SYSREG(ID_PFR1_EL1); =20 - c->dbg32.bits[0] =3D READ_SYSREG32(ID_DFR0_EL1); + c->dbg32.bits[0] =3D READ_SYSREG(ID_DFR0_EL1); =20 - c->aux32.bits[0] =3D READ_SYSREG32(ID_AFR0_EL1); + c->aux32.bits[0] =3D READ_SYSREG(ID_AFR0_EL1); =20 - c->mm32.bits[0] =3D READ_SYSREG32(ID_MMFR0_EL1); - c->mm32.bits[1] =3D READ_SYSREG32(ID_MMFR1_EL1); - c->mm32.bits[2] =3D READ_SYSREG32(ID_MMFR2_EL1); - c->mm32.bits[3] =3D READ_SYSREG32(ID_MMFR3_EL1); + c->mm32.bits[0] =3D READ_SYSREG(ID_MMFR0_EL1); + c->mm32.bits[1] =3D READ_SYSREG(ID_MMFR1_EL1); + c->mm32.bits[2] =3D READ_SYSREG(ID_MMFR2_EL1); + c->mm32.bits[3] =3D READ_SYSREG(ID_MMFR3_EL1); =20 - c->isa32.bits[0] =3D READ_SYSREG32(ID_ISAR0_EL1); - c->isa32.bits[1] =3D READ_SYSREG32(ID_ISAR1_EL1); - c->isa32.bits[2] =3D READ_SYSREG32(ID_ISAR2_EL1); - c->isa32.bits[3] =3D READ_SYSREG32(ID_ISAR3_EL1); - c->isa32.bits[4] =3D READ_SYSREG32(ID_ISAR4_EL1); - c->isa32.bits[5] =3D READ_SYSREG32(ID_ISAR5_EL1); + c->isa32.bits[0] =3D READ_SYSREG(ID_ISAR0_EL1); + c->isa32.bits[1] =3D READ_SYSREG(ID_ISAR1_EL1); + c->isa32.bits[2] =3D READ_SYSREG(ID_ISAR2_EL1); + c->isa32.bits[3] =3D READ_SYSREG(ID_ISAR3_EL1); + c->isa32.bits[4] =3D READ_SYSREG(ID_ISAR4_EL1); + c->isa32.bits[5] =3D READ_SYSREG(ID_ISAR5_EL1); } =20 /* --=20 2.17.1 From nobody Wed May 8 20:21:36 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1608223769; cv=none; d=zohomail.com; s=zohoarc; b=eYhGAANblbNeJT3qtyC77RVIF/PckTNBYDb+F/e0d6KbsE7a4+eb6YgpGkMdyyLUWYVTkep8QX9wmwiCGQADb/jGdASC0JXgUoYxCFz/q2bhRWPHpOAAPoFjmYdPkniGrGvJt20SmENGFjFQAjUugeWzgGd6YgVVFadl/MigF/E= ARC-Message-Signature: i=1; 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Thu, 17 Dec 2020 15:42:35 +0000 Received: by outflank-mailman (output) from mailman id 55980.97676; Thu, 17 Dec 2020 15:42:35 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1kpvQJ-0004Hd-DZ; Thu, 17 Dec 2020 15:42:35 +0000 Received: by outflank-mailman (input) for mailman id 55980; Thu, 17 Dec 2020 15:42:34 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1kpvQI-0004GE-0U for xen-devel@lists.xenproject.org; Thu, 17 Dec 2020 15:42:34 +0000 Received: from foss.arm.com (unknown [217.140.110.172]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTP id 4bb17f7e-4ed5-4095-8d4e-a9faba7f8de8; Thu, 17 Dec 2020 15:42:33 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 16B8430E; Thu, 17 Dec 2020 07:42:33 -0800 (PST) Received: from e109506-lin.cambridge.arm.com (e109506-lin.cambridge.arm.com [10.1.199.1]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 377B63F66B; Thu, 17 Dec 2020 07:42:32 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 4bb17f7e-4ed5-4095-8d4e-a9faba7f8de8 From: Bertrand Marquis To: xen-devel@lists.xenproject.org Cc: Stefano Stabellini , Julien Grall , Volodymyr Babchuk Subject: [PATCH v4 2/8] xen/arm: Add ID registers and complete cpuinfo Date: Thu, 17 Dec 2020 15:38:02 +0000 Message-Id: <31d3537b11ba1a7531f1e3a38ba3b1e694a1224b.1608214355.git.bertrand.marquis@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add definition and entries in cpuinfo for ID registers introduced in newer Arm Architecture reference manual: - ID_PFR2: processor feature register 2 - ID_DFR1: debug feature register 1 - ID_MMFR4 and ID_MMFR5: Memory model feature registers 4 and 5 - ID_ISA6: ISA Feature register 6 Add more bitfield definitions in PFR fields of cpuinfo. Add MVFR2 register definition for aarch32. Add MVFRx_EL1 defines for aarch32. Add mvfr values in cpuinfo. Add some registers definition for arm64 in sysregs as some are not always know by compilers. Initialize the new values added in cpuinfo in identify_cpu during init. Signed-off-by: Bertrand Marquis Reviewed-by: Bertrand Marquis Reviewed-by: Stefano Stabellini --- Changes in V2: Fix dbg32 table size and add proper initialisation of the second entry of the table by reading ID_DFR1 register. Changes in V3: Fix typo in commit title Add MVFR2 definition and handling on aarch32 and remove specific case for mvfr field in cpuinfo (now the same on arm64 and arm32). Add MMFR4 definition if not known by the compiler. Changes in V4: Add MVFRx_EL1 defines for aarch32 Use READ_SYSREG instead of 32/64 versions of the function which removed the ifdef case for MVFR access. User register_t type for mvfr and zfr64 fields of cpuinfo structure. --- xen/arch/arm/cpufeature.c | 12 +++++++ xen/include/asm-arm/arm64/sysregs.h | 28 +++++++++++++++ xen/include/asm-arm/cpregs.h | 15 ++++++++ xen/include/asm-arm/cpufeature.h | 56 ++++++++++++++++++++++++----- 4 files changed, 102 insertions(+), 9 deletions(-) diff --git a/xen/arch/arm/cpufeature.c b/xen/arch/arm/cpufeature.c index 115e1b164d..86b99ee960 100644 --- a/xen/arch/arm/cpufeature.c +++ b/xen/arch/arm/cpufeature.c @@ -114,15 +114,20 @@ void identify_cpu(struct cpuinfo_arm *c) =20 c->mm64.bits[0] =3D READ_SYSREG(ID_AA64MMFR0_EL1); c->mm64.bits[1] =3D READ_SYSREG(ID_AA64MMFR1_EL1); + c->mm64.bits[2] =3D READ_SYSREG(ID_AA64MMFR2_EL1); =20 c->isa64.bits[0] =3D READ_SYSREG(ID_AA64ISAR0_EL1); c->isa64.bits[1] =3D READ_SYSREG(ID_AA64ISAR1_EL1); + + c->zfr64.bits[0] =3D READ_SYSREG(ID_AA64ZFR0_EL1); #endif =20 c->pfr32.bits[0] =3D READ_SYSREG(ID_PFR0_EL1); c->pfr32.bits[1] =3D READ_SYSREG(ID_PFR1_EL1); + c->pfr32.bits[2] =3D READ_SYSREG(ID_PFR2_EL1); =20 c->dbg32.bits[0] =3D READ_SYSREG(ID_DFR0_EL1); + c->dbg32.bits[1] =3D READ_SYSREG(ID_DFR1_EL1); =20 c->aux32.bits[0] =3D READ_SYSREG(ID_AFR0_EL1); =20 @@ -130,6 +135,8 @@ void identify_cpu(struct cpuinfo_arm *c) c->mm32.bits[1] =3D READ_SYSREG(ID_MMFR1_EL1); c->mm32.bits[2] =3D READ_SYSREG(ID_MMFR2_EL1); c->mm32.bits[3] =3D READ_SYSREG(ID_MMFR3_EL1); + c->mm32.bits[4] =3D READ_SYSREG(ID_MMFR4_EL1); + c->mm32.bits[5] =3D READ_SYSREG(ID_MMFR5_EL1); =20 c->isa32.bits[0] =3D READ_SYSREG(ID_ISAR0_EL1); c->isa32.bits[1] =3D READ_SYSREG(ID_ISAR1_EL1); @@ -137,6 +144,11 @@ void identify_cpu(struct cpuinfo_arm *c) c->isa32.bits[3] =3D READ_SYSREG(ID_ISAR3_EL1); c->isa32.bits[4] =3D READ_SYSREG(ID_ISAR4_EL1); c->isa32.bits[5] =3D READ_SYSREG(ID_ISAR5_EL1); + c->isa32.bits[6] =3D READ_SYSREG(ID_ISAR6_EL1); + + c->mvfr.bits[0] =3D READ_SYSREG(MVFR0_EL1); + c->mvfr.bits[1] =3D READ_SYSREG(MVFR1_EL1); + c->mvfr.bits[2] =3D READ_SYSREG(MVFR2_EL1); } =20 /* diff --git a/xen/include/asm-arm/arm64/sysregs.h b/xen/include/asm-arm/arm6= 4/sysregs.h index c60029d38f..077fd95fb7 100644 --- a/xen/include/asm-arm/arm64/sysregs.h +++ b/xen/include/asm-arm/arm64/sysregs.h @@ -57,6 +57,34 @@ #define ICH_AP1R2_EL2 __AP1Rx_EL2(2) #define ICH_AP1R3_EL2 __AP1Rx_EL2(3) =20 +/* + * Define ID coprocessor registers if they are not + * already defined by the compiler. + * + * Values picked from linux kernel + */ +#ifndef ID_AA64MMFR2_EL1 +#define ID_AA64MMFR2_EL1 S3_0_C0_C7_2 +#endif +#ifndef ID_PFR2_EL1 +#define ID_PFR2_EL1 S3_0_C0_C3_4 +#endif +#ifndef ID_MMFR4_EL1 +#define ID_MMFR4_EL1 S3_0_C0_C2_6 +#endif +#ifndef ID_MMFR5_EL1 +#define ID_MMFR5_EL1 S3_0_C0_C3_6 +#endif +#ifndef ID_ISAR6_EL1 +#define ID_ISAR6_EL1 S3_0_C0_C2_7 +#endif +#ifndef ID_AA64ZFR0_EL1 +#define ID_AA64ZFR0_EL1 S3_0_C0_C4_4 +#endif +#ifndef ID_DFR1_EL1 +#define ID_DFR1_EL1 S3_0_C0_C3_5 +#endif + /* Access to system registers */ =20 #define READ_SYSREG32(name) ((uint32_t)READ_SYSREG64(name)) diff --git a/xen/include/asm-arm/cpregs.h b/xen/include/asm-arm/cpregs.h index 8fd344146e..6daf2b1a30 100644 --- a/xen/include/asm-arm/cpregs.h +++ b/xen/include/asm-arm/cpregs.h @@ -63,6 +63,8 @@ #define FPSID p10,7,c0,c0,0 /* Floating-Point System ID Regist= er */ #define FPSCR p10,7,c1,c0,0 /* Floating-Point Status and Contr= ol Register */ #define MVFR0 p10,7,c7,c0,0 /* Media and VFP Feature Register = 0 */ +#define MVFR1 p10,7,c6,c0,0 /* Media and VFP Feature Register = 1 */ +#define MVFR2 p10,7,c5,c0,0 /* Media and VFP Feature Register = 2 */ #define FPEXC p10,7,c8,c0,0 /* Floating-Point Exception Contro= l Register */ #define FPINST p10,7,c9,c0,0 /* Floating-Point Instruction Regi= ster */ #define FPINST2 p10,7,c10,c0,0 /* Floating-point Instruction Regi= ster 2 */ @@ -108,18 +110,23 @@ #define MPIDR p15,0,c0,c0,5 /* Multiprocessor Affinity Registe= r */ #define ID_PFR0 p15,0,c0,c1,0 /* Processor Feature Register 0 */ #define ID_PFR1 p15,0,c0,c1,1 /* Processor Feature Register 1 */ +#define ID_PFR2 p15,0,c0,c3,4 /* Processor Feature Register 2 */ #define ID_DFR0 p15,0,c0,c1,2 /* Debug Feature Register 0 */ +#define ID_DFR1 p15,0,c0,c3,5 /* Debug Feature Register 1 */ #define ID_AFR0 p15,0,c0,c1,3 /* Auxiliary Feature Register 0 */ #define ID_MMFR0 p15,0,c0,c1,4 /* Memory Model Feature Register 0= */ #define ID_MMFR1 p15,0,c0,c1,5 /* Memory Model Feature Register 1= */ #define ID_MMFR2 p15,0,c0,c1,6 /* Memory Model Feature Register 2= */ #define ID_MMFR3 p15,0,c0,c1,7 /* Memory Model Feature Register 3= */ +#define ID_MMFR4 p15,0,c0,c2,6 /* Memory Model Feature Register 4= */ +#define ID_MMFR5 p15,0,c0,c3,6 /* Memory Model Feature Register 5= */ #define ID_ISAR0 p15,0,c0,c2,0 /* ISA Feature Register 0 */ #define ID_ISAR1 p15,0,c0,c2,1 /* ISA Feature Register 1 */ #define ID_ISAR2 p15,0,c0,c2,2 /* ISA Feature Register 2 */ #define ID_ISAR3 p15,0,c0,c2,3 /* ISA Feature Register 3 */ #define ID_ISAR4 p15,0,c0,c2,4 /* ISA Feature Register 4 */ #define ID_ISAR5 p15,0,c0,c2,5 /* ISA Feature Register 5 */ +#define ID_ISAR6 p15,0,c0,c2,7 /* ISA Feature Register 6 */ #define CCSIDR p15,1,c0,c0,0 /* Cache Size ID Registers */ #define CLIDR p15,1,c0,c0,1 /* Cache Level ID Register */ #define CSSELR p15,2,c0,c0,0 /* Cache Size Selection Register */ @@ -312,18 +319,23 @@ #define HSTR_EL2 HSTR #define ID_AFR0_EL1 ID_AFR0 #define ID_DFR0_EL1 ID_DFR0 +#define ID_DFR1_EL1 ID_DFR1 #define ID_ISAR0_EL1 ID_ISAR0 #define ID_ISAR1_EL1 ID_ISAR1 #define ID_ISAR2_EL1 ID_ISAR2 #define ID_ISAR3_EL1 ID_ISAR3 #define ID_ISAR4_EL1 ID_ISAR4 #define ID_ISAR5_EL1 ID_ISAR5 +#define ID_ISAR6_EL1 ID_ISAR6 #define ID_MMFR0_EL1 ID_MMFR0 #define ID_MMFR1_EL1 ID_MMFR1 #define ID_MMFR2_EL1 ID_MMFR2 #define ID_MMFR3_EL1 ID_MMFR3 +#define ID_MMFR4_EL1 ID_MMFR4 +#define ID_MMFR5_EL1 ID_MMFR5 #define ID_PFR0_EL1 ID_PFR0 #define ID_PFR1_EL1 ID_PFR1 +#define ID_PFR2_EL1 ID_PFR2 #define IFSR32_EL2 IFSR #define MDCR_EL2 HDCR #define MIDR_EL1 MIDR @@ -347,6 +359,9 @@ #define VPIDR_EL2 VPIDR #define VTCR_EL2 VTCR #define VTTBR_EL2 VTTBR +#define MVFR0_EL1 MVFR0 +#define MVFR1_EL1 MVFR1 +#define MVFR2_EL1 MVFR2 #endif =20 #endif diff --git a/xen/include/asm-arm/cpufeature.h b/xen/include/asm-arm/cpufeat= ure.h index c7b5052992..74139be1cc 100644 --- a/xen/include/asm-arm/cpufeature.h +++ b/xen/include/asm-arm/cpufeature.h @@ -148,6 +148,7 @@ struct cpuinfo_arm { union { uint64_t bits[2]; struct { + /* PFR0 */ unsigned long el0:4; unsigned long el1:4; unsigned long el2:4; @@ -155,9 +156,23 @@ struct cpuinfo_arm { unsigned long fp:4; /* Floating Point */ unsigned long simd:4; /* Advanced SIMD */ unsigned long gic:4; /* GIC support */ - unsigned long __res0:28; + unsigned long ras:4; + unsigned long sve:4; + unsigned long sel2:4; + unsigned long mpam:4; + unsigned long amu:4; + unsigned long dit:4; + unsigned long __res0:4; unsigned long csv2:4; - unsigned long __res1:4; + unsigned long cvs3:4; + + /* PFR1 */ + unsigned long bt:4; + unsigned long ssbs:4; + unsigned long mte:4; + unsigned long ras_frac:4; + unsigned long mpam_frac:4; + unsigned long __res1:44; }; } pfr64; =20 @@ -170,7 +185,7 @@ struct cpuinfo_arm { } aux64; =20 union { - uint64_t bits[2]; + uint64_t bits[3]; struct { unsigned long pa_range:4; unsigned long asid_bits:4; @@ -190,6 +205,8 @@ struct cpuinfo_arm { unsigned long pan:4; unsigned long __res1:8; unsigned long __res2:32; + + unsigned long __res3:64; }; } mm64; =20 @@ -197,6 +214,10 @@ struct cpuinfo_arm { uint64_t bits[2]; } isa64; =20 + struct { + register_t bits[1]; + } zfr64; + #endif =20 /* @@ -204,25 +225,38 @@ struct cpuinfo_arm { * when running in 32-bit mode. */ union { - uint32_t bits[2]; + uint32_t bits[3]; struct { + /* PFR0 */ unsigned long arm:4; unsigned long thumb:4; unsigned long jazelle:4; unsigned long thumbee:4; - unsigned long __res0:16; + unsigned long csv2:4; + unsigned long amu:4; + unsigned long dit:4; + unsigned long ras:4; =20 + /* PFR1 */ unsigned long progmodel:4; unsigned long security:4; unsigned long mprofile:4; unsigned long virt:4; unsigned long gentimer:4; - unsigned long __res1:12; + unsigned long sec_frac:4; + unsigned long virt_frac:4; + unsigned long gic:4; + + /* PFR2 */ + unsigned long csv3:4; + unsigned long ssbs:4; + unsigned long ras_frac:4; + unsigned long __res2:20; }; } pfr32; =20 struct { - uint32_t bits[1]; + uint32_t bits[2]; } dbg32; =20 struct { @@ -230,12 +264,16 @@ struct cpuinfo_arm { } aux32; =20 struct { - uint32_t bits[4]; + uint32_t bits[6]; } mm32; =20 struct { - uint32_t bits[6]; + uint32_t bits[7]; } isa32; + + struct { + register_t bits[3]; + } mvfr; }; =20 extern struct cpuinfo_arm boot_cpu_data; --=20 2.17.1 From nobody Wed May 8 20:21:36 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; 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xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 03bed0a0-1b34-4d46-a2ea-fdd55279b29f From: Bertrand Marquis To: xen-devel@lists.xenproject.org Cc: Stefano Stabellini , Julien Grall , Volodymyr Babchuk Subject: [PATCH v4 3/8] xen/arm: Add arm64 ID registers definitions Date: Thu, 17 Dec 2020 15:38:03 +0000 Message-Id: <905822b31f5494bf20e1e2a0a56f935db0550aef.1608214355.git.bertrand.marquis@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add coprocessor registers definitions for all ID registers trapped through the TID3 bit of HSR. Those are the one that will be emulated in Xen to only publish to guests the features that are supported by Xen and that are accessible to guests. Signed-off-by: Bertrand Marquis Reviewed-by: Bertrand Marquis Reviewed-by: Stefano Stabellini --- Changes in V2: Rebase Changes in V3: Add case definition for reserved registers. Changes in V4: Remove case definition for reserved registers and move it to the code directly. --- xen/include/asm-arm/arm64/hsr.h | 37 +++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/xen/include/asm-arm/arm64/hsr.h b/xen/include/asm-arm/arm64/hs= r.h index ca931dd2fe..e691d41c17 100644 --- a/xen/include/asm-arm/arm64/hsr.h +++ b/xen/include/asm-arm/arm64/hsr.h @@ -110,6 +110,43 @@ #define HSR_SYSREG_CNTP_CTL_EL0 HSR_SYSREG(3,3,c14,c2,1) #define HSR_SYSREG_CNTP_CVAL_EL0 HSR_SYSREG(3,3,c14,c2,2) =20 +/* Those registers are used when HCR_EL2.TID3 is set */ +#define HSR_SYSREG_ID_PFR0_EL1 HSR_SYSREG(3,0,c0,c1,0) +#define HSR_SYSREG_ID_PFR1_EL1 HSR_SYSREG(3,0,c0,c1,1) +#define HSR_SYSREG_ID_PFR2_EL1 HSR_SYSREG(3,0,c0,c3,4) +#define HSR_SYSREG_ID_DFR0_EL1 HSR_SYSREG(3,0,c0,c1,2) +#define HSR_SYSREG_ID_DFR1_EL1 HSR_SYSREG(3,0,c0,c3,5) +#define HSR_SYSREG_ID_AFR0_EL1 HSR_SYSREG(3,0,c0,c1,3) +#define HSR_SYSREG_ID_MMFR0_EL1 HSR_SYSREG(3,0,c0,c1,4) +#define HSR_SYSREG_ID_MMFR1_EL1 HSR_SYSREG(3,0,c0,c1,5) +#define HSR_SYSREG_ID_MMFR2_EL1 HSR_SYSREG(3,0,c0,c1,6) +#define HSR_SYSREG_ID_MMFR3_EL1 HSR_SYSREG(3,0,c0,c1,7) +#define HSR_SYSREG_ID_MMFR4_EL1 HSR_SYSREG(3,0,c0,c2,6) +#define HSR_SYSREG_ID_MMFR5_EL1 HSR_SYSREG(3,0,c0,c3,6) +#define HSR_SYSREG_ID_ISAR0_EL1 HSR_SYSREG(3,0,c0,c2,0) +#define HSR_SYSREG_ID_ISAR1_EL1 HSR_SYSREG(3,0,c0,c2,1) +#define HSR_SYSREG_ID_ISAR2_EL1 HSR_SYSREG(3,0,c0,c2,2) +#define HSR_SYSREG_ID_ISAR3_EL1 HSR_SYSREG(3,0,c0,c2,3) +#define HSR_SYSREG_ID_ISAR4_EL1 HSR_SYSREG(3,0,c0,c2,4) +#define HSR_SYSREG_ID_ISAR5_EL1 HSR_SYSREG(3,0,c0,c2,5) +#define HSR_SYSREG_ID_ISAR6_EL1 HSR_SYSREG(3,0,c0,c2,7) +#define HSR_SYSREG_MVFR0_EL1 HSR_SYSREG(3,0,c0,c3,0) +#define HSR_SYSREG_MVFR1_EL1 HSR_SYSREG(3,0,c0,c3,1) +#define HSR_SYSREG_MVFR2_EL1 HSR_SYSREG(3,0,c0,c3,2) + +#define HSR_SYSREG_ID_AA64PFR0_EL1 HSR_SYSREG(3,0,c0,c4,0) +#define HSR_SYSREG_ID_AA64PFR1_EL1 HSR_SYSREG(3,0,c0,c4,1) +#define HSR_SYSREG_ID_AA64DFR0_EL1 HSR_SYSREG(3,0,c0,c5,0) +#define HSR_SYSREG_ID_AA64DFR1_EL1 HSR_SYSREG(3,0,c0,c5,1) +#define HSR_SYSREG_ID_AA64ISAR0_EL1 HSR_SYSREG(3,0,c0,c6,0) +#define HSR_SYSREG_ID_AA64ISAR1_EL1 HSR_SYSREG(3,0,c0,c6,1) +#define HSR_SYSREG_ID_AA64MMFR0_EL1 HSR_SYSREG(3,0,c0,c7,0) +#define HSR_SYSREG_ID_AA64MMFR1_EL1 HSR_SYSREG(3,0,c0,c7,1) +#define HSR_SYSREG_ID_AA64MMFR2_EL1 HSR_SYSREG(3,0,c0,c7,2) +#define HSR_SYSREG_ID_AA64AFR0_EL1 HSR_SYSREG(3,0,c0,c5,4) +#define HSR_SYSREG_ID_AA64AFR1_EL1 HSR_SYSREG(3,0,c0,c5,5) +#define HSR_SYSREG_ID_AA64ZFR0_EL1 HSR_SYSREG(3,0,c0,c4,4) + #endif /* __ASM_ARM_ARM64_HSR_H */ =20 /* --=20 2.17.1 From nobody Wed May 8 20:21:36 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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Thu, 17 Dec 2020 15:42:37 +0000 Received: from foss.arm.com (unknown [217.140.110.172]) by us1-rack-iad1.inumbo.com (Halon) with ESMTP id d4cbdaf9-5fdb-4233-8850-c7547c976cfc; Thu, 17 Dec 2020 15:42:35 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0D45330E; Thu, 17 Dec 2020 07:42:35 -0800 (PST) Received: from e109506-lin.cambridge.arm.com (e109506-lin.cambridge.arm.com [10.1.199.1]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 4BD273F66B; Thu, 17 Dec 2020 07:42:34 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: d4cbdaf9-5fdb-4233-8850-c7547c976cfc From: Bertrand Marquis To: xen-devel@lists.xenproject.org Cc: Stefano Stabellini , Julien Grall , Volodymyr Babchuk Subject: [PATCH v4 4/8] xen/arm: create a cpuinfo structure for guest Date: Thu, 17 Dec 2020 15:38:04 +0000 Message-Id: <8a93d20d20fae570c83c4d7bea0c882735496f34.1608214355.git.bertrand.marquis@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Create a cpuinfo structure for guest and mask into it the features that we do not support in Xen or that we do not want to publish to guests. Modify some values in the cpuinfo structure for guests to mask some features which we do not want to allow to guests (like AMU) or we do not support (like SVE). Modify some values in the guest cpuinfo structure to guests to hide some processor features: - SVE as this is not supported by Xen and guest are not allowed to use this features (ZEN is set to 0 in CPTR_EL2). - AMU as HCPTR_TAM is set in CPTR_EL2 so AMU cannot be used by guests All other bits are left untouched. - RAS as this is not supported by Xen. The code is trying to group together registers modifications for the same feature to be able in the long term to easily enable/disable a feature depending on user parameters or add other registers modification in the same place (like enabling/disabling HCR bits). Signed-off-by: Bertrand Marquis Reviewed-by: Bertrand Marquis Reviewed-by: Stefano Stabellini --- Changes in V2: Rebase Changes in V3: Use current_cpu_data info instead of recalling identify_cpu Changes in V4: Use boot_cpu_data instead of current_cpu_data Use "hide XX support" instead of disable as this part of the code is actually only hidding feature to guests but not disabling them (this is done through the HCR register). Modify commit message to be more clear about what is done in guest_cpuinfo. --- xen/arch/arm/cpufeature.c | 51 ++++++++++++++++++++++++++++++++ xen/include/asm-arm/cpufeature.h | 2 ++ 2 files changed, 53 insertions(+) diff --git a/xen/arch/arm/cpufeature.c b/xen/arch/arm/cpufeature.c index 86b99ee960..1f6a85aafe 100644 --- a/xen/arch/arm/cpufeature.c +++ b/xen/arch/arm/cpufeature.c @@ -24,6 +24,8 @@ =20 DECLARE_BITMAP(cpu_hwcaps, ARM_NCAPS); =20 +struct cpuinfo_arm __read_mostly guest_cpuinfo; + void update_cpu_capabilities(const struct arm_cpu_capabilities *caps, const char *info) { @@ -151,6 +153,55 @@ void identify_cpu(struct cpuinfo_arm *c) c->mvfr.bits[2] =3D READ_SYSREG(MVFR2_EL1); } =20 +/* + * This function is creating a cpuinfo structure with values modified to m= ask + * all cpu features that should not be published to guest. + * The created structure is then used to provide ID registers values to gu= ests. + */ +static int __init create_guest_cpuinfo(void) +{ + /* + * TODO: The code is currently using only the features detected on the= boot + * core. In the long term we should try to compute values containing o= nly + * features supported by all cores. + */ + guest_cpuinfo =3D boot_cpu_data; + +#ifdef CONFIG_ARM_64 + /* Hide MPAM support as xen does not support it */ + guest_cpuinfo.pfr64.mpam =3D 0; + guest_cpuinfo.pfr64.mpam_frac =3D 0; + + /* Hide SVE as Xen does not support it */ + guest_cpuinfo.pfr64.sve =3D 0; + guest_cpuinfo.zfr64.bits[0] =3D 0; + + /* Hide MTE support as Xen does not support it */ + guest_cpuinfo.pfr64.mte =3D 0; +#endif + + /* Hide AMU support */ +#ifdef CONFIG_ARM_64 + guest_cpuinfo.pfr64.amu =3D 0; +#endif + guest_cpuinfo.pfr32.amu =3D 0; + + /* Hide RAS support as Xen does not support it */ +#ifdef CONFIG_ARM_64 + guest_cpuinfo.pfr64.ras =3D 0; + guest_cpuinfo.pfr64.ras_frac =3D 0; +#endif + guest_cpuinfo.pfr32.ras =3D 0; + guest_cpuinfo.pfr32.ras_frac =3D 0; + + return 0; +} +/* + * This function needs to be run after all smp are started to have + * cpuinfo structures for all cores. + */ +__initcall(create_guest_cpuinfo); + /* * Local variables: * mode: C diff --git a/xen/include/asm-arm/cpufeature.h b/xen/include/asm-arm/cpufeat= ure.h index 74139be1cc..6058744c18 100644 --- a/xen/include/asm-arm/cpufeature.h +++ b/xen/include/asm-arm/cpufeature.h @@ -283,6 +283,8 @@ extern void identify_cpu(struct cpuinfo_arm *); extern struct cpuinfo_arm cpu_data[]; #define current_cpu_data cpu_data[smp_processor_id()] =20 +extern struct cpuinfo_arm guest_cpuinfo; + #endif /* __ASSEMBLY__ */ =20 #endif --=20 2.17.1 From nobody Wed May 8 20:21:36 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=1; 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Thu, 17 Dec 2020 07:42:36 -0800 (PST) Received: from e109506-lin.cambridge.arm.com (e109506-lin.cambridge.arm.com [10.1.199.1]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 46A263F66B; Thu, 17 Dec 2020 07:42:35 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: e99d0a0f-ebf0-460c-b3a9-5ba4df1b471f From: Bertrand Marquis To: xen-devel@lists.xenproject.org Cc: Stefano Stabellini , Julien Grall , Volodymyr Babchuk Subject: [PATCH v4 5/8] xen/arm: Add handler for ID registers on arm64 Date: Thu, 17 Dec 2020 15:38:05 +0000 Message-Id: <46c4c7e8ec64a48ecefd894d436c116bab5d4a86.1608214355.git.bertrand.marquis@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add vsysreg emulation for registers trapped when TID3 bit is activated in HSR. The emulation is returning the value stored in cpuinfo_guest structure for know registers and is handling reserved registers as RAZ. Signed-off-by: Bertrand Marquis Reviewed-by: Bertrand Marquis Reviewed-by: Stefano Stabellini --- Changes in V2: Rebase Changes in V3: Fix commit message Fix code style for GENERATE_TID3_INFO declaration Add handling of reserved registers as RAZ. Changes in V4: Fix indentation in GENERATE_TID3_INFO macro Add explicit case code for reserved registers --- xen/arch/arm/arm64/vsysreg.c | 82 ++++++++++++++++++++++++++++++++++++ 1 file changed, 82 insertions(+) diff --git a/xen/arch/arm/arm64/vsysreg.c b/xen/arch/arm/arm64/vsysreg.c index 8a85507d9d..41f18612c6 100644 --- a/xen/arch/arm/arm64/vsysreg.c +++ b/xen/arch/arm/arm64/vsysreg.c @@ -69,6 +69,14 @@ TVM_REG(CONTEXTIDR_EL1) break; \ } =20 +/* Macro to generate easily case for ID co-processor emulation */ +#define GENERATE_TID3_INFO(reg, field, offset) \ + case HSR_SYSREG_##reg: \ + { \ + return handle_ro_read_val(regs, regidx, hsr.sysreg.read, hsr, \ + 1, guest_cpuinfo.field.bits[offset]); \ + } + void do_sysreg(struct cpu_user_regs *regs, const union hsr hsr) { @@ -259,6 +267,80 @@ void do_sysreg(struct cpu_user_regs *regs, */ return handle_raz_wi(regs, regidx, hsr.sysreg.read, hsr, 1); =20 + /* + * HCR_EL2.TID3 + * + * This is trapping most Identification registers used by a guest + * to identify the processor features + */ + GENERATE_TID3_INFO(ID_PFR0_EL1, pfr32, 0) + GENERATE_TID3_INFO(ID_PFR1_EL1, pfr32, 1) + GENERATE_TID3_INFO(ID_PFR2_EL1, pfr32, 2) + GENERATE_TID3_INFO(ID_DFR0_EL1, dbg32, 0) + GENERATE_TID3_INFO(ID_DFR1_EL1, dbg32, 1) + GENERATE_TID3_INFO(ID_AFR0_EL1, aux32, 0) + GENERATE_TID3_INFO(ID_MMFR0_EL1, mm32, 0) + GENERATE_TID3_INFO(ID_MMFR1_EL1, mm32, 1) + GENERATE_TID3_INFO(ID_MMFR2_EL1, mm32, 2) + GENERATE_TID3_INFO(ID_MMFR3_EL1, mm32, 3) + GENERATE_TID3_INFO(ID_MMFR4_EL1, mm32, 4) + GENERATE_TID3_INFO(ID_MMFR5_EL1, mm32, 5) + GENERATE_TID3_INFO(ID_ISAR0_EL1, isa32, 0) + GENERATE_TID3_INFO(ID_ISAR1_EL1, isa32, 1) + GENERATE_TID3_INFO(ID_ISAR2_EL1, isa32, 2) + GENERATE_TID3_INFO(ID_ISAR3_EL1, isa32, 3) + GENERATE_TID3_INFO(ID_ISAR4_EL1, isa32, 4) + GENERATE_TID3_INFO(ID_ISAR5_EL1, isa32, 5) + GENERATE_TID3_INFO(ID_ISAR6_EL1, isa32, 6) + GENERATE_TID3_INFO(MVFR0_EL1, mvfr, 0) + GENERATE_TID3_INFO(MVFR1_EL1, mvfr, 1) + GENERATE_TID3_INFO(MVFR2_EL1, mvfr, 2) + GENERATE_TID3_INFO(ID_AA64PFR0_EL1, pfr64, 0) + GENERATE_TID3_INFO(ID_AA64PFR1_EL1, pfr64, 1) + GENERATE_TID3_INFO(ID_AA64DFR0_EL1, dbg64, 0) + GENERATE_TID3_INFO(ID_AA64DFR1_EL1, dbg64, 1) + GENERATE_TID3_INFO(ID_AA64ISAR0_EL1, isa64, 0) + GENERATE_TID3_INFO(ID_AA64ISAR1_EL1, isa64, 1) + GENERATE_TID3_INFO(ID_AA64MMFR0_EL1, mm64, 0) + GENERATE_TID3_INFO(ID_AA64MMFR1_EL1, mm64, 1) + GENERATE_TID3_INFO(ID_AA64MMFR2_EL1, mm64, 2) + GENERATE_TID3_INFO(ID_AA64AFR0_EL1, aux64, 0) + GENERATE_TID3_INFO(ID_AA64AFR1_EL1, aux64, 1) + GENERATE_TID3_INFO(ID_AA64ZFR0_EL1, zfr64, 0) + + /* + * Those cases are catching all Reserved registers trapped by TID3 whi= ch + * currently have no assignment. + * HCR.TID3 is trapping all registers in the group 3: + * Op0 =3D=3D 3, op1 =3D=3D 0, CRn =3D=3D c0,CRm =3D=3D {c1-c7}, op2 = =3D=3D {0-7}. + * Those registers are defined as being RO in the Arm Architecture + * Reference manual Armv8 (Chapter D12.3.2 of issue F.c) so handle them + * as Read-only read as zero. + */ + case HSR_SYSREG(3,0,c0,c3,3): + case HSR_SYSREG(3,0,c0,c3,7): + case HSR_SYSREG(3,0,c0,c4,2): + case HSR_SYSREG(3,0,c0,c4,3): + case HSR_SYSREG(3,0,c0,c4,5): + case HSR_SYSREG(3,0,c0,c4,6): + case HSR_SYSREG(3,0,c0,c4,7): + case HSR_SYSREG(3,0,c0,c5,2): + case HSR_SYSREG(3,0,c0,c5,3): + case HSR_SYSREG(3,0,c0,c5,6): + case HSR_SYSREG(3,0,c0,c5,7): + case HSR_SYSREG(3,0,c0,c6,2): + case HSR_SYSREG(3,0,c0,c6,3): + case HSR_SYSREG(3,0,c0,c6,4): + case HSR_SYSREG(3,0,c0,c6,5): + case HSR_SYSREG(3,0,c0,c6,6): + case HSR_SYSREG(3,0,c0,c6,7): + case HSR_SYSREG(3,0,c0,c7,3): + case HSR_SYSREG(3,0,c0,c7,4): + case HSR_SYSREG(3,0,c0,c7,5): + case HSR_SYSREG(3,0,c0,c7,6): + case HSR_SYSREG(3,0,c0,c7,7): + return handle_ro_raz(regs, regidx, hsr.sysreg.read, hsr, 1); + /* * HCR_EL2.TIDCP * --=20 2.17.1 From nobody Wed May 8 20:21:36 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1608219779; cv=none; d=zohomail.com; s=zohoarc; b=jkA5zgvjgOvV/uw0b/FkeLRBp4nlo8u5f3QexcYnM+TE/TY5juOPZ1c2cEa4K+5Hqw7QdCOKsL/lIw6LMkdGqCpwyjuOeWbAKqyCq1bb93NmYfRRQy3QboUr60qOFPqmR6EPxIp++8KwWniX4RJ8Ke/9ql1nPexQyOGqD2zfNVQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1608219779; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; 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charset="utf-8" Add support for emulation of cp15 based ID registers (on arm32 or when running a 32bit guest on arm64). The handlers are returning the values stored in the guest_cpuinfo structure for known registers and RAZ for all reserved registers. In the current status the MVFR registers are no supported. Signed-off-by: Bertrand Marquis Reviewed-by: Bertrand Marquis Reviewed-by: Stefano Stabellini --- Changes in V2: Rebase Changes in V3: Add case definition for reserved registers Add handling of reserved registers as RAZ. Fix code style in GENERATE_TID3_INFO declaration Changes in V4: Fix comment for missing t (no to not) Put cases for reserved registers directly in the code instead of using a define in the cpregs.h header. --- xen/arch/arm/vcpreg.c | 65 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 65 insertions(+) diff --git a/xen/arch/arm/vcpreg.c b/xen/arch/arm/vcpreg.c index cdc91cdf5b..1fe07fe02a 100644 --- a/xen/arch/arm/vcpreg.c +++ b/xen/arch/arm/vcpreg.c @@ -155,6 +155,24 @@ TVM_REG32(CONTEXTIDR, CONTEXTIDR_EL1) break; \ } =20 +/* Macro to generate easily case for ID co-processor emulation */ +#define GENERATE_TID3_INFO(reg, field, offset) \ + case HSR_CPREG32(reg): \ + { \ + return handle_ro_read_val(regs, regidx, cp32.read, hsr, \ + 1, guest_cpuinfo.field.bits[offset]); \ + } + +/* helper to define cases for all registers for one CRm value */ +#define HSR_CPREG32_TID3_CASES(REG) case HSR_CPREG32(p15,0,c0,REG,0): \ + case HSR_CPREG32(p15,0,c0,REG,1): \ + case HSR_CPREG32(p15,0,c0,REG,2): \ + case HSR_CPREG32(p15,0,c0,REG,3): \ + case HSR_CPREG32(p15,0,c0,REG,4): \ + case HSR_CPREG32(p15,0,c0,REG,5): \ + case HSR_CPREG32(p15,0,c0,REG,6): \ + case HSR_CPREG32(p15,0,c0,REG,7) + void do_cp15_32(struct cpu_user_regs *regs, const union hsr hsr) { const struct hsr_cp32 cp32 =3D hsr.cp32; @@ -286,6 +304,53 @@ void do_cp15_32(struct cpu_user_regs *regs, const unio= n hsr hsr) */ return handle_raz_wi(regs, regidx, cp32.read, hsr, 1); =20 + /* + * HCR_EL2.TID3 + * + * This is trapping most Identification registers used by a guest + * to identify the processor features + */ + GENERATE_TID3_INFO(ID_PFR0, pfr32, 0) + GENERATE_TID3_INFO(ID_PFR1, pfr32, 1) + GENERATE_TID3_INFO(ID_PFR2, pfr32, 2) + GENERATE_TID3_INFO(ID_DFR0, dbg32, 0) + GENERATE_TID3_INFO(ID_DFR1, dbg32, 1) + GENERATE_TID3_INFO(ID_AFR0, aux32, 0) + GENERATE_TID3_INFO(ID_MMFR0, mm32, 0) + GENERATE_TID3_INFO(ID_MMFR1, mm32, 1) + GENERATE_TID3_INFO(ID_MMFR2, mm32, 2) + GENERATE_TID3_INFO(ID_MMFR3, mm32, 3) + GENERATE_TID3_INFO(ID_MMFR4, mm32, 4) + GENERATE_TID3_INFO(ID_MMFR5, mm32, 5) + GENERATE_TID3_INFO(ID_ISAR0, isa32, 0) + GENERATE_TID3_INFO(ID_ISAR1, isa32, 1) + GENERATE_TID3_INFO(ID_ISAR2, isa32, 2) + GENERATE_TID3_INFO(ID_ISAR3, isa32, 3) + GENERATE_TID3_INFO(ID_ISAR4, isa32, 4) + GENERATE_TID3_INFO(ID_ISAR5, isa32, 5) + GENERATE_TID3_INFO(ID_ISAR6, isa32, 6) + /* MVFR registers are in cp10 not cp15 */ + + /* + * Those cases are catching all Reserved registers trapped by TID3 whi= ch + * currently have no assignment. + * HCR.TID3 is trapping all registers in the group 3: + * coproc =3D=3D p15, opc1 =3D=3D 0, CRn =3D=3D c0, CRm =3D=3D {c2-c7}= , opc2 =3D=3D {0-7}. + * Those registers are defined as being RO in the Arm Architecture + * Reference manual Armv8 (Chapter D12.3.2 of issue F.c) so handle them + * as Read-only read as zero. + */ + case HSR_CPREG32(p15,0,c0,c3,0): + case HSR_CPREG32(p15,0,c0,c3,1): + case HSR_CPREG32(p15,0,c0,c3,2): + case HSR_CPREG32(p15,0,c0,c3,3): + case HSR_CPREG32(p15,0,c0,c3,7): + HSR_CPREG32_TID3_CASES(c4): + HSR_CPREG32_TID3_CASES(c5): + HSR_CPREG32_TID3_CASES(c6): + HSR_CPREG32_TID3_CASES(c7): + return handle_ro_raz(regs, regidx, cp32.read, hsr, 1); + /* * HCR_EL2.TIDCP * --=20 2.17.1 From nobody Wed May 8 20:21:36 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1608219788; cv=none; d=zohomail.com; s=zohoarc; b=NBzinupNL8055lNiPkImUAY/xaG925gC994MPRmVxR2F9gvIbPzCxh7iuBP4padHPG2zPqC1wyjK7NU1d4HtWWlxrX9610VFZXY76lBmtEtQ05wY9QtUaSOwd2s7EP7XHtmMyn49QDSq206By8xDOsztofHK/7x2GDKgGyuT+M4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1608219788; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; 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Thu, 17 Dec 2020 15:42:51 +0000 Received: by outflank-mailman (input) for mailman id 55987; Thu, 17 Dec 2020 15:42:49 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1kpvQW-0004GE-W1 for xen-devel@lists.xenproject.org; Thu, 17 Dec 2020 15:42:49 +0000 Received: from foss.arm.com (unknown [217.140.110.172]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTP id 3eabbf11-50b1-4745-a474-c7cc8f6ea9d8; Thu, 17 Dec 2020 15:42:38 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id F2C1F101E; Thu, 17 Dec 2020 07:42:37 -0800 (PST) Received: from e109506-lin.cambridge.arm.com (e109506-lin.cambridge.arm.com [10.1.199.1]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 3CE683F66B; Thu, 17 Dec 2020 07:42:37 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 3eabbf11-50b1-4745-a474-c7cc8f6ea9d8 From: Bertrand Marquis To: xen-devel@lists.xenproject.org Cc: Stefano Stabellini , Julien Grall , Volodymyr Babchuk Subject: [PATCH v4 7/8] xen/arm: Add CP10 exception support to handle MVFR Date: Thu, 17 Dec 2020 15:38:07 +0000 Message-Id: <841e5cd22290158d9b0c5d6dedafd01ed9a3d0bc.1608214355.git.bertrand.marquis@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add support for cp10 exceptions decoding to be able to emulate the values for MVFR0, MVFR1 and MVFR2 when TID3 bit of HSR is activated. This is required for aarch32 guests accessing MVFR registers using vmrs and vmsr instructions. Signed-off-by: Bertrand Marquis Reviewed-by: Bertrand Marquis Reviewed-by: Stefano Stabellini --- Changes in V2: Rebase Changes in V3: Add case for MVFR2, fix typo VMFR <-> MVFR. Changes in V4: Fix typo HSR -> HCR Move no to not comment fix to previous patch --- xen/arch/arm/traps.c | 5 +++++ xen/arch/arm/vcpreg.c | 37 ++++++++++++++++++++++++++++++++ xen/include/asm-arm/perfc_defn.h | 1 + xen/include/asm-arm/traps.h | 1 + 4 files changed, 44 insertions(+) diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index 22bd1bd4c6..28d9d64558 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -2097,6 +2097,11 @@ void do_trap_guest_sync(struct cpu_user_regs *regs) perfc_incr(trap_cp14_dbg); do_cp14_dbg(regs, hsr); break; + case HSR_EC_CP10: + GUEST_BUG_ON(!psr_mode_is_32bit(regs)); + perfc_incr(trap_cp10); + do_cp10(regs, hsr); + break; case HSR_EC_CP: GUEST_BUG_ON(!psr_mode_is_32bit(regs)); perfc_incr(trap_cp); diff --git a/xen/arch/arm/vcpreg.c b/xen/arch/arm/vcpreg.c index 1fe07fe02a..cbad8f25a0 100644 --- a/xen/arch/arm/vcpreg.c +++ b/xen/arch/arm/vcpreg.c @@ -664,6 +664,43 @@ void do_cp14_dbg(struct cpu_user_regs *regs, const uni= on hsr hsr) inject_undef_exception(regs, hsr); } =20 +void do_cp10(struct cpu_user_regs *regs, const union hsr hsr) +{ + const struct hsr_cp32 cp32 =3D hsr.cp32; + int regidx =3D cp32.reg; + + if ( !check_conditional_instr(regs, hsr) ) + { + advance_pc(regs, hsr); + return; + } + + switch ( hsr.bits & HSR_CP32_REGS_MASK ) + { + /* + * HCR.TID3 is trapping access to MVFR register used to identify the + * VFP/Simd using VMRS/VMSR instructions. + * Exception encoding is using MRC/MCR standard with the reg field in = Crn + * as are declared MVFR0 and MVFR1 in cpregs.h + */ + GENERATE_TID3_INFO(MVFR0, mvfr, 0) + GENERATE_TID3_INFO(MVFR1, mvfr, 1) + GENERATE_TID3_INFO(MVFR2, mvfr, 2) + + default: + gdprintk(XENLOG_ERR, + "%s p10, %d, r%d, cr%d, cr%d, %d @ 0x%"PRIregister"\n", + cp32.read ? "mrc" : "mcr", + cp32.op1, cp32.reg, cp32.crn, cp32.crm, cp32.op2, regs->p= c); + gdprintk(XENLOG_ERR, "unhandled 32-bit CP10 access %#x\n", + hsr.bits & HSR_CP32_REGS_MASK); + inject_undef_exception(regs, hsr); + return; + } + + advance_pc(regs, hsr); +} + void do_cp(struct cpu_user_regs *regs, const union hsr hsr) { const struct hsr_cp cp =3D hsr.cp; diff --git a/xen/include/asm-arm/perfc_defn.h b/xen/include/asm-arm/perfc_d= efn.h index 6a83185163..31f071222b 100644 --- a/xen/include/asm-arm/perfc_defn.h +++ b/xen/include/asm-arm/perfc_defn.h @@ -11,6 +11,7 @@ PERFCOUNTER(trap_cp15_64, "trap: cp15 64-bit access") PERFCOUNTER(trap_cp14_32, "trap: cp14 32-bit access") PERFCOUNTER(trap_cp14_64, "trap: cp14 64-bit access") PERFCOUNTER(trap_cp14_dbg, "trap: cp14 dbg access") +PERFCOUNTER(trap_cp10, "trap: cp10 access") PERFCOUNTER(trap_cp, "trap: cp access") PERFCOUNTER(trap_smc32, "trap: 32-bit smc") PERFCOUNTER(trap_hvc32, "trap: 32-bit hvc") diff --git a/xen/include/asm-arm/traps.h b/xen/include/asm-arm/traps.h index 997c37884e..c4a3d0fb1b 100644 --- a/xen/include/asm-arm/traps.h +++ b/xen/include/asm-arm/traps.h @@ -62,6 +62,7 @@ void do_cp15_64(struct cpu_user_regs *regs, const union h= sr hsr); void do_cp14_32(struct cpu_user_regs *regs, const union hsr hsr); void do_cp14_64(struct cpu_user_regs *regs, const union hsr hsr); void do_cp14_dbg(struct cpu_user_regs *regs, const union hsr hsr); +void do_cp10(struct cpu_user_regs *regs, const union hsr hsr); void do_cp(struct cpu_user_regs *regs, const union hsr hsr); =20 /* SMCCC handling */ --=20 2.17.1 From nobody Wed May 8 20:21:36 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1608219786; cv=none; d=zohomail.com; s=zohoarc; b=NkZ4JluwoNOY/YHPiTqukT5OhSV3d5P8ijNEvPaniOjwSpa0jmnigZdd2yHxV57+/XETEd9EnY66gU2ap0wQgsktLw07KIAGiaUWAxV/JaBnqnGC5w5dQmZQEQRmOV3/aOF93Dj7oa7gMwz4poDKaYTn1geTotOLtm/WO9yEAw8= ARC-Message-Signature: i=1; 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Thu, 17 Dec 2020 07:42:38 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 158ab480-93c7-46a5-a1b6-5fec4addc648 From: Bertrand Marquis To: xen-devel@lists.xenproject.org Cc: Stefano Stabellini , Julien Grall , Volodymyr Babchuk Subject: [PATCH v4 8/8] xen/arm: Activate TID3 in HCR_EL2 Date: Thu, 17 Dec 2020 15:38:08 +0000 Message-Id: X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Activate TID3 bit in HCR register when starting a guest. This will trap all coprecessor ID registers so that we can give to guest values corresponding to what they can actually use and mask some features to guests even though they would be supported by the underlying hardware (like SVE or MPAM). Signed-off-by: Bertrand Marquis Reviewed-by: Bertrand Marquis Reviewed-by: Stefano Stabellini --- Changes in V2: Rebase Changes in V3: Rebase Changes in V4: Rebase --- xen/arch/arm/traps.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index 28d9d64558..c1a9ad6056 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -98,7 +98,7 @@ register_t get_default_hcr_flags(void) { return (HCR_PTW|HCR_BSU_INNER|HCR_AMO|HCR_IMO|HCR_FMO|HCR_VM| (vwfi !=3D NATIVE ? (HCR_TWI|HCR_TWE) : 0) | - HCR_TSC|HCR_TAC|HCR_SWIO|HCR_TIDCP|HCR_FB|HCR_TSW); + HCR_TID3|HCR_TSC|HCR_TAC|HCR_SWIO|HCR_TIDCP|HCR_FB|HCR_TSW); } =20 static enum { --=20 2.17.1