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[109.243.67.101]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b8edacf1564sm415776866b.52.2026.02.09.08.52.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Feb 2026 08:52:40 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: bfbf3b32-05d7-11f1-b162-2bf370ae4941 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1770655961; x=1771260761; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=u33CKgrUFdgsGpUw8x9D4VJJRV1mttKFRSeG1+lahcw=; b=b8Nd+ojWbI8XN2n5eAKILcx6uqvdDJKfbggqnaTqo7ApKHvcDbPfx2MyFigUqmmyrz klTR7uMuoEO1VAEuiElllK/5ni1ezrnrhcwHsAnrqJSZZDVMFR2U+ZcM3Kwydhval5f9 jH39wyueqqPpL+Hcypj4BXKsvIv2xOAsf7X2DqHw266UvUgNgHeI467n8cxpFeXPg6V0 ieW1N46VeQGeq85Pn/AnW25N9w+bz3VvmfIt8kla9JvDvWPWxPCg5vuZ6SUJa1Kf7XHw ZYKhSZP04T1RNNWssE7e9YkkDzRbsZz1BDp6wn/dDNdZd71ZpVLNKFcSyveYaTkYpk9J tzrw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1770655961; x=1771260761; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=u33CKgrUFdgsGpUw8x9D4VJJRV1mttKFRSeG1+lahcw=; b=AL6bGU+kKig8Mp7A/f0MUlhCiACxa4D4nxRUoltnbeE88LMFCD07f9+n7QNr6zQvlK EFRNY67ji+ELWndFN9zjybm+7CDFS8Y9BtWbBvp6zXKWAoCJj5OmKdU/Z4IqKX4iOhUV b61UODt3LtBGhefi7f7O9RZ02lows/Vz24+0CPp44+e+Ru2UTaYNrSi40SPkU0BSASFC g104SLKqEDuH7UMOz0B9u1FZIjXWGeZ/Y+dokY7GZ4r1AL2/YiQqmNu+vYPBAwgpUXMv 6FUEELhHKBC7DAJDHTixREZRHt3UtxRmXFgbTnz5DvYX0ymxjVqrw+PE6cQBcwiFP0CP ERVA== X-Gm-Message-State: AOJu0Yxd7ZzaX8x62qo4qEieZiOHrd2s+BmwDRW0A2C9fREeZcq0i4Vi C5wuPBM9W+KLPskwCMVzsxTaBfb5wq3S2d7VqPh9TOpfHUPhdbIUOLe+j2UoUos+ X-Gm-Gg: AZuq6aIaRyiaxM+dYFVfmw3aWvSxJW59v7a+BMAslgI27eaB1/D0KqVwzGDc8cunb/W vt5n7mWlNvY6/HmALj7rzRjZobHpJsImfQjew1PLUzBLVlZgzZjzsUB1e7bDmO9fSVbnA+AybA3 BPQIbpN8g82dX1lvceuswHTs67en2a/vKPYr64pf4N5x3IbdVcYTj1d0qxW2OnJj9+Mwpz8Fq2I +o7JPwqUhEF0oJMka6FpxWsG58Evaq3Wo1dUJ+sZCHAEQLLCCCscIdysLUMc0tLbnDECcwkIFRP rwFALI+5v0gm8zDvkZ9KFqRcxNltC5QgxHugZGyRDwcHSGwy6SERhr3yLwxTCDxyWk1zHJd83wj frslqnH2beXk9QsyQ7oVathygRMPVbzdPzTGVdye5+JRNqe/uOswO/gtN3E5ROfmQW+UUdc0Amv tjoy9WuUr1SWWMkPHoXyrrduYJc4gGt3/VbkqDPsGjzFhGmC9K9fFIww== X-Received: by 2002:a17:907:9409:b0:b88:5a61:5461 with SMTP id a640c23a62f3a-b8f4d34f084mr6259266b.2.1770655960777; Mon, 09 Feb 2026 08:52:40 -0800 (PST) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Romain Caritey , Oleksii Kurochko , Alistair Francis , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH v3 03/16] xen/riscv: detect and store supported hypervisor CSR bits at boot Date: Mon, 9 Feb 2026 17:52:16 +0100 Message-ID: X-Mailer: git-send-email 2.52.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1770655988836158500 Content-Type: text/plain; charset="utf-8" Some hypervisor CSRs expose optional functionality and may not implement all architectural bits. Writing unsupported bits can either be ignored or raise an exception depending on the platform. Detect the set of writable bits for selected hypervisor CSRs at boot and store the resulting masks for later use. This allows safely programming these CSRs during vCPU context switching and avoids relying on hardcoded architectural assumptions. Note that csr_set() is used instead of csr_write() to write all ones to the mask, as the CSRRS instruction, according to the RISC-V specification, sets only those bits that are writable: Any bit that is high in rs1 will cause the corresponding bit to be set in the CSR, if that CSR bit is writable. In contrast, the CSRRW instruction does not take CSR bit writability into account, which could lead to unintended side effects when writing all ones to a CSR. Masks are calculated at the moment only for hdeleg, henvcfg, hideleg, hstateen0 registers as only them are going to be used in the follow up patch. If the Smstateen extension is not implemented, hstateen0 cannot be read because the register is considered non-existent. Instructions that attempt to access a CSR that is not implemented or not visible in the current mode are reserved and will raise an illegal-instruction exception. Signed-off-by: Oleksii Kurochko --- Changes in V3: - New patch. --- xen/arch/riscv/include/asm/setup.h | 9 +++++++++ xen/arch/riscv/setup.c | 26 ++++++++++++++++++++++++++ 2 files changed, 35 insertions(+) diff --git a/xen/arch/riscv/include/asm/setup.h b/xen/arch/riscv/include/as= m/setup.h index c9d69cdf5166..d54f6a2d1d29 100644 --- a/xen/arch/riscv/include/asm/setup.h +++ b/xen/arch/riscv/include/asm/setup.h @@ -5,6 +5,15 @@ =20 #include =20 +struct csr_masks { + register_t hedeleg; + register_t henvcfg; + register_t hideleg; + register_t hstateen0; +}; + +extern struct csr_masks csr_masks; + #define max_init_domid (0) =20 void setup_mm(void); diff --git a/xen/arch/riscv/setup.c b/xen/arch/riscv/setup.c index 9b4835960d20..010489f0b713 100644 --- a/xen/arch/riscv/setup.c +++ b/xen/arch/riscv/setup.c @@ -32,6 +32,8 @@ unsigned char __initdata cpu0_boot_stack[STACK_SIZE] __aligned(STACK_SIZE); =20 +struct csr_masks __ro_after_init csr_masks; + /** * copy_from_paddr - copy data from a physical address * @dst: destination virtual address @@ -70,6 +72,28 @@ static void * __init relocate_fdt(paddr_t dtb_paddr, siz= e_t dtb_size) return fdt; } =20 +void __init init_csr_masks(void) +{ + register_t old; + +#define X(csr, field) \ + old =3D csr_read(CSR_##csr); \ + csr_set(CSR_##csr, ULONG_MAX); \ + csr_masks.field =3D csr_read(CSR_##csr); \ + csr_write(CSR_##csr, old) + + X(HEDELEG, hedeleg); + X(HENVCFG, henvcfg); + X(HIDELEG, hideleg); + + if ( riscv_isa_extension_available(NULL, RISCV_ISA_EXT_smstateen) ) + { + X(HSTATEEN0, hstateen0); + } + +#undef X +} + void __init noreturn start_xen(unsigned long bootcpu_id, paddr_t dtb_addr) { @@ -137,6 +161,8 @@ void __init noreturn start_xen(unsigned long bootcpu_id, =20 riscv_fill_hwcap(); =20 + init_csr_masks(); + preinit_xen_time(); =20 intc_preinit(); --=20 2.52.0