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Mon, 20 Oct 2025 04:18:33 -0700 (PDT) Message-ID: Date: Mon, 20 Oct 2025 13:18:34 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH v2 for-4.21 2/9] x86/HPET: use single, global, low-priority vector for broadcast IRQ From: Jan Beulich To: "xen-devel@lists.xenproject.org" Cc: Andrew Cooper , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Oleksii Kurochko References: Content-Language: en-US Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @suse.com) X-ZM-MESSAGEID: 1760959135756158500 Content-Type: text/plain; charset="utf-8" Using dynamically allocated / maintained vectors has several downsides: - possible nesting of IRQs due to the effects of IRQ migration, - reduction of vectors available for devices, - IRQs not moving as intended if there's shortage of vectors, - higher runtime overhead. As the vector also doesn't need to be of any priority (first and foremost it really shouldn't be of higher or same priority as the timer IRQ, as that raises TIMER_SOFTIRQ anyway), avoid any "ordinary" vectors altogther and use a vector from the 0x10...0x1f exception vector space. Exception vs interrupt can easily be distinguished by checking for the presence of an error code. With a fixed vector, less updating is now necessary in set_channel_irq_affinity(); in particular channels don't need transiently masking anymore, as the necessary update is now atomic. To fully leverage this, however, we want to stop using hpet_msi_set_affinity() there. With the transient masking dropped, we're no longer at risk of missing events. In principle a change to setup_vector_irq() would be necessary, but only if we used low-prio vectors as direct-APIC ones. Since the change would be at best benign here, it is being omitted. Fixes: 996576b965cc ("xen: allow up to 16383 cpus") Signed-off-by: Jan Beulich Release-Acked-by: Oleksii Kurochko --- This is an alternative proposal to https://lists.xen.org/archives/html/xen-devel/2014-03/msg00399.html. Should we keep hpet_msi_set_affinity() at all? We'd better not have the generic IRQ subsystem play with our IRQs' affinities ... (If so, this likely would want to be a separate patch, though.) The hpet_enable_channel() call could in principle be made (effectively) conditional, at the price of introducing a check in hpet_enable_channel(). However, as much as eliminating the masking didn't help with the many excess (early) IRQs I'm observing on Intel hardware, doing so doesn't help either. The Fixes: tag indicates where the problem got signficantly worse; in principle it was there already before (crashing at perhaps 6 or 7 levels of nested IRQs). --- v2: Re-work set_channel_irq_affinity() intensively. Re-base over the dropping of another patch. Drop setup_vector_irq() change. --- a/xen/arch/x86/hpet.c +++ b/xen/arch/x86/hpet.c @@ -9,17 +9,19 @@ #include #include #include +#include #include #include #include #include =20 #include -#include #include +#include +#include #include +#include #include -#include =20 #define MAX_DELTA_NS MILLISECS(10*1000) #define MIN_DELTA_NS MICROSECS(20) @@ -251,10 +253,9 @@ static void cf_check hpet_interrupt_hand ch->event_handler(ch); } =20 -static void cf_check hpet_msi_unmask(struct irq_desc *desc) +static void hpet_enable_channel(struct hpet_event_channel *ch) { u32 cfg; - struct hpet_event_channel *ch =3D desc->action->dev_id; =20 cfg =3D hpet_read32(HPET_Tn_CFG(ch->idx)); cfg |=3D HPET_TN_ENABLE; @@ -262,6 +263,11 @@ static void cf_check hpet_msi_unmask(str ch->msi.msi_attrib.host_masked =3D 0; } =20 +static void cf_check hpet_msi_unmask(struct irq_desc *desc) +{ + hpet_enable_channel(desc->action->dev_id); +} + static void hpet_disable_channel(struct hpet_event_channel *ch) { u32 cfg; @@ -307,15 +313,13 @@ static void cf_check hpet_msi_set_affini struct hpet_event_channel *ch =3D desc->action->dev_id; struct msi_msg msg =3D ch->msi.msg; =20 - msg.dest32 =3D set_desc_affinity(desc, mask); - if ( msg.dest32 =3D=3D BAD_APICID ) - return; + /* This really is only for dump_irqs(). */ + cpumask_copy(desc->arch.cpu_mask, mask); =20 - msg.data &=3D ~MSI_DATA_VECTOR_MASK; - msg.data |=3D MSI_DATA_VECTOR(desc->arch.vector); + msg.dest32 =3D cpu_mask_to_apicid(mask); msg.address_lo &=3D ~MSI_ADDR_DEST_ID_MASK; msg.address_lo |=3D MSI_ADDR_DEST_ID(msg.dest32); - if ( msg.data !=3D ch->msi.msg.data || msg.dest32 !=3D ch->msi.msg.des= t32 ) + if ( msg.dest32 !=3D ch->msi.msg.dest32 ) hpet_msi_write(ch, &msg); } =20 @@ -328,7 +332,7 @@ static hw_irq_controller hpet_msi_type =3D .shutdown =3D hpet_msi_shutdown, .enable =3D hpet_msi_unmask, .disable =3D hpet_msi_mask, - .ack =3D ack_nonmaskable_msi_irq, + .ack =3D irq_actor_none, .end =3D end_nonmaskable_irq, .set_affinity =3D hpet_msi_set_affinity, }; @@ -347,6 +351,12 @@ static int __init hpet_setup_msi_irq(str u32 cfg =3D hpet_read32(HPET_Tn_CFG(ch->idx)); irq_desc_t *desc =3D irq_to_desc(ch->msi.irq); =20 + clear_irq_vector(ch->msi.irq); + ret =3D bind_irq_vector(ch->msi.irq, HPET_BROADCAST_VECTOR, &cpu_onlin= e_map); + if ( ret ) + return ret; + cpumask_setall(desc->affinity); + if ( iommu_intremap !=3D iommu_intremap_off ) { ch->msi.hpet_id =3D hpet_blockid; @@ -476,19 +486,50 @@ static struct hpet_event_channel *hpet_g static void set_channel_irq_affinity(struct hpet_event_channel *ch) { struct irq_desc *desc =3D irq_to_desc(ch->msi.irq); + struct msi_msg msg =3D ch->msi.msg; =20 ASSERT(!local_irq_is_enabled()); spin_lock(&desc->lock); - hpet_msi_mask(desc); - hpet_msi_set_affinity(desc, cpumask_of(ch->cpu)); - hpet_msi_unmask(desc); + + per_cpu(vector_irq, ch->cpu)[HPET_BROADCAST_VECTOR] =3D ch->msi.irq; + + /* + * Open-coding a reduced form of hpet_msi_set_affinity() here. With t= he + * actual update below (either of the IRTE or of [just] message addres= s; + * with interrupt remapping message address/data don't change) now bei= ng + * atomic, we can avoid masking the IRQ around the update. As a result + * we're no longer at risk of missing IRQs (provided hpet_broadcast_en= ter() + * keeps setting the new deadline only afterwards). + */ + cpumask_copy(desc->arch.cpu_mask, cpumask_of(ch->cpu)); + spin_unlock(&desc->lock); =20 - spin_unlock(&ch->lock); + msg.dest32 =3D cpu_physical_id(ch->cpu); + msg.address_lo &=3D ~MSI_ADDR_DEST_ID_MASK; + msg.address_lo |=3D MSI_ADDR_DEST_ID(msg.dest32); + if ( msg.dest32 !=3D ch->msi.msg.dest32 ) + { + ch->msi.msg =3D msg; + + if ( iommu_intremap !=3D iommu_intremap_off ) + { + int rc =3D iommu_update_ire_from_msi(&ch->msi, &msg); =20 - /* We may have missed an interrupt due to the temporary masking. */ - if ( ch->event_handler && ch->next_event < NOW() ) - ch->event_handler(ch); + ASSERT(rc <=3D 0); + if ( rc > 0 ) + { + ASSERT(msg.data =3D=3D hpet_read32(HPET_Tn_ROUTE(ch->idx))= ); + ASSERT(msg.address_lo =3D=3D + hpet_read32(HPET_Tn_ROUTE(ch->idx) + 4)); + } + } + else + hpet_write32(msg.address_lo, HPET_Tn_ROUTE(ch->idx) + 4); + } + + hpet_enable_channel(ch); + spin_unlock(&ch->lock); } =20 static void hpet_attach_channel(unsigned int cpu, --- a/xen/arch/x86/include/asm/irq-vectors.h +++ b/xen/arch/x86/include/asm/irq-vectors.h @@ -18,6 +18,15 @@ /* IRQ0 (timer) is statically allocated but must be high priority. */ #define IRQ0_VECTOR 0xf0 =20 +/* + * Low-priority (for now statically allocated) vectors, sharing entry + * points with exceptions in the 0x10 ... 0x1f range, as long as the + * respective exception has an error code. + */ +#define FIRST_LOPRIORITY_VECTOR 0x10 +#define HPET_BROADCAST_VECTOR X86_EXC_AC +#define LAST_LOPRIORITY_VECTOR 0x1f + /* Legacy PIC uses vectors 0x20-0x2f. */ #define FIRST_LEGACY_VECTOR FIRST_DYNAMIC_VECTOR #define LAST_LEGACY_VECTOR (FIRST_LEGACY_VECTOR + 0xf) @@ -40,7 +49,7 @@ /* There's no IRQ2 at the PIC. */ #define IRQ_MOVE_CLEANUP_VECTOR (FIRST_LEGACY_VECTOR + 2) =20 -#define FIRST_IRQ_VECTOR FIRST_DYNAMIC_VECTOR +#define FIRST_IRQ_VECTOR FIRST_LOPRIORITY_VECTOR #define LAST_IRQ_VECTOR LAST_HIPRIORITY_VECTOR =20 #endif /* _ASM_IRQ_VECTORS_H */ --- a/xen/arch/x86/msi.c +++ b/xen/arch/x86/msi.c @@ -158,7 +158,7 @@ void msi_compose_msg(unsigned vector, co { memset(msg, 0, sizeof(*msg)); =20 - if ( vector < FIRST_DYNAMIC_VECTOR ) + if ( vector < FIRST_LOPRIORITY_VECTOR ) return; =20 if ( cpu_mask ) --- a/xen/arch/x86/x86_64/entry.S +++ b/xen/arch/x86/x86_64/entry.S @@ -1045,7 +1045,13 @@ END(entry_GP) =20 FUNC(entry_AC) ENDBR64 + /* #AC shares its entry point with the HPET broadcast interrupt. */ + test $8, %spl + jz .Lac + push $0 +.Lac: movb $X86_EXC_AC, EFRAME_entry_vector(%rsp) + jnz common_interrupt jmp handle_exception END(entry_AC)