From nobody Thu May 2 07:35:26 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=quarantine dis=none) header.from=suse.com ARC-Seal: i=1; a=rsa-sha256; t=1622033969; cv=none; d=zohomail.com; s=zohoarc; b=RZNs6tSWHr3SkX6jU56Sdp7cOQZfCwEqWk6pWoNF0wVWaVcLxhISdTUybqPVYtolLHOeeCHuyf+z9ZZY1fNjePjIFJcG1VkpvOwrvQdUUWIGORgApG6KsxaKVFLYBsih3XoXDEgBFBzpF2H/QgximRr2h+TtS6816eIeKRNKLOw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622033969; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:To; bh=jwQbCnoo88KOyKF0JjLRzmmEZgGZkhuakgk/vH3ZXoI=; b=QvY/hCKoUwm4Tz2t4yD376WjxMMpZW2d50FFdoL2NDYlZ5lS+zXrPEHRzGrPvuqVv8HKQLeryScU11+uwDeRLBL2tZr0bTwJZY/zl2ylWxwSsCaXom8HviXRjslmBVyRi5IRSU/l35hdDzHwLyECjwJJT19H+ild9AcGPXmq5nE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=quarantine dis=none) header.from= Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1622033969340528.6016223089819; Wed, 26 May 2021 05:59:29 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.132487.247104 (Exim 4.92) (envelope-from ) id 1llt7t-0002dJ-32; Wed, 26 May 2021 12:59:09 +0000 Received: by outflank-mailman (output) from mailman id 132487.247104; Wed, 26 May 2021 12:59:09 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1llt7t-0002dC-05; Wed, 26 May 2021 12:59:09 +0000 Received: by outflank-mailman (input) for mailman id 132487; Wed, 26 May 2021 12:59:07 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1llt7r-0002d6-Od for xen-devel@lists.xenproject.org; Wed, 26 May 2021 12:59:07 +0000 Received: from smtp-out2.suse.de (unknown [195.135.220.29]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTPS id 8d95842c-955c-406e-9398-81d2508af71c; Wed, 26 May 2021 12:59:06 +0000 (UTC) Received: from imap.suse.de (imap-alt.suse-dmz.suse.de [192.168.254.47]) by smtp-out2.suse.de (Postfix) with ESMTP id 378841FD29; Wed, 26 May 2021 12:59:05 +0000 (UTC) Received: from director2.suse.de (director2.suse-dmz.suse.de [192.168.254.72]) by imap.suse.de (Postfix) with ESMTPSA id 1445111A98; Wed, 26 May 2021 12:59:05 +0000 (UTC) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 8d95842c-955c-406e-9398-81d2508af71c DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=susede1; t=1622033945; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=jwQbCnoo88KOyKF0JjLRzmmEZgGZkhuakgk/vH3ZXoI=; b=bLiabYByA7DFE4/6NIgc86DpE4LdM41qd06Gqj7y8gU5nI6y5lUB87gdnwj4RMgfGwrroV cI7YkZ5Cd9QA85lWMVl0GRNldD4SOJ/rSbTFS08jEiLwOaSn1OxrL/Wei8r5YNxAXAKTD0 0vT7oc7pF92JdoPsN+smz8+mB7PWS+c= To: "xen-devel@lists.xenproject.org" Cc: Andrew Cooper , Wei Liu , =?UTF-8?Q?Roger_Pau_Monn=c3=a9?= , Olaf Hering From: Jan Beulich Subject: [PATCH] x86/AMD: expose SYSCFG, TOM, and TOM2 to Dom0 Message-ID: Date: Wed, 26 May 2021 14:59:00 +0200 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.10.2 MIME-Version: 1.0 Content-Language: en-US Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @suse.com) Content-Type: text/plain; charset="utf-8" Sufficiently old Linux (3.12-ish) accesses these MSRs in an unguarded manner. Furthermore these MSRs, at least on Fam11 and older CPUs, are also consulted by modern Linux, and their (bogus) built-in zapping of #GP faults from MSR accesses leads to it effectively reading zero instead of the intended values, which are relevant for PCI BAR placement (which ought to all live in MMIO-type space, not in DRAM-type one). For SYSCFG, only certain bits get exposed. In fact, whether to expose MtrrVarDramEn is debatable: It controls use of not just TOM, but also the IORRs. Introduce (consistently named) constants for the bits we're interested in and use them in pre-existing code as well. As a welcome side effect, verbosity on/of debug builds gets (perhaps significantly) reduced. Note that at least as far as those MSR accesses by Linux are concerned, there's no similar issue for DomU-s, as the accesses sit behind PCI device matching logic. The checked for devices would never be exposed to DomU-s in the first place. Nevertheless I think that at least for HVM we should return sensible values, not 0 (as svm_msr_read_intercept() does right now). The intended values may, however, need to be determined by hvmloader, and then get made known to Xen. Fixes: 322ec7c89f66 ("x86/pv: disallow access to unknown MSRs") Reported-by: Olaf Hering Signed-off-by: Jan Beulich --- a/xen/arch/x86/cpu/amd.c +++ b/xen/arch/x86/cpu/amd.c @@ -468,14 +468,14 @@ static void check_syscfg_dram_mod_en(voi return; =20 rdmsrl(MSR_K8_SYSCFG, syscfg); - if (!(syscfg & K8_MTRRFIXRANGE_DRAM_MODIFY)) + if (!(syscfg & SYSCFG_MTRR_FIX_DRAM_MOD_EN)) return; =20 if (!test_and_set_bool(printed)) printk(KERN_ERR "MTRR: SYSCFG[MtrrFixDramModEn] not " "cleared by BIOS, clearing this bit\n"); =20 - syscfg &=3D ~K8_MTRRFIXRANGE_DRAM_MODIFY; + syscfg &=3D ~SYSCFG_MTRR_FIX_DRAM_MOD_EN; wrmsrl(MSR_K8_SYSCFG, syscfg); } =20 --- a/xen/arch/x86/cpu/mtrr/generic.c +++ b/xen/arch/x86/cpu/mtrr/generic.c @@ -224,7 +224,7 @@ static void __init print_mtrr_state(cons uint64_t syscfg, tom2; =20 rdmsrl(MSR_K8_SYSCFG, syscfg); - if (syscfg & (1 << 21)) { + if (syscfg & SYSCFG_MTRR_TOM2_EN) { rdmsrl(MSR_K8_TOP_MEM2, tom2); printk("%sTOM2: %012"PRIx64"%s\n", level, tom2, syscfg & (1 << 22) ? " (WB)" : ""); --- a/xen/arch/x86/msr.c +++ b/xen/arch/x86/msr.c @@ -339,6 +339,19 @@ int guest_rdmsr(struct vcpu *v, uint32_t *val =3D msrs->tsc_aux; break; =20 + case MSR_K8_SYSCFG: + case MSR_K8_TOP_MEM1: + case MSR_K8_TOP_MEM2: + if ( !(cp->x86_vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON)) ) + goto gp_fault; + if ( !is_hardware_domain(d) ) + return X86EMUL_UNHANDLEABLE; + rdmsrl(msr, *val); + if ( msr =3D=3D MSR_K8_SYSCFG ) + *val &=3D (SYSCFG_TOM2_FORCE_WB | SYSCFG_MTRR_TOM2_EN | + SYSCFG_MTRR_VAR_DRAM_EN | SYSCFG_MTRR_FIX_DRAM_EN); + break; + case MSR_K8_HWCR: if ( !(cp->x86_vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON)) ) goto gp_fault; --- a/xen/arch/x86/x86_64/mmconf-fam10h.c +++ b/xen/arch/x86/x86_64/mmconf-fam10h.c @@ -69,7 +69,7 @@ static void __init get_fam10h_pci_mmconf rdmsrl(address, val); =20 /* TOP_MEM2 is not enabled? */ - if (!(val & (1<<21))) { + if (!(val & SYSCFG_MTRR_TOM2_EN)) { tom2 =3D 1ULL << 32; } else { /* TOP_MEM2 */ --- a/xen/include/asm-x86/msr-index.h +++ b/xen/include/asm-x86/msr-index.h @@ -116,6 +116,13 @@ #define PASID_PASID_MASK 0x000fffff #define PASID_VALID (_AC(1, ULL) << 31) =20 +#define MSR_K8_SYSCFG 0xc0010010 +#define SYSCFG_MTRR_FIX_DRAM_EN (_AC(1, ULL) << 18) +#define SYSCFG_MTRR_FIX_DRAM_MOD_EN (_AC(1, ULL) << 19) +#define SYSCFG_MTRR_VAR_DRAM_EN (_AC(1, ULL) << 20) +#define SYSCFG_MTRR_TOM2_EN (_AC(1, ULL) << 21) +#define SYSCFG_TOM2_FORCE_WB (_AC(1, ULL) << 22) + #define MSR_K8_VM_CR 0xc0010114 #define VM_CR_INIT_REDIRECTION (_AC(1, ULL) << 1) #define VM_CR_SVM_DISABLE (_AC(1, ULL) << 4) @@ -279,10 +286,7 @@ #define MSR_K8_TOP_MEM1 0xc001001a #define MSR_K7_CLK_CTL 0xc001001b #define MSR_K8_TOP_MEM2 0xc001001d -#define MSR_K8_SYSCFG 0xc0010010 =20 -#define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */ -#define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */ #define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */ =20 #define MSR_K7_HWCR 0xc0010015