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[37.24.206.209]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a80f414e18csm148065366b.177.2024.08.14.01.51.21 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 14 Aug 2024 01:51:21 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 61b2a581-5a1a-11ef-8776-851b0ebba9a2 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=google; t=1723625482; x=1724230282; darn=lists.xenproject.org; h=content-transfer-encoding:in-reply-to:autocrypt:content-language :references:cc:to:from:subject:user-agent:mime-version:date :message-id:from:to:cc:subject:date:message-id:reply-to; bh=7NIzDq8nKrmgupkcpKHhiCNLWhQt61fPrxdoZjP5mbI=; b=hGjtcdz+ZME3jQx0LtWNOhZb/DeFqSAriHOw9xDzpY29ve2ZRwX65kVTsh6URLECKS nw+NqcrjIbO13uPvhwtXckdgLFWoEAwQcjPXyZhot2f3fbHisRBPNXPnAIvEwhWngONK DFFE6CttElWq4PWzDOKDgAZDF+Y6mAuo4WNjsep3+UBJNaQX4gAo4a/mtlSled+oj86N aqvqSlbtNWv/g+4ah7YzqZnaqD6HvmjrVT4GVZ/VVpszW3DZC2jKJtwxhJ7ZfZ7fgZhh HgkCkgoOgMilp9KlO+yoReTzGI1hMbnEYBuYBY4zZ+a2nUx4ApXIzj69u9TNvm4MrsDa nS2w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1723625482; x=1724230282; h=content-transfer-encoding:in-reply-to:autocrypt:content-language :references:cc:to:from:subject:user-agent:mime-version:date :message-id:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=7NIzDq8nKrmgupkcpKHhiCNLWhQt61fPrxdoZjP5mbI=; b=nk/ZV6YrYOWcGBq91rR/CHU5QPGv6eUcYS+UUws0pDWrJdumX8+IuQrJHCs7E92oLe BkrFU0qdLx43m7Y4In/05XYKW7CZkc7T+KMj8+uCoWWfAQaGWqrAhcCbr51ns9/fIVNR BJgJ/bhbOH4VDGb9koOeIrR+Rpr/wkFY5MEATvvksjjPYTNL5cyx6XH9r/lA2eHVmKVh 7BorUEbV14kVTd9GNlX22bBwPuPPXa48gFqbLW4hk59XQPuRQwI7nqMRB9oUJf/ROgXZ 1Pc/vYJu/WFGftC8SPoCmoRiHbfDHQ7pdYMVdyPQC4d0R1qWUww6F/w7zg6EpTxZB6fY +nGQ== X-Gm-Message-State: AOJu0YxjAIkqiZpj2f+/SK3rwVa0YLxt5TYxtcbQZ0Q7Gdl+Kyw8Wo8Q bti1YvBqv2TyDA9CJskdyyTsDBs9k94JVfdS75lh3pWUvIvILvWIxHfHfiEuXUra8FgvNgLuP80 = X-Google-Smtp-Source: AGHT+IEyNycA81jEG7Xdtj8sKMuH1EZpK8J8nnKiiyCc/6KwL+CW5qeZuVsBs9CSb8EVTYowZcEbfQ== X-Received: by 2002:a17:907:e88:b0:a79:7ec8:f3f3 with SMTP id a640c23a62f3a-a83670c01c0mr104292466b.58.1723625481977; Wed, 14 Aug 2024 01:51:21 -0700 (PDT) Message-ID: <27866cd1-495f-4b86-986d-31003dad9c23@suse.com> Date: Wed, 14 Aug 2024 10:51:20 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH v2 1/9] x86/CPUID: enable AVX10 leaf From: Jan Beulich To: "xen-devel@lists.xenproject.org" Cc: Andrew Cooper , Wei Liu , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= References: Content-Language: en-US Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @suse.com) X-ZM-MESSAGEID: 1723625503455116600 Content-Type: text/plain; charset="utf-8" This requires bumping the number of basic leaves we support. Apart from this the logic is modeled as closely as possible after that of leaf 7 handling. Signed-off-by: Jan Beulich --- The gen-cpuid.py adjustment is merely the minimum needed. It's not really clear to me whether someone turning off e.g. AVX512BW might then also validly expect AVX10 to be turned off. Spec version 2 leaves unclear what the xstate components are which would need enabling for AVX10/256. recalculate_{xstate,misc}() are therefore conservative for now. Do we want to synthesize AVX10 in the policy when all necessary AVX512* features are available, thus allowing migration from an AVX10 host to a suitable non-AVX10 one? How a toolstack side equivalent (if any) of the init_dom0_cpuid_policy() change would look like is entirely unclear to me. How much should we take from the max policy, and how much should we require the user to specify (and how would the latter look like)? --- v2: Add logic to init_dom0_cpuid_policy(). Drop vsz128 field. Re-base. --- a/xen/arch/x86/cpu-policy.c +++ b/xen/arch/x86/cpu-policy.c @@ -210,7 +210,7 @@ static void recalculate_xstate(struct cp if ( p->feat.mpx ) xstates |=3D X86_XCR0_BNDREGS | X86_XCR0_BNDCSR; =20 - if ( p->feat.avx512f ) + if ( p->feat.avx512f || (p->feat.avx10 && p->avx10.vsz512) ) xstates |=3D X86_XCR0_OPMASK | X86_XCR0_ZMM | X86_XCR0_HI_ZMM; =20 if ( p->feat.pku ) @@ -268,6 +268,16 @@ static void recalculate_misc(struct cpu_ =20 p->basic.raw[0xc] =3D EMPTY_LEAF; =20 + zero_leaves(p->basic.raw, 0xe, 0x23); + + p->avx10.raw[0].b &=3D 0x000700ff; + p->avx10.raw[0].c =3D p->avx10.raw[0].d =3D 0; + if ( !p->feat.avx10 || !p->avx10.version || !p->avx10.vsz512 ) + { + p->feat.avx10 =3D false; + memset(p->avx10.raw, 0, sizeof(p->avx10.raw)); + } + p->extd.e1d &=3D ~CPUID_COMMON_1D_FEATURES; =20 /* Most of Power/RAS hidden from guests. */ @@ -885,6 +895,7 @@ void recalculate_cpuid_policy(struct dom =20 p->basic.max_leaf =3D min(p->basic.max_leaf, max->basic.max_leaf); p->feat.max_subleaf =3D min(p->feat.max_subleaf, max->feat.max_subleaf= ); + p->avx10.max_subleaf =3D min(p->avx10.max_subleaf, max->avx10.max_subl= eaf); p->extd.max_leaf =3D 0x80000000U | min(p->extd.max_leaf & 0xffff, ((p->x86_vendor & (X86_VENDOR_= AMD | X86_VENDOR_= HYGON)) @@ -931,6 +942,8 @@ void recalculate_cpuid_policy(struct dom =20 if ( p->basic.max_leaf < XSTATE_CPUID ) __clear_bit(X86_FEATURE_XSAVE, fs); + if ( p->basic.max_leaf < 0x24 ) + __clear_bit(X86_FEATURE_AVX10, fs); =20 sanitise_featureset(fs); =20 @@ -1000,9 +1013,18 @@ void __init init_dom0_cpuid_policy(struc /* Apply dom0-cpuid=3D command line settings, if provided. */ if ( dom0_cpuid_cmdline ) { + const struct cpu_policy *max =3D is_pv_domain(d) + ? (IS_ENABLED(CONFIG_PV) ? &pv_max_cpu_policy : NULL) + : (IS_ENABLED(CONFIG_HVM) ? &hvm_max_cpu_policy : NULL); uint32_t fs[FSCAPINTS]; unsigned int i; =20 + if ( !max ) + { + ASSERT_UNREACHABLE(); + return; + } + x86_cpu_policy_to_featureset(p, fs); =20 for ( i =3D 0; i < ARRAY_SIZE(fs); ++i ) @@ -1012,6 +1034,13 @@ void __init init_dom0_cpuid_policy(struc } =20 x86_cpu_featureset_to_policy(fs, p); + + /* + * Default-off features with their own leaves need those leaves + * re-populated from the max policy. + */ + if ( p->feat.avx10 ) + p->avx10 =3D max->avx10; } =20 /* @@ -1044,6 +1073,8 @@ static void __init __maybe_unused build_ sizeof(raw_cpu_policy.feat.raw)); BUILD_BUG_ON(sizeof(raw_cpu_policy.xstate) !=3D sizeof(raw_cpu_policy.xstate.raw)); + BUILD_BUG_ON(sizeof(raw_cpu_policy.avx10) !=3D + sizeof(raw_cpu_policy.avx10.raw)); BUILD_BUG_ON(sizeof(raw_cpu_policy.extd) !=3D sizeof(raw_cpu_policy.extd.raw)); } --- a/xen/arch/x86/cpuid.c +++ b/xen/arch/x86/cpuid.c @@ -87,6 +87,15 @@ void guest_cpuid(const struct vcpu *v, u *res =3D array_access_nospec(p->xstate.raw, subleaf); break; =20 + case 0x24: + ASSERT(p->avx10.max_subleaf < ARRAY_SIZE(p->avx10.raw)); + if ( subleaf > min_t(uint32_t, p->avx10.max_subleaf, + ARRAY_SIZE(p->avx10.raw) - 1) ) + return; + + *res =3D array_access_nospec(p->avx10.raw, subleaf); + break; + default: *res =3D array_access_nospec(p->basic.raw, leaf); break; --- a/xen/include/public/arch-x86/cpufeatureset.h +++ b/xen/include/public/arch-x86/cpufeatureset.h @@ -334,6 +334,7 @@ XEN_CPUFEATURE(AVX_NE_CONVERT, 15*32 XEN_CPUFEATURE(AVX_VNNI_INT16, 15*32+10) /*A AVX-VNNI-INT16 Instructi= ons */ XEN_CPUFEATURE(PREFETCHI, 15*32+14) /*A PREFETCHIT{0,1} Instruct= ions */ XEN_CPUFEATURE(CET_SSS, 15*32+18) /* CET Supervisor Shadow St= acks safe to use */ +XEN_CPUFEATURE(AVX10, 15*32+19) /* AVX10 Converged Vector I= SA */ =20 /* Intel-defined CPU features, MSR_ARCH_CAPS 0x10a.eax, word 16 */ XEN_CPUFEATURE(RDCL_NO, 16*32+ 0) /*A No Rogue Data Cache Load= (Meltdown) */ --- a/xen/include/xen/lib/x86/cpu-policy.h +++ b/xen/include/xen/lib/x86/cpu-policy.h @@ -85,11 +85,12 @@ unsigned int x86_cpuid_lookup_vendor(uin */ const char *x86_cpuid_vendor_to_str(unsigned int vendor); =20 -#define CPUID_GUEST_NR_BASIC (0xdu + 1) +#define CPUID_GUEST_NR_BASIC (0x24u + 1) #define CPUID_GUEST_NR_CACHE (5u + 1) #define CPUID_GUEST_NR_FEAT (2u + 1) #define CPUID_GUEST_NR_TOPO (1u + 1) #define CPUID_GUEST_NR_XSTATE (62u + 1) +#define CPUID_GUEST_NR_AVX10 (0u + 1) #define CPUID_GUEST_NR_EXTD_INTEL (0x8u + 1) #define CPUID_GUEST_NR_EXTD_AMD (0x21u + 1) #define CPUID_GUEST_NR_EXTD MAX(CPUID_GUEST_NR_EXTD_INTEL, \ @@ -255,6 +256,19 @@ struct cpu_policy } comp[CPUID_GUEST_NR_XSTATE]; } xstate; =20 + /* Structured AVX10 information leaf: 0x000000024[xx] */ + union { + struct cpuid_leaf raw[CPUID_GUEST_NR_AVX10]; + struct { + /* Subleaf 0. */ + uint32_t max_subleaf; + uint32_t version:8, :9; + bool vsz256:1, vsz512:1; + uint32_t :13; + uint32_t /* c */:32, /* d */:32; + }; + } avx10; + /* Extended leaves: 0x800000xx */ union { struct cpuid_leaf raw[CPUID_GUEST_NR_EXTD]; --- a/xen/lib/x86/cpuid.c +++ b/xen/lib/x86/cpuid.c @@ -123,6 +123,7 @@ void x86_cpu_policy_fill_native(struct c switch ( i ) { case 0x4: case 0x7: case 0xb: case 0xd: + case 0x24: /* Multi-invocation leaves. Deferred. */ continue; } @@ -216,6 +217,15 @@ void x86_cpu_policy_fill_native(struct c } } =20 + if ( p->basic.max_leaf >=3D 0x24 ) + { + cpuid_count_leaf(0x24, 0, &p->avx10.raw[0]); + + for ( i =3D 1; i <=3D MIN(p->avx10.max_subleaf, + ARRAY_SIZE(p->avx10.raw) - 1); ++i ) + cpuid_count_leaf(0x24, i, &p->avx10.raw[i]); + } + /* Extended leaves. */ cpuid_leaf(0x80000000U, &p->extd.raw[0]); for ( i =3D 1; i <=3D MIN(p->extd.max_leaf & 0xffffU, @@ -285,6 +295,9 @@ void x86_cpu_policy_clear_out_of_range_l ARRAY_SIZE(p->xstate.raw) - 1); } =20 + if ( p->basic.max_leaf < 0x24 ) + memset(p->avx10.raw, 0, sizeof(p->avx10.raw)); + zero_leaves(p->extd.raw, ((p->extd.max_leaf >> 16) =3D=3D 0x8000 ? (p->extd.max_leaf & 0xffff) + 1 : 0), @@ -297,6 +310,8 @@ void __init x86_cpu_policy_bound_max_lea min_t(uint32_t, p->basic.max_leaf, ARRAY_SIZE(p->basic.raw) - 1); p->feat.max_subleaf =3D min_t(uint32_t, p->feat.max_subleaf, ARRAY_SIZE(p->feat.raw) - 1); + p->avx10.max_subleaf =3D + min_t(uint32_t, p->avx10.max_subleaf, ARRAY_SIZE(p->avx10.raw) - 1= ); p->extd.max_leaf =3D 0x80000000U | min_t(uint32_t, p->extd.max_leaf & = 0xffff, ARRAY_SIZE(p->extd.raw) - 1); } @@ -324,6 +339,8 @@ void x86_cpu_policy_shrink_max_leaves(st */ p->basic.raw[0xd] =3D p->xstate.raw[0]; =20 + p->basic.raw[0x24] =3D p->avx10.raw[0]; + for ( i =3D p->basic.max_leaf; i; --i ) if ( p->basic.raw[i].a | p->basic.raw[i].b | p->basic.raw[i].c | p->basic.raw[i].d ) @@ -457,6 +474,13 @@ int x86_cpuid_copy_to_buffer(const struc break; } =20 + case 0x24: + for ( subleaf =3D 0; + subleaf <=3D MIN(p->avx10.max_subleaf, + ARRAY_SIZE(p->avx10.raw) - 1); ++subleaf ) + COPY_LEAF(leaf, subleaf, &p->avx10.raw[subleaf]); + break; + default: COPY_LEAF(leaf, XEN_CPUID_NO_SUBLEAF, &p->basic.raw[leaf]); break; @@ -549,6 +573,13 @@ int x86_cpuid_copy_from_buffer(struct cp array_access_nospec(p->xstate.raw, data.subleaf) =3D l; break; =20 + case 0x24: + if ( data.subleaf >=3D ARRAY_SIZE(p->avx10.raw) ) + goto out_of_range; + + array_access_nospec(p->avx10.raw, data.subleaf) =3D l; + break; + default: if ( data.subleaf !=3D XEN_CPUID_NO_SUBLEAF ) goto out_of_range; --- a/xen/lib/x86/policy.c +++ b/xen/lib/x86/policy.c @@ -21,6 +21,12 @@ int x86_cpu_policies_are_compatible(cons if ( guest->feat.max_subleaf > host->feat.max_subleaf ) FAIL_CPUID(7, 0); =20 + if ( guest->avx10.version > host->avx10.version || + (guest->avx10.vsz512 + ? !host->avx10.vsz512 + : guest->avx10.vsz256 && !host->avx10.vsz256 && !host->avx10.vsz= 512) ) + FAIL_CPUID(0x24, 0); + if ( guest->extd.max_leaf > host->extd.max_leaf ) FAIL_CPUID(0x80000000U, NA); =20 --- a/xen/tools/gen-cpuid.py +++ b/xen/tools/gen-cpuid.py @@ -285,7 +285,7 @@ def crunch_numbers(state): # enabled. Certain later extensions, acting on 256-bit vectors of # integers, better depend on AVX2 than AVX. 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[37.24.206.209]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5bd1a5dfdbbsm3627397a12.69.2024.08.14.01.51.49 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 14 Aug 2024 01:51:50 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 72bd90d2-5a1a-11ef-8776-851b0ebba9a2 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=google; t=1723625511; x=1724230311; darn=lists.xenproject.org; h=content-transfer-encoding:in-reply-to:autocrypt:content-language :references:cc:to:from:subject:user-agent:mime-version:date :message-id:from:to:cc:subject:date:message-id:reply-to; bh=dG2vMvLcW/CKv3B8uTWG6y9mz8h5Sex7Ma69J4j6IRs=; b=fPsF4k5PqZFFoeZSoT0urYHtRKEJSvg+8wTm19+ZecYnsOvwicPpEvGrNNQcn6CD5Y KDBh7oViXp27nc0PjXVgB5K42FasYqMaBZzGaSgxN0pK0nYSM9G+vf595bOzVuKFhSjJ CCl5+wPPOgl97mOvfFfbgdhDi+suZ1clQBPL7gz2pxN+H+FFhvPHSpyVgZmfT+UzfYGf B5x9ktKa1ESN3X0macMB//mfnJoSlse+Z+PQyJBK+oDy7x8PaiYHem+yuIE7DZYIX+9W iNMHJWKQ3bs33FIfY2cwk9AePOw6lk/ua1wTYfeMrl2gL/uBBrux3OHkbHva3MjNTGv9 1odg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1723625511; x=1724230311; h=content-transfer-encoding:in-reply-to:autocrypt:content-language :references:cc:to:from:subject:user-agent:mime-version:date :message-id:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=dG2vMvLcW/CKv3B8uTWG6y9mz8h5Sex7Ma69J4j6IRs=; b=dhZQgOyDx8fdJiu/hgaVTCoGT1CI6XzhvZP8g6O9UDa4S7utDuHwU72UoIFeqbkPcb J17sySq0+NERkZrCACHDmQVabym+OpbEVAhRwYbAzpUUW1xE9W4S7vf/RZTcTiCKaF9m 44eAvHzqjNkuHWUKut2Mbdi4hn0yykt35j6AvJVXkGhSO4hYQbtgbZ+/EUlK+ultWd6W gl3hmiQG68xIeTrfdPa9UpqMT3C7Y5Ubdw9Ruagmo2FRe4gaTbtgduQa0yEud4VN21lM FOvWMss4u0a1gqa8Ik1nA4BDewiTYr48n/IDtyUfs5L1lBuymlZVoZi9H+fJ5UL4m+FU a+ZA== X-Gm-Message-State: AOJu0YwVjd+eVVnfffdlawtaqVRBo+1s4WyfQ+vV34ZbKRD3rBC7XYlS GtfbqR4R1lLf1PgZJ3XJeP/XIYW7mJdEKJIHmrekHHvjvMqOGM/B7ipdoooJoFmjJzWKiIdZJGA = X-Google-Smtp-Source: AGHT+IH1ClCcbXutHY4znaus4vLnl67NAk0QPYuj/ezD5b1l8gJbxbjCLOZj9uGbIeLgXvdq0LIx/Q== X-Received: by 2002:a2e:8185:0:b0:2f3:a06a:4c5 with SMTP id 38308e7fff4ca-2f3aa1c945fmr12984971fa.29.1723625510404; Wed, 14 Aug 2024 01:51:50 -0700 (PDT) Message-ID: Date: Wed, 14 Aug 2024 10:51:49 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH v2 2/9] x86emul/test: rename "cp" From: Jan Beulich To: "xen-devel@lists.xenproject.org" Cc: Andrew Cooper , Wei Liu , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= References: Content-Language: en-US Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @suse.com) X-ZM-MESSAGEID: 1723625527517116600 Content-Type: text/plain; charset="utf-8" In preparation of introducing a const struct cpu_policy * local in x86_emulate(), rename that global variable to something more suitable: "cp" is our commonly used name for function parameters or local variables of type struct cpu_policy *, and the present name of the global could hence have interfered already. Signed-off-by: Jan Beulich --- v2: Re-base over dropping of Xeon Phi support. --- a/tools/fuzz/x86_instruction_emulator/fuzz-emul.c +++ b/tools/fuzz/x86_instruction_emulator/fuzz-emul.c @@ -899,7 +899,7 @@ int LLVMFuzzerTestOneInput(const uint8_t int rc; =20 /* Not part of the initializer, for old gcc to cope. */ - ctxt.cpu_policy =3D &cp; + ctxt.cpu_policy =3D &cpu_policy; =20 /* Reset all global state variables */ memset(&input, 0, sizeof(input)); --- a/tools/tests/x86_emulator/test_x86_emulator.c +++ b/tools/tests/x86_emulator/test_x86_emulator.c @@ -779,7 +779,8 @@ static void zap_fpsel(unsigned int *env, env[3] &=3D ~0xffff; } =20 - if ( cp.x86_vendor !=3D X86_VENDOR_AMD && cp.x86_vendor !=3D X86_VENDO= R_HYGON ) + if ( cpu_policy.x86_vendor !=3D X86_VENDOR_AMD && + cpu_policy.x86_vendor !=3D X86_VENDOR_HYGON ) return; =20 if ( is_32bit ) @@ -913,7 +914,7 @@ int main(int argc, char **argv) =20 ctxt.regs =3D ®s; ctxt.force_writeback =3D 0; - ctxt.cpu_policy =3D &cp; + ctxt.cpu_policy =3D &cpu_policy; ctxt.lma =3D sizeof(void *) =3D=3D 8; ctxt.addr_size =3D 8 * sizeof(void *); ctxt.sp_size =3D 8 * sizeof(void *); @@ -1487,11 +1488,11 @@ int main(int argc, char **argv) goto fail; printf("okay\n"); =20 - vendor_native =3D cp.x86_vendor; - for ( cp.x86_vendor =3D X86_VENDOR_AMD; ; ) + vendor_native =3D cpu_policy.x86_vendor; + for ( cpu_policy.x86_vendor =3D X86_VENDOR_AMD; ; ) { - unsigned int v =3D cp.x86_vendor =3D=3D X86_VENDOR_INTEL; - const char *vendor =3D cp.x86_vendor =3D=3D X86_VENDOR_INTEL ? "In= tel" : "AMD"; + unsigned int v =3D cpu_policy.x86_vendor =3D=3D X86_VENDOR_INTEL; + const char *vendor =3D cpu_policy.x86_vendor =3D=3D X86_VENDOR_INT= EL ? "Intel" : "AMD"; uint64_t *stk =3D (void *)res + MMAP_SZ - 16; =20 regs.rcx =3D 2; @@ -1527,11 +1528,11 @@ int main(int argc, char **argv) printf("okay\n"); } =20 - if ( cp.x86_vendor =3D=3D X86_VENDOR_INTEL ) + if ( cpu_policy.x86_vendor =3D=3D X86_VENDOR_INTEL ) break; - cp.x86_vendor =3D X86_VENDOR_INTEL; + cpu_policy.x86_vendor =3D X86_VENDOR_INTEL; } - cp.x86_vendor =3D vendor_native; + cpu_policy.x86_vendor =3D vendor_native; #endif /* x86-64 */ =20 printf("%-40s", "Testing shld $1,%ecx,(%edx)..."); --- a/tools/tests/x86_emulator/x86-emulate.c +++ b/tools/tests/x86_emulator/x86-emulate.c @@ -25,7 +25,7 @@ #endif =20 uint32_t mxcsr_mask =3D 0x0000ffbf; -struct cpu_policy cp; +struct cpu_policy cpu_policy; =20 static char fpu_save_area[0x4000] __attribute__((__aligned__((64)))); static bool use_xsave; @@ -75,21 +75,21 @@ bool emul_test_init(void) =20 unsigned long sp; =20 - x86_cpu_policy_fill_native(&cp); - x86_cpu_policy_bound_max_leaves(&cp); + x86_cpu_policy_fill_native(&cpu_policy); + x86_cpu_policy_bound_max_leaves(&cpu_policy); =20 /* * The emulator doesn't use these instructions, so can always emulate * them. */ - cp.basic.movbe =3D true; - cp.feat.invpcid =3D true; - cp.feat.adx =3D true; - cp.feat.rdpid =3D true; - cp.feat.wrmsrns =3D true; - cp.extd.clzero =3D true; + cpu_policy.basic.movbe =3D true; + cpu_policy.feat.invpcid =3D true; + cpu_policy.feat.adx =3D true; + cpu_policy.feat.rdpid =3D true; + cpu_policy.feat.wrmsrns =3D true; + cpu_policy.extd.clzero =3D true; =20 - x86_cpu_policy_shrink_max_leaves(&cp); + x86_cpu_policy_shrink_max_leaves(&cpu_policy); =20 if ( cpu_has_xsave ) { --- a/tools/tests/x86_emulator/x86-emulate.h +++ b/tools/tests/x86_emulator/x86-emulate.h @@ -69,7 +69,7 @@ #define is_canonical_address(x) (((int64_t)(x) >> 47) =3D=3D ((int64_t)(x)= >> 63)) =20 extern uint32_t mxcsr_mask; -extern struct cpu_policy cp; +extern struct cpu_policy cpu_policy; =20 #define MMAP_SZ 16384 bool emul_test_init(void); @@ -123,7 +123,7 @@ static inline uint64_t xgetbv(uint32_t x } =20 /* Intentionally checking OSXSAVE here. */ -#define cpu_has_xsave (cp.basic.raw[1].c & (1u << 27)) +#define cpu_has_xsave (cpu_policy.basic.raw[1].c & (1u << 27)) =20 static inline bool xcr0_mask(uint64_t mask) { @@ -133,63 +133,63 @@ static inline bool xcr0_mask(uint64_t ma unsigned int rdpkru(void); void wrpkru(unsigned int val); =20 -#define cache_line_size() (cp.basic.clflush_size * 8) -#define cpu_has_fpu cp.basic.fpu -#define cpu_has_mmx cp.basic.mmx -#define cpu_has_fxsr cp.basic.fxsr -#define cpu_has_sse cp.basic.sse -#define cpu_has_sse2 cp.basic.sse2 -#define cpu_has_sse3 cp.basic.sse3 -#define cpu_has_pclmulqdq cp.basic.pclmulqdq -#define cpu_has_ssse3 cp.basic.ssse3 -#define cpu_has_fma (cp.basic.fma && xcr0_mask(6)) -#define cpu_has_sse4_1 cp.basic.sse4_1 -#define cpu_has_sse4_2 cp.basic.sse4_2 -#define cpu_has_popcnt cp.basic.popcnt -#define cpu_has_aesni cp.basic.aesni -#define cpu_has_avx (cp.basic.avx && xcr0_mask(6)) -#define cpu_has_f16c (cp.basic.f16c && xcr0_mask(6)) - -#define cpu_has_avx2 (cp.feat.avx2 && xcr0_mask(6)) -#define cpu_has_bmi1 cp.feat.bmi1 -#define cpu_has_bmi2 cp.feat.bmi2 -#define cpu_has_avx512f (cp.feat.avx512f && xcr0_mask(0xe6)) -#define cpu_has_avx512dq (cp.feat.avx512dq && xcr0_mask(0xe6)) -#define cpu_has_avx512_ifma (cp.feat.avx512_ifma && xcr0_mask(0xe6)) -#define cpu_has_avx512cd (cp.feat.avx512cd && xcr0_mask(0xe6)) -#define cpu_has_sha cp.feat.sha -#define cpu_has_avx512bw (cp.feat.avx512bw && xcr0_mask(0xe6)) -#define cpu_has_avx512vl (cp.feat.avx512vl && xcr0_mask(0xe6)) -#define cpu_has_avx512_vbmi (cp.feat.avx512_vbmi && xcr0_mask(0xe6)) -#define cpu_has_avx512_vbmi2 (cp.feat.avx512_vbmi2 && xcr0_mask(0xe6)) -#define cpu_has_gfni cp.feat.gfni -#define cpu_has_vaes (cp.feat.vaes && xcr0_mask(6)) -#define cpu_has_vpclmulqdq (cp.feat.vpclmulqdq && xcr0_mask(6)) -#define cpu_has_avx512_vnni (cp.feat.avx512_vnni && xcr0_mask(0xe6)) -#define cpu_has_avx512_bitalg (cp.feat.avx512_bitalg && xcr0_mask(0xe6)) -#define cpu_has_avx512_vpopcntdq (cp.feat.avx512_vpopcntdq && xcr0_mask(0x= e6)) -#define cpu_has_movdiri cp.feat.movdiri -#define cpu_has_movdir64b cp.feat.movdir64b -#define cpu_has_avx512_vp2intersect (cp.feat.avx512_vp2intersect && xcr0_m= ask(0xe6)) -#define cpu_has_serialize cp.feat.serialize -#define cpu_has_avx512_fp16 (cp.feat.avx512_fp16 && xcr0_mask(0xe6)) -#define cpu_has_sha512 (cp.feat.sha512 && xcr0_mask(6)) -#define cpu_has_sm3 (cp.feat.sm3 && xcr0_mask(6)) -#define cpu_has_sm4 (cp.feat.sm4 && xcr0_mask(6)) -#define cpu_has_avx_vnni (cp.feat.avx_vnni && xcr0_mask(6)) -#define cpu_has_avx512_bf16 (cp.feat.avx512_bf16 && xcr0_mask(0xe6)) -#define cpu_has_avx_ifma (cp.feat.avx_ifma && xcr0_mask(6)) -#define cpu_has_avx_vnni_int8 (cp.feat.avx_vnni_int8 && xcr0_mask(6)) -#define cpu_has_avx_ne_convert (cp.feat.avx_ne_convert && xcr0_mask(6)) -#define cpu_has_avx_vnni_int16 (cp.feat.avx_vnni_int16 && xcr0_mask(6)) - -#define cpu_has_xgetbv1 (cpu_has_xsave && cp.xstate.xgetbv1) - -#define cpu_has_3dnow_ext cp.extd._3dnowext -#define cpu_has_sse4a cp.extd.sse4a -#define cpu_has_xop (cp.extd.xop && xcr0_mask(6)) -#define cpu_has_fma4 (cp.extd.fma4 && xcr0_mask(6)) -#define cpu_has_tbm cp.extd.tbm +#define cache_line_size() (cpu_policy.basic.clflush_size * 8) +#define cpu_has_fpu cpu_policy.basic.fpu +#define cpu_has_mmx cpu_policy.basic.mmx +#define cpu_has_fxsr cpu_policy.basic.fxsr +#define cpu_has_sse cpu_policy.basic.sse +#define cpu_has_sse2 cpu_policy.basic.sse2 +#define cpu_has_sse3 cpu_policy.basic.sse3 +#define cpu_has_pclmulqdq cpu_policy.basic.pclmulqdq +#define cpu_has_ssse3 cpu_policy.basic.ssse3 +#define cpu_has_fma (cpu_policy.basic.fma && xcr0_mask(6)) +#define cpu_has_sse4_1 cpu_policy.basic.sse4_1 +#define cpu_has_sse4_2 cpu_policy.basic.sse4_2 +#define cpu_has_popcnt cpu_policy.basic.popcnt +#define cpu_has_aesni cpu_policy.basic.aesni +#define cpu_has_avx (cpu_policy.basic.avx && xcr0_mask(6)) +#define cpu_has_f16c (cpu_policy.basic.f16c && xcr0_mask(6)) + +#define cpu_has_avx2 (cpu_policy.feat.avx2 && xcr0_mask(6)) +#define cpu_has_bmi1 cpu_policy.feat.bmi1 +#define cpu_has_bmi2 cpu_policy.feat.bmi2 +#define cpu_has_avx512f (cpu_policy.feat.avx512f && xcr0_mask(0xe6)) +#define cpu_has_avx512dq (cpu_policy.feat.avx512dq && xcr0_mask(0xe6)) +#define cpu_has_avx512_ifma (cpu_policy.feat.avx512_ifma && xcr0_mask(0xe6= )) +#define cpu_has_avx512cd (cpu_policy.feat.avx512cd && xcr0_mask(0xe6)) +#define cpu_has_sha cpu_policy.feat.sha +#define cpu_has_avx512bw (cpu_policy.feat.avx512bw && xcr0_mask(0xe6)) +#define cpu_has_avx512vl (cpu_policy.feat.avx512vl && xcr0_mask(0xe6)) +#define cpu_has_avx512_vbmi (cpu_policy.feat.avx512_vbmi && xcr0_mask(0xe6= )) +#define cpu_has_avx512_vbmi2 (cpu_policy.feat.avx512_vbmi2 && xcr0_mask(0x= e6)) +#define cpu_has_gfni cpu_policy.feat.gfni +#define cpu_has_vaes (cpu_policy.feat.vaes && xcr0_mask(6)) +#define cpu_has_vpclmulqdq (cpu_policy.feat.vpclmulqdq && xcr0_mask(6)) +#define cpu_has_avx512_vnni (cpu_policy.feat.avx512_vnni && xcr0_mask(0xe6= )) +#define cpu_has_avx512_bitalg (cpu_policy.feat.avx512_bitalg && xcr0_mask(= 0xe6)) +#define cpu_has_avx512_vpopcntdq (cpu_policy.feat.avx512_vpopcntdq && xcr0= _mask(0xe6)) +#define cpu_has_movdiri cpu_policy.feat.movdiri +#define cpu_has_movdir64b cpu_policy.feat.movdir64b +#define cpu_has_avx512_vp2intersect (cpu_policy.feat.avx512_vp2intersect &= & xcr0_mask(0xe6)) +#define cpu_has_serialize cpu_policy.feat.serialize +#define cpu_has_avx512_fp16 (cpu_policy.feat.avx512_fp16 && xcr0_mask(0xe6= )) +#define cpu_has_sha512 (cpu_policy.feat.sha512 && xcr0_mask(6)) +#define cpu_has_sm3 (cpu_policy.feat.sm3 && xcr0_mask(6)) +#define cpu_has_sm4 (cpu_policy.feat.sm4 && xcr0_mask(6)) +#define cpu_has_avx_vnni (cpu_policy.feat.avx_vnni && xcr0_mask(6)) +#define cpu_has_avx512_bf16 (cpu_policy.feat.avx512_bf16 && xcr0_mask(0xe6= )) +#define cpu_has_avx_ifma (cpu_policy.feat.avx_ifma && xcr0_mask(6)) +#define cpu_has_avx_vnni_int8 (cpu_policy.feat.avx_vnni_int8 && xcr0_mask(= 6)) +#define cpu_has_avx_ne_convert (cpu_policy.feat.avx_ne_convert && xcr0_mas= k(6)) +#define cpu_has_avx_vnni_int16 (cpu_policy.feat.avx_vnni_int16 && xcr0_mas= k(6)) + +#define cpu_has_xgetbv1 (cpu_has_xsave && cpu_policy.xstate.xgetbv1) + +#define cpu_has_3dnow_ext cpu_policy.extd._3dnowext +#define cpu_has_sse4a cpu_policy.extd.sse4a +#define cpu_has_xop (cpu_policy.extd.xop && xcr0_mask(6)) +#define cpu_has_fma4 (cpu_policy.extd.fma4 && xcr0_mask(6)) +#define cpu_has_tbm cpu_policy.extd.tbm =20 int emul_test_cpuid( uint32_t leaf, From nobody Thu Nov 21 21:14:12 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; 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Signed-off-by: Jan Beulich Acked-by: Andrew Cooper --- a/xen/arch/x86/x86_emulate/x86_emulate.c +++ b/xen/arch/x86/x86_emulate/x86_emulate.c @@ -1232,6 +1232,7 @@ x86_emulate( { /* Shadow copy of register state. Committed on successful emulation. */ struct cpu_user_regs _regs =3D *ctxt->regs; + const struct cpu_policy *cp =3D ctxt->cpu_policy; struct x86_emulate_state state; int rc; uint8_t b, d, *opc =3D NULL; @@ -3074,7 +3075,7 @@ x86_emulate( * in fact risking to make guest OSes vulnerable to the equivalent= of * XSA-7 (CVE-2012-0217). */ - generate_exception_if(ctxt->cpuid->x86_vendor =3D=3D X86_VENDOR_IN= TEL && + generate_exception_if(cp->x86_vendor =3D=3D X86_VENDOR_INTEL && op_bytes =3D=3D 8 && !is_canonical_address(_= regs.rcx), X86_EXC_GP, 0); #endif From nobody Thu Nov 21 21:14:12 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=quarantine dis=none) header.from=suse.com ARC-Seal: i=1; a=rsa-sha256; t=1723625575; cv=none; d=zohomail.com; s=zohoarc; b=WZsfEY4dVHVWfl7Iv3a9iQY40UiRGOTurFogRtXpPlgauA/LsgV4h9AyLu6Es9Oy9I6216eVn1AdRBmuRg7s1ShijOR6/lk3aosXz33W3qzv/6ntVeGKzAm18qXzXX7nXqqG3rLAp9rOZHFQWqq5Lja5/uy69EUe6lqgyUD2zhA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1723625575; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=azFeXUFYL/HqKu6YZuXLAM4CTGgPPTsfBxGQiHIqQA8=; b=ISVjnO8JBeDTTNvzv8G99b4UGBldx6KfGITUR5XfNpuEj9HhMdu/tRinA4Hlye9MG3Wf+QHnt7sCapbWubuSvxzlNUcYqyJ8JAz2UDSLNjvTjiwE+kwaKrB3WIZyLBH9V9XInNgYyMMBbIooyBBGQiVFVSNBA00gm9YEorsiugA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=quarantine dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1723625575061153.0477117960903; Wed, 14 Aug 2024 01:52:55 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.776937.1187135 (Exim 4.92) (envelope-from ) id 1se9kF-0005YS-PY; Wed, 14 Aug 2024 08:52:39 +0000 Received: by outflank-mailman (output) from mailman id 776937.1187135; Wed, 14 Aug 2024 08:52:39 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1se9kF-0005YL-Mh; Wed, 14 Aug 2024 08:52:39 +0000 Received: by outflank-mailman (input) for mailman id 776937; Wed, 14 Aug 2024 08:52:38 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1se9kD-0004KL-N1 for xen-devel@lists.xenproject.org; Wed, 14 Aug 2024 08:52:38 +0000 Received: from mail-ed1-x530.google.com (mail-ed1-x530.google.com [2a00:1450:4864:20::530]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 8d3c3a56-5a1a-11ef-a505-bb4a2ccca743; Wed, 14 Aug 2024 10:52:35 +0200 (CEST) Received: by mail-ed1-x530.google.com with SMTP id 4fb4d7f45d1cf-5a15692b6f6so7261844a12.0 for ; Wed, 14 Aug 2024 01:52:35 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. [37.24.206.209]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a80f411b110sm147393266b.109.2024.08.14.01.52.34 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 14 Aug 2024 01:52:34 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 8d3c3a56-5a1a-11ef-a505-bb4a2ccca743 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=google; t=1723625555; x=1724230355; darn=lists.xenproject.org; h=content-transfer-encoding:in-reply-to:autocrypt:content-language :references:cc:to:from:subject:user-agent:mime-version:date :message-id:from:to:cc:subject:date:message-id:reply-to; bh=azFeXUFYL/HqKu6YZuXLAM4CTGgPPTsfBxGQiHIqQA8=; b=XAC0ri+CFd3FEvrwZrQEyabERjsznJK8zTxPIhrtxX1oV/pYaMzj2/5+FPwwbCYkN3 fcj6hZR5uwIJgxRTTUWdKHoSauWW0FrQ9QGZiVRjWF4m69iR1Ew6Il23ZArR63UMF4av bOT8p16NGPzWw0zxtr8LF9swnHfpPTytfgVO2SNyjBruwI3lsw1BzsfeDBRXKLqpLNP2 lpvM/vhL2KAZpFW9nAi2hfMqIBtJ8V4Q00Piu3W20kmGRWrMRR693v9p9vEfGImEOV3F Cq95SJxvFevxYIm5PyuuVTtEvwo2yei9QycxM40jClirw7tpfDOQT9h5eFeeWZNnbCyL x7lQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1723625555; x=1724230355; h=content-transfer-encoding:in-reply-to:autocrypt:content-language :references:cc:to:from:subject:user-agent:mime-version:date :message-id:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=azFeXUFYL/HqKu6YZuXLAM4CTGgPPTsfBxGQiHIqQA8=; b=QOvg+lxGeArdu+kie7p3nc2eMGmEJnZqCvXp/0f/fN7vsrgRue6q37ZL34nZnLmlFh kH7gicHINSmOtmuDybDljsbWa2wl8T5W1OMwx6rvKVfytY99g7ya+1BhAVdqtmcX8VFC pXXqVtMrogugTfBIHKqz2NrCxMpnsxtFO+JubTIbpLFhnSAMr3H7Hv33wzx1Rz1esy4C yGPIUMAfBbIegRsM4ADDgJLsmhWhRtvHXQzqGgMOWUVE7YkylcVNeLZ6/V88sVyqCn0X IgQXa5mSO2dtkyLfBZexFtY6vF1qI2tQkSHLsOCv6+ORlD5biOUuDs5zRRAt2iJI9WY9 Kzsw== X-Gm-Message-State: AOJu0YxU4ZjaMIzNYLpDe56+AJ0E37dXVKbVq0+QsL55E1UlYnh62JKW +RChZjDLmL0A7zj3k5lEwck8h6fBizuEzKDCfYpQb/jwzOdpBIpcammCtDLZlpKkiY5/A2S0afs = X-Google-Smtp-Source: AGHT+IGvLi/8j1/GY+IuVDvvHlw9TaDIm56vbvIOe570XLGqyh0Iso4c/B/ccRFhfnnDqXOnTifAXA== X-Received: by 2002:a17:907:3205:b0:a7a:847d:63b7 with SMTP id a640c23a62f3a-a83670700f1mr137910766b.59.1723625554895; Wed, 14 Aug 2024 01:52:34 -0700 (PDT) Message-ID: <59e1de8d-af41-416c-9dbb-555539a20ff0@suse.com> Date: Wed, 14 Aug 2024 10:52:33 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH v2 4/9] x86emul: support AVX10.1 From: Jan Beulich To: "xen-devel@lists.xenproject.org" Cc: Andrew Cooper , Wei Liu , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= References: Content-Language: en-US Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @suse.com) X-ZM-MESSAGEID: 1723625575819116600 Content-Type: text/plain; charset="utf-8" This requires relaxing various pre-existing AVX512* checks, as AVX10.1 covers all AVX512* except PF, ER, 4FMAPS, 4VNNIW (support for all of which was removed meanwhile anyway), and VP2INTERSECT. Yet potentially with only less than 512-bit vector width, while otoh guaranteeing more narrow widths being available when wider are (i.e. unlike AVX512VL being an add-on feature on top of AVX512F). Note that visa_check(), replacing host_and_vcpu_must_have() uses, checks only the guest capability: We wouldn't expose AVX512* (nor AVX10) without the hardware supporting it. Similarly in vlen_check() the original host_and_vcpu_must_have() is reduced to the equivalent of just vcpu_must_have(). This also simplifies (resulting) code in the test and fuzzing harnesses, as there the XCR0 checks that are part of cpu_has_avx512* are only needed in local code, not in the emulator itself (where respective checking occurs elsewhere anyway, utilizing emul_test_read_xcr()). While in most cases the changes to x86_emulate() are entirely mechanical, for opmask insns earlier unconditional AVX512F checks are converted into "else" clauses to existing if/else-if ones. To be certain that no uses remain, also drop respective cpu_has_avx512* (except in the test harness) and vcpu_has_avx512*(). Signed-off-by: Jan Beulich --- Probably avx512_vlen_check() should have the avx512_ prefix dropped, now that it also covers AVX10. But if so that wants to be either a prereq or a follow-on patch. visa_check() won't cover AVX10.2 and higher, but probably we will want independent checking logic for that anyway. Spec version 2 still leaves unclear what the xstate components are which would need enabling for AVX10/256. x86emul_get_fpu() is therefore untouched for now. Since it'll be reducing code size, we may want to further convert host_and_vcpu_must_have() to just vcpu_must_have() where appropriate (should be [almost?] everywhere). --- v2: Drop use of vsz128 field. Re-base, in particular over dropping of Xeon Phi support. --- a/xen/arch/x86/include/asm/cpufeature.h +++ b/xen/arch/x86/include/asm/cpufeature.h @@ -133,29 +133,18 @@ static inline bool boot_cpu_has(unsigned #define cpu_has_pqe boot_cpu_has(X86_FEATURE_PQE) #define cpu_has_fpu_sel (!boot_cpu_has(X86_FEATURE_NO_FPU_SEL)) #define cpu_has_mpx boot_cpu_has(X86_FEATURE_MPX) -#define cpu_has_avx512f boot_cpu_has(X86_FEATURE_AVX512F) -#define cpu_has_avx512dq boot_cpu_has(X86_FEATURE_AVX512DQ) #define cpu_has_rdseed boot_cpu_has(X86_FEATURE_RDSEED) #define cpu_has_smap boot_cpu_has(X86_FEATURE_SMAP) -#define cpu_has_avx512_ifma boot_cpu_has(X86_FEATURE_AVX512_IFMA) #define cpu_has_clflushopt boot_cpu_has(X86_FEATURE_CLFLUSHOPT) #define cpu_has_clwb boot_cpu_has(X86_FEATURE_CLWB) -#define cpu_has_avx512cd boot_cpu_has(X86_FEATURE_AVX512CD) #define cpu_has_proc_trace boot_cpu_has(X86_FEATURE_PROC_TRACE) #define cpu_has_sha boot_cpu_has(X86_FEATURE_SHA) -#define cpu_has_avx512bw boot_cpu_has(X86_FEATURE_AVX512BW) -#define cpu_has_avx512vl boot_cpu_has(X86_FEATURE_AVX512VL) =20 /* CPUID level 0x00000007:0.ecx */ -#define cpu_has_avx512_vbmi boot_cpu_has(X86_FEATURE_AVX512_VBMI) #define cpu_has_pku boot_cpu_has(X86_FEATURE_PKU) -#define cpu_has_avx512_vbmi2 boot_cpu_has(X86_FEATURE_AVX512_VBMI2) #define cpu_has_gfni boot_cpu_has(X86_FEATURE_GFNI) #define cpu_has_vaes boot_cpu_has(X86_FEATURE_VAES) #define cpu_has_vpclmulqdq boot_cpu_has(X86_FEATURE_VPCLMULQDQ) -#define cpu_has_avx512_vnni boot_cpu_has(X86_FEATURE_AVX512_VNNI) -#define cpu_has_avx512_bitalg boot_cpu_has(X86_FEATURE_AVX512_BITALG) -#define cpu_has_avx512_vpopcntdq boot_cpu_has(X86_FEATURE_AVX512_VPOPCNTDQ) #define cpu_has_rdpid boot_cpu_has(X86_FEATURE_RDPID) #define cpu_has_movdiri boot_cpu_has(X86_FEATURE_MOVDIRI) #define cpu_has_movdir64b boot_cpu_has(X86_FEATURE_MOVDIR64B) @@ -180,7 +169,6 @@ static inline bool boot_cpu_has(unsigned #define cpu_has_tsx_force_abort boot_cpu_has(X86_FEATURE_TSX_FORCE_ABORT) #define cpu_has_serialize boot_cpu_has(X86_FEATURE_SERIALIZE) #define cpu_has_hybrid boot_cpu_has(X86_FEATURE_HYBRID) -#define cpu_has_avx512_fp16 boot_cpu_has(X86_FEATURE_AVX512_FP16) #define cpu_has_arch_caps boot_cpu_has(X86_FEATURE_ARCH_CAPS) =20 /* CPUID level 0x00000007:1.eax */ @@ -188,7 +176,6 @@ static inline bool boot_cpu_has(unsigned #define cpu_has_sm3 boot_cpu_has(X86_FEATURE_SM3) #define cpu_has_sm4 boot_cpu_has(X86_FEATURE_SM4) #define cpu_has_avx_vnni boot_cpu_has(X86_FEATURE_AVX_VNNI) -#define cpu_has_avx512_bf16 boot_cpu_has(X86_FEATURE_AVX512_BF16) #define cpu_has_avx_ifma boot_cpu_has(X86_FEATURE_AVX_IFMA) =20 /* CPUID level 0x00000007:1.edx */ --- a/xen/arch/x86/x86_emulate/private.h +++ b/xen/arch/x86/x86_emulate/private.h @@ -556,26 +556,15 @@ amd_like(const struct x86_emulate_ctxt * #define vcpu_has_invpcid() (ctxt->cpuid->feat.invpcid) #define vcpu_has_rtm() (ctxt->cpuid->feat.rtm) #define vcpu_has_mpx() (ctxt->cpuid->feat.mpx) -#define vcpu_has_avx512f() (ctxt->cpuid->feat.avx512f) -#define vcpu_has_avx512dq() (ctxt->cpuid->feat.avx512dq) #define vcpu_has_rdseed() (ctxt->cpuid->feat.rdseed) #define vcpu_has_adx() (ctxt->cpuid->feat.adx) #define vcpu_has_smap() (ctxt->cpuid->feat.smap) -#define vcpu_has_avx512_ifma() (ctxt->cpuid->feat.avx512_ifma) #define vcpu_has_clflushopt() (ctxt->cpuid->feat.clflushopt) #define vcpu_has_clwb() (ctxt->cpuid->feat.clwb) -#define vcpu_has_avx512cd() (ctxt->cpuid->feat.avx512cd) #define vcpu_has_sha() (ctxt->cpuid->feat.sha) -#define vcpu_has_avx512bw() (ctxt->cpuid->feat.avx512bw) -#define vcpu_has_avx512vl() (ctxt->cpuid->feat.avx512vl) -#define vcpu_has_avx512_vbmi() (ctxt->cpuid->feat.avx512_vbmi) -#define vcpu_has_avx512_vbmi2() (ctxt->cpuid->feat.avx512_vbmi2) #define vcpu_has_gfni() (ctxt->cpuid->feat.gfni) #define vcpu_has_vaes() (ctxt->cpuid->feat.vaes) #define vcpu_has_vpclmulqdq() (ctxt->cpuid->feat.vpclmulqdq) -#define vcpu_has_avx512_vnni() (ctxt->cpuid->feat.avx512_vnni) -#define vcpu_has_avx512_bitalg() (ctxt->cpuid->feat.avx512_bitalg) -#define vcpu_has_avx512_vpopcntdq() (ctxt->cpuid->feat.avx512_vpopcntdq) #define vcpu_has_rdpid() (ctxt->cpuid->feat.rdpid) #define vcpu_has_movdiri() (ctxt->cpuid->feat.movdiri) #define vcpu_has_movdir64b() (ctxt->cpuid->feat.movdir64b) @@ -583,12 +572,10 @@ amd_like(const struct x86_emulate_ctxt * #define vcpu_has_avx512_vp2intersect() (ctxt->cpuid->feat.avx512_vp2inters= ect) #define vcpu_has_serialize() (ctxt->cpuid->feat.serialize) #define vcpu_has_tsxldtrk() (ctxt->cpuid->feat.tsxldtrk) -#define vcpu_has_avx512_fp16() (ctxt->cpuid->feat.avx512_fp16) #define vcpu_has_sha512() (ctxt->cpuid->feat.sha512) #define vcpu_has_sm3() (ctxt->cpuid->feat.sm3) #define vcpu_has_sm4() (ctxt->cpuid->feat.sm4) #define vcpu_has_avx_vnni() (ctxt->cpuid->feat.avx_vnni) -#define vcpu_has_avx512_bf16() (ctxt->cpuid->feat.avx512_bf16) #define vcpu_has_wrmsrns() (ctxt->cpuid->feat.wrmsrns) #define vcpu_has_avx_ifma() (ctxt->cpuid->feat.avx_ifma) #define vcpu_has_avx_vnni_int8() (ctxt->cpuid->feat.avx_vnni_int8) --- a/xen/arch/x86/x86_emulate/x86_emulate.c +++ b/xen/arch/x86/x86_emulate/x86_emulate.c @@ -1125,19 +1125,40 @@ static unsigned long *decode_vex_gpr( return decode_gpr(regs, ~vex_reg & (mode_64bit() ? 0xf : 7)); } =20 -#define avx512_vlen_check(lig) do { \ - switch ( evex.lr ) \ - { \ - default: \ - generate_exception(X86_EXC_UD); \ - case 2: \ - break; \ - case 0: case 1: \ - if ( !(lig) ) \ - host_and_vcpu_must_have(avx512vl); \ - break; \ - } \ -} while ( false ) +#define visa_check(subfeat) \ + generate_exception_if(!cp->feat.avx512 ## subfeat && !cp->feat.avx= 10, \ + X86_EXC_UD) + +static bool _vlen_check( + const struct x86_emulate_state *s, + const struct cpu_policy *cp, + bool lig) +{ + if ( s->evex.lr > 2 ) + return false; + + if ( lig ) + return true; + + if ( cp->feat.avx10 ) + switch ( s->evex.lr ) + { + case 0: + case 1: + if ( cp->avx10.vsz256 ) + return true; + /* fall through */ + case 2: + if ( cp->avx10.vsz512 ) + return true; + break; + } + + return s->evex.lr =3D=3D 2 || cp->feat.avx512vl; +} + +#define avx512_vlen_check(lig) \ + generate_exception_if(!_vlen_check(state, cp, lig), X86_EXC_UD) =20 static bool is_branch_step(struct x86_emulate_ctxt *ctxt, const struct x86_emulate_ops *ops) @@ -1369,7 +1390,9 @@ x86_emulate( /* KMOV{W,Q} %k, (%rax) */ stb[0] =3D 0xc4; stb[1] =3D 0xe1; - stb[2] =3D cpu_has_avx512bw ? 0xf8 : 0x78; + stb[2] =3D cp->feat.avx512bw || cp->feat.avx10 + ? 0xf8 /* L0.NP.W1 - kmovq */ + : 0x78 /* L0.NP.W0 - kmovw */; stb[3] =3D 0x91; stb[4] =3D evex.opmsk << 3; insn_bytes =3D 5; @@ -3365,7 +3388,7 @@ x86_emulate( (ea.type !=3D OP_REG && evex.brs && (evex.pfx & VEX_PREFIX_SCALAR_MASK))), X86_EXC_UD); - host_and_vcpu_must_have(avx512f); + visa_check(f); if ( ea.type !=3D OP_REG || !evex.brs ) avx512_vlen_check(evex.pfx & VEX_PREFIX_SCALAR_MASK); simd_zmm: @@ -3421,7 +3444,7 @@ x86_emulate( generate_exception_if((evex.lr || evex.opmsk || evex.brs || evex.w !=3D (evex.pfx & VEX_PREFIX_DOUBLE_M= ASK)), X86_EXC_UD); - host_and_vcpu_must_have(avx512f); + visa_check(f); if ( (d & DstMask) !=3D DstMem ) d &=3D ~TwoOp; op_bytes =3D 8; @@ -3448,7 +3471,7 @@ x86_emulate( generate_exception_if((evex.brs || evex.w !=3D (evex.pfx & VEX_PREFIX_DOUBLE_M= ASK)), X86_EXC_UD); - host_and_vcpu_must_have(avx512f); + visa_check(f); avx512_vlen_check(false); d |=3D TwoOp; op_bytes =3D !(evex.pfx & VEX_PREFIX_DOUBLE_MASK) || evex.lr @@ -3485,7 +3508,7 @@ x86_emulate( case X86EMUL_OPC_EVEX_66(0x0f38, 0x64): /* vpblendm{d,q} [xyz]mm/mem,[= xyz]mm,[xyz]mm{k} */ case X86EMUL_OPC_EVEX_66(0x0f38, 0x65): /* vblendmp{s,d} [xyz]mm/mem,[= xyz]mm,[xyz]mm{k} */ avx512f_no_sae: - host_and_vcpu_must_have(avx512f); + visa_check(f); generate_exception_if(ea.type !=3D OP_MEM && evex.brs, X86_EXC_UD); avx512_vlen_check(false); goto simd_zmm; @@ -3565,13 +3588,13 @@ x86_emulate( =20 case X86EMUL_OPC_EVEX_F3(5, 0x2a): /* vcvtsi2sh r/m,xmm,xmm */ case X86EMUL_OPC_EVEX_F3(5, 0x7b): /* vcvtusi2sh r/m,xmm,xmm */ - host_and_vcpu_must_have(avx512_fp16); + visa_check(_fp16); /* fall through */ CASE_SIMD_SCALAR_FP(_EVEX, 0x0f, 0x2a): /* vcvtsi2s{s,d} r/m,xmm,xmm */ CASE_SIMD_SCALAR_FP(_EVEX, 0x0f, 0x7b): /* vcvtusi2s{s,d} r/m,xmm,xmm = */ generate_exception_if(evex.opmsk || (ea.type !=3D OP_REG && evex.b= rs), X86_EXC_UD); - host_and_vcpu_must_have(avx512f); + visa_check(f); if ( !evex.brs ) avx512_vlen_check(true); get_fpu(X86EMUL_FPU_zmm); @@ -3681,7 +3704,7 @@ x86_emulate( case X86EMUL_OPC_EVEX_F3(5, 0x2d): /* vcvtsh2si xmm/mem,reg */ case X86EMUL_OPC_EVEX_F3(5, 0x78): /* vcvttsh2usi xmm/mem,reg */ case X86EMUL_OPC_EVEX_F3(5, 0x79): /* vcvtsh2usi xmm/mem,reg */ - host_and_vcpu_must_have(avx512_fp16); + visa_check(_fp16); /* fall through */ CASE_SIMD_SCALAR_FP(_EVEX, 0x0f, 0x2c): /* vcvtts{s,d}2si xmm/mem,reg = */ CASE_SIMD_SCALAR_FP(_EVEX, 0x0f, 0x2d): /* vcvts{s,d}2si xmm/mem,reg */ @@ -3691,7 +3714,7 @@ x86_emulate( evex.opmsk || (ea.type !=3D OP_REG && evex.brs)), X86_EXC_UD); - host_and_vcpu_must_have(avx512f); + visa_check(f); if ( !evex.brs ) avx512_vlen_check(true); get_fpu(X86EMUL_FPU_zmm); @@ -3757,7 +3780,7 @@ x86_emulate( =20 case X86EMUL_OPC_EVEX(5, 0x2e): /* vucomish xmm/m16,xmm */ case X86EMUL_OPC_EVEX(5, 0x2f): /* vcomish xmm/m16,xmm */ - host_and_vcpu_must_have(avx512_fp16); + visa_check(_fp16); generate_exception_if(evex.w, X86_EXC_UD); /* fall through */ CASE_SIMD_PACKED_FP(_EVEX, 0x0f, 0x2e): /* vucomis{s,d} xmm/mem,xmm */ @@ -3766,7 +3789,7 @@ x86_emulate( (ea.type !=3D OP_REG && evex.brs) || evex.w !=3D evex.pfx), X86_EXC_UD); - host_and_vcpu_must_have(avx512f); + visa_check(f); if ( !evex.brs ) avx512_vlen_check(true); get_fpu(X86EMUL_FPU_zmm); @@ -3910,7 +3933,7 @@ x86_emulate( =20 case X86EMUL_OPC_VEX(0x0f, 0x4a): /* kadd{w,q} k,k,k */ if ( !vex.w ) - host_and_vcpu_must_have(avx512dq); + visa_check(dq); /* fall through */ case X86EMUL_OPC_VEX(0x0f, 0x41): /* kand{w,q} k,k,k */ case X86EMUL_OPC_VEX_66(0x0f, 0x41): /* kand{b,d} k,k,k */ @@ -3926,11 +3949,12 @@ x86_emulate( generate_exception_if(!vex.l, X86_EXC_UD); opmask_basic: if ( vex.w ) - host_and_vcpu_must_have(avx512bw); + visa_check(bw); else if ( vex.pfx ) - host_and_vcpu_must_have(avx512dq); + visa_check(dq); + else + visa_check(f); opmask_common: - host_and_vcpu_must_have(avx512f); generate_exception_if(!vex.r || (mode_64bit() && !(vex.reg & 8)) || ea.type !=3D OP_REG, X86_EXC_UD); =20 @@ -3953,13 +3977,14 @@ x86_emulate( generate_exception_if(vex.l || vex.reg !=3D 0xf, X86_EXC_UD); goto opmask_basic; =20 - case X86EMUL_OPC_VEX(0x0f, 0x4b): /* kunpck{w,d}{d,q} k,k,k */ + case X86EMUL_OPC_VEX(0x0f, 0x4b): /* kunpck{wd,dq} k,k,k */ generate_exception_if(!vex.l, X86_EXC_UD); - host_and_vcpu_must_have(avx512bw); + visa_check(bw); goto opmask_common; =20 case X86EMUL_OPC_VEX_66(0x0f, 0x4b): /* kunpckbw k,k,k */ generate_exception_if(!vex.l || vex.w, X86_EXC_UD); + visa_check(f); goto opmask_common; =20 #endif /* X86EMUL_NO_SIMD */ @@ -4027,7 +4052,7 @@ x86_emulate( generate_exception_if((evex.w !=3D (evex.pfx & VEX_PREFIX_DOUBLE_M= ASK) || (ea.type !=3D OP_MEM && evex.brs)), X86_EXC_UD); - host_and_vcpu_must_have(avx512dq); + visa_check(dq); avx512_vlen_check(false); goto simd_zmm; =20 @@ -4066,12 +4091,12 @@ x86_emulate( case X86EMUL_OPC_EVEX_F2(0x0f, 0x7a): /* vcvtudq2ps [xyz]mm/mem,[xyz]m= m{k} */ /* vcvtuqq2ps [xyz]mm/mem,{x,y}m= m{k} */ if ( evex.w ) - host_and_vcpu_must_have(avx512dq); + visa_check(dq); else { case X86EMUL_OPC_EVEX(0x0f, 0x78): /* vcvttp{s,d}2udq [xyz]mm/mem,[= xyz]mm{k} */ case X86EMUL_OPC_EVEX(0x0f, 0x79): /* vcvtp{s,d}2udq [xyz]mm/mem,[x= yz]mm{k} */ - host_and_vcpu_must_have(avx512f); + visa_check(f); } if ( ea.type !=3D OP_REG || !evex.brs ) avx512_vlen_check(false); @@ -4288,7 +4313,7 @@ x86_emulate( case X86EMUL_OPC_EVEX_66(0x0f38, 0x0b): /* vpmulhrsw [xyz]mm/mem,[xyz]= mm,[xyz]mm{k} */ case X86EMUL_OPC_EVEX_66(0x0f38, 0x1c): /* vpabsb [xyz]mm/mem,[xyz]mm{= k} */ case X86EMUL_OPC_EVEX_66(0x0f38, 0x1d): /* vpabsw [xyz]mm/mem,[xyz]mm{= k} */ - host_and_vcpu_must_have(avx512bw); + visa_check(bw); generate_exception_if(evex.brs, X86_EXC_UD); elem_bytes =3D 1 << (b & 1); goto avx512f_no_sae; @@ -4320,7 +4345,7 @@ x86_emulate( generate_exception_if(b !=3D 0x27 && evex.w !=3D (b & 1), X86_= EXC_UD); goto avx512f_no_sae; } - host_and_vcpu_must_have(avx512bw); + visa_check(bw); generate_exception_if(evex.brs, X86_EXC_UD); elem_bytes =3D 1 << (ext =3D=3D ext_0f ? b & 1 : evex.w); avx512_vlen_check(false); @@ -4393,7 +4418,7 @@ x86_emulate( dst.bytes =3D 2; /* fall through */ case X86EMUL_OPC_EVEX_66(5, 0x6e): /* vmovw r/m16,xmm */ - host_and_vcpu_must_have(avx512_fp16); + visa_check(_fp16); generate_exception_if(evex.w, X86_EXC_UD); /* fall through */ case X86EMUL_OPC_EVEX_66(0x0f, 0x6e): /* vmov{d,q} r/m,xmm */ @@ -4401,7 +4426,7 @@ x86_emulate( generate_exception_if((evex.lr || evex.opmsk || evex.brs || evex.reg !=3D 0xf || !evex.RX), X86_EXC_UD); - host_and_vcpu_must_have(avx512f); + visa_check(f); get_fpu(X86EMUL_FPU_zmm); =20 opc =3D init_evex(stub); @@ -4459,7 +4484,7 @@ x86_emulate( =20 case X86EMUL_OPC_EVEX_F2(0x0f, 0x6f): /* vmovdqu{8,16} [xyz]mm/mem,[xy= z]mm{k} */ case X86EMUL_OPC_EVEX_F2(0x0f, 0x7f): /* vmovdqu{8,16} [xyz]mm,[xyz]mm= /mem{k} */ - host_and_vcpu_must_have(avx512bw); + visa_check(bw); elem_bytes =3D 1 << evex.w; goto vmovdqa; =20 @@ -4552,7 +4577,7 @@ x86_emulate( generate_exception_if(evex.w, X86_EXC_UD); else { - host_and_vcpu_must_have(avx512bw); + visa_check(bw); generate_exception_if(evex.brs, X86_EXC_UD); } d =3D (d & ~SrcMask) | SrcMem | TwoOp; @@ -4800,7 +4825,7 @@ x86_emulate( case X86EMUL_OPC_EVEX_F3(0x0f, 0xe6): /* vcvtdq2pd {x,y}mm/mem,[xyz]= mm{k} */ /* vcvtqq2pd [xyz]mm/mem,[xyz]= mm{k} */ if ( evex.pfx !=3D vex_f3 ) - host_and_vcpu_must_have(avx512f); + visa_check(f); else if ( evex.w ) { case X86EMUL_OPC_EVEX_66(0x0f, 0x78): /* vcvttps2uqq {x,y}mm/mem,[xy= z]mm{k} */ @@ -4811,11 +4836,11 @@ x86_emulate( /* vcvttpd2qq [xyz]mm/mem,[xyz= ]mm{k} */ case X86EMUL_OPC_EVEX_66(0x0f, 0x7b): /* vcvtps2qq {x,y}mm/mem,[xyz]= mm{k} */ /* vcvtpd2qq [xyz]mm/mem,[xyz]= mm{k} */ - host_and_vcpu_must_have(avx512dq); + visa_check(dq); } else { - host_and_vcpu_must_have(avx512f); + visa_check(f); generate_exception_if(ea.type !=3D OP_MEM && evex.brs, X86_EXC= _UD); } if ( ea.type !=3D OP_REG || !evex.brs ) @@ -4853,7 +4878,7 @@ x86_emulate( case X86EMUL_OPC_EVEX_66(0x0f, 0xd6): /* vmovq xmm,xmm/m64 */ generate_exception_if(evex.lr || !evex.w || evex.opmsk || evex.brs, X86_EXC_UD); - host_and_vcpu_must_have(avx512f); + visa_check(f); d |=3D TwoOp; op_bytes =3D 8; goto simd_zmm; @@ -4879,19 +4904,21 @@ x86_emulate( case X86EMUL_OPC_VEX(0x0f, 0x90): /* kmov{w,q} k/mem,k */ case X86EMUL_OPC_VEX_66(0x0f, 0x90): /* kmov{b,d} k/mem,k */ generate_exception_if(vex.l || !vex.r, X86_EXC_UD); - host_and_vcpu_must_have(avx512f); if ( vex.w ) { - host_and_vcpu_must_have(avx512bw); + visa_check(bw); op_bytes =3D 4 << !vex.pfx; } else if ( vex.pfx ) { - host_and_vcpu_must_have(avx512dq); + visa_check(dq); op_bytes =3D 1; } else + { + visa_check(f); op_bytes =3D 2; + } =20 get_fpu(X86EMUL_FPU_opmask); =20 @@ -4913,14 +4940,15 @@ x86_emulate( generate_exception_if(vex.l || !vex.r || vex.reg !=3D 0xf || ea.type !=3D OP_REG, X86_EXC_UD); =20 - host_and_vcpu_must_have(avx512f); if ( vex.pfx =3D=3D vex_f2 ) - host_and_vcpu_must_have(avx512bw); + visa_check(bw); else { generate_exception_if(vex.w, X86_EXC_UD); if ( vex.pfx ) - host_and_vcpu_must_have(avx512dq); + visa_check(dq); + else + visa_check(f); } =20 get_fpu(X86EMUL_FPU_opmask); @@ -4952,10 +4980,9 @@ x86_emulate( dst =3D ea; dst.reg =3D decode_gpr(&_regs, modrm_reg); =20 - host_and_vcpu_must_have(avx512f); if ( vex.pfx =3D=3D vex_f2 ) { - host_and_vcpu_must_have(avx512bw); + visa_check(bw); dst.bytes =3D 4 << (mode_64bit() && vex.w); } else @@ -4963,7 +4990,9 @@ x86_emulate( generate_exception_if(vex.w, X86_EXC_UD); dst.bytes =3D 4; if ( vex.pfx ) - host_and_vcpu_must_have(avx512dq); + visa_check(dq); + else + visa_check(f); } =20 get_fpu(X86EMUL_FPU_opmask); @@ -4985,20 +5014,18 @@ x86_emulate( ASSERT(!state->simd_size); break; =20 - case X86EMUL_OPC_VEX(0x0f, 0x99): /* ktest{w,q} k,k */ - if ( !vex.w ) - host_and_vcpu_must_have(avx512dq); - /* fall through */ case X86EMUL_OPC_VEX(0x0f, 0x98): /* kortest{w,q} k,k */ case X86EMUL_OPC_VEX_66(0x0f, 0x98): /* kortest{b,d} k,k */ + case X86EMUL_OPC_VEX(0x0f, 0x99): /* ktest{w,q} k,k */ case X86EMUL_OPC_VEX_66(0x0f, 0x99): /* ktest{b,d} k,k */ generate_exception_if(vex.l || !vex.r || vex.reg !=3D 0xf || ea.type !=3D OP_REG, X86_EXC_UD); - host_and_vcpu_must_have(avx512f); if ( vex.w ) - host_and_vcpu_must_have(avx512bw); - else if ( vex.pfx ) - host_and_vcpu_must_have(avx512dq); + visa_check(bw); + else if ( vex.pfx || (b & 1) ) + visa_check(dq); + else + visa_check(f); =20 get_fpu(X86EMUL_FPU_opmask); =20 @@ -5336,7 +5363,7 @@ x86_emulate( (evex.pfx & VEX_PREFIX_SCALAR_MASK)) || !evex.r || !evex.R || evex.z), X86_EXC_UD); - host_and_vcpu_must_have(avx512f); + visa_check(f); if ( ea.type !=3D OP_REG || !evex.brs ) avx512_vlen_check(evex.pfx & VEX_PREFIX_SCALAR_MASK); simd_imm8_zmm: @@ -5380,9 +5407,9 @@ x86_emulate( case X86EMUL_OPC_EVEX_66(0x0f3a, 0x22): /* vpinsr{d,q} $imm8,r/m,xmm,x= mm */ generate_exception_if(evex.lr || evex.opmsk || evex.brs, X86_EXC_U= D); if ( b & 2 ) - host_and_vcpu_must_have(avx512dq); + visa_check(dq); else - host_and_vcpu_must_have(avx512bw); + visa_check(bw); if ( !mode_64bit() ) evex.w =3D 0; memcpy(mmvalp, &src.val, src.bytes); @@ -5419,7 +5446,7 @@ x86_emulate( /* fall through */ case X86EMUL_OPC_EVEX_66(0x0f3a, 0x25): /* vpternlog{d,q} $imm8,[xyz]m= m/mem,[xyz]mm,[xyz]mm{k} */ avx512f_imm8_no_sae: - host_and_vcpu_must_have(avx512f); + visa_check(f); generate_exception_if(ea.type !=3D OP_MEM && evex.brs, X86_EXC_UD); avx512_vlen_check(false); goto simd_imm8_zmm; @@ -5518,7 +5545,7 @@ x86_emulate( case X86EMUL_OPC_EVEX_66(0x0f, 0xe4): /* vpmulhuw [xyz]mm/mem,[xyz]mm,= [xyz]mm{k} */ case X86EMUL_OPC_EVEX_66(0x0f, 0xea): /* vpminsw [xyz]mm/mem,[xyz]mm,[= xyz]mm{k} */ case X86EMUL_OPC_EVEX_66(0x0f, 0xee): /* vpmaxsw [xyz]mm/mem,[xyz]mm,[= xyz]mm{k} */ - host_and_vcpu_must_have(avx512bw); + visa_check(bw); generate_exception_if(evex.brs, X86_EXC_UD); elem_bytes =3D b & 0x10 ? 1 : 2; goto avx512f_no_sae; @@ -5743,7 +5770,7 @@ x86_emulate( case X86EMUL_OPC_EVEX_66(0x0f38, 0x10): /* vpsrlvw [xyz]mm/mem,[xyz]mm= ,[xyz]mm{k} */ case X86EMUL_OPC_EVEX_66(0x0f38, 0x11): /* vpsravw [xyz]mm/mem,[xyz]mm= ,[xyz]mm{k} */ case X86EMUL_OPC_EVEX_66(0x0f38, 0x12): /* vpsllvw [xyz]mm/mem,[xyz]mm= ,[xyz]mm{k} */ - host_and_vcpu_must_have(avx512bw); + visa_check(bw); generate_exception_if(!evex.w || evex.brs, X86_EXC_UD); elem_bytes =3D 2; goto avx512f_no_sae; @@ -5753,7 +5780,7 @@ x86_emulate( case X86EMUL_OPC_EVEX_F3(0x0f38, 0x20): /* vpmovswb [xyz]mm,{x,y}mm/me= m{k} */ case X86EMUL_OPC_EVEX_66(0x0f38, 0x30): /* vpmovzxbw {x,y}mm/mem,[xyz]= mm{k} */ case X86EMUL_OPC_EVEX_F3(0x0f38, 0x30): /* vpmovwb [xyz]mm,{x,y}mm/mem= {k} */ - host_and_vcpu_must_have(avx512bw); + visa_check(bw); if ( evex.pfx !=3D vex_f3 ) { case X86EMUL_OPC_EVEX_66(0x0f38, 0x21): /* vpmovsxbd xmm/mem,[xyz]mm{k= } */ @@ -5801,7 +5828,7 @@ x86_emulate( =20 case X86EMUL_OPC_EVEX_66(0x0f38, 0x13): /* vcvtph2ps {x,y}mm/mem,[xyz]= mm{k} */ generate_exception_if(evex.w || (ea.type !=3D OP_REG && evex.brs),= X86_EXC_UD); - host_and_vcpu_must_have(avx512f); + visa_check(f); if ( !evex.brs ) avx512_vlen_check(false); op_bytes =3D 8 << evex.lr; @@ -5855,7 +5882,7 @@ x86_emulate( op_bytes =3D 8; generate_exception_if(evex.brs, X86_EXC_UD); if ( !evex.w ) - host_and_vcpu_must_have(avx512dq); + visa_check(dq); goto avx512_broadcast; =20 case X86EMUL_OPC_EVEX_66(0x0f38, 0x1a): /* vbroadcastf32x4 m128,{y,z}m= m{k} */ @@ -5865,7 +5892,7 @@ x86_emulate( generate_exception_if(ea.type !=3D OP_MEM || !evex.lr || evex.brs, X86_EXC_UD); if ( evex.w ) - host_and_vcpu_must_have(avx512dq); + visa_check(dq); goto avx512_broadcast; =20 case X86EMUL_OPC_VEX_66(0x0f38, 0x20): /* vpmovsxbw xmm/mem,{x,y}mm */ @@ -5890,9 +5917,9 @@ x86_emulate( case X86EMUL_OPC_EVEX_F3(0x0f38, 0x28): /* vpmovm2{b,w} k,[xyz]mm */ case X86EMUL_OPC_EVEX_F3(0x0f38, 0x38): /* vpmovm2{d,q} k,[xyz]mm */ if ( b & 0x10 ) - host_and_vcpu_must_have(avx512dq); + visa_check(dq); else - host_and_vcpu_must_have(avx512bw); + visa_check(bw); generate_exception_if(evex.opmsk || ea.type !=3D OP_REG, X86_EXC_U= D); d |=3D TwoOp; op_bytes =3D 16 << evex.lr; @@ -5934,7 +5961,7 @@ x86_emulate( fault_suppression =3D false; /* fall through */ case X86EMUL_OPC_EVEX_66(0x0f38, 0x44): /* vplzcnt{d,q} [xyz]mm/mem,[x= yz]mm{k} */ - host_and_vcpu_must_have(avx512cd); + visa_check(cd); goto avx512f_no_sae; =20 case X86EMUL_OPC_VEX_66(0x0f38, 0x2c): /* vmaskmovps mem,{x,y}mm,{x,y}= mm */ @@ -6010,7 +6037,7 @@ x86_emulate( case X86EMUL_OPC_EVEX_66(0x0f38, 0xba): /* vfmsub231p{s,d} [xyz]mm/mem= ,[xyz]mm,[xyz]mm{k} */ case X86EMUL_OPC_EVEX_66(0x0f38, 0xbc): /* vfnmadd231p{s,d} [xyz]mm/me= m,[xyz]mm,[xyz]mm{k} */ case X86EMUL_OPC_EVEX_66(0x0f38, 0xbe): /* vfnmsub231p{s,d} [xyz]mm/me= m,[xyz]mm,[xyz]mm{k} */ - host_and_vcpu_must_have(avx512f); + visa_check(f); if ( ea.type !=3D OP_REG || !evex.brs ) avx512_vlen_check(false); goto simd_zmm; @@ -6029,7 +6056,7 @@ x86_emulate( case X86EMUL_OPC_EVEX_66(0x0f38, 0xbb): /* vfmsub231s{s,d} xmm/mem,xmm= ,xmm{k} */ case X86EMUL_OPC_EVEX_66(0x0f38, 0xbd): /* vfnmadd231s{s,d} xmm/mem,xm= m,xmm{k} */ case X86EMUL_OPC_EVEX_66(0x0f38, 0xbf): /* vfnmsub231s{s,d} xmm/mem,xm= m,xmm{k} */ - host_and_vcpu_must_have(avx512f); + visa_check(f); generate_exception_if(ea.type !=3D OP_REG && evex.brs, X86_EXC_UD); if ( !evex.brs ) avx512_vlen_check(true); @@ -6043,14 +6070,14 @@ x86_emulate( case X86EMUL_OPC_EVEX_66(0x0f38, 0x3a): /* vpminuw [xyz]mm/mem,[xyz]mm= ,[xyz]mm{k} */ case X86EMUL_OPC_EVEX_66(0x0f38, 0x3c): /* vpmaxsb [xyz]mm/mem,[xyz]mm= ,[xyz]mm{k} */ case X86EMUL_OPC_EVEX_66(0x0f38, 0x3e): /* vpmaxuw [xyz]mm/mem,[xyz]mm= ,[xyz]mm{k} */ - host_and_vcpu_must_have(avx512bw); + visa_check(bw); generate_exception_if(evex.brs, X86_EXC_UD); elem_bytes =3D b & 2 ?: 1; goto avx512f_no_sae; =20 case X86EMUL_OPC_EVEX_66(0x0f38, 0x40): /* vpmull{d,q} [xyz]mm/mem,[xy= z]mm,[xyz]mm{k} */ if ( evex.w ) - host_and_vcpu_must_have(avx512dq); + visa_check(dq); goto avx512f_no_sae; =20 case X86EMUL_OPC_66(0x0f38, 0xdb): /* aesimc xmm/m128,xmm */ @@ -6089,7 +6116,7 @@ x86_emulate( case X86EMUL_OPC_EVEX_66(0x0f38, 0x51): /* vpdpbusds [xyz]mm/mem,[xyz]= mm,[xyz]mm{k} */ case X86EMUL_OPC_EVEX_66(0x0f38, 0x52): /* vpdpwssd [xyz]mm/mem,[xyz]m= m,[xyz]mm{k} */ case X86EMUL_OPC_EVEX_66(0x0f38, 0x53): /* vpdpwssds [xyz]mm/mem,[xyz]= mm,[xyz]mm{k} */ - host_and_vcpu_must_have(avx512_vnni); + visa_check(_vnni); generate_exception_if(evex.w, X86_EXC_UD); goto avx512f_no_sae; =20 @@ -6101,7 +6128,7 @@ x86_emulate( d |=3D TwoOp; /* fall through */ case X86EMUL_OPC_EVEX_F3(0x0f38, 0x52): /* vdpbf16ps [xyz]mm/mem,[xyz]= mm,[xyz]mm{k} */ - host_and_vcpu_must_have(avx512_bf16); + visa_check(_bf16); generate_exception_if(evex.w, X86_EXC_UD); op_bytes =3D 16 << evex.lr; goto avx512f_no_sae; @@ -6118,7 +6145,7 @@ x86_emulate( =20 case X86EMUL_OPC_EVEX_66(0x0f38, 0x4d): /* vrcp14s{s,d} xmm/mem,xmm,xm= m{k} */ case X86EMUL_OPC_EVEX_66(0x0f38, 0x4f): /* vrsqrt14s{s,d} xmm/mem,xmm,= xmm{k} */ - host_and_vcpu_must_have(avx512f); + visa_check(f); generate_exception_if(evex.brs, X86_EXC_UD); avx512_vlen_check(true); goto simd_zmm; @@ -6127,16 +6154,16 @@ x86_emulate( generate_exception_if(evex.w || !evex.r || !evex.R || evex.z, X86_= EXC_UD); /* fall through */ case X86EMUL_OPC_EVEX_66(0x0f38, 0x54): /* vpopcnt{b,w} [xyz]mm/mem,[x= yz]mm{k} */ - host_and_vcpu_must_have(avx512_bitalg); + visa_check(_bitalg); /* fall through */ case X86EMUL_OPC_EVEX_66(0x0f38, 0x66): /* vpblendm{b,w} [xyz]mm/mem,[= xyz]mm,[xyz]mm{k} */ - host_and_vcpu_must_have(avx512bw); + visa_check(bw); generate_exception_if(evex.brs, X86_EXC_UD); elem_bytes =3D 1 << evex.w; goto avx512f_no_sae; =20 case X86EMUL_OPC_EVEX_66(0x0f38, 0x55): /* vpopcnt{d,q} [xyz]mm/mem,[x= yz]mm{k} */ - host_and_vcpu_must_have(avx512_vpopcntdq); + visa_check(_vpopcntdq); goto avx512f_no_sae; =20 case X86EMUL_OPC_VEX_66(0x0f38, 0x5a): /* vbroadcasti128 m128,ymm */ @@ -6145,14 +6172,14 @@ x86_emulate( =20 case X86EMUL_OPC_EVEX_66(0x0f38, 0x62): /* vpexpand{b,w} [xyz]mm/mem,[= xyz]mm{k} */ case X86EMUL_OPC_EVEX_66(0x0f38, 0x63): /* vpcompress{b,w} [xyz]mm,[xy= z]mm/mem{k} */ - host_and_vcpu_must_have(avx512_vbmi2); + visa_check(_vbmi2); elem_bytes =3D 1 << evex.w; /* fall through */ case X86EMUL_OPC_EVEX_66(0x0f38, 0x88): /* vexpandp{s,d} [xyz]mm/mem,[= xyz]mm{k} */ case X86EMUL_OPC_EVEX_66(0x0f38, 0x89): /* vpexpand{d,q} [xyz]mm/mem,[= xyz]mm{k} */ case X86EMUL_OPC_EVEX_66(0x0f38, 0x8a): /* vcompressp{s,d} [xyz]mm,[xy= z]mm/mem{k} */ case X86EMUL_OPC_EVEX_66(0x0f38, 0x8b): /* vpcompress{d,q} [xyz]mm,[xy= z]mm/mem{k} */ - host_and_vcpu_must_have(avx512f); + visa_check(f); generate_exception_if(evex.brs, X86_EXC_UD); avx512_vlen_check(false); /* @@ -6186,7 +6213,7 @@ x86_emulate( /* fall through */ case X86EMUL_OPC_EVEX_66(0x0f38, 0x71): /* vpshldv{d,q} [xyz]mm/mem,[x= yz]mm,[xyz]mm{k} */ case X86EMUL_OPC_EVEX_66(0x0f38, 0x73): /* vpshrdv{d,q} [xyz]mm/mem,[x= yz]mm,[xyz]mm{k} */ - host_and_vcpu_must_have(avx512_vbmi2); + visa_check(_vbmi2); goto avx512f_no_sae; =20 case X86EMUL_OPC_VEX (0x0f38, 0xb0): /* vcvtneoph2ps mem,[xy]mm */ @@ -6206,16 +6233,16 @@ x86_emulate( case X86EMUL_OPC_EVEX_66(0x0f38, 0x7d): /* vpermt2{b,w} [xyz]mm/mem,[x= yz]mm,[xyz]mm{k} */ case X86EMUL_OPC_EVEX_66(0x0f38, 0x8d): /* vperm{b,w} [xyz]mm/mem,[xyz= ]mm,[xyz]mm{k} */ if ( !evex.w ) - host_and_vcpu_must_have(avx512_vbmi); + visa_check(_vbmi); else - host_and_vcpu_must_have(avx512bw); + visa_check(bw); generate_exception_if(evex.brs, X86_EXC_UD); fault_suppression =3D false; goto avx512f_no_sae; =20 case X86EMUL_OPC_EVEX_66(0x0f38, 0x78): /* vpbroadcastb xmm/m8,[xyz]mm= {k} */ case X86EMUL_OPC_EVEX_66(0x0f38, 0x79): /* vpbroadcastw xmm/m16,[xyz]m= m{k} */ - host_and_vcpu_must_have(avx512bw); + visa_check(bw); generate_exception_if(evex.w || evex.brs, X86_EXC_UD); op_bytes =3D elem_bytes =3D 1 << (b & 1); /* See the comment at the avx512_broadcast label. */ @@ -6224,14 +6251,14 @@ x86_emulate( =20 case X86EMUL_OPC_EVEX_66(0x0f38, 0x7a): /* vpbroadcastb r32,[xyz]mm{k}= */ case X86EMUL_OPC_EVEX_66(0x0f38, 0x7b): /* vpbroadcastw r32,[xyz]mm{k}= */ - host_and_vcpu_must_have(avx512bw); + visa_check(bw); generate_exception_if(evex.w, X86_EXC_UD); /* fall through */ case X86EMUL_OPC_EVEX_66(0x0f38, 0x7c): /* vpbroadcast{d,q} reg,[xyz]m= m{k} */ generate_exception_if((ea.type !=3D OP_REG || evex.brs || evex.reg !=3D 0xf || !evex.RX), X86_EXC_UD); - host_and_vcpu_must_have(avx512f); + visa_check(f); avx512_vlen_check(false); get_fpu(X86EMUL_FPU_zmm); =20 @@ -6300,7 +6327,7 @@ x86_emulate( =20 case X86EMUL_OPC_EVEX_66(0x0f38, 0x83): /* vpmultishiftqb [xyz]mm/mem,= [xyz]mm,[xyz]mm{k} */ generate_exception_if(!evex.w, X86_EXC_UD); - host_and_vcpu_must_have(avx512_vbmi); + visa_check(_vbmi); fault_suppression =3D false; goto avx512f_no_sae; =20 @@ -6448,8 +6475,8 @@ x86_emulate( evex.reg !=3D 0xf || modrm_reg =3D=3D state->sib_index), X86_EXC_UD); + visa_check(f); avx512_vlen_check(false); - host_and_vcpu_must_have(avx512f); get_fpu(X86EMUL_FPU_zmm); =20 /* Read destination and index registers. */ @@ -6610,8 +6637,8 @@ x86_emulate( evex.reg !=3D 0xf || modrm_reg =3D=3D state->sib_index), X86_EXC_UD); + visa_check(f); avx512_vlen_check(false); - host_and_vcpu_must_have(avx512f); get_fpu(X86EMUL_FPU_zmm); =20 /* Read source and index registers. */ @@ -6727,7 +6754,7 @@ x86_emulate( =20 case X86EMUL_OPC_EVEX_66(0x0f38, 0xb4): /* vpmadd52luq [xyz]mm/mem,[xy= z]mm,[xyz]mm{k} */ case X86EMUL_OPC_EVEX_66(0x0f38, 0xb5): /* vpmadd52huq [xyz]mm/mem,[xy= z]mm,[xyz]mm{k} */ - host_and_vcpu_must_have(avx512_ifma); + visa_check(_ifma); generate_exception_if(!evex.w, X86_EXC_UD); goto avx512f_no_sae; =20 @@ -7090,7 +7117,7 @@ x86_emulate( /* fall through */ case X86EMUL_OPC_EVEX_66(0x0f3a, 0x08): /* vrndscaleps $imm8,[xyz]mm/m= em,[xyz]mm{k} */ case X86EMUL_OPC_EVEX_66(0x0f3a, 0x09): /* vrndscalepd $imm8,[xyz]mm/m= em,[xyz]mm{k} */ - host_and_vcpu_must_have(avx512f); + visa_check(f); generate_exception_if(evex.w !=3D (b & 1), X86_EXC_UD); avx512_vlen_check(b & 2); goto simd_imm8_zmm; @@ -7099,7 +7126,7 @@ x86_emulate( generate_exception_if(ea.type !=3D OP_REG && evex.brs, X86_EXC_UD); /* fall through */ case X86EMUL_OPC_EVEX(0x0f3a, 0x08): /* vrndscaleph $imm8,[xyz]mm/mem,= [xyz]mm{k} */ - host_and_vcpu_must_have(avx512_fp16); + visa_check(_fp16); generate_exception_if(evex.w, X86_EXC_UD); avx512_vlen_check(b & 2); goto simd_imm8_zmm; @@ -7212,11 +7239,11 @@ x86_emulate( evex.opmsk || evex.brs), X86_EXC_UD); if ( !(b & 2) ) - host_and_vcpu_must_have(avx512bw); + visa_check(bw); else if ( !(b & 1) ) - host_and_vcpu_must_have(avx512dq); + visa_check(dq); else - host_and_vcpu_must_have(avx512f); + visa_check(f); get_fpu(X86EMUL_FPU_zmm); opc =3D init_evex(stub); goto pextr; @@ -7230,7 +7257,7 @@ x86_emulate( case X86EMUL_OPC_EVEX_66(0x0f3a, 0x39): /* vextracti32x4 $imm8,{y,z}mm= ,xmm/m128{k} */ /* vextracti64x2 $imm8,{y,z}mm= ,xmm/m128{k} */ if ( evex.w ) - host_and_vcpu_must_have(avx512dq); + visa_check(dq); generate_exception_if(evex.brs, X86_EXC_UD); /* fall through */ case X86EMUL_OPC_EVEX_66(0x0f3a, 0x23): /* vshuff32x4 $imm8,{y,z}mm/me= m,{y,z}mm,{y,z}mm{k} */ @@ -7250,7 +7277,7 @@ x86_emulate( case X86EMUL_OPC_EVEX_66(0x0f3a, 0x3b): /* vextracti32x8 $imm8,zmm,ymm= /m256{k} */ /* vextracti64x4 $imm8,zmm,ymm= /m256{k} */ if ( !evex.w ) - host_and_vcpu_must_have(avx512dq); + visa_check(dq); generate_exception_if(evex.lr !=3D 2 || evex.brs, X86_EXC_UD); fault_suppression =3D false; goto avx512f_imm8_no_sae; @@ -7266,7 +7293,7 @@ x86_emulate( generate_exception_if((evex.w || evex.reg !=3D 0xf || !evex.RX= || (ea.type !=3D OP_REG && (evex.z || evex= .brs))), X86_EXC_UD); - host_and_vcpu_must_have(avx512f); + visa_check(f); avx512_vlen_check(false); opc =3D init_evex(stub); } @@ -7358,7 +7385,7 @@ x86_emulate( if ( !(b & 0x20) ) goto avx512f_imm8_no_sae; avx512bw_imm: - host_and_vcpu_must_have(avx512bw); + visa_check(bw); generate_exception_if(evex.brs, X86_EXC_UD); elem_bytes =3D 1 << evex.w; avx512_vlen_check(false); @@ -7397,7 +7424,7 @@ x86_emulate( goto simd_0f_imm8_avx; =20 case X86EMUL_OPC_EVEX_66(0x0f3a, 0x21): /* vinsertps $imm8,xmm/m32,xmm= ,xmm */ - host_and_vcpu_must_have(avx512f); + visa_check(f); generate_exception_if(evex.lr || evex.w || evex.opmsk || evex.brs, X86_EXC_UD); op_bytes =3D 4; @@ -7405,18 +7432,18 @@ x86_emulate( =20 case X86EMUL_OPC_EVEX_66(0x0f3a, 0x50): /* vrangep{s,d} $imm8,[xyz]mm/= mem,[xyz]mm,[xyz]mm{k} */ case X86EMUL_OPC_EVEX_66(0x0f3a, 0x56): /* vreducep{s,d} $imm8,[xyz]mm= /mem,[xyz]mm{k} */ - host_and_vcpu_must_have(avx512dq); + visa_check(dq); /* fall through */ case X86EMUL_OPC_EVEX_66(0x0f3a, 0x26): /* vgetmantp{s,d} $imm8,[xyz]m= m/mem,[xyz]mm{k} */ case X86EMUL_OPC_EVEX_66(0x0f3a, 0x54): /* vfixupimmp{s,d} $imm8,[xyz]= mm/mem,[xyz]mm,[xyz]mm{k} */ - host_and_vcpu_must_have(avx512f); + visa_check(f); if ( ea.type !=3D OP_REG || !evex.brs ) avx512_vlen_check(false); goto simd_imm8_zmm; =20 case X86EMUL_OPC_EVEX(0x0f3a, 0x26): /* vgetmantph $imm8,[xyz]mm/mem,[= xyz]mm{k} */ case X86EMUL_OPC_EVEX(0x0f3a, 0x56): /* vreduceph $imm8,[xyz]mm/mem,[x= yz]mm{k} */ - host_and_vcpu_must_have(avx512_fp16); + visa_check(_fp16); generate_exception_if(evex.w, X86_EXC_UD); if ( ea.type !=3D OP_REG || !evex.brs ) avx512_vlen_check(false); @@ -7424,11 +7451,11 @@ x86_emulate( =20 case X86EMUL_OPC_EVEX_66(0x0f3a, 0x51): /* vranges{s,d} $imm8,xmm/mem,= xmm,xmm{k} */ case X86EMUL_OPC_EVEX_66(0x0f3a, 0x57): /* vreduces{s,d} $imm8,xmm/mem= ,xmm,xmm{k} */ - host_and_vcpu_must_have(avx512dq); + visa_check(dq); /* fall through */ case X86EMUL_OPC_EVEX_66(0x0f3a, 0x27): /* vgetmants{s,d} $imm8,xmm/me= m,xmm,xmm{k} */ case X86EMUL_OPC_EVEX_66(0x0f3a, 0x55): /* vfixupimms{s,d} $imm8,xmm/m= em,xmm,xmm{k} */ - host_and_vcpu_must_have(avx512f); + visa_check(f); generate_exception_if(ea.type !=3D OP_REG && evex.brs, X86_EXC_UD); if ( !evex.brs ) avx512_vlen_check(true); @@ -7436,7 +7463,7 @@ x86_emulate( =20 case X86EMUL_OPC_EVEX(0x0f3a, 0x27): /* vgetmantsh $imm8,xmm/mem,xmm,x= mm{k} */ case X86EMUL_OPC_EVEX(0x0f3a, 0x57): /* vreducesh $imm8,xmm/mem,xmm,xm= m{k} */ - host_and_vcpu_must_have(avx512_fp16); + visa_check(_fp16); generate_exception_if(evex.w, X86_EXC_UD); if ( !evex.brs ) avx512_vlen_check(true); @@ -7447,18 +7474,19 @@ x86_emulate( case X86EMUL_OPC_VEX_66(0x0f3a, 0x30): /* kshiftr{b,w} $imm8,k,k */ case X86EMUL_OPC_VEX_66(0x0f3a, 0x32): /* kshiftl{b,w} $imm8,k,k */ if ( !vex.w ) - host_and_vcpu_must_have(avx512dq); + visa_check(dq); + else + visa_check(f); opmask_shift_imm: generate_exception_if(vex.l || !vex.r || vex.reg !=3D 0xf || ea.type !=3D OP_REG, X86_EXC_UD); - host_and_vcpu_must_have(avx512f); get_fpu(X86EMUL_FPU_opmask); op_bytes =3D 1; /* Any non-zero value will do. */ goto simd_0f_imm8; =20 case X86EMUL_OPC_VEX_66(0x0f3a, 0x31): /* kshiftr{d,q} $imm8,k,k */ case X86EMUL_OPC_VEX_66(0x0f3a, 0x33): /* kshiftl{d,q} $imm8,k,k */ - host_and_vcpu_must_have(avx512bw); + visa_check(bw); goto opmask_shift_imm; =20 case X86EMUL_OPC_66(0x0f3a, 0x44): /* pclmulqdq $imm8,xmm/m128,xmm= */ @@ -7599,7 +7627,7 @@ x86_emulate( =20 case X86EMUL_OPC_EVEX_66(0x0f3a, 0x66): /* vfpclassp{s,d} $imm8,[xyz]m= m/mem,k{k} */ case X86EMUL_OPC_EVEX_66(0x0f3a, 0x67): /* vfpclasss{s,d} $imm8,xmm/me= m,k{k} */ - host_and_vcpu_must_have(avx512dq); + visa_check(dq); generate_exception_if(!evex.r || !evex.R || evex.z, X86_EXC_UD); if ( !(b & 1) ) goto avx512f_imm8_no_sae; @@ -7609,7 +7637,7 @@ x86_emulate( =20 case X86EMUL_OPC_EVEX(0x0f3a, 0x66): /* vfpclassph $imm8,[xyz]mm/mem,k= {k} */ case X86EMUL_OPC_EVEX(0x0f3a, 0x67): /* vfpclasssh $imm8,xmm/mem,k{k} = */ - host_and_vcpu_must_have(avx512_fp16); + visa_check(_fp16); generate_exception_if(evex.w || !evex.r || !evex.R || evex.z, X86_= EXC_UD); if ( !(b & 1) ) goto avx512f_imm8_no_sae; @@ -7624,14 +7652,14 @@ x86_emulate( /* fall through */ case X86EMUL_OPC_EVEX_66(0x0f3a, 0x71): /* vpshld{d,q} $imm8,[xyz]mm/m= em,[xyz]mm,[xyz]mm{k} */ case X86EMUL_OPC_EVEX_66(0x0f3a, 0x73): /* vpshrd{d,q} $imm8,[xyz]mm/m= em,[xyz]mm,[xyz]mm{k} */ - host_and_vcpu_must_have(avx512_vbmi2); + visa_check(_vbmi2); goto avx512f_imm8_no_sae; =20 case X86EMUL_OPC_EVEX_F3(0x0f3a, 0xc2): /* vcmpsh $imm8,xmm/mem,xmm,k{= k} */ generate_exception_if(ea.type !=3D OP_REG && evex.brs, X86_EXC_UD); /* fall through */ case X86EMUL_OPC_EVEX(0x0f3a, 0xc2): /* vcmpph $imm8,[xyz]mm/mem,[xyz]= mm,k{k} */ - host_and_vcpu_must_have(avx512_fp16); + visa_check(_fp16); generate_exception_if(evex.w || !evex.r || !evex.R || evex.z, X86_= EXC_UD); if ( ea.type !=3D OP_REG || !evex.brs ) avx512_vlen_check(evex.pfx & VEX_PREFIX_SCALAR_MASK); @@ -7712,13 +7740,13 @@ x86_emulate( CASE_SIMD_SINGLE_FP(_EVEX, 5, 0x5d): /* vmin{p,s}h [xyz]mm/mem,[xyz]mm= ,[xyz]mm{k} */ CASE_SIMD_SINGLE_FP(_EVEX, 5, 0x5e): /* vdiv{p,s}h [xyz]mm/mem,[xyz]mm= ,[xyz]mm{k} */ CASE_SIMD_SINGLE_FP(_EVEX, 5, 0x5f): /* vmax{p,s}h [xyz]mm/mem,[xyz]mm= ,[xyz]mm{k} */ - host_and_vcpu_must_have(avx512_fp16); + visa_check(_fp16); generate_exception_if(evex.w, X86_EXC_UD); goto avx512f_all_fp; =20 CASE_SIMD_ALL_FP(_EVEX, 5, 0x5a): /* vcvtp{h,d}2p{h,d} [xyz]mm/mem,[x= yz]mm{k} */ /* vcvts{h,d}2s{h,d} xmm/mem,xmm,xm= m{k} */ - host_and_vcpu_must_have(avx512_fp16); + visa_check(_fp16); if ( vex.pfx & VEX_PREFIX_SCALAR_MASK ) d &=3D ~TwoOp; op_bytes =3D 2 << (((evex.pfx & VEX_PREFIX_SCALAR_MASK) ? 0 : 1 + = evex.lr) + @@ -7729,7 +7757,7 @@ x86_emulate( /* vcvtqq2ph [xyz]mm/mem,xmm{k} */ case X86EMUL_OPC_EVEX_F2(5, 0x7a): /* vcvtudq2ph [xyz]mm/mem,[xy]mm{k}= */ /* vcvtuqq2ph [xyz]mm/mem,xmm{k} */ - host_and_vcpu_must_have(avx512_fp16); + visa_check(_fp16); if ( ea.type !=3D OP_REG || !evex.brs ) avx512_vlen_check(false); op_bytes =3D 16 << evex.lr; @@ -7739,7 +7767,7 @@ x86_emulate( case X86EMUL_OPC_EVEX_F3(5, 0x5b): /* vcvttph2dq [xy]mm/mem,[xyz]mm{k}= */ case X86EMUL_OPC_EVEX (5, 0x78): /* vcvttph2udq [xy]mm/mem,[xyz]mm{k= } */ case X86EMUL_OPC_EVEX (5, 0x79): /* vcvtph2udq [xy]mm/mem,[xyz]mm{k}= */ - host_and_vcpu_must_have(avx512_fp16); + visa_check(_fp16); generate_exception_if(evex.w, X86_EXC_UD); if ( ea.type !=3D OP_REG || !evex.brs ) avx512_vlen_check(false); @@ -7750,7 +7778,7 @@ x86_emulate( case X86EMUL_OPC_EVEX_66(5, 0x79): /* vcvtph2uqq xmm/mem,[xyz]mm{k} */ case X86EMUL_OPC_EVEX_66(5, 0x7a): /* vcvttph2qq xmm/mem,[xyz]mm{k} */ case X86EMUL_OPC_EVEX_66(5, 0x7b): /* vcvtph2qq xmm/mem,[xyz]mm{k} */ - host_and_vcpu_must_have(avx512_fp16); + visa_check(_fp16); generate_exception_if(evex.w, X86_EXC_UD); if ( ea.type !=3D OP_REG || !evex.brs ) avx512_vlen_check(false); @@ -7787,7 +7815,7 @@ x86_emulate( case X86EMUL_OPC_EVEX_66(6, 0xba): /* vfmsub231ph [xyz]mm/mem,[xyz]mm,= [xyz]mm{k} */ case X86EMUL_OPC_EVEX_66(6, 0xbc): /* vfnmadd231ph [xyz]mm/mem,[xyz]mm= ,[xyz]mm{k} */ case X86EMUL_OPC_EVEX_66(6, 0xbe): /* vfnmsub231ph [xyz]mm/mem,[xyz]mm= ,[xyz]mm{k} */ - host_and_vcpu_must_have(avx512_fp16); + visa_check(_fp16); generate_exception_if(evex.w, X86_EXC_UD); if ( ea.type !=3D OP_REG || !evex.brs ) avx512_vlen_check(false); @@ -7809,7 +7837,7 @@ x86_emulate( case X86EMUL_OPC_EVEX_66(6, 0xbb): /* vfmsub231sh xmm/m16,xmm,xmm{k} */ case X86EMUL_OPC_EVEX_66(6, 0xbd): /* vfnmadd231sh xmm/m16,xmm,xmm{k} = */ case X86EMUL_OPC_EVEX_66(6, 0xbf): /* vfnmsub231sh xmm/m16,xmm,xmm{k} = */ - host_and_vcpu_must_have(avx512_fp16); + visa_check(_fp16); generate_exception_if(evex.w || (ea.type !=3D OP_REG && evex.brs), X86_EXC_UD); if ( !evex.brs ) @@ -7818,13 +7846,13 @@ x86_emulate( =20 case X86EMUL_OPC_EVEX_66(6, 0x4c): /* vrcpph [xyz]mm/mem,[xyz]mm{k} */ case X86EMUL_OPC_EVEX_66(6, 0x4e): /* vrsqrtph [xyz]mm/mem,[xyz]mm{k} = */ - host_and_vcpu_must_have(avx512_fp16); + visa_check(_fp16); generate_exception_if(evex.w, X86_EXC_UD); goto avx512f_no_sae; =20 case X86EMUL_OPC_EVEX_66(6, 0x4d): /* vrcpsh xmm/m16,xmm,xmm{k} */ case X86EMUL_OPC_EVEX_66(6, 0x4f): /* vrsqrtsh xmm/m16,xmm,xmm{k} */ - host_and_vcpu_must_have(avx512_fp16); + visa_check(_fp16); generate_exception_if(evex.w || evex.brs, X86_EXC_UD); avx512_vlen_check(true); goto simd_zmm; @@ -7842,7 +7870,7 @@ x86_emulate( { unsigned int src1 =3D ~evex.reg; =20 - host_and_vcpu_must_have(avx512_fp16); + visa_check(_fp16); generate_exception_if(evex.w || ((b & 1) && ea.type !=3D OP_REG &&= evex.brs), X86_EXC_UD); if ( mode_64bit() ) --- a/xen/arch/x86/xstate.c +++ b/xen/arch/x86/xstate.c @@ -787,7 +787,7 @@ static void __init noinline xstate_check if ( cpu_has_mpx ) check_new_xstate(&s, X86_XCR0_BNDCSR | X86_XCR0_BNDREGS); =20 - if ( cpu_has_avx512f ) + if ( boot_cpu_has(X86_FEATURE_AVX512F) || boot_cpu_has(X86_FEATURE_AVX= 10) ) check_new_xstate(&s, X86_XCR0_HI_ZMM | X86_XCR0_ZMM | X86_XCR0_OPM= ASK); =20 /* --- a/xen/include/public/arch-x86/cpufeatureset.h +++ b/xen/include/public/arch-x86/cpufeatureset.h @@ -334,7 +334,7 @@ XEN_CPUFEATURE(AVX_NE_CONVERT, 15*32 XEN_CPUFEATURE(AVX_VNNI_INT16, 15*32+10) /*A AVX-VNNI-INT16 Instructi= ons */ XEN_CPUFEATURE(PREFETCHI, 15*32+14) /*A PREFETCHIT{0,1} Instruct= ions */ XEN_CPUFEATURE(CET_SSS, 15*32+18) /* CET Supervisor Shadow St= acks safe to use */ -XEN_CPUFEATURE(AVX10, 15*32+19) /* AVX10 Converged Vector I= SA */ +XEN_CPUFEATURE(AVX10, 15*32+19) /*a AVX10 Converged Vector I= SA */ =20 /* Intel-defined CPU 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[37.24.206.209]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5bd187f3306sm3671889a12.17.2024.08.14.01.52.56 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 14 Aug 2024 01:52:56 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 99f0b1bc-5a1a-11ef-a505-bb4a2ccca743 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=google; t=1723625576; x=1724230376; darn=lists.xenproject.org; h=content-transfer-encoding:in-reply-to:autocrypt:content-language :references:cc:to:from:subject:user-agent:mime-version:date :message-id:from:to:cc:subject:date:message-id:reply-to; bh=ZnNv/Ji9QwDXDDtnpehfNwAdKNqWREph7EusWegGIOY=; b=VFsOG1NfkhtDRjWb2Hdhu3yz8v6KkNbvoWwZxwOQjQ7LbC/uOEX0hcEBEWclvBCBZB QPVdRyUH6SO7PQ2fCpZvEsj0BHeqWPKhWRnJACAz/3cDEAdDm0Y5Cw1zcGSj6cGk5dsE G1QpqQhHxtT+OQjl1fTDvdzBL2KbFc6FkEGArD4NCl7sOuA3O9JGuGv0/e64uZPTcyLl HU7hOjsoLrqnsRMX2F/9FbIWma5RIevaGFpM2P+HfDL/2/7oXBwWM5oxXsG2xNfhSkH1 ky9aT1fgIqi9zWb/4QusyGwRExDgQOaWo9iB2eT5x48A5vAKlKsNtp5jT8MpY/VeE0dV YaYg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1723625576; x=1724230376; h=content-transfer-encoding:in-reply-to:autocrypt:content-language :references:cc:to:from:subject:user-agent:mime-version:date :message-id:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=ZnNv/Ji9QwDXDDtnpehfNwAdKNqWREph7EusWegGIOY=; b=SzWPpoFvnAyUEcUXBpUFpQ87wS6HkxqmvrnRSd41ZPLvA1XX/E5HoErdeycJEHA9TZ mHNtXn9APyxq7AvA60ryonW2RS/hxGH1IMDy3g0etJLt6hjwSgcCIDugjHTJxkZWwe/0 0CZ2SB9vbv7i7qUt6FpPeDm1+ubcxqgV94cChly11h0roBEtyRtVCXxnf4K9Jk5X75Py HLAAFfASJWnncsr43rCWckCVHzzQT7mOc2JnnVuPmxL3/k+AFyVzh4LVGuqnNvqXu9MX gM0vlKMSrdf+MNbwouf1zYdfwJHuYH+oQBZ2RHTJua0i9Y8rvoNVy3tVZrvmlW35ZVFT eaCw== X-Gm-Message-State: AOJu0Yy/MbFTILtTYAD+R9Y1tqhxWNmGbASD3RgzOTdpM8y5e/ZyVgGs 9dCSnWtH28sRoG/pvZBmeKHaNpRcac3hIwT4tlZ2+S/fKsCVt33y4vGCpZzH2DCl0B5HA2CID5Y = X-Google-Smtp-Source: AGHT+IFSX9nfFHp2Nmtb5zXDICfD7E8j/0oPb7tJYbK+SldtJqquczrLewxcZ48Qwnec6LtqNgJiog== X-Received: by 2002:a05:6402:2811:b0:5a2:68a2:ae57 with SMTP id 4fb4d7f45d1cf-5bea1cb2b95mr1220347a12.31.1723625576496; Wed, 14 Aug 2024 01:52:56 -0700 (PDT) Message-ID: Date: Wed, 14 Aug 2024 10:52:55 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH v2 5/9] x86emul/test: use simd_check_avx512*() in main() From: Jan Beulich To: "xen-devel@lists.xenproject.org" Cc: Andrew Cooper , Wei Liu , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= References: Content-Language: en-US Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @suse.com) X-ZM-MESSAGEID: 1723625597755116600 Content-Type: text/plain; charset="utf-8" In preparation for having these also cover AVX10, use the helper functions in preference of open-coded cpu_has_avx512* for those features that AVX10 includes. Introduce a couple further helper functions where they weren't previously needed. Note that this way simd_check_avx512f_sha_vl() gains an AVX512F check (which is likely benign) and simd_check_avx512bw_gf_vl() gains an AVX512BW check (which was clearly missing).=20 Signed-off-by: Jan Beulich --- v2: Re-base over dropping of Xeon Phi support. --- a/tools/tests/x86_emulator/test_x86_emulator.c +++ b/tools/tests/x86_emulator/test_x86_emulator.c @@ -167,6 +167,11 @@ static bool simd_check_avx512vbmi_vl(voi return cpu_has_avx512_vbmi && cpu_has_avx512vl; } =20 +static bool simd_check_avx512vbmi2(void) +{ + return cpu_has_avx512_vbmi2; +} + static bool simd_check_sse4_sha(void) { return cpu_has_sha && cpu_has_sse4_2; @@ -179,7 +184,7 @@ static bool simd_check_avx_sha(void) =20 static bool simd_check_avx512f_sha_vl(void) { - return cpu_has_sha && cpu_has_avx512vl; + return cpu_has_sha && simd_check_avx512f_vl(); } =20 static bool simd_check_avx2_vaes(void) @@ -189,13 +194,13 @@ static bool simd_check_avx2_vaes(void) =20 static bool simd_check_avx512bw_vaes(void) { - return cpu_has_aesni && cpu_has_vaes && cpu_has_avx512bw; + return cpu_has_aesni && cpu_has_vaes && simd_check_avx512bw(); } =20 static bool simd_check_avx512bw_vaes_vl(void) { return cpu_has_aesni && cpu_has_vaes && - cpu_has_avx512bw && cpu_has_avx512vl; + simd_check_avx512bw_vl(); } =20 static bool simd_check_avx2_vpclmulqdq(void) @@ -205,22 +210,22 @@ static bool simd_check_avx2_vpclmulqdq(v =20 static bool simd_check_avx512bw_vpclmulqdq(void) { - return cpu_has_vpclmulqdq && cpu_has_avx512bw; + return cpu_has_vpclmulqdq && simd_check_avx512bw(); } =20 static bool simd_check_avx512bw_vpclmulqdq_vl(void) { - return cpu_has_vpclmulqdq && cpu_has_avx512bw && cpu_has_avx512vl; + return cpu_has_vpclmulqdq && simd_check_avx512bw_vl(); } =20 static bool simd_check_avx512vbmi2_vpclmulqdq(void) { - return cpu_has_avx512_vbmi2 && simd_check_avx512bw_vpclmulqdq(); + return simd_check_avx512vbmi2() && simd_check_avx512bw_vpclmulqdq(); } =20 static bool simd_check_avx512vbmi2_vpclmulqdq_vl(void) { - return cpu_has_avx512_vbmi2 && simd_check_avx512bw_vpclmulqdq_vl(); + return simd_check_avx512vbmi2() && simd_check_avx512bw_vpclmulqdq_vl(); } =20 static bool simd_check_sse2_gf(void) @@ -235,12 +240,17 @@ static bool simd_check_avx2_gf(void) =20 static bool simd_check_avx512bw_gf(void) { - return cpu_has_gfni && cpu_has_avx512bw; + return cpu_has_gfni && simd_check_avx512bw(); } =20 static bool simd_check_avx512bw_gf_vl(void) { - return cpu_has_gfni && cpu_has_avx512vl; + return cpu_has_gfni && simd_check_avx512bw_vl(); +} + +static bool simd_check_avx512vnni(void) +{ + return cpu_has_avx512_vnni; } =20 static bool simd_check_avx512fp16(void) @@ -2800,7 +2810,7 @@ int main(int argc, char **argv) printf("skipped\n"); =20 printf("%-40s", "Testing {evex} vmovq %xmm1,32(%edx)..."); - if ( stack_exec && cpu_has_avx512f ) + if ( stack_exec && simd_check_avx512f() ) { decl_insn(evex_vmovq_to_mem); =20 @@ -2824,7 +2834,7 @@ int main(int argc, char **argv) printf("skipped\n"); =20 printf("%-40s", "Testing {evex} vmovq 32(%edx),%xmm0..."); - if ( stack_exec && cpu_has_avx512f ) + if ( stack_exec && simd_check_avx512f() ) { decl_insn(evex_vmovq_from_mem); =20 @@ -2947,7 +2957,7 @@ int main(int argc, char **argv) printf("skipped\n"); =20 printf("%-40s", "Testing vmovdqu32 %zmm2,(%ecx){%k1}..."); - if ( stack_exec && cpu_has_avx512f ) + if ( stack_exec && simd_check_avx512f() ) { decl_insn(vmovdqu32_to_mem); =20 @@ -2977,7 +2987,7 @@ int main(int argc, char **argv) printf("skipped\n"); =20 printf("%-40s", "Testing vmovdqu32 64(%edx),%zmm2{%k2}..."); - if ( stack_exec && cpu_has_avx512f ) + if ( stack_exec && simd_check_avx512f() ) { decl_insn(vmovdqu32_from_mem); =20 @@ -3002,7 +3012,7 @@ int main(int argc, char **argv) printf("skipped\n"); =20 printf("%-40s", "Testing vmovdqu16 %zmm3,(%ecx){%k1}..."); - if ( stack_exec && cpu_has_avx512bw ) + if ( stack_exec && simd_check_avx512bw() ) { decl_insn(vmovdqu16_to_mem); =20 @@ -3034,7 +3044,7 @@ int main(int argc, char **argv) printf("skipped\n"); =20 printf("%-40s", "Testing vmovdqu16 64(%edx),%zmm3{%k2}..."); - if ( stack_exec && cpu_has_avx512bw ) + if ( stack_exec && simd_check_avx512bw() ) { decl_insn(vmovdqu16_from_mem); =20 @@ -3162,7 +3172,7 @@ int main(int argc, char **argv) printf("%-40s", "Testing vmovsd %xmm5,16(%ecx){%k3}..."); memset(res, 0x88, 128); memset(res + 20, 0x77, 8); - if ( stack_exec && cpu_has_avx512f ) + if ( stack_exec && simd_check_avx512f() ) { decl_insn(vmovsd_masked_to_mem); =20 @@ -3197,7 +3207,7 @@ int main(int argc, char **argv) } =20 printf("%-40s", "Testing vmovaps (%edx),%zmm7{%k3}{z}..."); - if ( stack_exec && cpu_has_avx512f ) + if ( stack_exec && simd_check_avx512f() ) { decl_insn(vmovaps_masked_from_mem); =20 @@ -3380,7 +3390,7 @@ int main(int argc, char **argv) printf("skipped\n"); =20 printf("%-40s", "Testing {evex} vmovd %xmm3,32(%ecx)..."); - if ( stack_exec && cpu_has_avx512f ) + if ( stack_exec && simd_check_avx512f() ) { decl_insn(evex_vmovd_to_mem); =20 @@ -3405,7 +3415,7 @@ int main(int argc, char **argv) printf("skipped\n"); =20 printf("%-40s", "Testing {evex} vmovd 32(%ecx),%xmm4..."); - if ( stack_exec && cpu_has_avx512f ) + if ( stack_exec && simd_check_avx512f() ) { decl_insn(evex_vmovd_from_mem); =20 @@ -3595,7 +3605,7 @@ int main(int argc, char **argv) printf("skipped\n"); =20 printf("%-40s", "Testing {evex} vmovd %xmm2,%ebx..."); - if ( stack_exec && cpu_has_avx512f ) + if ( stack_exec && simd_check_avx512f() ) { decl_insn(evex_vmovd_to_reg); =20 @@ -3621,7 +3631,7 @@ int main(int argc, char **argv) printf("skipped\n"); =20 printf("%-40s", "Testing {evex} vmovd %ebx,%xmm1..."); - if ( stack_exec && cpu_has_avx512f ) + if ( stack_exec && simd_check_avx512f() ) { decl_insn(evex_vmovd_from_reg); =20 @@ -3723,7 +3733,7 @@ int main(int argc, char **argv) printf("skipped\n"); =20 printf("%-40s", "Testing {evex} vmovq %xmm11,32(%ecx)..."); - if ( stack_exec && cpu_has_avx512f ) + if ( stack_exec && simd_check_avx512f() ) { decl_insn(evex_vmovq_to_mem2); =20 @@ -3813,7 +3823,7 @@ int main(int argc, char **argv) printf("skipped\n"); =20 printf("%-40s", "Testing vmovq %xmm22,%rbx..."); - if ( stack_exec && cpu_has_avx512f ) + if ( stack_exec && simd_check_avx512f() ) { decl_insn(evex_vmovq_to_reg); =20 @@ -4006,7 +4016,7 @@ int main(int argc, char **argv) printf("skipped\n"); =20 printf("%-40s", "Testing vmovntdqa 64(%ecx),%zmm4..."); - if ( stack_exec && cpu_has_avx512f ) + if ( stack_exec && simd_check_avx512f() ) { decl_insn(evex_vmovntdqa); =20 @@ -4602,7 +4612,7 @@ int main(int argc, char **argv) printf("skipped\n"); =20 printf("%-40s", "Testing vcvtph2ps 32(%ecx),%zmm7{%k4}..."); - if ( stack_exec && cpu_has_avx512f ) + if ( stack_exec && simd_check_avx512f() ) { decl_insn(evex_vcvtph2ps); decl_insn(evex_vcvtps2ph); @@ -4645,7 +4655,7 @@ int main(int argc, char **argv) printf("skipped\n"); =20 printf("%-40s", "Testing vfixupimmpd $0,8(%edx){1to8},%zmm3,%zmm4..."); - if ( stack_exec && cpu_has_avx512f ) + if ( stack_exec && simd_check_avx512f() ) { decl_insn(vfixupimmpd); static const struct { @@ -4684,7 +4694,7 @@ int main(int argc, char **argv) =20 =20 printf("%-40s", "Testing vfpclasspsz $0x46,64(%edx),%k2..."); - if ( stack_exec && cpu_has_avx512dq ) + if ( stack_exec && simd_check_avx512dq() ) { decl_insn(vfpclassps); =20 @@ -4716,7 +4726,7 @@ int main(int argc, char **argv) printf("skipped\n"); =20 printf("%-40s", "Testing vfpclassphz $0x46,128(%ecx),%k3..."); - if ( stack_exec && cpu_has_avx512_fp16 ) + if ( stack_exec && simd_check_avx512fp16() ) { decl_insn(vfpclassph); =20 @@ -4759,7 +4769,7 @@ int main(int argc, char **argv) * on the mapping boundaries) that elements controlled by clear mask * bits don't get accessed. */ - if ( stack_exec && cpu_has_avx512f ) + if ( stack_exec && simd_check_avx512f() ) { decl_insn(vpcompressd); decl_insn(vpcompressq); @@ -4861,7 +4871,7 @@ int main(int argc, char **argv) } =20 #if __GNUC__ > 7 /* can't check for __AVX512VBMI2__ here */ - if ( stack_exec && cpu_has_avx512_vbmi2 ) + if ( stack_exec && simd_check_avx512vbmi2() ) { decl_insn(vpcompressb); decl_insn(vpcompressw); @@ -5049,7 +5059,7 @@ int main(int argc, char **argv) } =20 printf("%-40s", "Testing vpdpwssd (%ecx),%{y,z}mmA,%{y,z}mmB..."); - if ( stack_exec && cpu_has_avx512_vnni && cpu_has_avx_vnni ) + if ( stack_exec && simd_check_avx512vnni() && cpu_has_avx_vnni ) { /* Do the same operation two ways and compare the results. */ decl_insn(vpdpwssd_vex1); @@ -5104,7 +5114,7 @@ int main(int argc, char **argv) printf("skipped\n"); =20 printf("%-40s", "Testing vmovsh 8(%ecx),%xmm5..."); - if ( stack_exec && cpu_has_avx512_fp16 ) + if ( stack_exec && simd_check_avx512fp16() ) { decl_insn(vmovsh_from_mem); decl_insn(vmovw_to_gpr); From nobody Thu Nov 21 21:14:12 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=quarantine dis=none) header.from=suse.com ARC-Seal: i=1; a=rsa-sha256; t=1723625906; cv=none; d=zohomail.com; s=zohoarc; b=creBlu+K30NVsr4dWkhLuughb1tUKDwFfYLQPP7wTVo7F8wnKiicAMNzp6FBhtTuw34YYo0y9NnTg0gmqAFZYzLks+FyMdkv6vmhB2uxgjRt+zKg74FYqpYwTpyiKvJbhsrWbfA+yo9dZ7LE8uwyu++16eqjUdwVa6YItp2TigQ= ARC-Message-Signature: i=1; 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[37.24.206.209]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a80f3f4981dsm149376566b.18.2024.08.14.01.53.16 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 14 Aug 2024 01:53:16 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: a684e2b0-5a1a-11ef-8776-851b0ebba9a2 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=google; t=1723625598; x=1724230398; darn=lists.xenproject.org; h=content-transfer-encoding:in-reply-to:autocrypt:content-language :references:cc:to:from:subject:user-agent:mime-version:date :message-id:from:to:cc:subject:date:message-id:reply-to; bh=D2/zh/bchaIimR3ZyxsWSS2VxTLjlJtCdjnQQPFRqsU=; b=H8sp6iE16iq4oO+XVI9PfmMfNjOTT5eluwBGWOsHUtS09QxEWQhuTPFWqp9+kkkop+ whTTInR+T6T6C6r2QliK7KqQHy34eopKF2gLt8dCVLfaeBvO49JRwqQvonn0fIR8Po3r woOHYCQZqcWUYHrkNxkrfF5+UqjHH8LNvX9U8O0zkvUTGBiPwVLdIIMYkERAA4XJeerX +6L6D4GiGtb46ezUvQXLK4eGmVtN7h4PWCNW9CT5xVasNgwn4AMoX8FeRwVi0OHitWlZ xSBbShN/IFVonFbo4L5v6v5EpK47PVmddymCUHxGTQYRXjzxbNEfSWko6xSZwbKIUujP UVcQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1723625598; x=1724230398; h=content-transfer-encoding:in-reply-to:autocrypt:content-language :references:cc:to:from:subject:user-agent:mime-version:date :message-id:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=D2/zh/bchaIimR3ZyxsWSS2VxTLjlJtCdjnQQPFRqsU=; b=RHjYUcVFwmixC9smjJR/5HB4jqzWCSGTY6BgYg+7n3Ked7fa2Zy49b5jnQeXyd05LT q5M5SnDuPqRroAzGPencay22hPH4FoRhfbEYbQGh+0VzUXE0njVDcCDC5AopipzVqNvc kgovv28E53JsK9i4t/hFhiQBkU6+HJ2BJ41XWaPW+TNjfH2KP12ZVjsGAORVCEkngp0S x0V5KybXS4G2QYe9F7+I7wuJInPaZZmcsmZg87xh0lc/b3zvWJhzSptOTaw+UZPBEhh/ wI0/Jzs0KOe8LvLg/fIk/6R29fKLtJulVsRgmJLZTgvNLblMVdMDrkp3mp2r8XXMohza xkMQ== X-Gm-Message-State: AOJu0YxzTwpkU7cbld4Wj3Vm/t7WCZyM7y3TVOnRjyYYQ5u6YM47Jhnt 2RLr6b32tnGrmiIF6yRv6l4TlC/gC5jWVE+N5deWrMITz6Bi2GzzrR2NLlar6is5pfwWTC9pvKY = X-Google-Smtp-Source: AGHT+IFgKj7V+kkgDhundAx9tQO+8VFSUIZ1P2ZCmJTPRhypVFYeDCV/UpjyI6VC3XW0M+lR87vQgg== X-Received: by 2002:a17:907:e20f:b0:a7a:9144:e256 with SMTP id a640c23a62f3a-a8366c388bamr133984966b.6.1723625597464; Wed, 14 Aug 2024 01:53:17 -0700 (PDT) Message-ID: <4480c5c4-9b97-4fee-b086-22fc1006b7ac@suse.com> Date: Wed, 14 Aug 2024 10:53:15 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH v2 6/9] x86emul/test: drop cpu_has_avx512vl From: Jan Beulich To: "xen-devel@lists.xenproject.org" Cc: Andrew Cooper , Wei Liu , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= References: Content-Language: en-US Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @suse.com) X-ZM-MESSAGEID: 1723625907156116600 Content-Type: text/plain; charset="utf-8" AVX512VL not being a standalone feature anyway, but always needing to be combined with some other AVX512*, replace uses of cpu_has_avx512vl by just the feature bit check. Signed-off-by: Jan Beulich --- v2: Re-base over dropping of Xeon Phi support. --- a/tools/tests/x86_emulator/evex-disp8.c +++ b/tools/tests/x86_emulator/evex-disp8.c @@ -1000,7 +1000,8 @@ static void test_group(const struct test { for ( j =3D 0; j < nr_vl; ++j ) { - if ( vl[0] =3D=3D VL_512 && vl[j] !=3D VL_512 && !cpu_has_avx5= 12vl ) + if ( vl[0] =3D=3D VL_512 && vl[j] !=3D VL_512 && + !cpu_policy.feat.avx512vl ) continue; =20 switch ( tests[i].esz ) --- a/tools/tests/x86_emulator/test_x86_emulator.c +++ b/tools/tests/x86_emulator/test_x86_emulator.c @@ -131,7 +131,7 @@ static bool simd_check_avx512f(void) =20 static bool simd_check_avx512f_vl(void) { - return cpu_has_avx512f && cpu_has_avx512vl; + return cpu_has_avx512f && cpu_policy.feat.avx512vl; } #define simd_check_avx512vl_sg simd_check_avx512f_vl =20 @@ -143,7 +143,7 @@ static bool simd_check_avx512dq(void) =20 static bool simd_check_avx512dq_vl(void) { - return cpu_has_avx512dq && cpu_has_avx512vl; + return cpu_has_avx512dq && cpu_policy.feat.avx512vl; } =20 static bool simd_check_avx512bw(void) @@ -154,7 +154,7 @@ static bool simd_check_avx512bw(void) =20 static bool simd_check_avx512bw_vl(void) { - return cpu_has_avx512bw && cpu_has_avx512vl; + return cpu_has_avx512bw && cpu_policy.feat.avx512vl; } =20 static bool simd_check_avx512vbmi(void) @@ -164,7 +164,7 @@ static bool simd_check_avx512vbmi(void) =20 static bool simd_check_avx512vbmi_vl(void) { - return cpu_has_avx512_vbmi && cpu_has_avx512vl; + return cpu_has_avx512_vbmi && cpu_policy.feat.avx512vl; } =20 static bool simd_check_avx512vbmi2(void) @@ -260,7 +260,7 @@ static bool simd_check_avx512fp16(void) =20 static bool simd_check_avx512fp16_vl(void) { - return cpu_has_avx512_fp16 && cpu_has_avx512vl; + return cpu_has_avx512_fp16 && cpu_policy.feat.avx512vl; } =20 static void simd_set_regs(struct cpu_user_regs *regs) --- a/tools/tests/x86_emulator/x86-emulate.h +++ b/tools/tests/x86_emulator/x86-emulate.h @@ -159,7 +159,6 @@ void wrpkru(unsigned int val); #define cpu_has_avx512cd (cpu_policy.feat.avx512cd && xcr0_mask(0xe6)) #define cpu_has_sha cpu_policy.feat.sha #define cpu_has_avx512bw (cpu_policy.feat.avx512bw && xcr0_mask(0xe6)) -#define cpu_has_avx512vl (cpu_policy.feat.avx512vl && xcr0_mask(0xe6)) #define cpu_has_avx512_vbmi (cpu_policy.feat.avx512_vbmi && xcr0_mask(0xe6= )) #define cpu_has_avx512_vbmi2 (cpu_policy.feat.avx512_vbmi2 && xcr0_mask(0x= e6)) #define cpu_has_gfni cpu_policy.feat.gfni From nobody Thu Nov 21 21:14:12 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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[37.24.206.209]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a80f417fc88sm146204066b.188.2024.08.14.01.53.38 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 14 Aug 2024 01:53:38 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: b31c3d8b-5a1a-11ef-a505-bb4a2ccca743 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=google; t=1723625619; x=1724230419; darn=lists.xenproject.org; h=content-transfer-encoding:in-reply-to:autocrypt:content-language :references:cc:to:from:subject:user-agent:mime-version:date :message-id:from:to:cc:subject:date:message-id:reply-to; bh=qi/Fm+9B9f9VMuCLNtTiSs7SNFkgAwLJFrGTpFHQGfc=; b=WeFppuigx2sTq1xiUX7zNHyo0cjs5TBuV87jg7UBPpmjZ2gyBJjqM3FJ8t12CgyXBn 3iiQmawyCwcPiERin4ciNm00Q5UbBIC/VtIz75V2jfC2wJ9YMJgXcWdWoWUc4UQ/ZdH2 BDXSDO+k21IueB5YfYxOjRnoelvYqEVQVrMZRv+5BlArkGLmHOhhnnda+6R8ZHSxFhDP rA0inMeZ8LF/FaHhBr5X56xzgwsg5XPVxTBRwdlCfZ9R0aW+c7RtSnpTYpcFLJZXNm0O NK8xBroAFodZbdJUCrxU9iV9w/KhQ3IDYtDUgSOeAjCl4whP1Ei2xc1ZRlfIpGE08mUa 2+Sw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1723625619; x=1724230419; h=content-transfer-encoding:in-reply-to:autocrypt:content-language :references:cc:to:from:subject:user-agent:mime-version:date :message-id:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=qi/Fm+9B9f9VMuCLNtTiSs7SNFkgAwLJFrGTpFHQGfc=; b=QRyLvRhpgTq74mwCn3KeX3mRS6l0lOBBMUPq/zoG9HJJHqKdz7eTnhcfCVRkjwigk1 TIvbOCFjho5+zY7R254cSzJW0rOgQ8C6hIlHFZQIsZUD3WLhf3lZIKMAWSXiRYBsuvU1 G7kbz7sMA5y+SxWn3gzguRNlO7QYaYhV1yHB7gYp/8NwMFtIlXw09Xa/SmGufNDkiyPt 4vx1eSp5IZJtN++DLuPNIpIdKr/MbT0vP8Adkt04iY7rvhjZLwzM9glJhhfNvtJoj4hh 2sbDTFieQc4FvmtKbBFkHNk6f/e4QbfHhXhqzuYx6itOrAvEyvIruFerJ3CYCeU3GtoQ tyYQ== X-Gm-Message-State: AOJu0YyO31/N1eIesS0MD/zmYFsIC0V/mnRzCR+58ZGLejQyFVFnSmPU SSncnd9HXQtGz8viNAwz+QilcqJ8OaUsQusozNzrrRL118hb14VwkG9+0JRHXcTIegJ5SXJYXsk = X-Google-Smtp-Source: AGHT+IFgGkn6PNSTmOfTJA+DMN7NFjVSFGH0DV+Xhp2z61yYXHoUhT8dxqNBwJEveRcFniM3w17EBA== X-Received: by 2002:a17:907:d3d2:b0:a7a:aa35:4089 with SMTP id a640c23a62f3a-a8366c34018mr159528866b.24.1723625618616; Wed, 14 Aug 2024 01:53:38 -0700 (PDT) Message-ID: Date: Wed, 14 Aug 2024 10:53:37 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH v2 7/9] x86emul: AVX10.1 testing From: Jan Beulich To: "xen-devel@lists.xenproject.org" Cc: Andrew Cooper , Wei Liu , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= References: Content-Language: en-US Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @suse.com) X-ZM-MESSAGEID: 1723625939237116600 Content-Type: text/plain; charset="utf-8" Re-use respective AVX512 tests, by suitably adjusting the predicate functions. This leaves test names ("Testing ... NN-bit code sequence") somewhat misleading, but I think we can live with that. Note that the AVX512{BW,DQ} opmask tests cannot be run as-is for the AVX10/256 case, as they include 512-bit vector <-> opmask insn tests. Signed-off-by: Jan Beulich --- SDE: -gnr / -gnr256 --- TBD: For AVX10.1/256 need to somehow guarantee that the generated blobs really don't use 512-bit insns (it's uncertain whether passing -mprefer-vector-width=3D is enough). Right now according to my testing on SDE this is all fine. May need to probe for support of the new -mno-evex512 compiler option. The AVX512{BW,DQ} opmask tests could of course be cloned (i.e. rebuilt another time with -mavx512vl passed) accordingly, but the coverage gain wouldbe pretty marginal. --- v2: Drop SDE 9.27.0 workaround. Re-base over dropping of Xeon Phi support. --- a/tools/tests/x86_emulator/evex-disp8.c +++ b/tools/tests/x86_emulator/evex-disp8.c @@ -1001,7 +1001,11 @@ static void test_group(const struct test for ( j =3D 0; j < nr_vl; ++j ) { if ( vl[0] =3D=3D VL_512 && vl[j] !=3D VL_512 && - !cpu_policy.feat.avx512vl ) + !cpu_policy.feat.avx512vl && !cpu_policy.feat.avx10 ) + continue; + + if ( vl[j] =3D=3D VL_512 && !cpu_policy.feat.avx512f && + !cpu_policy.avx10.vsz512 ) continue; =20 switch ( tests[i].esz ) @@ -1052,6 +1056,27 @@ static void test_group(const struct test } } =20 +/* AVX512 (sub)features implied by AVX10. */ +#define avx10_has_avx512f true +#define avx10_has_avx512bw true +#define avx10_has_avx512cd true +#define avx10_has_avx512dq true +#define avx10_has_avx512_bf16 true +#define avx10_has_avx512_bitalg true +#define avx10_has_avx512_fp16 true +#define avx10_has_avx512_ifma true +#define avx10_has_avx512_vbmi true +#define avx10_has_avx512_vbmi2 true +#define avx10_has_avx512_vnni true +#define avx10_has_avx512_vpopcntdq true + +/* AVX512 sub-features /not/ implied by AVX10. */ +#define avx10_has_avx512er false +#define avx10_has_avx512pf false +#define avx10_has_avx512_4fmaps false +#define avx10_has_avx512_4vnniw false +#define avx10_has_avx512_vp2intersect false + void evex_disp8_test(void *instr, struct x86_emulate_ctxt *ctxt, const struct x86_emulate_ops *ops) { @@ -1059,8 +1084,8 @@ void evex_disp8_test(void *instr, struct emulops.read =3D read; emulops.write =3D write; =20 -#define RUN(feat, vl) do { \ - if ( cpu_has_##feat ) \ +#define run(cond, feat, vl) do { \ + if ( cond ) \ { \ printf("%-40s", "Testing " #feat "/" #vl " disp8 handling..."); \ test_group(feat ## _ ## vl, ARRAY_SIZE(feat ## _ ## vl), \ @@ -1069,6 +1094,12 @@ void evex_disp8_test(void *instr, struct } \ } while ( false ) =20 +#define RUN(feat, vl) \ + run(cpu_has_ ## feat || \ + (cpu_has_avx10_1 && cpu_policy.avx10.vsz256 && avx10_has_ ## feat = && \ + (ARRAY_SIZE(vl_ ## vl) > 1 || &vl_ ## vl[0] !=3D &vl_512[0])), \ + feat, vl) + RUN(avx512f, all); RUN(avx512f, 128); RUN(avx512f, no128); @@ -1091,10 +1122,15 @@ void evex_disp8_test(void *instr, struct RUN(avx512_fp16, all); RUN(avx512_fp16, 128); =20 - if ( cpu_has_avx512f ) +#undef RUN + + if ( cpu_has_avx512f || cpu_has_avx10_1 ) { +#define RUN(feat, vl) run(cpu_has_ ## feat, feat, vl) RUN(gfni, all); RUN(vaes, all); RUN(vpclmulqdq, all); +#undef RUN } +#undef run } --- a/tools/tests/x86_emulator/testcase.mk +++ b/tools/tests/x86_emulator/testcase.mk @@ -4,7 +4,27 @@ include $(XEN_ROOT)/tools/Rules.mk =20 $(call cc-options-add,CFLAGS,CC,$(EMBEDDED_EXTRA_CFLAGS)) =20 -CFLAGS +=3D -fno-builtin -g0 $($(TESTCASE)-cflags) +ifneq ($(filter -mavx512%,$($(TESTCASE)-cflags)),) + +cflags-vsz64 :=3D +cflags-vsz32 :=3D -mprefer-vector-width=3D256 +cflags-vsz16 :=3D -mprefer-vector-width=3D128 +# Scalar tests don't set VEC_SIZE (and VEC_MAX is used by S/G ones only) +cflags-vsz :=3D -mprefer-vector-width=3D128 + +ifneq ($(filter -DVEC_SIZE=3D%,$($(TESTCASE)-cflags)),) +CFLAGS-VSZ :=3D $(cflags-vsz$(patsubst -DVEC_SIZE=3D%,%,$(filter -DVEC_SIZ= E=3D%,$($(TESTCASE)-cflags)))) +else +CFLAGS-VSZ :=3D $(cflags-vsz$(patsubst -DVEC_MAX=3D%,%,$(filter -DVEC_MAX= =3D%,$($(TESTCASE)-cflags)))) +endif + +else + +CFLAGS-VSZ :=3D + +endif + +CFLAGS +=3D -fno-builtin -g0 $($(TESTCASE)-cflags) $(CFLAGS-VSZ) =20 LDFLAGS_DIRECT +=3D $(shell { $(LD) -v --warn-rwx-segments; } >/dev/null 2= >&1 && echo --no-warn-rwx-segments) =20 --- a/tools/tests/x86_emulator/test_x86_emulator.c +++ b/tools/tests/x86_emulator/test_x86_emulator.c @@ -124,52 +124,61 @@ static bool simd_check_avx_pclmul(void) =20 static bool simd_check_avx512f(void) { - return cpu_has_avx512f; + return cpu_has_avx512f || cpu_has_avx10_1_512; } -#define simd_check_avx512f_opmask simd_check_avx512f #define simd_check_avx512f_sg simd_check_avx512f =20 +static bool simd_check_avx512f_sc(void) +{ + return cpu_has_avx512f || cpu_has_avx10_1; +} +#define simd_check_avx512f_opmask simd_check_avx512f_sc + static bool simd_check_avx512f_vl(void) { - return cpu_has_avx512f && cpu_policy.feat.avx512vl; + return (cpu_has_avx512f && cpu_policy.feat.avx512vl) || + cpu_has_avx10_1_256; } #define simd_check_avx512vl_sg simd_check_avx512f_vl =20 static bool simd_check_avx512dq(void) { - return cpu_has_avx512dq; + return cpu_has_avx512dq || cpu_has_avx10_1_512; } #define simd_check_avx512dq_opmask simd_check_avx512dq =20 static bool simd_check_avx512dq_vl(void) { - return cpu_has_avx512dq && cpu_policy.feat.avx512vl; + return (cpu_has_avx512dq && cpu_policy.feat.avx512vl) || + cpu_has_avx10_1_256; } =20 static bool simd_check_avx512bw(void) { - return cpu_has_avx512bw; + return cpu_has_avx512bw || cpu_has_avx10_1_512; } #define simd_check_avx512bw_opmask simd_check_avx512bw =20 static bool simd_check_avx512bw_vl(void) { - return cpu_has_avx512bw && cpu_policy.feat.avx512vl; + return (cpu_has_avx512bw && cpu_policy.feat.avx512vl) || + cpu_has_avx10_1_256; } =20 static bool simd_check_avx512vbmi(void) { - return cpu_has_avx512_vbmi; + return cpu_has_avx512_vbmi || cpu_has_avx10_1_512; } =20 static bool simd_check_avx512vbmi_vl(void) { - return cpu_has_avx512_vbmi && cpu_policy.feat.avx512vl; + return (cpu_has_avx512_vbmi && cpu_policy.feat.avx512vl) || + cpu_has_avx10_1_256; } =20 static bool simd_check_avx512vbmi2(void) { - return cpu_has_avx512_vbmi2; + return cpu_has_avx512_vbmi2 || cpu_has_avx10_1_512; } =20 static bool simd_check_sse4_sha(void) @@ -250,17 +259,23 @@ static bool simd_check_avx512bw_gf_vl(vo =20 static bool simd_check_avx512vnni(void) { - return cpu_has_avx512_vnni; + return cpu_has_avx512_vnni || cpu_has_avx10_1_512; } =20 static bool simd_check_avx512fp16(void) { - return cpu_has_avx512_fp16; + return cpu_has_avx512_fp16 || cpu_has_avx10_1_512; +} + +static bool simd_check_avx512fp16_sc(void) +{ + return cpu_has_avx512_fp16 || cpu_has_avx10_1; } =20 static bool simd_check_avx512fp16_vl(void) { - return cpu_has_avx512_fp16 && cpu_policy.feat.avx512vl; + return (cpu_has_avx512_fp16 && cpu_policy.feat.avx512vl) || + cpu_has_avx10_1_256; } =20 static void simd_set_regs(struct cpu_user_regs *regs) @@ -433,9 +448,13 @@ static const struct { SIMD(OPMASK+DQ/w, avx512dq_opmask, 2), SIMD(OPMASK+BW/d, avx512bw_opmask, 4), SIMD(OPMASK+BW/q, avx512bw_opmask, 8), - SIMD(AVX512F f32 scalar, avx512f, f4), +#define avx512f_sc_x86_32_D_f4 avx512f_x86_32_D_f4 +#define avx512f_sc_x86_64_D_f4 avx512f_x86_64_D_f4 + SIMD(AVX512F f32 scalar, avx512f_sc, f4), SIMD(AVX512F f32x16, avx512f, 64f4), - SIMD(AVX512F f64 scalar, avx512f, f8), +#define avx512f_sc_x86_32_D_f8 avx512f_x86_32_D_f8 +#define avx512f_sc_x86_64_D_f8 avx512f_x86_64_D_f8 + SIMD(AVX512F f64 scalar, avx512f_sc, f8), SIMD(AVX512F f64x8, avx512f, 64f8), SIMD(AVX512F s32x16, avx512f, 64i4), SIMD(AVX512F u32x16, avx512f, 64u4), @@ -523,7 +542,9 @@ static const struct { AVX512VL(_VBMI+VL u16x8, avx512vbmi, 16u2), AVX512VL(_VBMI+VL s16x16, avx512vbmi, 32i2), AVX512VL(_VBMI+VL u16x16, avx512vbmi, 32u2), - SIMD(AVX512_FP16 f16 scal,avx512fp16, f2), +#define avx512fp16_sc_x86_32_D_f2 avx512fp16_x86_32_D_f2 +#define avx512fp16_sc_x86_64_D_f2 avx512fp16_x86_64_D_f2 + SIMD(AVX512_FP16 f16 scal,avx512fp16_sc, f2), SIMD(AVX512_FP16 f16x32, avx512fp16, 64f2), AVX512VL(_FP16+VL f16x8, avx512fp16, 16f2), AVX512VL(_FP16+VL f16x16,avx512fp16, 32f2), @@ -2810,7 +2831,7 @@ int main(int argc, char **argv) printf("skipped\n"); =20 printf("%-40s", "Testing {evex} vmovq %xmm1,32(%edx)..."); - if ( stack_exec && simd_check_avx512f() ) + if ( stack_exec && simd_check_avx512f_sc() ) { decl_insn(evex_vmovq_to_mem); =20 @@ -2834,7 +2855,7 @@ int main(int argc, char **argv) printf("skipped\n"); =20 printf("%-40s", "Testing {evex} vmovq 32(%edx),%xmm0..."); - if ( stack_exec && simd_check_avx512f() ) + if ( stack_exec && simd_check_avx512f_sc() ) { decl_insn(evex_vmovq_from_mem); =20 @@ -2846,11 +2867,22 @@ int main(int argc, char **argv) rc =3D x86_emulate(&ctxt, &emulops); if ( rc !=3D X86EMUL_OKAY || !check_eip(evex_vmovq_from_mem) ) goto fail; - asm ( "vmovq %1, %%xmm1\n\t" - "vpcmpeqq %%zmm0, %%zmm1, %%k0\n" - "kmovw %%k0, %0" : "=3Dr" (rc) : "m" (res[8]) ); - if ( rc !=3D 0xff ) - goto fail; + if ( simd_check_avx512f() ) + { + asm ( "vmovq %1, %%xmm1\n\t" + "vpcmpeqq %%zmm0, %%zmm1, %%k0\n" + "kmovw %%k0, %0" : "=3Dr" (rc) : "m" (res[8]) ); + if ( rc !=3D 0x00ff ) + goto fail; + } + else + { + asm ( "vmovq %1, %%xmm1\n\t" + "vpcmpeqq %%xmm0, %%xmm1, %%k0\n" + "kmovb %%k0, %0" : "=3Dr" (rc) : "m" (res[8]) ); + if ( rc !=3D 0x03 ) + goto fail; + } printf("okay\n"); } else @@ -3172,7 +3204,7 @@ int main(int argc, char **argv) printf("%-40s", "Testing vmovsd %xmm5,16(%ecx){%k3}..."); memset(res, 0x88, 128); memset(res + 20, 0x77, 8); - if ( stack_exec && simd_check_avx512f() ) + if ( stack_exec && simd_check_avx512f_sc() ) { decl_insn(vmovsd_masked_to_mem); =20 @@ -3390,7 +3422,7 @@ int main(int argc, char **argv) printf("skipped\n"); =20 printf("%-40s", "Testing {evex} vmovd %xmm3,32(%ecx)..."); - if ( stack_exec && simd_check_avx512f() ) + if ( stack_exec && simd_check_avx512f_sc() ) { decl_insn(evex_vmovd_to_mem); =20 @@ -3415,7 +3447,7 @@ int main(int argc, char **argv) printf("skipped\n"); =20 printf("%-40s", "Testing {evex} vmovd 32(%ecx),%xmm4..."); - if ( stack_exec && simd_check_avx512f() ) + if ( stack_exec && simd_check_avx512f_sc() ) { decl_insn(evex_vmovd_from_mem); =20 @@ -3428,11 +3460,22 @@ int main(int argc, char **argv) rc =3D x86_emulate(&ctxt, &emulops); if ( rc !=3D X86EMUL_OKAY || !check_eip(evex_vmovd_from_mem) ) goto fail; - asm ( "vmovd %1, %%xmm0\n\t" - "vpcmpeqd %%zmm4, %%zmm0, %%k0\n\t" - "kmovw %%k0, %0" : "=3Dr" (rc) : "m" (res[8]) ); - if ( rc !=3D 0xffff ) - goto fail; + if ( simd_check_avx512f() ) + { + asm ( "vmovd %1, %%xmm0\n\t" + "vpcmpeqd %%zmm4, %%zmm0, %%k0\n\t" + "kmovw %%k0, %0" : "=3Dr" (rc) : "m" (res[8]) ); + if ( rc !=3D 0xffff ) + goto fail; + } + else + { + asm ( "vmovd %1, %%xmm0\n\t" + "vpcmpeqd %%xmm4, %%xmm0, %%k0\n\t" + "kmovb %%k0, %0" : "=3Dr" (rc) : "m" (res[8]) ); + if ( rc !=3D 0x0f ) + goto fail; + } printf("okay\n"); } else @@ -3605,7 +3648,7 @@ int main(int argc, char **argv) printf("skipped\n"); =20 printf("%-40s", "Testing {evex} vmovd %xmm2,%ebx..."); - if ( stack_exec && simd_check_avx512f() ) + if ( stack_exec && simd_check_avx512f_sc() ) { decl_insn(evex_vmovd_to_reg); =20 @@ -3631,7 +3674,7 @@ int main(int argc, char **argv) printf("skipped\n"); =20 printf("%-40s", "Testing {evex} vmovd %ebx,%xmm1..."); - if ( stack_exec && simd_check_avx512f() ) + if ( stack_exec && simd_check_avx512f_sc() ) { decl_insn(evex_vmovd_from_reg); =20 @@ -3645,11 +3688,22 @@ int main(int argc, char **argv) rc =3D x86_emulate(&ctxt, &emulops); if ( (rc !=3D X86EMUL_OKAY) || !check_eip(evex_vmovd_from_reg) ) goto fail; - asm ( "vmovd %1, %%xmm0\n\t" - "vpcmpeqd %%zmm1, %%zmm0, %%k0\n\t" - "kmovw %%k0, %0" : "=3Dr" (rc) : "m" (res[8]) ); - if ( rc !=3D 0xffff ) - goto fail; + if ( simd_check_avx512f() ) + { + asm ( "vmovd %1, %%xmm0\n\t" + "vpcmpeqd %%zmm1, %%zmm0, %%k0\n\t" + "kmovw %%k0, %0" : "=3Dr" (rc) : "m" (res[8]) ); + if ( rc !=3D 0xffff ) + goto fail; + } + else + { + asm ( "vmovd %1, %%xmm0\n\t" + "vpcmpeqd %%xmm1, %%xmm0, %%k0\n\t" + "kmovb %%k0, %0" : "=3Dr" (rc) : "m" (res[8]) ); + if ( rc !=3D 0x0f ) + goto fail; + } printf("okay\n"); } else @@ -3733,7 +3787,7 @@ int main(int argc, char **argv) printf("skipped\n"); =20 printf("%-40s", "Testing {evex} vmovq %xmm11,32(%ecx)..."); - if ( stack_exec && simd_check_avx512f() ) + if ( stack_exec && simd_check_avx512f_sc() ) { decl_insn(evex_vmovq_to_mem2); =20 @@ -3823,7 +3877,7 @@ int main(int argc, char **argv) printf("skipped\n"); =20 printf("%-40s", "Testing vmovq %xmm22,%rbx..."); - if ( stack_exec && simd_check_avx512f() ) + if ( stack_exec && simd_check_avx512f_sc() ) { decl_insn(evex_vmovq_to_reg); =20 @@ -5114,7 +5168,7 @@ int main(int argc, char **argv) printf("skipped\n"); =20 printf("%-40s", "Testing vmovsh 8(%ecx),%xmm5..."); - if ( stack_exec && simd_check_avx512fp16() ) + if ( stack_exec && simd_check_avx512fp16_sc() ) { decl_insn(vmovsh_from_mem); decl_insn(vmovw_to_gpr); @@ -5132,14 +5186,28 @@ int main(int argc, char **argv) rc =3D x86_emulate(&ctxt, &emulops); if ( (rc !=3D X86EMUL_OKAY) || !check_eip(vmovsh_from_mem) ) goto fail; - asm volatile ( "kmovw %2, %%k1\n\t" - "vmovdqu16 %1, %%zmm4%{%%k1%}%{z%}\n\t" - "vpcmpeqw %%zmm4, %%zmm5, %%k0\n\t" - "kmovw %%k0, %0" - : "=3Dg" (rc) - : "m" (res[2]), "r" (1) ); - if ( rc !=3D 0xffff ) - goto fail; + if ( simd_check_avx512fp16() ) + { + asm volatile ( "kmovw %2, %%k1\n\t" + "vmovdqu16 %1, %%zmm4%{%%k1%}%{z%}\n\t" + "vpcmpeqw %%zmm4, %%zmm5, %%k0\n\t" + "kmovw %%k0, %0" + : "=3Dg" (rc) + : "m" (res[2]), "r" (1) ); + if ( rc !=3D 0xffff ) + goto fail; + } + else + { + asm volatile ( "kmovb %2, %%k1\n\t" + "vmovdqu16 %1, %%xmm4%{%%k1%}%{z%}\n\t" + "vpcmpeqw %%xmm4, %%xmm5, %%k0\n\t" + "kmovb %%k0, %0" + : "=3Dg" (rc) + : "m" (res[2]), "r" (1) ); + if ( rc !=3D 0xff ) + goto fail; + } printf("okay\n"); =20 printf("%-40s", "Testing vmovsh %xmm4,2(%eax){%k3}..."); --- a/tools/tests/x86_emulator/x86-emulate.c +++ b/tools/tests/x86_emulator/x86-emulate.c @@ -240,7 +240,7 @@ int emul_test_get_fpu( break; case X86EMUL_FPU_opmask: case X86EMUL_FPU_zmm: - if ( cpu_has_avx512f ) + if ( cpu_has_avx512f || cpu_has_avx10_1 ) break; default: return X86EMUL_UNHANDLEABLE; --- a/tools/tests/x86_emulator/x86-emulate.h +++ b/tools/tests/x86_emulator/x86-emulate.h @@ -181,6 +181,12 @@ void wrpkru(unsigned int val); #define cpu_has_avx_vnni_int8 (cpu_policy.feat.avx_vnni_int8 && xcr0_mask(= 6)) #define cpu_has_avx_ne_convert (cpu_policy.feat.avx_ne_convert && xcr0_mas= k(6)) #define cpu_has_avx_vnni_int16 (cpu_policy.feat.avx_vnni_int16 && xcr0_mas= k(6)) + /* TBD: Is bit 6 (ZMM_Hi256) really needed here= ? */ +#define cpu_has_avx10_1 (cpu_policy.feat.avx10 && xcr0_mask(0xe6)) +#define cpu_has_avx10_1_256 (cpu_has_avx10_1 && \ + (cpu_policy.avx10.vsz256 || \ + cpu_policy.avx10.vsz512)) +#define cpu_has_avx10_1_512 (cpu_has_avx10_1 && cpu_policy.avx10.vsz512) =20 #define cpu_has_xgetbv1 (cpu_has_xsave && cpu_policy.xstate.xgetbv1) From nobody Thu Nov 21 21:14:12 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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[37.24.206.209]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5bd187f3306sm3672671a12.17.2024.08.14.01.53.56 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 14 Aug 2024 01:53:56 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: be14fb1c-5a1a-11ef-a505-bb4a2ccca743 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=google; t=1723625637; x=1724230437; darn=lists.xenproject.org; h=content-transfer-encoding:in-reply-to:autocrypt:content-language :references:cc:to:from:subject:user-agent:mime-version:date :message-id:from:to:cc:subject:date:message-id:reply-to; bh=VGSyTsew86/TrCcru/Rk7R/2beYcoXHkI1pXLpAyXsw=; b=cFwoTxsJOf6h//TszOXsk553mQ7qFbylgD6q9a1XeuNTqO9221CN6Ua6/NuLoy5+Jo 1t6VWwXsThdhhRiYGq5l1MZLzhf9uQqqYVn21id9gJFxexNOFDLVbAw+JNwbD12dR7S9 9lIDDV5nSOS2Z1OmKBtieTCrD4aKgMc7vFVel2VcWoPxTL6yUpXF0E2Dln9D4dG8kNeL SDZyqBtyRMXSXvF+3VtXYrduKQ+hM+6iGRZLrQ+NonNPqs/mr5qnUZy2ERCIBsdieay1 c1Nxd5nZfTM/2J1SLDsMeS9QF7816y+9RKN3wL9GWolQYz/ZBoE6ByfJP9A1RIXxO81l rVBw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1723625637; x=1724230437; h=content-transfer-encoding:in-reply-to:autocrypt:content-language :references:cc:to:from:subject:user-agent:mime-version:date :message-id:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=VGSyTsew86/TrCcru/Rk7R/2beYcoXHkI1pXLpAyXsw=; b=AUEMv/o88rWTLYvkt2zQ3EdGR4RBIhmhRYTK/Uf4pjAdNRx+nYI0fFWc1eMfsWaVNJ xc5paLw4Hx/GlTsbmAbR4gi78IhLDSajnlmBoSE6wIgmZUvGvCutsLJwUQt662UulJxc Dc8kkvxuE9IOMD8JD32lldym7SAwmyiVPXAhJwKZv2zPakP9KgJG8wbVtbxKq5BZ6Clu 9mWjWmFP641X03viIc9jkPGou9b0xQtTGMWLTZZ5Vuu7TKEzO/AsCbggzsW0gPcemigG GZbWBwzLKVOxB1xa5PEUsWZJ2bUuvNh8j8a5crT6K4HPyaeVyJli4l1ec5RmyhM/DX6G yahA== X-Gm-Message-State: AOJu0YyX0LsV4jyWUGdFfneuAlKClZDCaeWhK/UoruvkfEN0iOn1Ai60 KoA4VOK1e9urnJMWX92h4eJwBbftT8xrst6e0MWfC+wSnebav43bYoYkyz3FRgMXKbzEJB+ZGK4 = X-Google-Smtp-Source: AGHT+IE68HR9zPeYJqpC26k+G87WcAmTROyAjMQ85LwKkgJVPau3FH01EvgH8hL4JVtRtVOGkObRrQ== X-Received: by 2002:a05:6402:1e91:b0:5a3:a4d7:caf5 with SMTP id 4fb4d7f45d1cf-5bea1cb3857mr1555308a12.36.1723625637144; Wed, 14 Aug 2024 01:53:57 -0700 (PDT) Message-ID: <1791dda8-694b-4ef9-b8f7-86f1eeca7719@suse.com> Date: Wed, 14 Aug 2024 10:53:55 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH v2 8/9] x86emul/test: engage AVX512VL via command line option From: Jan Beulich To: "xen-devel@lists.xenproject.org" Cc: Andrew Cooper , Wei Liu , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= References: Content-Language: en-US Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @suse.com) X-ZM-MESSAGEID: 1723625893035116600 Content-Type: text/plain; charset="utf-8" Now that we have machinery in testcase.mk to set vector length dependent flags for AVX512 tests, let's avoid using a pragma to enable AVX512VL insns for the compiler. This way, correct settings are in place from the very beginning of compilation. No change to the generated test blobs, and hence no functional change. Signed-off-by: Jan Beulich --- a/tools/tests/x86_emulator/simd.h +++ b/tools/tests/x86_emulator/simd.h @@ -215,10 +215,6 @@ DECL_OCTET(half); # define __builtin_ia32_shuf_i32x4_512_mask __builtin_ia32_shuf_i32x4_mask # define __builtin_ia32_shuf_i64x2_512_mask __builtin_ia32_shuf_i64x2_mask =20 -# if VEC_SIZE > ELEM_SIZE && (defined(VEC_MAX) ? VEC_MAX : VEC_SIZE) < 64 -# pragma GCC target ( "avx512vl" ) -# endif - # define REN(insn, old, new) \ asm ( ".macro v" #insn #old " o:vararg \n\t" \ "v" #insn #new " \\o \n\t" \ --- a/tools/tests/x86_emulator/testcase.mk +++ b/tools/tests/x86_emulator/testcase.mk @@ -7,8 +7,8 @@ $(call cc-options-add,CFLAGS,CC,$(EMBEDD ifneq ($(filter -mavx512%,$($(TESTCASE)-cflags)),) =20 cflags-vsz64 :=3D -cflags-vsz32 :=3D -mprefer-vector-width=3D256 -cflags-vsz16 :=3D -mprefer-vector-width=3D128 +cflags-vsz32 :=3D -mavx512vl -mprefer-vector-width=3D256 +cflags-vsz16 :=3D -mavx512vl -mprefer-vector-width=3D128 # Scalar tests don't set VEC_SIZE (and VEC_MAX is used by S/G ones only) cflags-vsz :=3D -mprefer-vector-width=3D128 From nobody Thu Nov 21 21:14:12 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=quarantine dis=none) header.from=suse.com ARC-Seal: i=1; a=rsa-sha256; t=1723625686; cv=none; d=zohomail.com; s=zohoarc; b=jJVD7ACvjspEMCwsHs46HzsPUyvdSqsxgObuHWEqlbOfzVaXmLscVdlSI/c1zwJiNZbTMpgmd4JO+e6ZLtMoVDmrQ1pYisReK4+Qk7fmNHeo3Plf/tlHZmh5PBET2BjxMaGqPgJNn6rqgf5A1M+UIDQRioVKGUdOfM+IySrKm6Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1723625686; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=VEMbn57k+IX3mUL6ZJ4mDTAe8F4l+MGuoPMbxvAr1xg=; b=LGnxKy9S9mIuo1IcD+6CbsJ47m681BuApB5MwSt4JgONK2HltinX4akocYVVNEmzkMnbA4/EWiEhwzjU0bfk2w/vIdNDoXVNdfr+e7E2eF1C0QUZxyLMwNr9fG9gL5M1jt0R7Rry0su39jchlYtnASwJWwDzPCt+qVlVKM5QT/o= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=quarantine dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1723625686394977.7535706743399; Wed, 14 Aug 2024 01:54:46 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.776951.1187155 (Exim 4.92) (envelope-from ) id 1se9m4-0006nm-Hw; Wed, 14 Aug 2024 08:54:32 +0000 Received: by outflank-mailman (output) from mailman id 776951.1187155; Wed, 14 Aug 2024 08:54:32 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1se9m4-0006nf-FL; Wed, 14 Aug 2024 08:54:32 +0000 Received: by outflank-mailman (input) for mailman id 776951; Wed, 14 Aug 2024 08:54:31 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1se9m3-0006nV-51 for xen-devel@lists.xenproject.org; Wed, 14 Aug 2024 08:54:31 +0000 Received: from mail-ed1-x534.google.com (mail-ed1-x534.google.com [2a00:1450:4864:20::534]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id d0cd9e20-5a1a-11ef-8776-851b0ebba9a2; Wed, 14 Aug 2024 10:54:29 +0200 (CEST) Received: by mail-ed1-x534.google.com with SMTP id 4fb4d7f45d1cf-5bd13ea7604so5082465a12.1 for ; Wed, 14 Aug 2024 01:54:29 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. [37.24.206.209]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5beadd60ca1sm253121a12.8.2024.08.14.01.54.28 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 14 Aug 2024 01:54:28 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: d0cd9e20-5a1a-11ef-8776-851b0ebba9a2 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=google; t=1723625669; x=1724230469; darn=lists.xenproject.org; h=content-transfer-encoding:in-reply-to:autocrypt:content-language :references:cc:to:from:subject:user-agent:mime-version:date :message-id:from:to:cc:subject:date:message-id:reply-to; bh=VEMbn57k+IX3mUL6ZJ4mDTAe8F4l+MGuoPMbxvAr1xg=; b=AFJ3j9yqajvsLThckgbYyCkpMTUiTwrgjLHrmpnUmNECObAc9z5mxDvITljwjoohtx Rvg1LL/wE0ILSNJx0lJ2iGNl1yvyLD2Q52E4Kbwz6vMAPbDwtQAVrRc/MKKVYKKxyyFg i/49M/BD6qTilMmtdAgtxuul+1WhmhZtWYG/spZJPPhtJyXkGL2HGjPQ1WgN1YuXQpyX AN5BNg2rkBMXa3ob1GQnK3gccZhNTKS6J3s5qJ4O5UUHC9yTp/1xofCI0GmvhzOlO3VT X0WLJOk9/TIQeWnLxoB1QYqZ5SSalYBKV0chEm2h+hBglX/oZeNveg7HlU/Gw6K9pNew /+bw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1723625669; x=1724230469; h=content-transfer-encoding:in-reply-to:autocrypt:content-language :references:cc:to:from:subject:user-agent:mime-version:date :message-id:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=VEMbn57k+IX3mUL6ZJ4mDTAe8F4l+MGuoPMbxvAr1xg=; b=wnJECOVOEEyTkOzBjtb4bVnT2Vc1O2N8LRpOTXkGiprra8OfHWix3bs8UbmksVCr2f OOy1V2G3BQ3eUUYuvAD9/XEBZ49s0jfo2IgtziREb1QukwndsqxYTZii/Ugfjbhzxg3v CQVYgDQsNdroQa0GuNi3IFPSDxFvEZzW4UEU4NiK/QCfwU2vTIVXoa02Q2v/6QBmQXEj 5p6zNvflnHHwBJ8927HMi69NA8QUCKsnNgjOct+hlF0NjBCtZUaCXibbwoW1uYKhT0xs lSPztz3IH1fDII+CcyN2GpLheRLJWZqfQUXrPZ4fHdQpU5dmDk7y/L2+yL6musLQ8NRJ B+zQ== X-Gm-Message-State: AOJu0YxzlUXnFy2WR6tltiAmqyiilQ+dd9YrhsfdB5abX7en5hZNp7mv hLOc/jQ0Ob+cmE/wayPK5B5iqn7JlfGds/lctWStjlubzEYIwVtTLZ4K9s5dDyQTqZQTAocgZ8E = X-Google-Smtp-Source: AGHT+IFBudeW5U9jWYxBouE8CiPLodiB68nvHdXzAUYvXOmhVFSI3KqW4rHDceWL0EOFvSBGurXgbg== X-Received: by 2002:a05:6402:34d2:b0:5a0:e4a6:b3c9 with SMTP id 4fb4d7f45d1cf-5bea1c6ab94mr1303154a12.7.1723625668549; Wed, 14 Aug 2024 01:54:28 -0700 (PDT) Message-ID: <3a72e8f6-926f-4492-b310-df96f279a2b7@suse.com> Date: Wed, 14 Aug 2024 10:54:27 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH v2 9/9] x86emul: support AVX10.2 256-bit embedded rounding / SAE From: Jan Beulich To: "xen-devel@lists.xenproject.org" Cc: Andrew Cooper , Wei Liu , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= References: Content-Language: en-US Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @suse.com) X-ZM-MESSAGEID: 1723625688236116600 Content-Type: text/plain; charset="utf-8" AVX10.2 (along with APX) assigns new meaning to the bit that previsouly distinguished EVEX from the Phi co-processor's MVEX. Therefore evex_encoded() now needs to key off of something else: Use the opcode mapping field for this, leveraging that map 0 has no assigned opcodes (and appears unlikely to gain any). Place the check of EVEX.U such that it'll cover all insns. EVEX.b is being checked for individual insns as applicable - whenever that's valid for (register-only) 512-bit forms, it becomes valid for 256-bit forms as well when AVX10.2 is permitted for a guest. Signed-off-by: Jan Beulich --- To raise the question early: It is entirely unclear to me how we want to allow control over the AVX10 minor version number from guest configs, as that's not a boolean field and hence not suitable for simple bit-wise masking of feature sets. --- v2: New. --- a/xen/arch/x86/x86_emulate/decode.c +++ b/xen/arch/x86/x86_emulate/decode.c @@ -16,7 +16,7 @@ # define ERR_PTR(val) NULL #endif =20 -#define evex_encoded() (s->evex.mbs) +#define evex_encoded() (s->evex.opcx) =20 struct x86_emulate_state * x86_decode_insn( @@ -1179,8 +1179,15 @@ int x86emul_decode(struct x86_emulate_st s->evex.raw[1] =3D s->vex.raw[1]; s->evex.raw[2] =3D insn_fetch_type(uint8_t); =20 - generate_exception_if(!s->evex.mbs || s->evex.mbz,= X86_EXC_UD); - generate_exception_if(!s->evex.opmsk && s->evex.z,= X86_EXC_UD); + /* + * .opcx is being checked here just to be on the s= afe + * side, especially as long as evex_encoded() uses + * this field. + */ + generate_exception_if(s->evex.mbz || !s->evex.opcx, + X86_EXC_UD); + generate_exception_if(!s->evex.opmsk && s->evex.z, + X86_EXC_UD); =20 if ( !mode_64bit() ) s->evex.R =3D 1; @@ -1758,6 +1765,12 @@ int x86emul_decode(struct x86_emulate_st if ( override_seg !=3D x86_seg_none ) s->ea.mem.seg =3D override_seg; =20 + generate_exception_if((evex_encoded() && + !s->evex.u && + (s->modrm_mod !=3D 3 || + !vcpu_has_avx10(2) || !s->evex.brs)), + X86_EXC_UD); + /* Fetch the immediate operand, if present. */ switch ( d & SrcMask ) { --- a/xen/arch/x86/x86_emulate/private.h +++ b/xen/arch/x86/x86_emulate/private.h @@ -221,7 +221,7 @@ union evex { uint8_t x:1; /* X */ uint8_t r:1; /* R */ uint8_t pfx:2; /* pp */ - uint8_t mbs:1; + uint8_t u:1; /* U */ uint8_t reg:4; /* vvvv */ uint8_t w:1; /* W */ uint8_t opmsk:3; /* aaa */ @@ -582,6 +582,8 @@ amd_like(const struct x86_emulate_ctxt * #define vcpu_has_avx_ne_convert() (ctxt->cpuid->feat.avx_ne_convert) #define vcpu_has_avx_vnni_int16() (ctxt->cpuid->feat.avx_vnni_int16) =20 +#define vcpu_has_avx10(minor) (ctxt->cpuid->avx10.version >=3D (minor)) + #define vcpu_must_have(feat) \ generate_exception_if(!vcpu_has_##feat(), X86_EXC_UD) =20 --- a/xen/arch/x86/x86_emulate/x86_emulate.c +++ b/xen/arch/x86/x86_emulate/x86_emulate.c @@ -1240,7 +1240,7 @@ int cf_check x86emul_unhandleable_rw( #define lock_prefix (state->lock_prefix) #define vex (state->vex) #define evex (state->evex) -#define evex_encoded() (evex.mbs) +#define evex_encoded() (evex.opcx) #define ea (state->ea) =20 /* Undo DEBUG wrapper. */