From nobody Sat Nov 23 03:44:39 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail(p=quarantine dis=quarantine) header.from=epam.com ARC-Seal: i=1; a=rsa-sha256; t=1717414397; cv=none; d=zohomail.com; s=zohoarc; b=SwB7G6JXiLUK3AgfYQ3HT09o9tQ/JyIfGokNijp1ZA3fomuexosg9SSX5YztSza1XYd7pcsCMOJZqWR2zGjlq7vkk0Jw4B3W7VoE0Va4zDqyrNtjGfY801nGK7UJZp03HzSVISTDiHIKWJCpoWCE0nT68+R34DuBhDPgwpn62i8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1717414397; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=6nYuvDbHrOaqkVtwQGUD8Woo9bW0XXOdPiJR9aABHMY=; b=MkL+6qKW8lTwQigFPgUYYbJWeH9d14UonLtf2RjMQP74EwsEiRrTymYeynR22WTFGANcgX6X25NPt7JpY6U8M6CLDmuHTUUvKVCE1z3nBWyucbT+jskCIueyfHVCnD4pPTPP0w8WgCGQRnKUKaianSig2CIDBma6yQHss+1j2A4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail header.from= (p=quarantine dis=quarantine) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 171741439736572.59508611733281; Mon, 3 Jun 2024 04:33:17 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.734878.1140997 (Exim 4.92) (envelope-from ) id 1sE5vv-0001tz-2M; Mon, 03 Jun 2024 11:32:59 +0000 Received: by outflank-mailman (output) from mailman id 734878.1140997; Mon, 03 Jun 2024 11:32:59 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1sE5vu-0001ts-VJ; Mon, 03 Jun 2024 11:32:58 +0000 Received: by outflank-mailman (input) for mailman id 734878; Mon, 03 Jun 2024 11:32:57 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1sE5vt-0001tR-Je for xen-devel@lists.xenproject.org; Mon, 03 Jun 2024 11:32:57 +0000 Received: from pb-smtp2.pobox.com (pb-smtp2.pobox.com [64.147.108.71]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 03e42810-219d-11ef-b4bb-af5377834399; Mon, 03 Jun 2024 13:32:54 +0200 (CEST) Received: from pb-smtp2.pobox.com (unknown [127.0.0.1]) by pb-smtp2.pobox.com (Postfix) with ESMTP id 9F1E42A952; Mon, 3 Jun 2024 07:32:52 -0400 (EDT) (envelope-from sakib@darkstar.site) Received: from pb-smtp2.nyi.icgroup.com (unknown [127.0.0.1]) by pb-smtp2.pobox.com (Postfix) with ESMTP id 954432A951; Mon, 3 Jun 2024 07:32:52 -0400 (EDT) (envelope-from sakib@darkstar.site) Received: from localhost (unknown [185.130.54.75]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by pb-smtp2.pobox.com (Postfix) with ESMTPSA id C5AB22A950; Mon, 3 Jun 2024 07:32:51 -0400 (EDT) (envelope-from sakib@darkstar.site) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 03e42810-219d-11ef-b4bb-af5377834399 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed; d=pobox.com; h=from:to:cc :subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; s=sasl; bh=qFt1GhHtKwmXz/WKqzqf/F4up h4obWVv/1gPxRugSAk=; b=eb/w/s2vBAl1xjuLGLhjiOsOKxouCwL4tCmyPuNr4 s1tVy5bcyujmGfgxPFTy1dwn0MDaMpN+BwVG4rD+PXRwZB1oJU9AqHZ9qN9CpRq0 sNwmfOpNyAp3UM4gOoNlXy7GX/cm1nhomnFHH+rwaG28E/bf732DDkGHyNDLJz6M bs= From: Sergiy Kibrik To: xen-devel@lists.xenproject.org Cc: Sergiy Kibrik , Jan Beulich , Andrew Cooper , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini , Xenia Ragiadakou Subject: [XEN PATCH v3 13/16] x86/vpmu: guard calls to vmx/svm functions Date: Mon, 3 Jun 2024 14:32:49 +0300 Message-Id: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-Pobox-Relay-ID: 03271692-219D-11EF-AFD9-6488940A682E-90055647!pb-smtp2.pobox.com Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @pobox.com) X-ZM-MESSAGEID: 1717414398005100005 Content-Type: text/plain; charset="utf-8" If VMX/SVM disabled in the build, we may still want to have vPMU drivers for PV guests. Yet in such case before using VMX/SVM features and functions we = have to explicitly check if they're available in the build. For this puspose (and also not to complicate conditionals) two helpers introduced -- is_{vmx,svm}_vcpu(v) that check both HVM & VMX/SVM conditions at the same t= ime, and they replace is_hvm_vcpu(v) macro where needed. Signed-off-by: Sergiy Kibrik --- changes in v3: - introduced macro is_{vmx,svm}_vcpu(v) - changed description - reordered patch, do not modify conditionals w/ cpu_has_vmx_msr_bitmap ch= eck --- xen/arch/x86/cpu/vpmu_amd.c | 9 +++++---- xen/arch/x86/cpu/vpmu_intel.c | 16 +++++++++------- 2 files changed, 14 insertions(+), 11 deletions(-) diff --git a/xen/arch/x86/cpu/vpmu_amd.c b/xen/arch/x86/cpu/vpmu_amd.c index 97e6315bd9..217501ecd3 100644 --- a/xen/arch/x86/cpu/vpmu_amd.c +++ b/xen/arch/x86/cpu/vpmu_amd.c @@ -27,6 +27,7 @@ #define is_pmu_enabled(msr) ((msr) & (1ULL << MSR_F10H_EVNTSEL_EN_SHIFT)) #define set_guest_mode(msr) ((msr) |=3D (1ULL << MSR_F10H_EVNTSEL_GO_SHIFT= )) #define is_overflowed(msr) (!((msr) & (1ULL << (MSR_F10H_COUNTER_LENGTH - = 1)))) +#define is_svm_vcpu(v) (using_svm && is_hvm_vcpu(v)) =20 static unsigned int __read_mostly num_counters; static const u32 __read_mostly *counters; @@ -289,7 +290,7 @@ static int cf_check amd_vpmu_save(struct vcpu *v, bool= to_guest) =20 context_save(v); =20 - if ( !vpmu_is_set(vpmu, VPMU_RUNNING) && is_hvm_vcpu(v) && + if ( !vpmu_is_set(vpmu, VPMU_RUNNING) && is_svm_vcpu(v) && is_msr_bitmap_on(vpmu) ) amd_vpmu_unset_msr_bitmap(v); =20 @@ -363,7 +364,7 @@ static int cf_check amd_vpmu_do_wrmsr(unsigned int msr,= uint64_t msr_content) return 0; vpmu_set(vpmu, VPMU_RUNNING); =20 - if ( is_hvm_vcpu(v) && is_msr_bitmap_on(vpmu) ) + if ( is_svm_vcpu(v) && is_msr_bitmap_on(vpmu) ) amd_vpmu_set_msr_bitmap(v); } =20 @@ -372,7 +373,7 @@ static int cf_check amd_vpmu_do_wrmsr(unsigned int msr,= uint64_t msr_content) (is_pmu_enabled(msr_content) =3D=3D 0) && vpmu_is_set(vpmu, VPMU_R= UNNING) ) { vpmu_reset(vpmu, VPMU_RUNNING); - if ( is_hvm_vcpu(v) && is_msr_bitmap_on(vpmu) ) + if ( is_svm_vcpu(v) && is_msr_bitmap_on(vpmu) ) amd_vpmu_unset_msr_bitmap(v); release_pmu_ownership(PMU_OWNER_HVM); } @@ -415,7 +416,7 @@ static void cf_check amd_vpmu_destroy(struct vcpu *v) { struct vpmu_struct *vpmu =3D vcpu_vpmu(v); =20 - if ( is_hvm_vcpu(v) && is_msr_bitmap_on(vpmu) ) + if ( is_svm_vcpu(v) && is_msr_bitmap_on(vpmu) ) amd_vpmu_unset_msr_bitmap(v); =20 xfree(vpmu->context); diff --git a/xen/arch/x86/cpu/vpmu_intel.c b/xen/arch/x86/cpu/vpmu_intel.c index cd414165df..f95a9b058d 100644 --- a/xen/arch/x86/cpu/vpmu_intel.c +++ b/xen/arch/x86/cpu/vpmu_intel.c @@ -54,6 +54,8 @@ #define MSR_PMC_ALIAS_MASK (~(MSR_IA32_PERFCTR0 ^ MSR_IA32_A_PERFCTR= 0)) static bool __read_mostly full_width_write; =20 +#define is_vmx_vcpu(v) ( using_vmx && is_hvm_vcpu(v) ) + /* * MSR_CORE_PERF_FIXED_CTR_CTRL contains the configuration of all fixed * counters. 4 bits for every counter. @@ -269,7 +271,7 @@ static inline void __core2_vpmu_save(struct vcpu *v) if ( !is_hvm_vcpu(v) ) rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, core2_vpmu_cxt->global_status); /* Save MSR to private context to make it fork-friendly */ - else if ( mem_sharing_enabled(v->domain) ) + else if ( is_vmx_vcpu(v) && mem_sharing_enabled(v->domain) ) vmx_read_guest_msr(v, MSR_CORE_PERF_GLOBAL_CTRL, &core2_vpmu_cxt->global_ctrl); } @@ -333,7 +335,7 @@ static inline void __core2_vpmu_load(struct vcpu *v) wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, core2_vpmu_cxt->global_ctrl); } /* Restore MSR from context when used with a fork */ - else if ( mem_sharing_is_fork(v->domain) ) + else if ( is_vmx_vcpu(v) && mem_sharing_is_fork(v->domain) ) vmx_write_guest_msr(v, MSR_CORE_PERF_GLOBAL_CTRL, core2_vpmu_cxt->global_ctrl); } @@ -442,7 +444,7 @@ static int cf_check core2_vpmu_alloc_resource(struct vc= pu *v) if ( !acquire_pmu_ownership(PMU_OWNER_HVM) ) return 0; =20 - if ( is_hvm_vcpu(v) ) + if ( is_vmx_vcpu(v) ) { if ( vmx_add_host_load_msr(v, MSR_CORE_PERF_GLOBAL_CTRL, 0) ) goto out_err; @@ -584,7 +586,7 @@ static int cf_check core2_vpmu_do_wrmsr(unsigned int ms= r, uint64_t msr_content) if ( msr_content & fixed_ctrl_mask ) return -EINVAL; =20 - if ( is_hvm_vcpu(v) ) + if ( is_vmx_vcpu(v) ) vmx_read_guest_msr(v, MSR_CORE_PERF_GLOBAL_CTRL, &core2_vpmu_cxt->global_ctrl); else @@ -653,7 +655,7 @@ static int cf_check core2_vpmu_do_wrmsr(unsigned int ms= r, uint64_t msr_content) if ( blocked ) return -EINVAL; =20 - if ( is_hvm_vcpu(v) ) + if ( is_vmx_vcpu(v) ) vmx_read_guest_msr(v, MSR_CORE_PERF_GLOBAL_CTRL, &core2_vpmu_cxt->global_ctrl); else @@ -672,7 +674,7 @@ static int cf_check core2_vpmu_do_wrmsr(unsigned int ms= r, uint64_t msr_content) wrmsrl(msr, msr_content); else { - if ( is_hvm_vcpu(v) ) + if ( is_vmx_vcpu(v) ) vmx_write_guest_msr(v, MSR_CORE_PERF_GLOBAL_CTRL, msr_content); else wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, msr_content); @@ -706,7 +708,7 @@ static int cf_check core2_vpmu_do_rdmsr(unsigned int ms= r, uint64_t *msr_content) *msr_content =3D core2_vpmu_cxt->global_status; break; case MSR_CORE_PERF_GLOBAL_CTRL: - if ( is_hvm_vcpu(v) ) + if ( is_vmx_vcpu(v) ) vmx_read_guest_msr(v, MSR_CORE_PERF_GLOBAL_CTRL, msr_conte= nt); else rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, *msr_content); --=20 2.25.1