From nobody Sun May 5 04:37:24 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1615223943; cv=none; d=zohomail.com; s=zohoarc; b=HZNrgj6uh9yj4aX7eX2xmT0PjTBka7ZUaLQUTJGPVuGMEOcNk2LvYq9B5jLSWfi5M6wOdTbVlGQsP9YbTYt3B4VCHEESxKVQbG1DdNSS0BTwAQ2/cRmELKBRufJ/FMuWGBnTS4tQX7rs45+frwHqYCXpaWd4/K0c3GSwSrVilgw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1615223943; h=Cc:Date:From:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:Message-ID:Sender:Subject:To; bh=hXCfct5CSWVWHgKHRLqw7DQLGWnZSNshNAN36J8UuK0=; b=EfJc90uDTjw82quTCVohgdZi2+w7C2KS3aNKnh9EDUia7NXDms6DZc/g06g/wnSrc2D0zOOg086ifST3FTVVaYC/n8aDePz2k2K2ZeicSODW92s7gQj6D0ypX9ajP2zLT+NtIiXW6/7ECc0W7PDJxD70cC4ss3iouxHZ/7n16e0= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1615223943203337.6464592674304; Mon, 8 Mar 2021 09:19:03 -0800 (PST) Received: from list by lists.xenproject.org with outflank-mailman.95035.179232 (Exim 4.92) (envelope-from ) id 1lJJWj-00023t-Tg; Mon, 08 Mar 2021 17:18:41 +0000 Received: by outflank-mailman (output) from mailman id 95035.179232; Mon, 08 Mar 2021 17:18:41 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1lJJWj-00023m-Qh; Mon, 08 Mar 2021 17:18:41 +0000 Received: by outflank-mailman (input) for mailman id 95035; Mon, 08 Mar 2021 17:18:39 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1lJJWh-00023h-T5 for xen-devel@lists.xenproject.org; Mon, 08 Mar 2021 17:18:39 +0000 Received: from foss.arm.com (unknown [217.140.110.172]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTP id 90b721a6-bf77-4706-a9d2-c7fd849cce55; Mon, 08 Mar 2021 17:18:39 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id AF1ADD6E; Mon, 8 Mar 2021 09:18:38 -0800 (PST) Received: from e109506.cambridge.arm.com (e109506.cambridge.arm.com [10.1.199.1]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 091833F71B; Mon, 8 Mar 2021 09:18:37 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 90b721a6-bf77-4706-a9d2-c7fd849cce55 From: Bertrand Marquis To: xen-devel@lists.xenproject.org Cc: Stefano Stabellini , Julien Grall , Volodymyr Babchuk Subject: [PATCH] xen/arm: Use register_t type in cpuinfo entries Date: Mon, 8 Mar 2021 17:18:19 +0000 Message-Id: X-Mailer: git-send-email 2.17.1 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" All cpu identification registers that we store in the cpuinfo structure are 64bit on arm64 and 32bit on arm32 so storing the values in 32bit on arm64 is removing the higher bits which might contain information in the future. This patch is changing the types in cpuinfo to register_t (which is 32bit on arm32 and 64bit on arm64) and adding the necessary paddings inside the unions. It is also fixing all prints using directly the bits values from cpuinfo to use PRIregister and adapt the printed value to print all bits available on the architecture. Signed-off-by: Bertrand Marquis Acked-by: Julien Grall Reviewed-by: Stefano Stabellini --- xen/arch/arm/setup.c | 17 ++++++++-------- xen/arch/arm/smpboot.c | 3 ++- xen/include/asm-arm/cpufeature.h | 34 +++++++++++++++++++++----------- 3 files changed, 34 insertions(+), 20 deletions(-) diff --git a/xen/arch/arm/setup.c b/xen/arch/arm/setup.c index 2532ec9739..9ba2f267f6 100644 --- a/xen/arch/arm/setup.c +++ b/xen/arch/arm/setup.c @@ -116,8 +116,8 @@ static void __init processor_id(void) printk("Huh, cpu architecture %x, expected 0xf (defined by cpuid)\= n", c->midr.architecture); =20 - printk("Processor: %08"PRIx32": \"%s\", variant: 0x%x, part 0x%03x, re= v 0x%x\n", - c->midr.bits, implementer, + printk("Processor: %"PRIregister": \"%s\", variant: 0x%x, part 0x%03x," + "rev 0x%x\n", c->midr.bits, implementer, c->midr.variant, c->midr.part_number, c->midr.revision); =20 #if defined(CONFIG_ARM_64) @@ -163,7 +163,7 @@ static void __init processor_id(void) if ( cpu_has_aarch32 ) { printk("32-bit Execution:\n"); - printk(" Processor Features: %08"PRIx32":%08"PRIx32"\n", + printk(" Processor Features: %"PRIregister":%"PRIregister"\n", boot_cpu_data.pfr32.bits[0], boot_cpu_data.pfr32.bits[1]); printk(" Instruction Sets:%s%s%s%s%s%s\n", cpu_has_aarch32 ? " AArch32" : "", @@ -176,15 +176,16 @@ static void __init processor_id(void) cpu_has_gentimer ? " GenericTimer" : "", cpu_has_security ? " Security" : ""); =20 - printk(" Debug Features: %08"PRIx32"\n", + printk(" Debug Features: %"PRIregister"\n", boot_cpu_data.dbg32.bits[0]); - printk(" Auxiliary Features: %08"PRIx32"\n", + printk(" Auxiliary Features: %"PRIregister"\n", boot_cpu_data.aux32.bits[0]); - printk(" Memory Model Features: " - "%08"PRIx32" %08"PRIx32" %08"PRIx32" %08"PRIx32"\n", + printk(" Memory Model Features: %"PRIregister" %"PRIregister"\n" + " %"PRIregister" %"PRIregister"\n", boot_cpu_data.mm32.bits[0], boot_cpu_data.mm32.bits[1], boot_cpu_data.mm32.bits[2], boot_cpu_data.mm32.bits[3]); - printk(" ISA Features: %08x %08x %08x %08x %08x %08x\n", + printk(" ISA Features: %"PRIregister" %"PRIregister" %"PRIregiste= r"\n" + " %"PRIregister" %"PRIregister" %"PRIregiste= r"\n", boot_cpu_data.isa32.bits[0], boot_cpu_data.isa32.bits[1], boot_cpu_data.isa32.bits[2], boot_cpu_data.isa32.bits[3], boot_cpu_data.isa32.bits[4], boot_cpu_data.isa32.bits[5]); diff --git a/xen/arch/arm/smpboot.c b/xen/arch/arm/smpboot.c index cae2179126..ea0dd3451e 100644 --- a/xen/arch/arm/smpboot.c +++ b/xen/arch/arm/smpboot.c @@ -321,7 +321,8 @@ void start_secondary(void) if ( !opt_hmp_unsafe && current_cpu_data.midr.bits !=3D boot_cpu_data.midr.bits ) { - printk(XENLOG_ERR "CPU%u MIDR (0x%x) does not match boot CPU MIDR = (0x%x),\n" + printk(XENLOG_ERR "CPU%u MIDR (0x%"PRIregister") does not match bo= ot " + "CPU MIDR (0x%"PRIregister"),\n" "disable cpu (see big.LITTLE.txt under docs/).\n", smp_processor_id(), current_cpu_data.midr.bits, boot_cpu_data.midr.bits); diff --git a/xen/include/asm-arm/cpufeature.h b/xen/include/asm-arm/cpufeat= ure.h index 9ea3970c70..ba48db3eac 100644 --- a/xen/include/asm-arm/cpufeature.h +++ b/xen/include/asm-arm/cpufeature.h @@ -118,13 +118,16 @@ int enable_nonboot_cpu_caps(const struct arm_cpu_capa= bilities *caps); */ struct cpuinfo_arm { union { - uint32_t bits; + register_t bits; struct { unsigned long revision:4; unsigned long part_number:12; unsigned long architecture:4; unsigned long variant:4; unsigned long implementer:8; +#ifdef CONFIG_ARM_64 + unsigned long _res0:32; +#endif }; } midr; union { @@ -148,7 +151,7 @@ struct cpuinfo_arm { #ifdef CONFIG_ARM_64 /* 64-bit CPUID registers. */ union { - uint64_t bits[2]; + register_t bits[2]; struct { /* PFR0 */ unsigned long el0:4; @@ -179,15 +182,15 @@ struct cpuinfo_arm { } pfr64; =20 struct { - uint64_t bits[2]; + register_t bits[2]; } dbg64; =20 struct { - uint64_t bits[2]; + register_t bits[2]; } aux64; =20 union { - uint64_t bits[3]; + register_t bits[3]; struct { unsigned long pa_range:4; unsigned long asid_bits:4; @@ -213,7 +216,7 @@ struct cpuinfo_arm { } mm64; =20 union { - uint64_t bits[2]; + register_t bits[2]; struct { /* ISAR0 */ unsigned long __res0:4; @@ -263,7 +266,7 @@ struct cpuinfo_arm { * when running in 32-bit mode. */ union { - uint32_t bits[3]; + register_t bits[3]; struct { /* PFR0 */ unsigned long arm:4; @@ -274,6 +277,9 @@ struct cpuinfo_arm { unsigned long amu:4; unsigned long dit:4; unsigned long ras:4; +#ifdef CONFIG_ARM_64 + unsigned long __res0:32; +#endif =20 /* PFR1 */ unsigned long progmodel:4; @@ -284,29 +290,35 @@ struct cpuinfo_arm { unsigned long sec_frac:4; unsigned long virt_frac:4; unsigned long gic:4; +#ifdef CONFIG_ARM_64 + unsigned long __res1:32; +#endif =20 /* PFR2 */ unsigned long csv3:4; unsigned long ssbs:4; unsigned long ras_frac:4; unsigned long __res2:20; +#ifdef CONFIG_ARM_64 + unsigned long __res3:32; +#endif }; } pfr32; =20 struct { - uint32_t bits[2]; + register_t bits[2]; } dbg32; =20 struct { - uint32_t bits[1]; + register_t bits[1]; } aux32; =20 struct { - uint32_t bits[6]; + register_t bits[6]; } mm32; =20 struct { - uint32_t bits[7]; + register_t bits[7]; } isa32; =20 struct { --=20 2.17.1