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charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZM-MESSAGEID: 1654612312321100008 Handle parameters similar to dbgp=3Dehci. Implement this by not resettting xhc_cf8 again in xue_init_xhc(), but using a value found there if non-zero. Additionally, add xue->xhc_num to select n-th controller. Signed-off-by: Marek Marczykowski-G=C3=B3recki --- docs/misc/xen-command-line.pandoc | 5 +++- xen/drivers/char/xue.c | 56 ++++++++++++++++++++++++-------- 2 files changed, 47 insertions(+), 14 deletions(-) diff --git a/docs/misc/xen-command-line.pandoc b/docs/misc/xen-command-line= .pandoc index 881fe409ac76..37a564c2386f 100644 --- a/docs/misc/xen-command-line.pandoc +++ b/docs/misc/xen-command-line.pandoc @@ -721,10 +721,15 @@ Available alternatives, with their meaning, are: =20 ### dbgp > `=3D ehci[ | @pci:. ]` +> `=3D xue[ | @pci:. ]` =20 Specify the USB controller to use, either by instance number (when going over the PCI busses sequentially) or by PCI device (must be on segment 0). =20 +Use `ehci` for EHCI debug port, use `xue` for XHCI debug capability. +Xue driver will wait indefinitely for the debug host to connect - make sur= e the +cable is connected. + ### debug_stack_lines > `=3D ` =20 diff --git a/xen/drivers/char/xue.c b/xen/drivers/char/xue.c index a9ba25d9d07e..b253426a95f8 100644 --- a/xen/drivers/char/xue.c +++ b/xen/drivers/char/xue.c @@ -204,6 +204,7 @@ struct xue { void *xhc_mmio; =20 int open; + int xhc_num; /* look for n-th xhc */ }; =20 static void xue_sys_pause(void) @@ -252,24 +253,34 @@ static int xue_init_xhc(struct xue *xue) uint64_t bar1; uint64_t devfn; =20 - /* - * Search PCI bus 0 for the xHC. All the host controllers supported so= far - * are part of the chipset and are on bus 0. - */ - for ( devfn =3D 0; devfn < 256; devfn++ ) { - uint32_t dev =3D (devfn & 0xF8) >> 3; - uint32_t fun =3D devfn & 0x07; - pci_sbdf_t sbdf =3D PCI_SBDF(0, dev, fun); - uint32_t hdr =3D pci_conf_read8(sbdf, PCI_HEADER_TYPE); - - if ( hdr =3D=3D 0 || hdr =3D=3D 0x80 ) + if ( xue->sbdf.sbdf =3D=3D 0 ) + { + /* + * Search PCI bus 0 for the xHC. All the host controllers supporte= d so far + * are part of the chipset and are on bus 0. + */ + for ( devfn =3D 0; devfn < 256; devfn++ ) { - if ( (pci_conf_read32(sbdf, PCI_CLASS_REVISION) >> 8) =3D=3D X= UE_XHC_CLASSC ) + uint32_t dev =3D (devfn & 0xF8) >> 3; + uint32_t fun =3D devfn & 0x07; + pci_sbdf_t sbdf =3D PCI_SBDF(0, dev, fun); + uint32_t hdr =3D pci_conf_read8(sbdf, PCI_HEADER_TYPE); + + if ( hdr =3D=3D 0 || hdr =3D=3D 0x80 ) { - xue->sbdf =3D sbdf; - break; + if ( (pci_conf_read32(sbdf, PCI_CLASS_REVISION) >> 8) =3D= =3D XUE_XHC_CLASSC ) + { + if ( xue->xhc_num-- ) + continue; + xue->sbdf =3D sbdf; + break; + } } } + } else { + /* Verify if selected device is really xHC */ + if ( (pci_conf_read32(xue->sbdf, PCI_CLASS_REVISION) >> 8) !=3D XU= E_XHC_CLASSC ) + xue->sbdf.sbdf =3D 0; } =20 if ( !xue->sbdf.sbdf ) @@ -999,12 +1010,29 @@ void __init xue_uart_init(void) { struct xue_uart *uart =3D &xue_uart; struct xue *xue =3D &uart->xue; + const char *e; =20 if ( strncmp(opt_dbgp, "xue", 3) ) return; =20 memset(xue, 0, sizeof(*xue)); =20 + if ( isdigit(opt_dbgp[3]) || !opt_dbgp[3] ) + { + if ( opt_dbgp[3] ) + xue->xhc_num =3D simple_strtoul(opt_dbgp + 3, &e, 10); + } + else if ( strncmp(opt_dbgp + 3, "@pci", 4) =3D=3D 0 ) + { + unsigned int bus, slot, func; + + e =3D parse_pci(opt_dbgp + 7, NULL, &bus, &slot, &func); + if ( !e || *e ) + return; + + xue->sbdf =3D PCI_SBDF(0, bus, slot, func); + } + xue->dbc_ctx =3D &ctx; xue->dbc_erst =3D &erst; xue->dbc_ering.trb =3D evt_trb; --=20 git-series 0.9.1