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Mon, 25 Nov 2024 07:08:47 -0800 (PST) Message-ID: Date: Mon, 25 Nov 2024 16:08:46 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH v7 7/7] x86emul: support non-SIMD MOVRS From: Jan Beulich To: "xen-devel@lists.xenproject.org" Cc: Andrew Cooper , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= References: <3a25cd59-e1cb-4bfc-b868-fb11599d22f5@suse.com> Content-Language: en-US Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <3a25cd59-e1cb-4bfc-b868-fb11599d22f5@suse.com> Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @suse.com) X-ZM-MESSAGEID: 1732547342655019100 Content-Type: text/plain; charset="utf-8" As we ignore cachability aspects of insns, they're treated like simple MOVs. Signed-off-by: Jan Beulich --- v7: New. --- a/tools/tests/x86_emulator/predicates.c +++ b/tools/tests/x86_emulator/predicates.c @@ -843,6 +843,9 @@ static const struct { { { 0x80 }, { 2, 2 }, T, R, pfx_66 }, /* invept */ { { 0x81 }, { 2, 2 }, T, R, pfx_66 }, /* invvpid */ { { 0x82 }, { 2, 2 }, T, R, pfx_66 }, /* invpcid */ + { { 0x8a }, { 2, 2 }, T, R, pfx_no }, /* movrsb */ + { { 0x8b }, { 2, 2 }, T, R, pfx_no }, /* movrs{d,q} */ + { { 0x8b }, { 2, 2 }, T, R, pfx_66 }, /* movrsw */ { { 0xc8 }, { 2, 2 }, T, R, pfx_no }, /* sha1nexte */ { { 0xc9 }, { 2, 2 }, T, R, pfx_no }, /* sha1msg1 */ { { 0xca }, { 2, 2 }, T, R, pfx_no }, /* sha1msg2 */ --- a/tools/tests/x86_emulator/test_x86_emulator.c +++ b/tools/tests/x86_emulator/test_x86_emulator.c @@ -1864,6 +1864,29 @@ int main(int argc, char **argv) } else printf("skipped\n"); + + { + /* For the non-SIMD forms the emulator doesn't itself use MOVRS. */ + bool movrs =3D cpu_policy.feat.movrs; + + cpu_policy.feat.movrs =3D true; + + printf("%-40s", "Testing movrs 6(%rdi),%si..."); + instr[0] =3D 0x66; instr[1] =3D 0x0f; instr[2] =3D 0x38; + instr[3] =3D 0x8b; instr[4] =3D 0x77; instr[5] =3D 0x06; + regs.rip =3D (unsigned long)&instr[0]; + regs.rsi =3D 0x8888777766665555UL; + regs.rdi =3D (unsigned long)res; + res[1] =3D 0x88777788U; + rc =3D x86_emulate(&ctxt, &emulops); + if ( (rc !=3D X86EMUL_OKAY) || + (regs.eip !=3D (unsigned long)&instr[6]) || + (regs.rsi !=3D 0x8888777766668877UL) ) + goto fail; + printf("okay\n"); + + cpu_policy.feat.movrs =3D movrs; + } #endif /* x86-64 */ =20 printf("%-40s", "Testing shld $1,%ecx,(%edx)..."); --- a/xen/arch/x86/x86_emulate/decode.c +++ b/xen/arch/x86/x86_emulate/decode.c @@ -901,7 +901,8 @@ decode_0f38(struct x86_emulate_state *s, { switch ( ctxt->opcode & X86EMUL_OPC_MASK ) { - case 0x00 ... 0xef: + case 0x00 ... 0x89: + case 0x8c ... 0xef: case 0xf2 ... 0xf5: case 0xf7: case 0xfa ... 0xff: @@ -912,6 +913,13 @@ decode_0f38(struct x86_emulate_state *s, ctxt->opcode |=3D MASK_INSR(s->vex.pfx, X86EMUL_OPC_PFX_MASK); break; =20 + case 0x8a ... 0x8b: /* movrs */ + s->desc =3D DstReg | SrcMem | Mov; + if ( !(ctxt->opcode & 1) ) + s->desc |=3D ByteOp; + s->simd_size =3D simd_none; + break; + case X86EMUL_OPC_VEX_66(0, 0x2d): /* vmaskmovpd */ s->simd_size =3D simd_packed_fp; break; --- a/xen/arch/x86/x86_emulate/private.h +++ b/xen/arch/x86/x86_emulate/private.h @@ -600,6 +600,7 @@ amd_like(const struct x86_emulate_ctxt * #define vcpu_has_wrmsrns() (ctxt->cpuid->feat.wrmsrns) #define vcpu_has_avx_ifma() (ctxt->cpuid->feat.avx_ifma) #define vcpu_has_msrlist() (ctxt->cpuid->feat.msrlist) +#define vcpu_has_movrs() (ctxt->cpuid->feat.movrs) #define vcpu_has_msr_imm() (ctxt->cpuid->feat.msr_imm) #define vcpu_has_avx_vnni_int8() (ctxt->cpuid->feat.avx_vnni_int8) #define vcpu_has_avx_ne_convert() (ctxt->cpuid->feat.avx_ne_convert) --- a/xen/arch/x86/x86_emulate/x86_emulate.c +++ b/xen/arch/x86/x86_emulate/x86_emulate.c @@ -6336,6 +6336,16 @@ x86_emulate( fault_suppression =3D false; goto avx512f_no_sae; =20 +#endif /* !X86EMUL_NO_SIMD */ + + case X86EMUL_OPC(0x0f38, 0x8a) + ... X86EMUL_OPC(0x0f38, 0x8b): /* movrs */ + vcpu_must_have(movrs); + dst.val =3D src.val; + break; + +#ifndef X86EMUL_NO_SIMD + case X86EMUL_OPC_VEX_66(0x0f38, 0x8c): /* vpmaskmov{d,q} mem,{x,y}mm,{= x,y}mm */ case X86EMUL_OPC_VEX_66(0x0f38, 0x8e): /* vpmaskmov{d,q} {x,y}mm,{x,y}= mm,mem */ generate_exception_if(ea.type !=3D OP_MEM, X86_EXC_UD); --- a/xen/include/public/arch-x86/cpufeatureset.h +++ b/xen/include/public/arch-x86/cpufeatureset.h @@ -314,6 +314,7 @@ XEN_CPUFEATURE(NMI_SRC, 10*32+20) / XEN_CPUFEATURE(AMX_FP16, 10*32+21) /* AMX FP16 instruction */ XEN_CPUFEATURE(AVX_IFMA, 10*32+23) /*A AVX-IFMA Instructions */ XEN_CPUFEATURE(MSRLIST, 10*32+27) /*s MSR list instructions */ +XEN_CPUFEATURE(MOVRS, 10*32+31) /*a MOV-read-shared instructions */ =20 /* AMD-defined CPU features, CPUID level 0x80000021.eax, word 11 */ XEN_CPUFEATURE(NO_NEST_BP, 11*32+ 0) /*A No Nested Data Breakpoin= ts */ --- a/xen/tools/gen-cpuid.py +++ b/xen/tools/gen-cpuid.py @@ -275,7 +275,7 @@ def crunch_numbers(state): # NO_LMSL indicates the absense of Long Mode Segment Limits, which # have been dropped in hardware. LM: [CX16, PCID, LAHF_LM, PAGE1GB, PKU, NO_LMSL, AMX_TILE, CMPCCXA= DD, - LKGS, MSRLIST, USER_MSR, MSR_IMM], + LKGS, MSRLIST, USER_MSR, MSR_IMM, MOVRS], =20 # AMD K6-2+ and K6-III processors shipped with 3DNow+, beyond the # standard 3DNow in the earlier K6 processors.