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b=BIHUK4dWh1wDLvywfUYcd2E14HUdi7dTgR0HEPB15DmOzLIpeXqZLRGJuuatQ5/GtGB+Q92D7+bEHNee2AidC3tAxwJYRDJjUPgmdSECiWJvaeuH10MamSulNzRa8UqF9wzmLTsIUi8FgWgxaEml5SHfheUEJE34QN7r8kSzexmTTqykH7nihqGjGquMDSo1kosg7pLM+4zdvuO0y0G2rIeWjpVuijhZoiBIQ32dONrfrh7LmA2PTbwCvD2ahO0nAYgDQxcxCue8pt1kK6F3PYwYlsTMx6Tq2XreIZxfPmBXdg7HU/V35HGDWF9IZROj9PnDqMdFhONebL4ijzGFrQ== From: Milan Djokic To: "xen-devel@lists.xenproject.org" CC: Rahul Singh , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk , Milan Djokic Subject: [PATCH v3 12/23] xen/arm: vsmmuv3: Add support for event queue and global error Thread-Topic: [PATCH v3 12/23] xen/arm: vsmmuv3: Add support for event queue and global error Thread-Index: AQHcwLD8TbB0vBk5KkOu1RGZU75M7A== Date: Tue, 31 Mar 2026 01:52:09 +0000 Message-ID: References: In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=epam.com; 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charset="utf-8" From: Rahul Singh Event queue is used to send the events to guest when there is an events/ faults. Add support for event queue to send events to guest. Global error in SMMUv3 hw will be updated in smmu_gerror and smmu_gerrorn register. Add support for global error registers to send global error to guest. Signed-off-by: Rahul Singh Signed-off-by: Milan Djokic --- xen/drivers/passthrough/arm/smmu-v3.h | 20 +++ xen/drivers/passthrough/arm/vsmmu-v3.c | 163 ++++++++++++++++++++++++- xen/include/public/arch-arm.h | 5 +- 3 files changed, 183 insertions(+), 5 deletions(-) diff --git a/xen/drivers/passthrough/arm/smmu-v3.h b/xen/drivers/passthroug= h/arm/smmu-v3.h index df3b7ec1b5..8d3e1877aa 100644 --- a/xen/drivers/passthrough/arm/smmu-v3.h +++ b/xen/drivers/passthrough/arm/smmu-v3.h @@ -354,6 +354,26 @@ =20 #define EVTQ_0_ID GENMASK_ULL(7, 0) =20 +#define EVT_ID_BAD_STREAMID 0x02 +#define EVT_ID_BAD_STE 0x04 +#define EVT_ID_TRANSLATION_FAULT 0x10 +#define EVT_ID_ADDR_SIZE_FAULT 0x11 +#define EVT_ID_ACCESS_FAULT 0x12 +#define EVT_ID_PERMISSION_FAULT 0x13 + +#define EVTQ_0_SSV (1UL << 11) +#define EVTQ_0_SSID GENMASK_ULL(31, 12) +#define EVTQ_0_SID GENMASK_ULL(63, 32) +#define EVTQ_1_STAG GENMASK_ULL(15, 0) +#define EVTQ_1_STALL (1UL << 31) +#define EVTQ_1_PnU (1UL << 33) +#define EVTQ_1_InD (1UL << 34) +#define EVTQ_1_RnW (1UL << 35) +#define EVTQ_1_S2 (1UL << 39) +#define EVTQ_1_CLASS GENMASK_ULL(41, 40) +#define EVTQ_1_TT_READ (1UL << 44) +#define EVTQ_2_ADDR GENMASK_ULL(63, 0) +#define EVTQ_3_IPA GENMASK_ULL(51, 12) /* PRI queue */ #define PRIQ_ENT_SZ_SHIFT 4 #define PRIQ_ENT_DWORDS ((1 << PRIQ_ENT_SZ_SHIFT) >> 3) diff --git a/xen/drivers/passthrough/arm/vsmmu-v3.c b/xen/drivers/passthrou= gh/arm/vsmmu-v3.c index 6d3636b18b..7a6c18df53 100644 --- a/xen/drivers/passthrough/arm/vsmmu-v3.c +++ b/xen/drivers/passthrough/arm/vsmmu-v3.c @@ -44,6 +44,7 @@ extern const struct viommu_desc __read_mostly *cur_viommu; =20 /* Helper Macros */ #define smmu_get_cmdq_enabled(x) FIELD_GET(CR0_CMDQEN, x) +#define smmu_get_evtq_enabled(x) FIELD_GET(CR0_EVTQEN, x) #define smmu_cmd_get_command(x) FIELD_GET(CMDQ_0_OP, x) #define smmu_cmd_get_sid(x) FIELD_GET(CMDQ_PREFETCH_0_SID, x) #define smmu_get_ste_s1cdmax(x) FIELD_GET(STRTAB_STE_0_S1CDMAX, x) @@ -52,6 +53,35 @@ extern const struct viommu_desc __read_mostly *cur_viomm= u; #define smmu_get_ste_s1ctxptr(x) FIELD_PREP(STRTAB_STE_0_S1CTXPTR_MASK,= \ FIELD_GET(STRTAB_STE_0_S1CTXPTR_MASK, = x)) =20 +/* event queue entry */ +struct arm_smmu_evtq_ent { + /* Common fields */ + uint8_t opcode; + uint32_t sid; + + /* Event-specific fields */ + union { + struct { + uint32_t ssid; + bool ssv; + } c_bad_ste_streamid; + + struct { + bool stall; + uint16_t stag; + uint32_t ssid; + bool ssv; + bool s2; + uint64_t addr; + bool rnw; + bool pnu; + bool ind; + uint8_t class; + uint64_t addr2; + } f_translation; + }; +}; + /* stage-1 translation configuration */ struct arm_vsmmu_s1_trans_cfg { paddr_t s1ctxptr; @@ -82,6 +112,7 @@ struct virt_smmu { uint32_t strtab_base_cfg; uint64_t strtab_base; uint32_t irq_ctrl; + uint32_t virq; uint64_t gerror_irq_cfg0; uint64_t evtq_irq_cfg0; struct arm_vsmmu_queue evtq, cmdq; @@ -89,6 +120,12 @@ struct virt_smmu { }; =20 /* Queue manipulation functions */ +static bool queue_full(struct arm_vsmmu_queue *q) +{ + return Q_IDX(q, q->prod) =3D=3D Q_IDX(q, q->cons) && + Q_WRP(q, q->prod) !=3D Q_WRP(q, q->cons); +} + static bool queue_empty(struct arm_vsmmu_queue *q) { return Q_IDX(q, q->prod) =3D=3D Q_IDX(q, q->cons) && @@ -101,11 +138,105 @@ static void queue_inc_cons(struct arm_vsmmu_queue *q) q->cons =3D Q_OVF(q->cons) | Q_WRP(q, cons) | Q_IDX(q, cons); } =20 +static void queue_inc_prod(struct arm_vsmmu_queue *q) +{ + u32 prod =3D (Q_WRP(q, q->prod) | Q_IDX(q, q->prod)) + 1; + q->prod =3D Q_OVF(q->prod) | Q_WRP(q, prod) | Q_IDX(q, prod); +} + static void dump_smmu_command(uint64_t *command) { gdprintk(XENLOG_ERR, "cmd 0x%02llx: %016lx %016lx\n", smmu_cmd_get_command(command[0]), command[0], command[1]); } + +static void arm_vsmmu_inject_irq(struct virt_smmu *smmu, bool is_gerror, + uint32_t gerror_err) +{ + uint32_t new_gerrors, pending; + + if ( is_gerror ) + { + /* trigger global error irq to guest */ + pending =3D smmu->gerror ^ smmu->gerrorn; + new_gerrors =3D ~pending & gerror_err; + + /* only toggle non pending errors */ + if (!new_gerrors) + return; + + smmu->gerror ^=3D new_gerrors; + } + + vgic_inject_irq(smmu->d, NULL, smmu->virq, true); +} + +static int arm_vsmmu_write_evtq(struct virt_smmu *smmu, uint64_t *evt) +{ + struct arm_vsmmu_queue *q =3D &smmu->evtq; + struct domain *d =3D smmu->d; + paddr_t addr; + int ret; + + if ( !smmu_get_evtq_enabled(smmu->cr[0]) ) + return -EINVAL; + + if ( queue_full(q) ) + return -EINVAL; + + addr =3D Q_PROD_ENT(q); + ret =3D access_guest_memory_by_gpa(d, addr, evt, + sizeof(*evt) * EVTQ_ENT_DWORDS, true); + if ( ret ) + return ret; + + queue_inc_prod(q); + + /* trigger eventq irq to guest */ + if ( !queue_empty(q) ) + arm_vsmmu_inject_irq(smmu, false, 0); + + return 0; +} + +void arm_vsmmu_send_event(struct virt_smmu *smmu, + struct arm_smmu_evtq_ent *ent) +{ + uint64_t evt[EVTQ_ENT_DWORDS]; + int ret; + + memset(evt, 0, 1 << EVTQ_ENT_SZ_SHIFT); + + if ( !smmu_get_evtq_enabled(smmu->cr[0]) ) + return; + + evt[0] |=3D FIELD_PREP(EVTQ_0_ID, ent->opcode); + evt[0] |=3D FIELD_PREP(EVTQ_0_SID, ent->sid); + + switch (ent->opcode) + { + case EVT_ID_BAD_STREAMID: + case EVT_ID_BAD_STE: + evt[0] |=3D FIELD_PREP(EVTQ_0_SSID, ent->c_bad_ste_streamid.ssid); + evt[0] |=3D FIELD_PREP(EVTQ_0_SSV, ent->c_bad_ste_streamid.ssv); + break; + case EVT_ID_TRANSLATION_FAULT: + case EVT_ID_ADDR_SIZE_FAULT: + case EVT_ID_ACCESS_FAULT: + case EVT_ID_PERMISSION_FAULT: + break; + default: + gdprintk(XENLOG_WARNING, "vSMMUv3: event opcode is bad\n"); + break; + } + + ret =3D arm_vsmmu_write_evtq(smmu, evt); + if ( ret ) + arm_vsmmu_inject_irq(smmu, true, GERROR_EVTQ_ABT_ERR); + + return; +} + static int arm_vsmmu_find_ste(struct virt_smmu *smmu, uint32_t sid, uint64_t *ste) { @@ -114,11 +245,22 @@ static int arm_vsmmu_find_ste(struct virt_smmu *smmu,= uint32_t sid, uint32_t log2size; int strtab_size_shift; int ret; + struct arm_smmu_evtq_ent ent =3D { + .sid =3D sid, + .c_bad_ste_streamid =3D { + .ssid =3D 0, + .ssv =3D false, + }, + }; =20 log2size =3D FIELD_GET(STRTAB_BASE_CFG_LOG2SIZE, smmu->strtab_base_cfg= ); =20 if ( sid >=3D (1 << MIN(log2size, SMMU_IDR1_SIDSIZE)) ) + { + ent.opcode =3D EVT_ID_BAD_STE; + arm_vsmmu_send_event(smmu, &ent); return -EINVAL; + } =20 if ( smmu->features & STRTAB_BASE_CFG_FMT_2LVL ) { @@ -156,6 +298,8 @@ static int arm_vsmmu_find_ste(struct virt_smmu *smmu, u= int32_t sid, { gdprintk(XENLOG_ERR, "idx=3D%d > max_l2_ste=3D%d\n", idx, max_l2_ste); + ent.opcode =3D EVT_ID_BAD_STREAMID; + arm_vsmmu_send_event(smmu, &ent); return -EINVAL; } addr =3D l2ptr + idx * sizeof(*ste) * STRTAB_STE_DWORDS; @@ -183,6 +327,14 @@ static int arm_vsmmu_decode_ste(struct virt_smmu *smmu= , uint32_t sid, uint64_t *ste) { uint64_t val =3D ste[0]; + struct arm_smmu_evtq_ent ent =3D { + .opcode =3D EVT_ID_BAD_STE, + .sid =3D sid, + .c_bad_ste_streamid =3D { + .ssid =3D 0, + .ssv =3D false, + }, + }; =20 if ( !(val & STRTAB_STE_0_V) ) return -EAGAIN; @@ -217,6 +369,7 @@ static int arm_vsmmu_decode_ste(struct virt_smmu *smmu,= uint32_t sid, return 0; =20 bad_ste: + arm_vsmmu_send_event(smmu, &ent); return -EINVAL; } =20 @@ -577,7 +730,8 @@ static const struct mmio_handler_ops vsmmuv3_mmio_handl= er =3D { .write =3D vsmmuv3_mmio_write, }; =20 -static int vsmmuv3_init_single(struct domain *d, paddr_t addr, paddr_t siz= e) +static int vsmmuv3_init_single(struct domain *d, paddr_t addr, + paddr_t size, uint32_t virq) { struct virt_smmu *smmu; =20 @@ -586,6 +740,7 @@ static int vsmmuv3_init_single(struct domain *d, paddr_= t addr, paddr_t size) return -ENOMEM; =20 smmu->d =3D d; + smmu->virq =3D virq; smmu->cmdq.q_base =3D FIELD_PREP(Q_BASE_LOG2SIZE, SMMU_CMDQS); smmu->cmdq.ent_size =3D CMDQ_ENT_DWORDS * DWORDS_BYTES; smmu->evtq.q_base =3D FIELD_PREP(Q_BASE_LOG2SIZE, SMMU_EVTQS); @@ -612,14 +767,16 @@ int domain_vsmmuv3_init(struct domain *d) =20 list_for_each_entry(hw_iommu, &host_iommu_list, entry) { - ret =3D vsmmuv3_init_single(d, hw_iommu->addr, hw_iommu->size); + ret =3D vsmmuv3_init_single(d, hw_iommu->addr, hw_iommu->size, + hw_iommu->irq); if ( ret ) return ret; } } else { - ret =3D vsmmuv3_init_single(d, GUEST_VSMMUV3_BASE, GUEST_VSMMUV3_S= IZE); + ret =3D vsmmuv3_init_single(d, GUEST_VSMMUV3_BASE, GUEST_VSMMUV3_S= IZE, + GUEST_VSMMU_SPI); if ( ret ) return ret; } diff --git a/xen/include/public/arch-arm.h b/xen/include/public/arch-arm.h index ebac02ed63..1b606e20fd 100644 --- a/xen/include/public/arch-arm.h +++ b/xen/include/public/arch-arm.h @@ -527,9 +527,10 @@ typedef uint64_t xen_callback_t; #define GUEST_EVTCHN_PPI 31 =20 #define GUEST_VPL011_SPI 32 +#define GUEST_VSMMU_SPI 33 =20 -#define GUEST_VIRTIO_MMIO_SPI_FIRST 33 -#define GUEST_VIRTIO_MMIO_SPI_LAST 43 +#define GUEST_VIRTIO_MMIO_SPI_FIRST 34 +#define GUEST_VIRTIO_MMIO_SPI_LAST 44 =20 /* * SGI is the preferred delivery mechanism of FF-A pending notifications or --=20 2.43.0