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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Jul 2025 18:32:42.7266 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6f678d0c-3cb4-4a9b-1d36-08ddbe4dd396 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099D7.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8255 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1751999590637116600 Content-Type: text/plain; charset="utf-8" On real time configuration with the null scheduler, we shouldn't interrupt the guest execution unless strictly necessary: the guest could be a real time guest (e.g. FreeRTOS) and interrupting its execution could lead to a missed deadline. The principal source of interruptions is IPIs. When TSC is the chosen clocksource, we know it is reliable and synchronized across cpus and clusters. Thus, we can return early time_calibration because the calibration is not needed, removing the related Xen timer and IPIs. Also remove the master_stime write as it is unnecessary. Signed-off-by: Stefano Stabellini --- Changes in v2: - simplify the patch simply by returning early if clocksource_is_tsc() - also remove setting r.master_stime as it is not needed --- xen/arch/x86/time.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/xen/arch/x86/time.c b/xen/arch/x86/time.c index 59129f419d..d72e640f72 100644 --- a/xen/arch/x86/time.c +++ b/xen/arch/x86/time.c @@ -2297,11 +2297,7 @@ static void cf_check time_calibration(void *unused) }; =20 if ( clocksource_is_tsc() ) - { - local_irq_disable(); - r.master_stime =3D read_platform_stime(&r.master_tsc_stamp); - local_irq_enable(); - } + return; =20 cpumask_copy(&r.cpu_calibration_map, &cpu_online_map); =20 --=20 2.25.1 From nobody Thu Oct 30 23:28:27 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; arc=pass (i=1 dmarc=pass fromdomain=amd.com); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Jul 2025 18:32:43.6128 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e4909112-987f-4acc-3808-08ddbe4dd41b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00003AE4.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR12MB7921 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1751999592690116600 Content-Type: text/plain; charset="utf-8" Today, checking for non-fatal MCE errors on AMD is very invasive: it involves a periodic timer interrupting the physical CPU execution at regular intervals. Moreover, when the timer fires, the handler sends an IPI to all physical CPUs. Both these actions are disruptive in terms of latency and deterministic execution times for real-time workloads. They might miss a deadline due to one of these IPIs. Make it possible to disable non-fatal MCE errors checking with a new Kconfig option (MCE_NONFATAL). Signed-off-by: Stefano Stabellini Acked-by: Jan Beulich --- Changes in v2: - generalize the appraoch and remove the code when MCE_NONFATAL is not set - move the new kconfig option to xen/arch/x86/Kconfig --- xen/arch/x86/Kconfig | 14 ++++++++++++++ xen/arch/x86/cpu/mcheck/Makefile | 6 +++--- 2 files changed, 17 insertions(+), 3 deletions(-) diff --git a/xen/arch/x86/Kconfig b/xen/arch/x86/Kconfig index 752d5141bb..9ec0fb0bed 100644 --- a/xen/arch/x86/Kconfig +++ b/xen/arch/x86/Kconfig @@ -248,6 +248,20 @@ config X2APIC_MIXED =20 endchoice =20 +config MCE_NONFATAL + bool "Check for non-fatal MCEs" if EXPERT + default y + help + Check for non-fatal MCE errors. +=09 + When this option is on (default), Xen regularly checks for + non-fatal MCEs potentially occurring on all physical CPUs. The + checking is done via timers and IPI interrupts, which is + acceptable in most configurations, but not for real-time. +=09 + Turn this option off if you plan on deploying real-time workloads + on Xen. + config GUEST bool =20 diff --git a/xen/arch/x86/cpu/mcheck/Makefile b/xen/arch/x86/cpu/mcheck/Mak= efile index e6cb4dd503..c70b441888 100644 --- a/xen/arch/x86/cpu/mcheck/Makefile +++ b/xen/arch/x86/cpu/mcheck/Makefile @@ -1,12 +1,12 @@ -obj-$(CONFIG_AMD) +=3D amd_nonfatal.o +obj-$(filter $(CONFIG_AMD),$(CONFIG_MCE_NONFATAL)) +=3D amd_nonfatal.o obj-$(CONFIG_AMD) +=3D mce_amd.o obj-y +=3D mcaction.o obj-y +=3D barrier.o -obj-$(CONFIG_INTEL) +=3D intel-nonfatal.o +obj-$(filter $(CONFIG_INTEL),$(CONFIG_MCE_NONFATAL)) +=3D intel-nonfatal.o obj-y +=3D mctelem.o obj-y +=3D mce.o obj-y +=3D mce-apei.o obj-$(CONFIG_INTEL) +=3D mce_intel.o -obj-y +=3D non-fatal.o +obj-$(CONFIG_MCE_NONFATAL) +=3D non-fatal.o obj-y +=3D util.o obj-y +=3D vmce.o --=20 2.25.1