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[37.24.206.209]) by smtp.gmail.com with ESMTPSA id h6-20020adf9cc6000000b003375d8b0460sm643239wre.1.2024.01.11.01.00.10 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 11 Jan 2024 01:00:10 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: d35fb0ba-b05f-11ee-9b0f-b553b5be7939 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=google; t=1704963610; x=1705568410; darn=lists.xenproject.org; h=content-transfer-encoding:in-reply-to:autocrypt:references:cc:to :from:content-language:subject:user-agent:mime-version:date :message-id:from:to:cc:subject:date:message-id:reply-to; bh=qawFEibbVgiRlO1H8/uU4f49OyAJbl7VHfPdVn+MISc=; b=PyNNb6egspxaHIasxBqh8q8bi+pABNwJWUmN5csi1CoNoQs14xlJvHx4v8X7WsrWR1 YbIadCLaN9MYuho+aiLftDKFmMoO7pRvAEgjmSAP9DGQg4SiLYufxb+5iGTAIwz1S192 N5bWesevjbA496grKoTEJ+cEGvgHfZl+gSRmwE8iPb8Hgxed7hYBuzeRAgqhY3zDfdMA NcTQrj6G8RaSqTxqMhDnCbJJ6y80VqyG+gcAvcnDCuWXJ0mPJXUeutl1xsfAvpbrCDAo rqvRPF0LiIpXzcb5cnxcXjdrrc7VrX1VhsBOo2RNhOeElkTjmBva3xRE697quCAsH4aA sYRA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704963610; x=1705568410; h=content-transfer-encoding:in-reply-to:autocrypt:references:cc:to :from:content-language:subject:user-agent:mime-version:date :message-id:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=qawFEibbVgiRlO1H8/uU4f49OyAJbl7VHfPdVn+MISc=; b=amJTXQXMML2qV37erpPzRnvNHy7BzLrWXhxyqtDFOMowdEkxOUjF4HrJj8VMZZuBkn 2cR03M7Qwb2HCUr4IXewLhvmv4Bc2+M2WSurmwWWINuxoOrWiKcUcVgso4TxxyOf/kdn GnZVQFtg7N/YBLt+XqSIe3kMtZ4tNzLA3wotrwtIm0BC/OHC0Oj4ApgFdb+49hbxIFPE Qsr7JRfXhxJxoJ+Kuj/hLsL0PKfMWROTs89DdaziLZGrVP7WBB6sAqD1voZBIxTIJVrg nkoAMeY4BamefUck+aJ972Rd4JaOURFq2iu6+9dfYODhES7Oy+AhfZl7ZK+uqUJSfZ8j 6Sgw== X-Gm-Message-State: AOJu0YxMfhh3pOjZ5JvNfjJE8XDnYBQtRONtxYJpzAL9beb5G4L8ZZ+y W5nARTVgXUQMdcy91zG6HrUhd5oiBWJGFSt+bXG/dwQr9Q== X-Google-Smtp-Source: AGHT+IEQKhzsNvlICIbgdAIU0k5/NJfJjUUsGbtye2SjRba9mbbQ6GOLq58VPZlbsRSgQzx0tQhCjQ== X-Received: by 2002:a2e:8655:0:b0:2cc:6f7f:6ba4 with SMTP id i21-20020a2e8655000000b002cc6f7f6ba4mr103630ljj.199.1704963610473; Thu, 11 Jan 2024 01:00:10 -0800 (PST) Message-ID: Date: Thu, 11 Jan 2024 10:00:10 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH v4 3/8] VMX: tertiary execution control infrastructure Content-Language: en-US From: Jan Beulich To: "xen-devel@lists.xenproject.org" Cc: Andrew Cooper , Wei Liu , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Kevin Tian , Jun Nakajima References: <9dd23064-c79e-4a50-9c71-c0e73b189944@suse.com> Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <9dd23064-c79e-4a50-9c71-c0e73b189944@suse.com> Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @suse.com) X-ZM-MESSAGEID: 1704963632093100001 Content-Type: text/plain; charset="utf-8" This is a prereq to enabling the MSRLIST feature. Note that the PROCBASED_CTLS3 MSR is different from other VMX feature reporting MSRs, in that all 64 bits report allowed 1-settings. vVMX code is left alone, though, for the time being. Signed-off-by: Jan Beulich --- v2: New. --- a/xen/arch/x86/hvm/vmx/vmcs.c +++ b/xen/arch/x86/hvm/vmx/vmcs.c @@ -164,6 +164,7 @@ static int cf_check parse_ept_param_runt u32 vmx_pin_based_exec_control __read_mostly; u32 vmx_cpu_based_exec_control __read_mostly; u32 vmx_secondary_exec_control __read_mostly; +uint64_t vmx_tertiary_exec_control __read_mostly; u32 vmx_vmexit_control __read_mostly; u32 vmx_vmentry_control __read_mostly; u64 vmx_ept_vpid_cap __read_mostly; @@ -228,10 +229,32 @@ static u32 adjust_vmx_controls( return ctl; } =20 -static bool cap_check(const char *name, u32 expected, u32 saw) +static uint64_t adjust_vmx_controls2( + const char *name, uint64_t ctl_min, uint64_t ctl_opt, unsigned int msr, + bool *mismatch) +{ + uint64_t vmx_msr, ctl =3D ctl_min | ctl_opt; + + rdmsrl(msr, vmx_msr); + + ctl &=3D vmx_msr; /* bit =3D=3D 0 =3D=3D> must be zero */ + + /* Ensure minimum (required) set of control bits are supported. */ + if ( ctl_min & ~ctl ) + { + *mismatch =3D true; + printk("VMX: CPU%u has insufficient %s (%#lx; requires %#lx)\n", + smp_processor_id(), name, ctl, ctl_min); + } + + return ctl; +} + +static bool cap_check( + const char *name, unsigned long expected, unsigned long saw) { if ( saw !=3D expected ) - printk("VMX %s: saw %#x expected %#x\n", name, saw, expected); + printk("VMX %s: saw %#lx expected %#lx\n", name, saw, expected); return saw !=3D expected; } =20 @@ -241,6 +264,7 @@ static int vmx_init_vmcs_config(bool bsp u32 _vmx_pin_based_exec_control; u32 _vmx_cpu_based_exec_control; u32 _vmx_secondary_exec_control =3D 0; + uint64_t _vmx_tertiary_exec_control =3D 0; u64 _vmx_ept_vpid_cap =3D 0; u64 _vmx_misc_cap =3D 0; u32 _vmx_vmexit_control; @@ -274,7 +298,8 @@ static int vmx_init_vmcs_config(bool bsp opt =3D (CPU_BASED_ACTIVATE_MSR_BITMAP | CPU_BASED_TPR_SHADOW | CPU_BASED_MONITOR_TRAP_FLAG | - CPU_BASED_ACTIVATE_SECONDARY_CONTROLS); + CPU_BASED_ACTIVATE_SECONDARY_CONTROLS | + CPU_BASED_ACTIVATE_TERTIARY_CONTROLS); _vmx_cpu_based_exec_control =3D adjust_vmx_controls( "CPU-Based Exec Control", min, opt, MSR_IA32_VMX_PROCBASED_CTLS, &mismatch); @@ -338,6 +363,15 @@ static int vmx_init_vmcs_config(bool bsp MSR_IA32_VMX_PROCBASED_CTLS2, &mismatch); } =20 + if ( _vmx_cpu_based_exec_control & CPU_BASED_ACTIVATE_TERTIARY_CONTROL= S ) + { + uint64_t opt =3D 0; + + _vmx_tertiary_exec_control =3D adjust_vmx_controls2( + "Tertiary Exec Control", 0, opt, + MSR_IA32_VMX_PROCBASED_CTLS3, &mismatch); + } + /* The IA32_VMX_EPT_VPID_CAP MSR exists only when EPT or VPID availabl= e */ if ( _vmx_secondary_exec_control & (SECONDARY_EXEC_ENABLE_EPT | SECONDARY_EXEC_ENABLE_VPID) ) @@ -468,6 +502,7 @@ static int vmx_init_vmcs_config(bool bsp vmx_pin_based_exec_control =3D _vmx_pin_based_exec_control; vmx_cpu_based_exec_control =3D _vmx_cpu_based_exec_control; vmx_secondary_exec_control =3D _vmx_secondary_exec_control; + vmx_tertiary_exec_control =3D _vmx_tertiary_exec_control; vmx_ept_vpid_cap =3D _vmx_ept_vpid_cap; vmx_vmexit_control =3D _vmx_vmexit_control; vmx_vmentry_control =3D _vmx_vmentry_control; @@ -503,6 +538,9 @@ static int vmx_init_vmcs_config(bool bsp "Secondary Exec Control", vmx_secondary_exec_control, _vmx_secondary_exec_control); mismatch |=3D cap_check( + "Tertiary Exec Control", + vmx_tertiary_exec_control, _vmx_tertiary_exec_control); + mismatch |=3D cap_check( "VMExit Control", vmx_vmexit_control, _vmx_vmexit_control); mismatch |=3D cap_check( @@ -1080,6 +1118,7 @@ static int construct_vmcs(struct vcpu *v v->arch.hvm.vmx.exec_control |=3D CPU_BASED_RDTSC_EXITING; =20 v->arch.hvm.vmx.secondary_exec_control =3D vmx_secondary_exec_control; + v->arch.hvm.vmx.tertiary_exec_control =3D vmx_tertiary_exec_control; =20 /* * Disable features which we don't want active by default: @@ -1134,6 +1173,10 @@ static int construct_vmcs(struct vcpu *v __vmwrite(SECONDARY_VM_EXEC_CONTROL, v->arch.hvm.vmx.secondary_exec_control); =20 + if ( cpu_has_vmx_tertiary_exec_control ) + __vmwrite(TERTIARY_VM_EXEC_CONTROL, + v->arch.hvm.vmx.tertiary_exec_control); + /* MSR access bitmap. */ if ( cpu_has_vmx_msr_bitmap ) { @@ -2068,10 +2111,12 @@ void vmcs_dump_vcpu(struct vcpu *v) vmr(HOST_PERF_GLOBAL_CTRL)); =20 printk("*** Control State ***\n"); - printk("PinBased=3D%08x CPUBased=3D%08x SecondaryExec=3D%08x\n", + printk("PinBased=3D%08x CPUBased=3D%08x\n", vmr32(PIN_BASED_VM_EXEC_CONTROL), - vmr32(CPU_BASED_VM_EXEC_CONTROL), - vmr32(SECONDARY_VM_EXEC_CONTROL)); + vmr32(CPU_BASED_VM_EXEC_CONTROL)); + printk("SecondaryExec=3D%08x TertiaryExec=3D%08lx\n", + vmr32(SECONDARY_VM_EXEC_CONTROL), + vmr(TERTIARY_VM_EXEC_CONTROL)); printk("EntryControls=3D%08x ExitControls=3D%08x\n", vmentry_ctl, vmex= it_ctl); printk("ExceptionBitmap=3D%08x PFECmask=3D%08x PFECmatch=3D%08x\n", vmr32(EXCEPTION_BITMAP), --- a/xen/arch/x86/include/asm/hvm/vmx/vmcs.h +++ b/xen/arch/x86/include/asm/hvm/vmx/vmcs.h @@ -114,6 +114,7 @@ struct vmx_vcpu { /* Cache of cpu execution control. */ u32 exec_control; u32 secondary_exec_control; + uint64_t tertiary_exec_control; u32 exception_bitmap; =20 uint64_t shadow_gs; @@ -196,6 +197,7 @@ void vmx_vmcs_reload(struct vcpu *v); #define CPU_BASED_RDTSC_EXITING 0x00001000U #define CPU_BASED_CR3_LOAD_EXITING 0x00008000U #define CPU_BASED_CR3_STORE_EXITING 0x00010000U +#define CPU_BASED_ACTIVATE_TERTIARY_CONTROLS 0x00020000U #define CPU_BASED_CR8_LOAD_EXITING 0x00080000U #define CPU_BASED_CR8_STORE_EXITING 0x00100000U #define CPU_BASED_TPR_SHADOW 0x00200000U @@ -260,6 +262,13 @@ extern u32 vmx_vmentry_control; #define SECONDARY_EXEC_NOTIFY_VM_EXITING 0x80000000U extern u32 vmx_secondary_exec_control; =20 +#define TERTIARY_EXEC_LOADIWKEY_EXITING BIT(0, UL) +#define TERTIARY_EXEC_ENABLE_HLAT BIT(1, UL) +#define TERTIARY_EXEC_EPT_PAGING_WRITE BIT(2, UL) +#define TERTIARY_EXEC_GUEST_PAGING_VERIFY BIT(3, UL) +#define TERTIARY_EXEC_IPI_VIRT BIT(4, UL) +extern uint64_t vmx_tertiary_exec_control; + #define VMX_EPT_EXEC_ONLY_SUPPORTED 0x00000001 #define VMX_EPT_WALK_LENGTH_4_SUPPORTED 0x00000040 #define VMX_EPT_MEMORY_TYPE_UC 0x00000100 @@ -295,6 +304,8 @@ extern u64 vmx_ept_vpid_cap; (vmx_cpu_based_exec_control & CPU_BASED_ACTIVATE_MSR_BITMAP) #define cpu_has_vmx_secondary_exec_control \ (vmx_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) +#define cpu_has_vmx_tertiary_exec_control \ + (vmx_cpu_based_exec_control & CPU_BASED_ACTIVATE_TERTIARY_CONTROLS) #define cpu_has_vmx_ept \ (vmx_secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) #define cpu_has_vmx_dt_exiting \ @@ -422,6 +433,7 @@ enum vmcs_field { VIRT_EXCEPTION_INFO =3D 0x0000202a, XSS_EXIT_BITMAP =3D 0x0000202c, TSC_MULTIPLIER =3D 0x00002032, + TERTIARY_VM_EXEC_CONTROL =3D 0x00002034, GUEST_PHYSICAL_ADDRESS =3D 0x00002400, VMCS_LINK_POINTER =3D 0x00002800, GUEST_IA32_DEBUGCTL =3D 0x00002802, --- a/xen/arch/x86/include/asm/msr-index.h +++ b/xen/arch/x86/include/asm/msr-index.h @@ -347,6 +347,7 @@ #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x48f #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x490 #define MSR_IA32_VMX_VMFUNC 0x491 +#define MSR_IA32_VMX_PROCBASED_CTLS3 0x492 =20 /* K7/K8 MSRs. Not complete. See the architecture manual for a more complete list. */ --- a/xen/arch/x86/hvm/vmx/vmx.c +++ b/xen/arch/x86/hvm/vmx/vmx.c @@ -760,6 +760,12 @@ void vmx_update_secondary_exec_control(s v->arch.hvm.vmx.secondary_exec_control); } =20 +void vmx_update_tertiary_exec_control(struct vcpu *v) +{ + __vmwrite(TERTIARY_VM_EXEC_CONTROL, + v->arch.hvm.vmx.tertiary_exec_control); +} + void vmx_update_exception_bitmap(struct vcpu *v) { u32 bitmap =3D unlikely(v->arch.hvm.vmx.vmx_realmode) --- a/xen/arch/x86/include/asm/hvm/vmx/vmx.h +++ b/xen/arch/x86/include/asm/hvm/vmx/vmx.h @@ -81,6 +81,7 @@ void vmx_realmode(struct cpu_user_regs * void vmx_update_exception_bitmap(struct vcpu *v); void vmx_update_cpu_exec_control(struct vcpu *v); void vmx_update_secondary_exec_control(struct vcpu *v); +void vmx_update_tertiary_exec_control(struct vcpu *v); =20 #define POSTED_INTR_ON 0 #define POSTED_INTR_SN 1