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[109.243.69.121]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-bc81d5e9583sm57549966b.17.2026.05.07.01.59.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 May 2026 01:59:16 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=20251104 header.d=gmail.com header.i="@gmail.com" header.h="Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1778144358; x=1778749158; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=x4xx6/9HjQw0qDDPVFVAifvL6T1Uk5lWG9wv0V6Tryc=; b=arfaYfjsPY0xibppCmeb4yALQvEfJo5UbdgLTT9a4KcOLx6jj8PA9l4o38QXhvJvDB LRBKkUAXYYIDwYy/A0rxHosR/naXy0Fzh6r+bp/YO1Q4Av3b7J/GmT6nTcT8vPsYcUMo pkP8Z480AIgoxtmXizFhf4Rc4kayEZKKpEOl/dD00VeuwFTBUu12nT109YH4yLR9UGZN MQwvsQy0urlgGUsE0WvQTrL4p7Ld5Y9hskWIfe0hpT+j+E4Ba78SlTLz8JlXNMnNKDVV oIp2Nu4cHVwzuPi9f/8eff6nM3vhrfR/r2ZHzpqKP8NWLe8dTuo3YA4o5Sm9g9qNB/J0 DqTg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1778144358; x=1778749158; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=x4xx6/9HjQw0qDDPVFVAifvL6T1Uk5lWG9wv0V6Tryc=; b=VSHczLp72NOjb1/r/zD2uBspNDz8ggO2t7LnyCqGz6g1LNAvldjCND7ojPSCaAhb7h u6CHRI+SxSYPe5bA9d9RSAkWrztxCZ/XTEeA4k0NvkeVv7hXdZqA5LJlQbZR+Inyvl4Q SPrJsMI5p1td5UHeIR+GMEd9TvE3KH3V4LmXXKl3HCC6iszyPDqzk7bU0HgUPrfr5veD 0pGz5CwhoZVYvR+SECwP8Io22y/QB5T6ulHJaZeYDxHZEn73hAQuQGfdotsmDk404omM N/0Is/7nQfjIdULNmZZW6nfvFfPItHxkzZBXAtO0QED264uGiUXdfuSv4kVEoXpEGFTJ K2Fg== X-Gm-Message-State: AOJu0YySDb9GhX2g9ipj4ndCS/378sd+GyQVN6A4hl4qQMBwOJSXSTVG xp9oMPdJTxHM+N+N4AALd90yXQcXsvMJplooEhVxVU9wlqkC5xENBDC7NAmKBg== X-Gm-Gg: AeBDiesNM1cwXQIhJsBi0R1RqRMkn10Gic30KDpaNCj9FkNnUyQTabEvMACLZCn9hjM gu4XuNkgj3/Eu5GlUIE3pk9L+3QQDYCieOFiyRizBUDeyDO5qcmbVfXcRjdual3G1DFSW+9VRxb Q3C/RLhqnnyJLBpaA4OtrBUmKyI6m8NgNvUXsNolyLTLhr3m1ZW+EtLGbOnY681WhwTEq7+rotB wbaF8EEn6EhFaByDYX/JWHUXsBCMN29c+ggWbYj1yEZwwfWLRVGU96M4xPAYX6LO6y8umGow7tp jyePTBlvgOOsSo4WnlbKX1Xhag/pPS4NCIf0H+jvJz1/NQXzjyMsiNfPHvedNwxThZoKJW1uJlS 51uO4OlOPk1q2Oam2f2zQrXFdPsoNAxcOYrDGXkZCA1FE8nvOpGuJhWZWs0CDWJ9ORk0WdFksWC UfZe2y3R80KMTU84jiezBs/Rby7Egf/LM32zTKTPynGbbZr5cB71OQ5cJkWRQYQaY3xf+HNYeqS 2EO X-Received: by 2002:a17:907:c06:b0:b9c:9594:e00 with SMTP id a640c23a62f3a-bc56aa4283emr413226166b.1.1778144357643; Thu, 07 May 2026 01:59:17 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Romain Caritey , Oleksii Kurochko , Alistair Francis , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH v5 10/11] xen/riscv: add definition of guest RAM banks Date: Thu, 7 May 2026 10:58:49 +0200 Message-ID: <9c04bfe7d7f5510e164567c35e6ea223509f45d5.1778140240.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-d62444/1778144358-AC457FF4-4B987711/10/73395122804 X-purgate-type: spam X-purgate-size: 3241 X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1778144381244158500 The dom0less solution uses defined RAM banks as compile-time constants, so introduce macros to describe guest RAM banks. The reason for 2 banks is that there is typically always a use case for low memory under 4 GB, but the bank under 4 GB ends up being small because there are other things under 4 GB it can conflict with (interrupt controller, PCI BARs, etc.). So a second bank is added above that MMIO region (starting at 8 GiB) to provide the remaining RAM; the gap between the two banks also exercises code paths handling discontiguous memory. For Sv32 guests (34-bit GPA, 16 GiB addressable), bank0 provides 2 GB (2=E2=80=934 GB) and the first 8 GB of bank1 (8=E2=80=9316 GB) is accessibl= e. Extended regions are useful for RISC-V: they could be used to provide a "space" for Linux to map grant mappings. Despite the fact that for every guest MMU mode the GPA could be up to 56 bits wide (except Sv32 whose GPA is 34 bits), the combined size of both banks is limited to 1018 GB as it is more than enough for most use cases. Add inclusion of asm/guest-layout.h to asm/domain.h to make dom0less common code build happy. Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich --- Changes in v5: - Nothing changed. Only rebase. --- Changes in v4: - Add Acked-by: Jan Beulich . --- Changes in v3: - Move GUEST_RAM*-related defines to asm/p2m.h instead of public header. --- Changes in v2: - New patch. --- --- xen/arch/riscv/include/asm/domain.h | 1 + xen/arch/riscv/include/asm/guest-layout.h | 23 +++++++++++++++++++++++ 2 files changed, 24 insertions(+) create mode 100644 xen/arch/riscv/include/asm/guest-layout.h diff --git a/xen/arch/riscv/include/asm/domain.h b/xen/arch/riscv/include/a= sm/domain.h index 6c48bf13111d..6044ce0feee0 100644 --- a/xen/arch/riscv/include/asm/domain.h +++ b/xen/arch/riscv/include/asm/domain.h @@ -7,6 +7,7 @@ #include #include =20 +#include #include #include =20 diff --git a/xen/arch/riscv/include/asm/guest-layout.h b/xen/arch/riscv/inc= lude/asm/guest-layout.h new file mode 100644 index 000000000000..68d95a09394c --- /dev/null +++ b/xen/arch/riscv/include/asm/guest-layout.h @@ -0,0 +1,23 @@ +#ifndef ASM_RISCV_GUEST_LAYOUT_H +#define ASM_RISCV_GUEST_LAYOUT_H + +#include + +#define GUEST_RAM_BANKS 2 + +/* + * The way to find the extended regions (to be exposed to the guest as unu= sed + * address space) relies on the fact that the regions reserved for the RAM + * below are big enough to also accommodate such regions. + */ +#define GUEST_RAM0_BASE xen_mk_ullong(0x80000000) /* 2GB of low RAM @ 2G= B */ +#define GUEST_RAM0_SIZE xen_mk_ullong(0x80000000) + +#define GUEST_RAM1_BASE xen_mk_ullong(0x0200000000) /* 1016 GB of RAM @ = 8GB */ +#define GUEST_RAM1_SIZE xen_mk_ullong(0xFE00000000) + +/* TODO: allocate these all dynamically */ +#define GUEST_RAM_BANK_BASES { GUEST_RAM0_BASE, GUEST_RAM1_BASE } +#define GUEST_RAM_BANK_SIZES { GUEST_RAM0_SIZE, GUEST_RAM1_SIZE } + +#endif /* ASM_RISCV_GUEST_LAYOUT_H */ --=20 2.54.0