From nobody Thu Oct 30 23:12:07 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail(p=none dis=none) header.from=arm.com Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1756379635469859.3527972460578; Thu, 28 Aug 2025 04:13:55 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.1098392.1452461 (Exim 4.92) (envelope-from ) id 1uraZY-0001ns-Ba; Thu, 28 Aug 2025 11:13:40 +0000 Received: by outflank-mailman (output) from mailman id 1098392.1452461; Thu, 28 Aug 2025 11:13:40 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uraZY-0001nj-8T; Thu, 28 Aug 2025 11:13:40 +0000 Received: by outflank-mailman (input) for mailman id 1098392; Thu, 28 Aug 2025 11:13:38 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uraZW-0001Z0-RA for xen-devel@lists.xenproject.org; Thu, 28 Aug 2025 11:13:38 +0000 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by se1-gles-sth1.inumbo.com (Halon) with ESMTP id 0bb0fe47-8400-11f0-aeb2-fb57b961d000; Thu, 28 Aug 2025 13:13:38 +0200 (CEST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 29D4B1688; Thu, 28 Aug 2025 04:13:29 -0700 (PDT) Received: from PWQ0QT7DJ1.emea.arm.com (PWQ0QT7DJ1.cambridge.arm.com [10.1.33.71]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 0D7CE3F694; Thu, 28 Aug 2025 04:13:35 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 0bb0fe47-8400-11f0-aeb2-fb57b961d000 From: Hari Limaye To: xen-devel@lists.xenproject.org Cc: luca.fancellu@arm.com, Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk Subject: [PATCH v3 1/5] arm/mpu: Implement setup_frametable_mappings for MPU systems Date: Thu, 28 Aug 2025 12:12:03 +0100 Message-ID: <99af1bac04c89a0c912f7f9c7e134ce79049e2a3.1756379422.git.hari.limaye@arm.com> X-Mailer: git-send-email 2.42.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZM-MESSAGEID: 1756379636863116600 Content-Type: text/plain; charset="utf-8" From: Luca Fancellu Implement the MPU variant of `setup_frametable_mappings`. This function will be called by `setup_mm` when an implementation for MPU systems is added in a follow up commit. Signed-off-by: Luca Fancellu Signed-off-by: Hari Limaye Reviewed-by: Michal Orzel --- Changes from v1: - Align ps and pe to page size - Add sanity checking for frametable size, as in MMU version - Add Michal's R-b --- xen/arch/arm/mpu/mm.c | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/xen/arch/arm/mpu/mm.c b/xen/arch/arm/mpu/mm.c index c6891607ec..3f155b7db2 100644 --- a/xen/arch/arm/mpu/mm.c +++ b/xen/arch/arm/mpu/mm.c @@ -168,6 +168,39 @@ int mpumap_contains_region(pr_t *table, uint8_t nr_reg= ions, paddr_t base, return MPUMAP_REGION_NOTFOUND; } =20 +/* Map a frame table to cover physical addresses ps through pe */ +void __init setup_frametable_mappings(paddr_t ps, paddr_t pe) +{ + mfn_t base_mfn; + paddr_t aligned_ps =3D ROUNDUP(ps, PAGE_SIZE); + paddr_t aligned_pe =3D ROUNDDOWN(pe, PAGE_SIZE); + + unsigned long nr_pdxs =3D mfn_to_pdx(mfn_add(maddr_to_mfn(aligned_pe),= -1)) - + mfn_to_pdx(maddr_to_mfn(aligned_ps)) + 1; + unsigned long frametable_size =3D nr_pdxs * sizeof(struct page_info); + + /* + * The size of paddr_t should be sufficient for the complete range of + * physical address. + */ + BUILD_BUG_ON((sizeof(paddr_t) * BITS_PER_BYTE) < PADDR_BITS); + BUILD_BUG_ON(sizeof(struct page_info) !=3D PAGE_INFO_SIZE); + + if ( frametable_size > FRAMETABLE_SIZE ) + panic("The frametable cannot cover the physical region %#"PRIpaddr= " - %#"PRIpaddr"\n", + ps, pe); + + frametable_base_pdx =3D paddr_to_pdx(aligned_ps); + frametable_size =3D ROUNDUP(frametable_size, PAGE_SIZE); + + base_mfn =3D alloc_boot_pages(frametable_size >> PAGE_SHIFT, 1); + frame_table =3D (struct page_info *)mfn_to_virt(mfn_x(base_mfn)); + + memset(&frame_table[0], 0, nr_pdxs * sizeof(struct page_info)); + memset(&frame_table[nr_pdxs], -1, + frametable_size - (nr_pdxs * sizeof(struct page_info))); +} + /* * Allocate an entry for a new EL2 MPU region in the bitmap xen_mpumap_mas= k. * @param idx Set to the index of the allocated EL2 MPU region on succes= s. --=20 2.34.1