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([45.12.24.216]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-67b86caae44sm3140490a12.12.2026.05.04.02.21.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 May 2026 02:21:14 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=20251104 header.d=gmail.com header.i="@gmail.com" header.h="Content-Transfer-Encoding:MIME-Version:Message-ID:Date:Subject:Cc:To:From" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1777886475; x=1778491275; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=wkyQEgJUNM3LgfrP5sMqaw1jbx8pNrvLd2PNokV1c2g=; b=cQAbONbbhKykHzbLCOt5MJjd5Dd59g/WmLotIBtyZ8oUNtt/9ZCHwvjyBsYDEXrwiU dK9FAhycHsJFOn5OIID839DNfm2h31meEAsvdzM1x5j3kssmcffHkVWB01LZeMr5gIal QUA3kfIiUovrl2sOIHkux9K4kej5ZUEQeeYFyaHdMEA1q0wpJ5QcOYPKNeRNIchND7Dw Mlpnj3ZsiEoPdd/3uY6ppd9/P7TNqfuStPjTcatIH7f8uhyZz3oHbHRMvTyLNTlGF9pP /c+BOUnBRQgDY4PHGZQjwjdNI3iKk64K8eLTmxqS18e/uBLlDz0484CitRwkZ6YhwsiW Qp+w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1777886475; x=1778491275; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-gg:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=wkyQEgJUNM3LgfrP5sMqaw1jbx8pNrvLd2PNokV1c2g=; b=W0GWa07CXaoYKxHV8+48rmktqaTf+RYIybJmxmtvz4XAp94lyjD3Hc1UOzYN5KiLLO k0cAQs5mpUmRyPsWf3bEHKu599idZ8aZIzeZNQkywXKx3cdsZ81/lkj3cLuy0Na6Lh61 xYsuIXw/6mZ8rCD99rv4Ti2ewQNiOZZrjTSqylAMC+G9jOdMJe44K/C6fJDLT/HzcKcC 2D8IDFCyiQxUn8d8XwBXprRmDXU2b5u2/Nh1g6qxIwC8QVggoaJic3Aewewfb/sZj0eP Y0wpR8BVoJXHXZ8LpHaJrJeoY7bEtNVXj1szpkEZE91kfGzZ1FHVkrPAzUfKi+bg1d6w vtKQ== X-Gm-Message-State: AOJu0Yw+QK4oWhwFfQtod5z0SV9rA8f7WwgboWkq8PH3uZu3rY9BJk+6 BZ73PTuQPtryM5LpEmVgyfHznBkArPuf+hn7EOZT23WgfTp4pXS8NIJ8CqBpdFvg X-Gm-Gg: AeBDieudiW+Mscr8jUUC4sP+zsWYXAMGmsEXaoB9Ka4Ylb8iDtCYrx8xV5vH8fb9cNR NQmYsi6TE49K21g7Ttcr2q2kPCFr0ABGFaJbnIaPgNCsgwOei5NGaeZSEEiPbFLZT/TH9QPx6i8 4HbL8edsJo9QdEMEFibEtP38fxxomfmPMz70rgpCn/y+uaf46UtMg2PGFyeIykvh+r1y6Km2eks F2fTRB1PFCZPB6cmmYS13b8QSlKv8cdvBGWhNp5fTFucOIDLisr/I6HuHPrjb103qLuMvItGVSL G+eRazLr/f7NCDvQGoAyCrJxE0D0AYJRDQUigADci0uxvYmNTOZnm6PEGARE1HVPFFvZD+gdhxu SQwkRLMNM6m3i76WyjCY8Re984m4Ej1tJr3v6cwQFcql7Iqz1RWf3MK9o8A/mHHNRp33FNdSB2Y HKJfyhJi+AdMzI3eD33rROV9xirZGCRO0lzKZwJg== X-Received: by 2002:a05:6402:5057:b0:676:6e7c:2e3b with SMTP id 4fb4d7f45d1cf-67c18122342mr2813961a12.7.1777886475082; Mon, 04 May 2026 02:21:15 -0700 (PDT) From: Mykola Kvach To: xen-devel@lists.xenproject.org Cc: Mykola Kvach , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk Subject: [PATCH] xen/arm: scan CLIDR Ctype fields upwards when probing LLC Date: Mon, 4 May 2026 12:19:06 +0300 Message-ID: <998162706f89bb3100bda409d8fde3c8b143eae6.1777886129.git.mykola_kvach@epam.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-4011c0/1777886476-4797E8B7-60F9D5E0/0/0 X-purgate-type: clean X-purgate-size: 3387 X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1777886499777158500 Content-Type: text/plain; charset="utf-8" From: Mykola Kvach get_llc_way_size() currently scans CLIDR_EL1 Ctype fields from the highest level downwards and stops at the first unified cache it finds. However, CLIDR_EL1 describes the cache hierarchy from Ctype1 upwards. Arm ARM DDI 0487J.a, D19.2.27 says that once software has seen a Ctype value of 0b000 while reading from Ctype1 upwards, no caches manageable by the architected set/way maintenance instructions exist at further-out levels, and the higher Ctype fields must be ignored. The current reverse scan can therefore select a unified cache level from a Ctype field above the first no-cache level. Such a field is not part of the architecturally described CLIDR/CCSIDR cache hierarchy and should not be used for selecting the CCSIDR level. Scan Ctype fields from L1 upwards, stop at the first no-cache level, and keep the outermost unified cache observed before that point. This preserves the result for regular cache hierarchies, while avoiding selection of an architecturally ignored Ctype field. Fixes: f4985fce6f0b ("xen/arm: add initial support for LLC coloring on arm6= 4") Signed-off-by: Mykola Kvach Reviewed-by: Luca Fancellu Reviewed-by: Michal Orzel --- This patch follows the xen-devel discussion: https://lists.xenproject.org/archives/html/xen-devel/2026-01/msg00345.html In that thread, Michal noted that the reverse scan was a simplification rather than an intentional requirement, and that changing the implementation would be fine. Testing performed: - standalone synthetic CLIDR tests covered both regular and pathological Ctype sequences and showed that the forward scan ignores unified cache levels above the first Ctype =3D=3D 0b000 while the reverse scan can pick them - Renesas H3ULCB booted with llc-coloring=3Don --- xen/arch/arm/llc-coloring.c | 22 +++++++++++++++++----- 1 file changed, 17 insertions(+), 5 deletions(-) diff --git a/xen/arch/arm/llc-coloring.c b/xen/arch/arm/llc-coloring.c index 6f78817c57..3783f4c824 100644 --- a/xen/arch/arm/llc-coloring.c +++ b/xen/arch/arm/llc-coloring.c @@ -22,21 +22,33 @@ unsigned int __init get_llc_way_size(void) register_t id_aa64mmfr2_el1 =3D READ_SYSREG(ID_AA64MMFR2_EL1); uint32_t ccsidr_numsets_shift =3D CCSIDR_NUMSETS_SHIFT; uint32_t ccsidr_numsets_mask =3D CCSIDR_NUMSETS_MASK; - unsigned int n, line_size, num_sets; - - for ( n =3D CLIDR_CTYPEn_LEVELS; n !=3D 0; n-- ) + unsigned int n, line_size, num_sets, llc_level =3D 0; + + /* + * CLIDR_EL1 Ctype fields are interpreted from Ctype1 upwards. Once a + * no-cache level is seen, higher Ctype fields are architecturally ign= ored + * for the CLIDR/CCSIDR set/way manageable cache hierarchy. + * + * Keep the outermost unified cache before that point. + */ + for ( n =3D 1; n <=3D CLIDR_CTYPEn_LEVELS; n++ ) { uint8_t ctype_n =3D (clidr_el1 >> CLIDR_CTYPEn_SHIFT(n)) & CLIDR_CTYPEn_MASK; =20 + if ( ctype_n =3D=3D 0b000 ) + break; + /* Unified cache (see Arm ARM DDI 0487J.a D19.2.27) */ if ( ctype_n =3D=3D 0b100 ) - break; + llc_level =3D n; } =20 - if ( n =3D=3D 0 ) + if ( !llc_level ) return 0; =20 + n =3D llc_level; + WRITE_SYSREG((n - 1) << CSSELR_LEVEL_SHIFT, CSSELR_EL1); isb(); =20 --=20 2.43.0