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mx.microsoft.com 1; spf=pass smtp.mailfrom=suse.com; dmarc=pass action=none header.from=suse.com; dkim=pass header.d=suse.com; arc=none Authentication-Results: xen.org; dkim=none (message not signed) header.d=none;xen.org; dmarc=none action=none header.from=suse.com; Subject: [PATCH v2 01/18] AMD/IOMMU: have callers specify the target level for page table walks From: Jan Beulich To: "xen-devel@lists.xenproject.org" Cc: Andrew Cooper , Paul Durrant References: <957f067b-9fe1-2350-4266-51982f09d3a9@suse.com> Message-ID: <57abd488-1fa1-8eae-66b9-196f32f7f4be@suse.com> Date: Fri, 24 Sep 2021 11:41:14 +0200 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.14.0 In-Reply-To: <957f067b-9fe1-2350-4266-51982f09d3a9@suse.com> Content-Language: en-US Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: PR3P192CA0013.EURP192.PROD.OUTLOOK.COM (2603:10a6:102:56::18) To VI1PR04MB5600.eurprd04.prod.outlook.com (2603:10a6:803:e7::16) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 41438e88-62c3-4c5c-ccd3-08d97f3f7462 X-MS-TrafficTypeDiagnostic: VI1PR0401MB2335: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:8273; 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charset="utf-8" In order to be able to insert/remove super-pages we need to allow callers of the walking function to specify at which point to stop the walk. (For now at least gcc will instantiate just a variant of the function with the parameter eliminated, so effectively no change to generated code as far as the parameter addition goes.) Instead of merely adjusting a BUG_ON() condition, convert it into an error return - there's no reason to crash the entire host in that case. Signed-off-by: Jan Beulich --- a/xen/drivers/passthrough/amd/iommu_map.c +++ b/xen/drivers/passthrough/amd/iommu_map.c @@ -178,7 +178,8 @@ void __init iommu_dte_add_device_entry(s * page tables. */ static int iommu_pde_from_dfn(struct domain *d, unsigned long dfn, - unsigned long *pt_mfn, bool map) + unsigned int target, unsigned long *pt_mfn, + bool map) { union amd_iommu_pte *pde, *next_table_vaddr; unsigned long next_table_mfn; @@ -189,7 +190,8 @@ static int iommu_pde_from_dfn(struct dom table =3D hd->arch.amd.root_table; level =3D hd->arch.amd.paging_mode; =20 - BUG_ON( table =3D=3D NULL || level < 1 || level > 6 ); + if ( !table || target < 1 || level < target || level > 6 ) + return 1; =20 /* * A frame number past what the current page tables can represent can't @@ -200,7 +202,7 @@ static int iommu_pde_from_dfn(struct dom =20 next_table_mfn =3D mfn_x(page_to_mfn(table)); =20 - while ( level > 1 ) + while ( level > target ) { unsigned int next_level =3D level - 1; =20 @@ -307,7 +309,7 @@ int amd_iommu_map_page(struct domain *d, return rc; } =20 - if ( iommu_pde_from_dfn(d, dfn_x(dfn), &pt_mfn, true) || !pt_mfn ) + if ( iommu_pde_from_dfn(d, dfn_x(dfn), 1, &pt_mfn, true) || !pt_mfn ) { spin_unlock(&hd->arch.mapping_lock); AMD_IOMMU_DEBUG("Invalid IO pagetable entry dfn =3D %"PRI_dfn"\n", @@ -340,7 +342,7 @@ int amd_iommu_unmap_page(struct domain * return 0; } =20 - if ( iommu_pde_from_dfn(d, dfn_x(dfn), &pt_mfn, false) ) + if ( iommu_pde_from_dfn(d, dfn_x(dfn), 1, &pt_mfn, false) ) { spin_unlock(&hd->arch.mapping_lock); AMD_IOMMU_DEBUG("Invalid IO pagetable entry dfn =3D %"PRI_dfn"\n", From nobody Fri Nov 29 16:38:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; 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charset="utf-8" In order to be able to insert/remove super-pages we need to allow callers of the walking function to specify at which point to stop the walk. For intel_iommu_lookup_page() integrate the last level access into the main walking function. dma_pte_clear_one() gets only partly adjusted for now: Error handling and order parameter get put in place, but the order parameter remains ignored (just like intel_iommu_map_page()'s order part of the flags). Signed-off-by: Jan Beulich --- I have to admit that I don't understand why domain_pgd_maddr() wants to populate all page table levels for DFN 0. I was actually wondering whether it wouldn't make sense to integrate dma_pte_clear_one() into its only caller intel_iommu_unmap_page(), for better symmetry with intel_iommu_map_page(). --- v2: Fix build. --- a/xen/drivers/passthrough/vtd/iommu.c +++ b/xen/drivers/passthrough/vtd/iommu.c @@ -264,63 +264,116 @@ static u64 bus_to_context_maddr(struct v return maddr; } =20 -static u64 addr_to_dma_page_maddr(struct domain *domain, u64 addr, int all= oc) +/* + * This function walks (and if requested allocates) page tables to the + * designated target level. It returns + * - 0 when a non-present entry was encountered and no allocation was + * requested, + * - a small positive value (the level, i.e. below PAGE_SIZE) upon allocat= ion + * failure, + * - for target > 0 the address of the page table holding the leaf PTE for + * the requested address, + * - for target =3D=3D 0 the full PTE. + */ +static uint64_t addr_to_dma_page_maddr(struct domain *domain, daddr_t addr, + unsigned int target, + unsigned int *flush_flags, bool all= oc) { struct domain_iommu *hd =3D dom_iommu(domain); int addr_width =3D agaw_to_width(hd->arch.vtd.agaw); struct dma_pte *parent, *pte =3D NULL; - int level =3D agaw_to_level(hd->arch.vtd.agaw); - int offset; + unsigned int level =3D agaw_to_level(hd->arch.vtd.agaw), offset; u64 pte_maddr =3D 0; =20 addr &=3D (((u64)1) << addr_width) - 1; ASSERT(spin_is_locked(&hd->arch.mapping_lock)); + ASSERT(target || !alloc); + if ( !hd->arch.vtd.pgd_maddr ) { struct page_info *pg; =20 - if ( !alloc || !(pg =3D iommu_alloc_pgtable(domain)) ) + if ( !alloc ) + goto out; + + pte_maddr =3D level; + if ( !(pg =3D iommu_alloc_pgtable(domain)) ) goto out; =20 hd->arch.vtd.pgd_maddr =3D page_to_maddr(pg); } =20 - parent =3D (struct dma_pte *)map_vtd_domain_page(hd->arch.vtd.pgd_madd= r); - while ( level > 1 ) + pte_maddr =3D hd->arch.vtd.pgd_maddr; + parent =3D map_vtd_domain_page(pte_maddr); + while ( level > target ) { offset =3D address_level_offset(addr, level); pte =3D &parent[offset]; =20 pte_maddr =3D dma_pte_addr(*pte); - if ( !pte_maddr ) + if ( !dma_pte_present(*pte) || (level > 1 && dma_pte_superpage(*pt= e)) ) { struct page_info *pg; + /* + * Higher level tables always set r/w, last level page table + * controls read/write. + */ + struct dma_pte new_pte =3D { DMA_PTE_PROT }; =20 if ( !alloc ) - break; + { + pte_maddr =3D 0; + if ( !dma_pte_present(*pte) ) + break; + + /* + * When the leaf entry was requested, pass back the full P= TE, + * with the address adjusted to account for the residual of + * the walk. + */ + pte_maddr =3D pte->val + + (addr & ((1UL << level_to_offset_bits(level)) - 1) & + PAGE_MASK); + if ( !target ) + break; + } =20 + pte_maddr =3D level - 1; pg =3D iommu_alloc_pgtable(domain); if ( !pg ) break; =20 pte_maddr =3D page_to_maddr(pg); - dma_set_pte_addr(*pte, pte_maddr); + dma_set_pte_addr(new_pte, pte_maddr); =20 - /* - * high level table always sets r/w, last level - * page table control read/write - */ - dma_set_pte_readable(*pte); - dma_set_pte_writable(*pte); + if ( dma_pte_present(*pte) ) + { + struct dma_pte *split =3D map_vtd_domain_page(pte_maddr); + unsigned long inc =3D 1UL << level_to_offset_bits(level - = 1); + + split[0].val =3D pte->val; + if ( inc =3D=3D PAGE_SIZE ) + split[0].val &=3D ~DMA_PTE_SP; + + for ( offset =3D 1; offset < PTE_NUM; ++offset ) + split[offset].val =3D split[offset - 1].val + inc; + + iommu_sync_cache(split, PAGE_SIZE); + unmap_vtd_domain_page(split); + + if ( flush_flags ) + *flush_flags |=3D IOMMU_FLUSHF_modified; + } + + write_atomic(&pte->val, new_pte.val); iommu_sync_cache(pte, sizeof(struct dma_pte)); } =20 - if ( level =3D=3D 2 ) + if ( --level =3D=3D target ) break; =20 unmap_vtd_domain_page(parent); parent =3D map_vtd_domain_page(pte_maddr); - level--; } =20 unmap_vtd_domain_page(parent); @@ -346,7 +399,7 @@ static uint64_t domain_pgd_maddr(struct if ( !hd->arch.vtd.pgd_maddr ) { /* Ensure we have pagetables allocated down to leaf PTE. */ - addr_to_dma_page_maddr(d, 0, 1); + addr_to_dma_page_maddr(d, 0, 1, NULL, true); =20 if ( !hd->arch.vtd.pgd_maddr ) return 0; @@ -691,8 +744,9 @@ static int __must_check iommu_flush_iotl } =20 /* clear one page's page table */ -static void dma_pte_clear_one(struct domain *domain, uint64_t addr, - unsigned int *flush_flags) +static int dma_pte_clear_one(struct domain *domain, daddr_t addr, + unsigned int order, + unsigned int *flush_flags) { struct domain_iommu *hd =3D dom_iommu(domain); struct dma_pte *page =3D NULL, *pte =3D NULL; @@ -700,11 +754,11 @@ static void dma_pte_clear_one(struct dom =20 spin_lock(&hd->arch.mapping_lock); /* get last level pte */ - pg_maddr =3D addr_to_dma_page_maddr(domain, addr, 0); - if ( pg_maddr =3D=3D 0 ) + pg_maddr =3D addr_to_dma_page_maddr(domain, addr, 1, flush_flags, fals= e); + if ( pg_maddr < PAGE_SIZE ) { spin_unlock(&hd->arch.mapping_lock); - return; + return pg_maddr ? -ENOMEM : 0; } =20 page =3D (struct dma_pte *)map_vtd_domain_page(pg_maddr); @@ -714,7 +768,7 @@ static void dma_pte_clear_one(struct dom { spin_unlock(&hd->arch.mapping_lock); unmap_vtd_domain_page(page); - return; + return 0; } =20 dma_clear_pte(*pte); @@ -724,6 +778,8 @@ static void dma_pte_clear_one(struct dom iommu_sync_cache(pte, sizeof(struct dma_pte)); =20 unmap_vtd_domain_page(page); + + return 0; } =20 static int iommu_set_root_entry(struct vtd_iommu *iommu) @@ -1836,8 +1892,9 @@ static int __must_check intel_iommu_map_ return 0; } =20 - pg_maddr =3D addr_to_dma_page_maddr(d, dfn_to_daddr(dfn), 1); - if ( !pg_maddr ) + pg_maddr =3D addr_to_dma_page_maddr(d, dfn_to_daddr(dfn), 1, flush_fla= gs, + true); + if ( pg_maddr < PAGE_SIZE ) { spin_unlock(&hd->arch.mapping_lock); return -ENOMEM; @@ -1887,17 +1944,14 @@ static int __must_check intel_iommu_unma if ( iommu_hwdom_passthrough && is_hardware_domain(d) ) return 0; =20 - dma_pte_clear_one(d, dfn_to_daddr(dfn), flush_flags); - - return 0; + return dma_pte_clear_one(d, dfn_to_daddr(dfn), 0, flush_flags); } =20 static int intel_iommu_lookup_page(struct domain *d, dfn_t dfn, mfn_t *mfn, unsigned int *flags) { struct domain_iommu *hd =3D dom_iommu(d); - struct dma_pte *page, val; - u64 pg_maddr; + uint64_t val; =20 /* * If VT-d shares EPT page table or if the domain is the hardware @@ -1909,25 +1963,16 @@ static int intel_iommu_lookup_page(struc =20 spin_lock(&hd->arch.mapping_lock); =20 - pg_maddr =3D addr_to_dma_page_maddr(d, dfn_to_daddr(dfn), 0); - if ( !pg_maddr ) - { - spin_unlock(&hd->arch.mapping_lock); - return -ENOENT; - } - - page =3D map_vtd_domain_page(pg_maddr); - val =3D page[dfn_x(dfn) & LEVEL_MASK]; + val =3D addr_to_dma_page_maddr(d, dfn_to_daddr(dfn), 0, NULL, false); =20 - unmap_vtd_domain_page(page); spin_unlock(&hd->arch.mapping_lock); =20 - if ( !dma_pte_present(val) ) + if ( val < PAGE_SIZE ) return -ENOENT; =20 - *mfn =3D maddr_to_mfn(dma_pte_addr(val)); - *flags =3D dma_pte_read(val) ? IOMMUF_readable : 0; - *flags |=3D dma_pte_write(val) ? IOMMUF_writable : 0; + *mfn =3D maddr_to_mfn(val); + *flags =3D val & DMA_PTE_READ ? IOMMUF_readable : 0; + *flags |=3D val & DMA_PTE_WRITE ? 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charset="utf-8" Generic code will use this information to determine what order values can legitimately be passed to the ->{,un}map_page() hooks. For now all ops structures simply get to announce 4k mappings (as base page size), and there is (and always has been) an assumption that this matches the CPU's MMU base page size (eventually we will want to permit IOMMUs with a base page size smaller than the CPU MMU's). Signed-off-by: Jan Beulich Reviewed-by: Kevin Tian Acked-by: Julien Grall Reviewed-by: Rahul Singh Reviewed-by: Roger Pau Monn=C3=A9 --- a/xen/drivers/passthrough/amd/pci_amd_iommu.c +++ b/xen/drivers/passthrough/amd/pci_amd_iommu.c @@ -629,6 +629,7 @@ static void amd_dump_page_tables(struct } =20 static const struct iommu_ops __initconstrel _iommu_ops =3D { + .page_sizes =3D PAGE_SIZE_4K, .init =3D amd_iommu_domain_init, .hwdom_init =3D amd_iommu_hwdom_init, .quarantine_init =3D amd_iommu_quarantine_init, --- a/xen/drivers/passthrough/arm/ipmmu-vmsa.c +++ b/xen/drivers/passthrough/arm/ipmmu-vmsa.c @@ -1298,6 +1298,7 @@ static void ipmmu_iommu_domain_teardown( =20 static const struct iommu_ops ipmmu_iommu_ops =3D { + .page_sizes =3D PAGE_SIZE_4K, .init =3D ipmmu_iommu_domain_init, .hwdom_init =3D ipmmu_iommu_hwdom_init, .teardown =3D ipmmu_iommu_domain_teardown, --- a/xen/drivers/passthrough/arm/smmu.c +++ b/xen/drivers/passthrough/arm/smmu.c @@ -2873,6 +2873,7 @@ static void arm_smmu_iommu_domain_teardo } =20 static const struct iommu_ops arm_smmu_iommu_ops =3D { + .page_sizes =3D PAGE_SIZE_4K, .init =3D arm_smmu_iommu_domain_init, .hwdom_init =3D arm_smmu_iommu_hwdom_init, .add_device =3D arm_smmu_dt_add_device_generic, --- a/xen/drivers/passthrough/arm/smmu-v3.c +++ b/xen/drivers/passthrough/arm/smmu-v3.c @@ -3426,7 +3426,8 @@ static void arm_smmu_iommu_xen_domain_te } =20 static const struct iommu_ops arm_smmu_iommu_ops =3D { - .init =3D arm_smmu_iommu_xen_domain_init, + .page_sizes =3D PAGE_SIZE_4K, + .init =3D arm_smmu_iommu_xen_domain_init, .hwdom_init =3D arm_smmu_iommu_hwdom_init, .teardown =3D arm_smmu_iommu_xen_domain_teardown, .iotlb_flush =3D arm_smmu_iotlb_flush, --- a/xen/drivers/passthrough/iommu.c +++ b/xen/drivers/passthrough/iommu.c @@ -470,7 +470,17 @@ int __init iommu_setup(void) =20 if ( iommu_enable ) { + const struct iommu_ops *ops =3D NULL; + rc =3D iommu_hardware_setup(); + if ( !rc ) + ops =3D iommu_get_ops(); + if ( ops && (ops->page_sizes & -ops->page_sizes) !=3D PAGE_SIZE ) + { + printk(XENLOG_ERR "IOMMU: page size mask %lx unsupported\n", + ops->page_sizes); + rc =3D ops->page_sizes ? -EPERM : -ENODATA; + } iommu_enabled =3D (rc =3D=3D 0); } =20 --- a/xen/drivers/passthrough/vtd/iommu.c +++ b/xen/drivers/passthrough/vtd/iommu.c @@ -2806,6 +2806,7 @@ static int __init intel_iommu_quarantine } =20 static struct iommu_ops __initdata vtd_ops =3D { + .page_sizes =3D PAGE_SIZE_4K, .init =3D intel_iommu_domain_init, .hwdom_init =3D intel_iommu_hwdom_init, .quarantine_init =3D intel_iommu_quarantine_init, --- a/xen/include/xen/iommu.h +++ b/xen/include/xen/iommu.h @@ -231,6 +231,7 @@ struct page_info; typedef int iommu_grdm_t(xen_pfn_t start, xen_ulong_t nr, u32 id, void *ct= xt); =20 struct iommu_ops { + unsigned long page_sizes; int (*init)(struct domain *d); void (*hwdom_init)(struct domain *d); int (*quarantine_init)(struct domain *d); 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charset="utf-8" Or really, in the case of ->map_page(), accommodate it in the existing "flags" parameter. All call sites will pass 0 for now. Signed-off-by: Jan Beulich Reviewed-by: Kevin Tian Acked-by: Julien Grall Reviewed-by: Roger Pau Monn=C3=A9 --- v2: Re-base over change earlier in the series. --- a/xen/drivers/passthrough/amd/iommu.h +++ b/xen/drivers/passthrough/amd/iommu.h @@ -230,6 +230,7 @@ int __must_check amd_iommu_map_page(stru mfn_t mfn, unsigned int flags, unsigned int *flush_flags); int __must_check amd_iommu_unmap_page(struct domain *d, dfn_t dfn, + unsigned int order, unsigned int *flush_flags); int __must_check amd_iommu_alloc_root(struct domain *d); int amd_iommu_reserve_domain_unity_map(struct domain *domain, --- a/xen/drivers/passthrough/amd/iommu_map.c +++ b/xen/drivers/passthrough/amd/iommu_map.c @@ -328,7 +328,7 @@ int amd_iommu_map_page(struct domain *d, return 0; } =20 -int amd_iommu_unmap_page(struct domain *d, dfn_t dfn, +int amd_iommu_unmap_page(struct domain *d, dfn_t dfn, unsigned int order, unsigned int *flush_flags) { unsigned long pt_mfn =3D 0; --- a/xen/drivers/passthrough/arm/iommu_helpers.c +++ b/xen/drivers/passthrough/arm/iommu_helpers.c @@ -57,11 +57,13 @@ int __must_check arm_iommu_map_page(stru * The function guest_physmap_add_entry replaces the current mapping * if there is already one... */ - return guest_physmap_add_entry(d, _gfn(dfn_x(dfn)), _mfn(dfn_x(dfn)), = 0, t); + return guest_physmap_add_entry(d, _gfn(dfn_x(dfn)), _mfn(dfn_x(dfn)), + IOMMUF_order(flags), t); } =20 /* Should only be used if P2M Table is shared between the CPU and the IOMM= U. */ int __must_check arm_iommu_unmap_page(struct domain *d, dfn_t dfn, + unsigned int order, unsigned int *flush_flags) { /* @@ -71,7 +73,8 @@ int __must_check arm_iommu_unmap_page(st if ( !is_domain_direct_mapped(d) ) return -EINVAL; =20 - return guest_physmap_remove_page(d, _gfn(dfn_x(dfn)), _mfn(dfn_x(dfn))= , 0); + return guest_physmap_remove_page(d, _gfn(dfn_x(dfn)), _mfn(dfn_x(dfn)), + order); } =20 /* --- a/xen/drivers/passthrough/iommu.c +++ b/xen/drivers/passthrough/iommu.c @@ -271,6 +271,8 @@ int iommu_map(struct domain *d, dfn_t df if ( !is_iommu_enabled(d) ) return 0; =20 + ASSERT(!IOMMUF_order(flags)); + for ( i =3D 0; i < page_count; i++ ) { rc =3D iommu_call(hd->platform_ops, map_page, d, dfn_add(dfn, i), @@ -288,7 +290,7 @@ int iommu_map(struct domain *d, dfn_t df while ( i-- ) /* if statement to satisfy __must_check */ if ( iommu_call(hd->platform_ops, unmap_page, d, dfn_add(dfn, = i), - flush_flags) ) + 0, flush_flags) ) continue; =20 if ( !is_hardware_domain(d) ) @@ -333,7 +335,7 @@ int iommu_unmap(struct domain *d, dfn_t for ( i =3D 0; i < page_count; i++ ) { int err =3D iommu_call(hd->platform_ops, unmap_page, d, dfn_add(df= n, i), - flush_flags); + 0, flush_flags); =20 if ( likely(!err) ) continue; --- a/xen/drivers/passthrough/vtd/iommu.c +++ b/xen/drivers/passthrough/vtd/iommu.c @@ -1934,6 +1934,7 @@ static int __must_check intel_iommu_map_ } =20 static int __must_check intel_iommu_unmap_page(struct domain *d, dfn_t dfn, + unsigned int order, unsigned int *flush_flags) { /* Do nothing if VT-d shares EPT page table */ @@ -1944,7 +1945,7 @@ static int __must_check intel_iommu_unma if ( iommu_hwdom_passthrough && is_hardware_domain(d) ) return 0; =20 - return dma_pte_clear_one(d, dfn_to_daddr(dfn), 0, flush_flags); + return dma_pte_clear_one(d, dfn_to_daddr(dfn), order, flush_flags); } =20 static int intel_iommu_lookup_page(struct domain *d, dfn_t dfn, mfn_t *mfn, --- a/xen/include/asm-arm/iommu.h +++ b/xen/include/asm-arm/iommu.h @@ -31,6 +31,7 @@ int __must_check arm_iommu_map_page(stru unsigned int flags, unsigned int *flush_flags); int __must_check arm_iommu_unmap_page(struct domain *d, dfn_t dfn, + unsigned int order, unsigned int *flush_flags); =20 #endif /* __ARCH_ARM_IOMMU_H__ */ --- a/xen/include/xen/iommu.h +++ b/xen/include/xen/iommu.h @@ -127,9 +127,10 @@ void arch_iommu_hwdom_init(struct domain * The following flags are passed to map operations and passed by lookup * operations. */ -#define _IOMMUF_readable 0 +#define IOMMUF_order(n) ((n) & 0x3f) +#define _IOMMUF_readable 6 #define IOMMUF_readable (1u<<_IOMMUF_readable) -#define _IOMMUF_writable 1 +#define _IOMMUF_writable 7 #define IOMMUF_writable (1u<<_IOMMUF_writable) =20 /* @@ -255,6 +256,7 @@ struct iommu_ops { unsigned int flags, unsigned int *flush_flags); int __must_check (*unmap_page)(struct domain *d, dfn_t dfn, + unsigned int order, unsigned int *flush_flags); int __must_check (*lookup_page)(struct domain *d, dfn_t dfn, mfn_t *mf= n, unsigned int *flags); From nobody Fri Nov 29 16:38:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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spf=pass smtp.mailfrom=suse.com; dmarc=pass action=none header.from=suse.com; dkim=pass header.d=suse.com; arc=none Authentication-Results: xen.org; dkim=none (message not signed) header.d=none;xen.org; dmarc=none action=none header.from=suse.com; Subject: [PATCH v2 05/18] IOMMU: have iommu_{,un}map() split requests into largest possible chunks From: Jan Beulich To: "xen-devel@lists.xenproject.org" Cc: Andrew Cooper , Paul Durrant References: <957f067b-9fe1-2350-4266-51982f09d3a9@suse.com> Message-ID: <134785fb-8ac1-50f0-de75-e0d6fe22f711@suse.com> Date: Fri, 24 Sep 2021 11:45:57 +0200 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.14.0 In-Reply-To: <957f067b-9fe1-2350-4266-51982f09d3a9@suse.com> Content-Language: en-US Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: PR2P264CA0028.FRAP264.PROD.OUTLOOK.COM (2603:10a6:101:1::16) To VI1PR04MB5600.eurprd04.prod.outlook.com (2603:10a6:803:e7::16) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 6bee5668-25ff-40b2-1e4e-08d97f401c46 X-MS-TrafficTypeDiagnostic: VI1PR04MB4383: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:1468; 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charset="utf-8" Introduce a helper function to determine the largest possible mapping that allows covering a request (or the next part of it that is left to be processed). In order to not add yet more recurring dfn_add() / mfn_add() to the two callers of the new helper, also introduce local variables holding the values presently operated on. Signed-off-by: Jan Beulich --- a/xen/drivers/passthrough/iommu.c +++ b/xen/drivers/passthrough/iommu.c @@ -260,12 +260,38 @@ void iommu_domain_destroy(struct domain arch_iommu_domain_destroy(d); } =20 -int iommu_map(struct domain *d, dfn_t dfn, mfn_t mfn, +static unsigned int mapping_order(const struct domain_iommu *hd, + dfn_t dfn, mfn_t mfn, unsigned long nr) +{ + unsigned long res =3D dfn_x(dfn) | mfn_x(mfn); + unsigned long sizes =3D hd->platform_ops->page_sizes; + unsigned int bit =3D find_first_set_bit(sizes), order =3D 0; + + ASSERT(bit =3D=3D PAGE_SHIFT); + + while ( (sizes =3D (sizes >> bit) & ~1) ) + { + unsigned long mask; + + bit =3D find_first_set_bit(sizes); + mask =3D (1UL << bit) - 1; + if ( nr <=3D mask || (res & mask) ) + break; + order +=3D bit; + nr >>=3D bit; + res >>=3D bit; + } + + return order; +} + +int iommu_map(struct domain *d, dfn_t dfn0, mfn_t mfn0, unsigned long page_count, unsigned int flags, unsigned int *flush_flags) { const struct domain_iommu *hd =3D dom_iommu(d); unsigned long i; + unsigned int order; int rc =3D 0; =20 if ( !is_iommu_enabled(d) ) @@ -273,10 +299,16 @@ int iommu_map(struct domain *d, dfn_t df =20 ASSERT(!IOMMUF_order(flags)); =20 - for ( i =3D 0; i < page_count; i++ ) + for ( i =3D 0; i < page_count; i +=3D 1UL << order ) { - rc =3D iommu_call(hd->platform_ops, map_page, d, dfn_add(dfn, i), - mfn_add(mfn, i), flags, flush_flags); + dfn_t dfn =3D dfn_add(dfn0, i); + mfn_t mfn =3D mfn_add(mfn0, i); + unsigned long j; + + order =3D mapping_order(hd, dfn, mfn, page_count - i); + + rc =3D iommu_call(hd->platform_ops, map_page, d, dfn, mfn, + flags | IOMMUF_order(order), flush_flags); =20 if ( likely(!rc) ) continue; @@ -284,14 +316,18 @@ int iommu_map(struct domain *d, dfn_t df if ( !d->is_shutting_down && printk_ratelimit() ) printk(XENLOG_ERR "d%d: IOMMU mapping dfn %"PRI_dfn" to mfn %"PRI_mfn" fa= iled: %d\n", - d->domain_id, dfn_x(dfn_add(dfn, i)), - mfn_x(mfn_add(mfn, i)), rc); + d->domain_id, dfn_x(dfn), mfn_x(mfn), rc); + + for ( j =3D 0; j < i; j +=3D 1UL << order ) + { + dfn =3D dfn_add(dfn0, j); + order =3D mapping_order(hd, dfn, _mfn(0), i - j); =20 - while ( i-- ) /* if statement to satisfy __must_check */ - if ( iommu_call(hd->platform_ops, unmap_page, d, dfn_add(dfn, = i), - 0, flush_flags) ) + if ( iommu_call(hd->platform_ops, unmap_page, d, dfn, order, + flush_flags) ) continue; + } =20 if ( !is_hardware_domain(d) ) domain_crash(d); @@ -322,20 +358,25 @@ int iommu_legacy_map(struct domain *d, d return rc; } =20 -int iommu_unmap(struct domain *d, dfn_t dfn, unsigned long page_count, +int iommu_unmap(struct domain *d, dfn_t dfn0, unsigned long page_count, unsigned int *flush_flags) { const struct domain_iommu *hd =3D dom_iommu(d); unsigned long i; + unsigned int order; int rc =3D 0; =20 if ( !is_iommu_enabled(d) ) return 0; =20 - for ( i =3D 0; i < page_count; i++ ) + for ( i =3D 0; i < page_count; i +=3D 1UL << order ) { - int err =3D iommu_call(hd->platform_ops, unmap_page, d, dfn_add(df= n, i), - 0, flush_flags); + dfn_t dfn =3D dfn_add(dfn0, i); + int err; + + order =3D mapping_order(hd, dfn, _mfn(0), page_count - i); + err =3D iommu_call(hd->platform_ops, unmap_page, d, dfn, + order, flush_flags); =20 if ( likely(!err) ) continue; @@ -343,7 +384,7 @@ int iommu_unmap(struct domain *d, dfn_t if ( !d->is_shutting_down && printk_ratelimit() ) printk(XENLOG_ERR "d%d: IOMMU unmapping dfn %"PRI_dfn" failed: %d\n", - d->domain_id, dfn_x(dfn_add(dfn, i)), err); + d->domain_id, dfn_x(dfn), err); =20 if ( !rc ) rc =3D err; From nobody Fri Nov 29 16:38:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; 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charset="utf-8" While already the case for PVH, there's no reason to treat PV differently here, though of course the addresses get taken from another source in this case. Except that, to match CPU side mappings, by default we permit r/o ones. This then also means we now deal consistently with IO-APICs whose MMIO is or is not covered by E820 reserved regions. Signed-off-by: Jan Beulich --- [integrated] v1: Integrate into series. [standalone] v2: Keep IOMMU mappings in sync with CPU ones. --- a/xen/drivers/passthrough/x86/iommu.c +++ b/xen/drivers/passthrough/x86/iommu.c @@ -253,12 +253,12 @@ void iommu_identity_map_teardown(struct } } =20 -static bool __hwdom_init hwdom_iommu_map(const struct domain *d, - unsigned long pfn, - unsigned long max_pfn) +static unsigned int __hwdom_init hwdom_iommu_map(const struct domain *d, + unsigned long pfn, + unsigned long max_pfn) { mfn_t mfn =3D _mfn(pfn); - unsigned int i, type; + unsigned int i, type, perms =3D IOMMUF_readable | IOMMUF_writable; =20 /* * Set up 1:1 mapping for dom0. Default to include only conventional R= AM @@ -267,44 +267,60 @@ static bool __hwdom_init hwdom_iommu_map * that fall in unusable ranges for PV Dom0. */ if ( (pfn > max_pfn && !mfn_valid(mfn)) || xen_in_range(pfn) ) - return false; + return 0; =20 switch ( type =3D page_get_ram_type(mfn) ) { case RAM_TYPE_UNUSABLE: - return false; + return 0; =20 case RAM_TYPE_CONVENTIONAL: if ( iommu_hwdom_strict ) - return false; + return 0; break; =20 default: if ( type & RAM_TYPE_RESERVED ) { if ( !iommu_hwdom_inclusive && !iommu_hwdom_reserved ) - return false; + perms =3D 0; } - else if ( is_hvm_domain(d) || !iommu_hwdom_inclusive || pfn > max_= pfn ) - return false; + else if ( is_hvm_domain(d) ) + return 0; + else if ( !iommu_hwdom_inclusive || pfn > max_pfn ) + perms =3D 0; } =20 /* Check that it doesn't overlap with the Interrupt Address Range. */ if ( pfn >=3D 0xfee00 && pfn <=3D 0xfeeff ) - return false; + return 0; /* ... or the IO-APIC */ - for ( i =3D 0; has_vioapic(d) && i < d->arch.hvm.nr_vioapics; i++ ) - if ( pfn =3D=3D PFN_DOWN(domain_vioapic(d, i)->base_address) ) - return false; + if ( has_vioapic(d) ) + { + for ( i =3D 0; i < d->arch.hvm.nr_vioapics; i++ ) + if ( pfn =3D=3D PFN_DOWN(domain_vioapic(d, i)->base_address) ) + return 0; + } + else if ( is_pv_domain(d) ) + { + /* + * Be consistent with CPU mappings: Dom0 is permitted to establish= r/o + * ones there, so it should also have such established for IOMMUs. + */ + for ( i =3D 0; i < nr_ioapics; i++ ) + if ( pfn =3D=3D PFN_DOWN(mp_ioapics[i].mpc_apicaddr) ) + return rangeset_contains_singleton(mmio_ro_ranges, pfn) + ? IOMMUF_readable : 0; + } /* * ... or the PCIe MCFG regions. * TODO: runtime added MMCFG regions are not checked to make sure they * don't overlap with already mapped regions, thus preventing trapping. */ if ( has_vpci(d) && vpci_is_mmcfg_address(d, pfn_to_paddr(pfn)) ) - return false; + return 0; =20 - return true; + return perms; } =20 void __hwdom_init arch_iommu_hwdom_init(struct domain *d) @@ -346,15 +362,19 @@ void __hwdom_init arch_iommu_hwdom_init( for ( ; i < top; i++ ) { unsigned long pfn =3D pdx_to_pfn(i); + unsigned int perms =3D hwdom_iommu_map(d, pfn, max_pfn); int rc; =20 - if ( !hwdom_iommu_map(d, pfn, max_pfn) ) + if ( !perms ) rc =3D 0; else if ( paging_mode_translate(d) ) - rc =3D set_identity_p2m_entry(d, pfn, p2m_access_rw, 0); + rc =3D set_identity_p2m_entry(d, pfn, + perms & IOMMUF_writable ? p2m_acce= ss_rw + : p2m_acce= ss_r, + 0); else rc =3D iommu_map(d, _dfn(pfn), _mfn(pfn), 1ul << PAGE_ORDER_4K, - IOMMUF_readable | IOMMUF_writable, &flush_flags= ); + perms, &flush_flags); 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charset="utf-8" For large page mappings to be easily usable (i.e. in particular without un-shattering of smaller page mappings) and for mapping operations to then also be more efficient, pass batches of Dom0 memory to iommu_map(). In dom0_construct_pv() and its helpers (covering strict mode) this additionally requires establishing the type of those pages (albeit with zero type references). The earlier establishing of PGT_writable_page | PGT_validated requires the existing places where this gets done (through get_page_and_type()) to be updated: For pages which actually have a mapping, the type refcount needs to be 1. There is actually a related bug that gets fixed here as a side effect: Typically the last L1 table would get marked as such only after get_page_and_type(..., PGT_writable_page). While this is fine as far as refcounting goes, the page did remain mapped in the IOMMU in this case (when "iommu=3Ddom0-strict"). Signed-off-by: Jan Beulich --- Subsequently p2m_add_identity_entry() may want to also gain an order parameter, for arch_iommu_hwdom_init() to use. While this only affects non-RAM regions, systems typically have 2-16Mb of reserved space immediately below 4Gb, which hence could be mapped more efficiently. The installing of zero-ref writable types has in fact shown (observed while putting together the change) that despite the intention by the XSA-288 changes (affecting DomU-s only) for Dom0 a number of sufficiently ordinary pages (at the very least initrd and P2M ones as well as pages that are part of the initial allocation but not part of the initial mapping) still have been starting out as PGT_none, meaning that they would have gained IOMMU mappings only the first time these pages would get mapped writably. I didn't think I need to address the bug mentioned in the description in a separate (prereq) patch, but if others disagree I could certainly break out that part (needing to first use iommu_legacy_unmap() then). Note that 4k P2M pages don't get (pre-)mapped in setup_pv_physmap(): They'll end up mapped via the later get_page_and_type(). As to the way these refs get installed: I've chosen to avoid the more expensive {get,put}_page_and_type(), putting in place the intended type directly. I guess I could be convinced to avoid this bypassing of the actual logic; I merely think it's unnecessarily expensive. --- a/xen/arch/x86/pv/dom0_build.c +++ b/xen/arch/x86/pv/dom0_build.c @@ -106,11 +106,26 @@ static __init void mark_pv_pt_pages_rdon unmap_domain_page(pl3e); } =20 +/* + * For IOMMU mappings done while building Dom0 the type of the pages needs= to + * match (for _get_page_type() to unmap upon type change). Set the pages to + * writable with no type ref. NB: This is benign when !need_iommu_pt_sync(= d). + */ +static void __init make_pages_writable(struct page_info *page, unsigned lo= ng nr) +{ + for ( ; nr--; ++page ) + { + ASSERT(!page->u.inuse.type_info); + page->u.inuse.type_info =3D PGT_writable_page | PGT_validated; + } +} + static __init void setup_pv_physmap(struct domain *d, unsigned long pgtbl_= pfn, unsigned long v_start, unsigned long v= _end, unsigned long vphysmap_start, unsigned long vphysmap_end, - unsigned long nr_pages) + unsigned long nr_pages, + unsigned int *flush_flags) { struct page_info *page =3D NULL; l4_pgentry_t *pl4e, *l4start =3D map_domain_page(_mfn(pgtbl_pfn)); @@ -123,6 +138,8 @@ static __init void setup_pv_physmap(stru =20 while ( vphysmap_start < vphysmap_end ) { + int rc =3D 0; + if ( domain_tot_pages(d) + ((round_pgup(vphysmap_end) - vphysmap_start) >> PAGE_SHIFT) + 3 > nr_pages ) @@ -176,7 +193,22 @@ static __init void setup_pv_physmap(stru L3_PAGETABLE_SHIFT - PAGE_SHI= FT, MEMF_no_scrub)) !=3D NULL ) { - *pl3e =3D l3e_from_page(page, L1_PROT|_PAGE_DIRTY|_PAGE_PS= E); + mfn_t mfn =3D page_to_mfn(page); + + if ( need_iommu_pt_sync(d) ) + rc =3D iommu_map(d, _dfn(mfn_x(mfn)), mfn, + SUPERPAGE_PAGES * SUPERPAGE_PAGES, + IOMMUF_readable | IOMMUF_writable, + flush_flags); + if ( !rc ) + make_pages_writable(page, + SUPERPAGE_PAGES * SUPERPAGE_PAGES); + else + printk(XENLOG_ERR + "pre-mapping P2M 1G-MFN %lx into IOMMU failed: = %d\n", + mfn_x(mfn), rc); + + *pl3e =3D l3e_from_mfn(mfn, L1_PROT|_PAGE_DIRTY|_PAGE_PSE); vphysmap_start +=3D 1UL << L3_PAGETABLE_SHIFT; continue; } @@ -202,7 +234,20 @@ static __init void setup_pv_physmap(stru L2_PAGETABLE_SHIFT - PAGE_SHI= FT, MEMF_no_scrub)) !=3D NULL ) { - *pl2e =3D l2e_from_page(page, L1_PROT|_PAGE_DIRTY|_PAGE_PS= E); + mfn_t mfn =3D page_to_mfn(page); + + if ( need_iommu_pt_sync(d) ) + rc =3D iommu_map(d, _dfn(mfn_x(mfn)), mfn, SUPERPAGE_P= AGES, + IOMMUF_readable | IOMMUF_writable, + flush_flags); + if ( !rc ) + make_pages_writable(page, SUPERPAGE_PAGES); + else + printk(XENLOG_ERR + "pre-mapping P2M 2M-MFN %lx into IOMMU failed: = %d\n", + mfn_x(mfn), rc); + + *pl2e =3D l2e_from_mfn(mfn, L1_PROT|_PAGE_DIRTY|_PAGE_PSE); vphysmap_start +=3D 1UL << L2_PAGETABLE_SHIFT; continue; } @@ -310,6 +355,7 @@ int __init dom0_construct_pv(struct doma unsigned long initrd_pfn =3D -1, initrd_mfn =3D 0; unsigned long count; struct page_info *page =3D NULL; + unsigned int flush_flags =3D 0; start_info_t *si; struct vcpu *v =3D d->vcpu[0]; void *image_base =3D bootstrap_map(image); @@ -572,6 +618,18 @@ int __init dom0_construct_pv(struct doma BUG(); } initrd->mod_end =3D 0; + + count =3D PFN_UP(initrd_len); + + if ( need_iommu_pt_sync(d) ) + rc =3D iommu_map(d, _dfn(initrd_mfn), _mfn(initrd_mfn), count, + IOMMUF_readable | IOMMUF_writable, &flush_flags= ); + if ( !rc ) + make_pages_writable(mfn_to_page(_mfn(initrd_mfn)), count); + else + printk(XENLOG_ERR + "pre-mapping initrd (MFN %lx) into IOMMU failed: %d\n", + initrd_mfn, rc); } =20 printk("PHYSICAL MEMORY ARRANGEMENT:\n" @@ -605,6 +663,22 @@ int __init dom0_construct_pv(struct doma =20 process_pending_softirqs(); =20 + /* + * We map the full range here and then punch a hole for page tables via + * iommu_unmap() further down, once they have got marked as such. + */ + if ( need_iommu_pt_sync(d) ) + rc =3D iommu_map(d, _dfn(alloc_spfn), _mfn(alloc_spfn), + alloc_epfn - alloc_spfn, + IOMMUF_readable | IOMMUF_writable, &flush_flags); + if ( !rc ) + make_pages_writable(mfn_to_page(_mfn(alloc_spfn)), + alloc_epfn - alloc_spfn); + else + printk(XENLOG_ERR + "pre-mapping MFNs [%lx,%lx) into IOMMU failed: %d\n", + alloc_spfn, alloc_epfn, rc); + mpt_alloc =3D (vpt_start - v_start) + pfn_to_paddr(alloc_spfn); if ( vinitrd_start ) mpt_alloc -=3D PAGE_ALIGN(initrd_len); @@ -689,7 +763,8 @@ int __init dom0_construct_pv(struct doma l1tab++; =20 page =3D mfn_to_page(_mfn(mfn)); - if ( !page->u.inuse.type_info && + if ( (!page->u.inuse.type_info || + page->u.inuse.type_info =3D=3D (PGT_writable_page | PGT_vali= dated)) && !get_page_and_type(page, d, PGT_writable_page) ) BUG(); } @@ -720,6 +795,17 @@ int __init dom0_construct_pv(struct doma /* Pages that are part of page tables must be read only. */ mark_pv_pt_pages_rdonly(d, l4start, vpt_start, nr_pt_pages); =20 + /* + * This needs to come after all potentially excess + * get_page_and_type(..., PGT_writable_page) invocations; see the loop= a + * few lines further up, where the effect of calling that function in = an + * earlier loop iteration may get overwritten by a later one. + */ + if ( need_iommu_pt_sync(d) && + iommu_unmap(d, _dfn(PFN_DOWN(mpt_alloc) - nr_pt_pages), nr_pt_pag= es, + &flush_flags) ) + BUG(); + /* Mask all upcalls... */ for ( i =3D 0; i < XEN_LEGACY_MAX_VCPUS; i++ ) shared_info(d, vcpu_info[i].evtchn_upcall_mask) =3D 1; @@ -793,7 +879,7 @@ int __init dom0_construct_pv(struct doma { pfn =3D pagetable_get_pfn(v->arch.guest_table); setup_pv_physmap(d, pfn, v_start, v_end, vphysmap_start, vphysmap_= end, - nr_pages); + nr_pages, &flush_flags); } =20 /* Write the phys->machine and machine->phys table entries. */ @@ -824,7 +910,9 @@ int __init dom0_construct_pv(struct doma if ( get_gpfn_from_mfn(mfn) >=3D count ) { BUG_ON(compat); - if ( !page->u.inuse.type_info && + if ( (!page->u.inuse.type_info || + page->u.inuse.type_info =3D=3D (PGT_writable_page | + PGT_validated)) && !get_page_and_type(page, d, PGT_writable_page) ) BUG(); =20 @@ -840,22 +928,41 @@ int __init dom0_construct_pv(struct doma #endif while ( pfn < nr_pages ) { - if ( (page =3D alloc_chunk(d, nr_pages - domain_tot_pages(d))) =3D= =3D NULL ) + count =3D domain_tot_pages(d); + if ( (page =3D alloc_chunk(d, nr_pages - count)) =3D=3D NULL ) panic("Not enough RAM for DOM0 reservation\n"); + mfn =3D mfn_x(page_to_mfn(page)); + + if ( need_iommu_pt_sync(d) ) + { + rc =3D iommu_map(d, _dfn(mfn), _mfn(mfn), domain_tot_pages(d) = - count, + IOMMUF_readable | IOMMUF_writable, &flush_flags= ); + if ( rc ) + printk(XENLOG_ERR + "pre-mapping MFN %lx (PFN %lx) into IOMMU failed: %= d\n", + mfn, pfn, rc); + } + while ( pfn < domain_tot_pages(d) ) { - mfn =3D mfn_x(page_to_mfn(page)); + if ( !rc ) + make_pages_writable(page, 1); + #ifndef NDEBUG #define pfn (nr_pages - 1 - (pfn - (alloc_epfn - alloc_spfn))) #endif dom0_update_physmap(compat, pfn, mfn, vphysmap_start); #undef pfn - page++; pfn++; + page++; mfn++; pfn++; if ( !(pfn & 0xfffff) ) process_pending_softirqs(); } } =20 + /* Use while() to avoid compiler warning. */ + while ( iommu_iotlb_flush_all(d, flush_flags) ) + break; + if ( initrd_len !=3D 0 ) { si->mod_start =3D vinitrd_start ?: initrd_pfn; --- a/xen/drivers/passthrough/x86/iommu.c +++ b/xen/drivers/passthrough/x86/iommu.c @@ -325,8 +325,8 @@ static unsigned int __hwdom_init hwdom_i =20 void __hwdom_init arch_iommu_hwdom_init(struct domain *d) { - unsigned long i, top, max_pfn; - unsigned int flush_flags =3D 0; + unsigned long i, top, max_pfn, start, count; + unsigned int flush_flags =3D 0, start_perms =3D 0; =20 BUG_ON(!is_hardware_domain(d)); =20 @@ -357,9 +357,9 @@ void __hwdom_init arch_iommu_hwdom_init( * First Mb will get mapped in one go by pvh_populate_p2m(). Avoid * setting up potentially conflicting mappings here. */ - i =3D paging_mode_translate(d) ? PFN_DOWN(MB(1)) : 0; + start =3D paging_mode_translate(d) ? PFN_DOWN(MB(1)) : 0; =20 - for ( ; i < top; i++ ) + for ( i =3D start, count =3D 0; i < top; ) { unsigned long pfn =3D pdx_to_pfn(i); unsigned int perms =3D hwdom_iommu_map(d, pfn, max_pfn); @@ -372,16 +372,30 @@ void __hwdom_init arch_iommu_hwdom_init( perms & IOMMUF_writable ? p2m_acce= ss_rw : p2m_acce= ss_r, 0); + else if ( pfn !=3D start + count || perms !=3D start_perms ) + { + commit: + rc =3D iommu_map(d, _dfn(start), _mfn(start), count, + start_perms, &flush_flags); + SWAP(start, pfn); + start_perms =3D perms; + count =3D 1; + } else - rc =3D iommu_map(d, _dfn(pfn), _mfn(pfn), 1ul << PAGE_ORDER_4K, - perms, &flush_flags); + { + ++count; + rc =3D 0; + } =20 if ( rc ) printk(XENLOG_WARNING "%pd: identity %smapping of %lx failed: = %d\n", d, !paging_mode_translate(d) ? "IOMMU " : "", pfn, rc); =20 - if (!(i & 0xfffff)) + if ( !(++i & 0xfffff) ) process_pending_softirqs(); + + if ( i =3D=3D top && count ) + goto commit; } =20 /* Use if to avoid compiler warning */ From nobody Fri Nov 29 16:38:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; arc=pass (i=1 dmarc=pass fromdomain=suse.com); dmarc=pass(p=quarantine dis=none) header.from=suse.com ARC-Seal: i=2; a=rsa-sha256; t=1632476924; cv=pass; d=zohomail.com; s=zohoarc; b=iGEYKzAlvPLDs6lp581TCnd5sI+acPL/sUsCsytLn4LNvgMN/+ur7ZEIOy1Krup8FK/z5IhwZhZceWx1CbWUIwf824RuUihKsExSPwNvrceGMN/XXRGrIOfkSLXSl5ORqFdq5HgA5XWezozR0CDJnAU92Bxzscjuh3G6r9x7g6I= ARC-Message-Signature: i=2; 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charset="utf-8" For vendor specific code to support superpages we need to be able to deal with a superpage mapping replacing an intermediate page table (or hierarchy thereof). Consequently an iommu_alloc_pgtable() counterpart is needed to free individual page tables while a domain is still alive. Since the freeing needs to be deferred until after a suitable IOTLB flush was performed, released page tables get queued for processing by a tasklet. Signed-off-by: Jan Beulich --- I was considering whether to use a softirq-taklet instead. This would have the benefit of avoiding extra scheduling operations, but come with the risk of the freeing happening prematurely because of a process_pending_softirqs() somewhere. --- a/xen/drivers/passthrough/x86/iommu.c +++ b/xen/drivers/passthrough/x86/iommu.c @@ -12,6 +12,7 @@ * this program; If not, see . */ =20 +#include #include #include #include @@ -463,6 +464,85 @@ struct page_info *iommu_alloc_pgtable(st return pg; } =20 +/* + * Intermediate page tables which get replaced by large pages may only be + * freed after a suitable IOTLB flush. Hence such pages get queued on a + * per-CPU list, with a per-CPU tasklet processing the list on the assumpt= ion + * that the necessary IOTLB flush will have occurred by the time tasklets = get + * to run. (List and tasklet being per-CPU has the benefit of accesses not + * requiring any locking.) + */ +static DEFINE_PER_CPU(struct page_list_head, free_pgt_list); +static DEFINE_PER_CPU(struct tasklet, free_pgt_tasklet); + +static void free_queued_pgtables(void *arg) +{ + struct page_list_head *list =3D arg; + struct page_info *pg; + + while ( (pg =3D page_list_remove_head(list)) ) + free_domheap_page(pg); +} + +void iommu_queue_free_pgtable(struct domain *d, struct page_info *pg) +{ + struct domain_iommu *hd =3D dom_iommu(d); + unsigned int cpu =3D smp_processor_id(); + + spin_lock(&hd->arch.pgtables.lock); + page_list_del(pg, &hd->arch.pgtables.list); + spin_unlock(&hd->arch.pgtables.lock); + + page_list_add_tail(pg, &per_cpu(free_pgt_list, cpu)); + + tasklet_schedule(&per_cpu(free_pgt_tasklet, cpu)); +} + +static int cpu_callback( + struct notifier_block *nfb, unsigned long action, void *hcpu) +{ + unsigned int cpu =3D (unsigned long)hcpu; + struct page_list_head *list =3D &per_cpu(free_pgt_list, cpu); + struct tasklet *tasklet =3D &per_cpu(free_pgt_tasklet, cpu); + + switch ( action ) + { + case CPU_DOWN_PREPARE: + tasklet_kill(tasklet); + break; + + case CPU_DEAD: + page_list_splice(list, &this_cpu(free_pgt_list)); + INIT_PAGE_LIST_HEAD(list); + tasklet_schedule(&this_cpu(free_pgt_tasklet)); + break; + + case CPU_UP_PREPARE: + case CPU_DOWN_FAILED: + tasklet_init(tasklet, free_queued_pgtables, list); + break; + } + + return NOTIFY_DONE; +} + +static struct notifier_block cpu_nfb =3D { + .notifier_call =3D cpu_callback, +}; + +static int __init bsp_init(void) +{ + if ( iommu_enabled ) + { + cpu_callback(&cpu_nfb, CPU_UP_PREPARE, + (void *)(unsigned long)smp_processor_id()); + register_cpu_notifier(&cpu_nfb); + } + + return 0; +} +presmp_initcall(bsp_init); + bool arch_iommu_use_permitted(const struct domain *d) { /* --- a/xen/include/asm-x86/iommu.h +++ b/xen/include/asm-x86/iommu.h @@ -143,6 +143,7 @@ int pi_update_irte(const struct pi_desc =20 int __must_check iommu_free_pgtables(struct domain *d); struct page_info *__must_check iommu_alloc_pgtable(struct domain *d); +void iommu_queue_free_pgtable(struct domain *d, struct page_info *pg); =20 #endif /* !__ARCH_X86_IOMMU_H__ */ /* From nobody Fri Nov 29 16:38:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; arc=pass (i=1 dmarc=pass fromdomain=suse.com); dmarc=pass(p=quarantine dis=none) header.from=suse.com ARC-Seal: i=2; a=rsa-sha256; t=1632476959; cv=pass; d=zohomail.com; s=zohoarc; b=g5sm2A6a7U29pC75zEiGsCrgrM7Ez+5m9XjR/kq+0Ez80MxA5+E5WqhGOjJqutgAduICh/M6wyOZ3BAUbhDDYjgkhn+L+CYxw8l39lI/P0XtoQiw+HwV5R5QSj4NWK7H+oV8qP3+IZOHuRSYtA7U9zBxbf+lNsmkPS+m6RL6uNI= ARC-Message-Signature: i=2; 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charset="utf-8" I think this flush was overlooked when flushing was moved out of the core (un)mapping functions. The flush the caller is required to invoke anyway will satisfy the needs resulting from the splitting of a superpage. Signed-off-by: Jan Beulich Reviewed-by: Roger Pau Monn=C3=A9 --- a/xen/drivers/passthrough/amd/iommu_map.c +++ b/xen/drivers/passthrough/amd/iommu_map.c @@ -179,7 +179,7 @@ void __init iommu_dte_add_device_entry(s */ static int iommu_pde_from_dfn(struct domain *d, unsigned long dfn, unsigned int target, unsigned long *pt_mfn, - bool map) + unsigned int *flush_flags, bool map) { union amd_iommu_pte *pde, *next_table_vaddr; unsigned long next_table_mfn; @@ -237,7 +237,7 @@ static int iommu_pde_from_dfn(struct dom set_iommu_pde_present(pde, next_table_mfn, next_level, true, true); =20 - amd_iommu_flush_all_pages(d); + *flush_flags |=3D IOMMU_FLUSHF_modified; } =20 /* Install lower level page table for non-present entries */ @@ -309,7 +309,8 @@ int amd_iommu_map_page(struct domain *d, return rc; } =20 - if ( iommu_pde_from_dfn(d, dfn_x(dfn), 1, &pt_mfn, true) || !pt_mfn ) + if ( iommu_pde_from_dfn(d, dfn_x(dfn), 1, &pt_mfn, flush_flags, true) = || + !pt_mfn ) { spin_unlock(&hd->arch.mapping_lock); AMD_IOMMU_DEBUG("Invalid IO pagetable entry dfn =3D %"PRI_dfn"\n", @@ -342,7 +343,7 @@ int amd_iommu_unmap_page(struct domain * return 0; } =20 - if ( iommu_pde_from_dfn(d, dfn_x(dfn), 1, &pt_mfn, false) ) + if ( iommu_pde_from_dfn(d, dfn_x(dfn), 1, &pt_mfn, flush_flags, false)= ) { spin_unlock(&hd->arch.mapping_lock); AMD_IOMMU_DEBUG("Invalid IO pagetable entry dfn =3D %"PRI_dfn"\n", From nobody Fri Nov 29 16:38:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; arc=pass (i=1 dmarc=pass fromdomain=suse.com); dmarc=pass(p=quarantine dis=none) header.from=suse.com ARC-Seal: i=2; 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spf=pass smtp.mailfrom=suse.com; dmarc=pass action=none header.from=suse.com; dkim=pass header.d=suse.com; arc=none Authentication-Results: xen.org; dkim=none (message not signed) header.d=none;xen.org; dmarc=none action=none header.from=suse.com; Subject: [PATCH v2 10/18] AMD/IOMMU: walk trees upon page fault From: Jan Beulich To: "xen-devel@lists.xenproject.org" Cc: Andrew Cooper , Paul Durrant References: <957f067b-9fe1-2350-4266-51982f09d3a9@suse.com> Message-ID: <5d4a4cd8-ffb0-951a-c86d-98f659ab8d0b@suse.com> Date: Fri, 24 Sep 2021 11:51:15 +0200 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.14.0 In-Reply-To: <957f067b-9fe1-2350-4266-51982f09d3a9@suse.com> Content-Language: en-US Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: FR0P281CA0076.DEUP281.PROD.OUTLOOK.COM (2603:10a6:d10:1e::6) To VI1PR04MB5600.eurprd04.prod.outlook.com (2603:10a6:803:e7::16) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: d8386776-8669-4586-927a-08d97f40da44 X-MS-TrafficTypeDiagnostic: VI1PR0401MB2446: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:989; 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charset="utf-8" This is to aid diagnosing issues and largely matches VT-d's behavior. Since I'm adding permissions output here as well, take the opportunity and also add their displaying to amd_dump_page_table_level(). Signed-off-by: Jan Beulich --- a/xen/drivers/passthrough/amd/iommu.h +++ b/xen/drivers/passthrough/amd/iommu.h @@ -243,6 +243,8 @@ int __must_check amd_iommu_flush_iotlb_p unsigned long page_count, unsigned int flush_flags); int __must_check amd_iommu_flush_iotlb_all(struct domain *d); +void amd_iommu_print_entries(const struct amd_iommu *iommu, unsigned int d= ev_id, + dfn_t dfn); =20 /* device table functions */ int get_dma_requestor_id(uint16_t seg, uint16_t bdf); --- a/xen/drivers/passthrough/amd/iommu_init.c +++ b/xen/drivers/passthrough/amd/iommu_init.c @@ -573,6 +573,9 @@ static void parse_event_log_entry(struct (flags & 0x002) ? " NX" : "", (flags & 0x001) ? " GN" : ""); =20 + if ( iommu_verbose ) + amd_iommu_print_entries(iommu, device_id, daddr_to_dfn(addr)); + for ( bdf =3D 0; bdf < ivrs_bdf_entries; bdf++ ) if ( get_dma_requestor_id(iommu->seg, bdf) =3D=3D device_id ) pci_check_disable_device(iommu->seg, PCI_BUS(bdf), --- a/xen/drivers/passthrough/amd/iommu_map.c +++ b/xen/drivers/passthrough/amd/iommu_map.c @@ -363,6 +363,50 @@ int amd_iommu_unmap_page(struct domain * return 0; } =20 +void amd_iommu_print_entries(const struct amd_iommu *iommu, unsigned int d= ev_id, + dfn_t dfn) +{ + mfn_t pt_mfn; + unsigned int level; + const struct amd_iommu_dte *dt =3D iommu->dev_table.buffer; + + if ( !dt[dev_id].tv ) + { + printk("%pp: no root\n", &PCI_SBDF2(iommu->seg, dev_id)); + return; + } + + pt_mfn =3D _mfn(dt[dev_id].pt_root); + level =3D dt[dev_id].paging_mode; + printk("%pp root @ %"PRI_mfn" (%u levels) dfn=3D%"PRI_dfn"\n", + &PCI_SBDF2(iommu->seg, dev_id), mfn_x(pt_mfn), level, dfn_x(dfn= )); + + while ( level ) + { + const union amd_iommu_pte *pt =3D map_domain_page(pt_mfn); + unsigned int idx =3D pfn_to_pde_idx(dfn_x(dfn), level); + union amd_iommu_pte pte =3D pt[idx]; + + unmap_domain_page(pt); + + printk(" L%u[%03x] =3D %"PRIx64" %c%c\n", level, idx, pte.raw, + pte.pr ? pte.ir ? 'r' : '-' : 'n', + pte.pr ? pte.iw ? 'w' : '-' : 'p'); + + if ( !pte.pr ) + break; + + if ( pte.next_level >=3D level ) + { + printk(" L%u[%03x]: next: %u\n", level, idx, pte.next_level); + break; + } + + pt_mfn =3D _mfn(pte.mfn); + level =3D pte.next_level; + } +} + static unsigned long flush_count(unsigned long dfn, unsigned long page_cou= nt, unsigned int order) { --- a/xen/drivers/passthrough/amd/pci_amd_iommu.c +++ b/xen/drivers/passthrough/amd/pci_amd_iommu.c @@ -607,10 +607,11 @@ static void amd_dump_page_table_level(st mfn_to_page(_mfn(pde->mfn)), pde->next_level, address, indent + 1); else - printk("%*sdfn: %08lx mfn: %08lx\n", + printk("%*sdfn: %08lx mfn: %08lx %c%c\n", indent, "", (unsigned long)PFN_DOWN(address), - (unsigned long)PFN_DOWN(pfn_to_paddr(pde->mfn))); + (unsigned long)PFN_DOWN(pfn_to_paddr(pde->mfn)), + pde->ir ? 'r' : '-', pde->iw ? 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charset="utf-8" In order to free intermediate page tables when replacing smaller mappings by a single larger one callers will need to know the full PTE. Flush indicators can be derived from this in the callers (and outside the locked regions). First split set_iommu_pte_present() from set_iommu_ptes_present(): Only the former needs to return the old PTE, while the latter (like also set_iommu_pde_present()) doesn't even need to return flush indicators. Then change return types/values and callers accordingly. Signed-off-by: Jan Beulich --- a/xen/drivers/passthrough/amd/iommu_map.c +++ b/xen/drivers/passthrough/amd/iommu_map.c @@ -31,30 +31,28 @@ static unsigned int pfn_to_pde_idx(unsig return idx; } =20 -static unsigned int clear_iommu_pte_present(unsigned long l1_mfn, - unsigned long dfn) +static union amd_iommu_pte clear_iommu_pte_present(unsigned long l1_mfn, + unsigned long dfn) { - union amd_iommu_pte *table, *pte; - unsigned int flush_flags; + union amd_iommu_pte *table, *pte, old; =20 table =3D map_domain_page(_mfn(l1_mfn)); pte =3D &table[pfn_to_pde_idx(dfn, 1)]; + old =3D *pte; =20 - flush_flags =3D pte->pr ? IOMMU_FLUSHF_modified : 0; write_atomic(&pte->raw, 0); =20 unmap_domain_page(table); =20 - return flush_flags; + return old; } =20 -static unsigned int set_iommu_pde_present(union amd_iommu_pte *pte, - unsigned long next_mfn, - unsigned int next_level, bool iw, - bool ir) +static void set_iommu_pde_present(union amd_iommu_pte *pte, + unsigned long next_mfn, + unsigned int next_level, + bool iw, bool ir) { - union amd_iommu_pte new =3D {}, old; - unsigned int flush_flags =3D IOMMU_FLUSHF_added; + union amd_iommu_pte new =3D {}; =20 /* * FC bit should be enabled in PTE, this helps to solve potential @@ -68,28 +66,42 @@ static unsigned int set_iommu_pde_presen new.next_level =3D next_level; new.pr =3D true; =20 - old.raw =3D read_atomic(&pte->raw); - old.ign0 =3D 0; - old.ign1 =3D 0; - old.ign2 =3D 0; + write_atomic(&pte->raw, new.raw); +} =20 - if ( old.pr && old.raw !=3D new.raw ) - flush_flags |=3D IOMMU_FLUSHF_modified; +static union amd_iommu_pte set_iommu_pte_present(unsigned long pt_mfn, + unsigned long dfn, + unsigned long next_mfn, + unsigned int level, + bool iw, bool ir) +{ + union amd_iommu_pte *table, *pde, old; =20 - write_atomic(&pte->raw, new.raw); + table =3D map_domain_page(_mfn(pt_mfn)); + pde =3D &table[pfn_to_pde_idx(dfn, level)]; + + old =3D *pde; + if ( !old.pr || old.next_level || + old.mfn !=3D next_mfn || + old.iw !=3D iw || old.ir !=3D ir ) + set_iommu_pde_present(pde, next_mfn, 0, iw, ir); + else + old.pr =3D false; /* signal "no change" to the caller */ =20 - return flush_flags; + unmap_domain_page(table); + + return old; } =20 -static unsigned int set_iommu_ptes_present(unsigned long pt_mfn, - unsigned long dfn, - unsigned long next_mfn, - unsigned int nr_ptes, - unsigned int pde_level, - bool iw, bool ir) +static void set_iommu_ptes_present(unsigned long pt_mfn, + unsigned long dfn, + unsigned long next_mfn, + unsigned int nr_ptes, + unsigned int pde_level, + bool iw, bool ir) { union amd_iommu_pte *table, *pde; - unsigned int page_sz, flush_flags =3D 0; + unsigned int page_sz; =20 table =3D map_domain_page(_mfn(pt_mfn)); pde =3D &table[pfn_to_pde_idx(dfn, pde_level)]; @@ -98,20 +110,18 @@ static unsigned int set_iommu_ptes_prese if ( (void *)(pde + nr_ptes) > (void *)table + PAGE_SIZE ) { ASSERT_UNREACHABLE(); - return 0; + return; } =20 while ( nr_ptes-- ) { - flush_flags |=3D set_iommu_pde_present(pde, next_mfn, 0, iw, ir); + set_iommu_pde_present(pde, next_mfn, 0, iw, ir); =20 ++pde; next_mfn +=3D page_sz; } =20 unmap_domain_page(table); - - return flush_flags; } =20 void amd_iommu_set_root_page_table(struct amd_iommu_dte *dte, @@ -284,6 +294,7 @@ int amd_iommu_map_page(struct domain *d, struct domain_iommu *hd =3D dom_iommu(d); int rc; unsigned long pt_mfn =3D 0; + union amd_iommu_pte old; =20 spin_lock(&hd->arch.mapping_lock); =20 @@ -320,12 +331,16 @@ int amd_iommu_map_page(struct domain *d, } =20 /* Install 4k mapping */ - *flush_flags |=3D set_iommu_ptes_present(pt_mfn, dfn_x(dfn), mfn_x(mfn= ), - 1, 1, (flags & IOMMUF_writable), - (flags & IOMMUF_readable)); + old =3D set_iommu_pte_present(pt_mfn, dfn_x(dfn), mfn_x(mfn), 1, + (flags & IOMMUF_writable), + (flags & IOMMUF_readable)); =20 spin_unlock(&hd->arch.mapping_lock); =20 + *flush_flags |=3D IOMMU_FLUSHF_added; + if ( old.pr ) + *flush_flags |=3D IOMMU_FLUSHF_modified; + return 0; } =20 @@ -334,6 +349,7 @@ int amd_iommu_unmap_page(struct domain * { unsigned long pt_mfn =3D 0; struct domain_iommu *hd =3D dom_iommu(d); + union amd_iommu_pte old =3D {}; =20 spin_lock(&hd->arch.mapping_lock); =20 @@ -355,11 +371,14 @@ int amd_iommu_unmap_page(struct domain * if ( pt_mfn ) { /* Mark PTE as 'page not present'. */ - *flush_flags |=3D clear_iommu_pte_present(pt_mfn, dfn_x(dfn)); + old =3D clear_iommu_pte_present(pt_mfn, dfn_x(dfn)); } =20 spin_unlock(&hd->arch.mapping_lock); =20 + if ( old.pr ) + *flush_flags |=3D IOMMU_FLUSHF_modified; + return 0; } =20 From nobody Fri Nov 29 16:38:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; 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spf=pass smtp.mailfrom=suse.com; dmarc=pass action=none header.from=suse.com; dkim=pass header.d=suse.com; arc=none Authentication-Results: xen.org; dkim=none (message not signed) header.d=none;xen.org; dmarc=none action=none header.from=suse.com; Subject: [PATCH v2 12/18] AMD/IOMMU: allow use of superpage mappings From: Jan Beulich To: "xen-devel@lists.xenproject.org" Cc: Paul Durrant , Andrew Cooper , George Dunlap , Ian Jackson , Julien Grall , Stefano Stabellini , Wei Liu References: <957f067b-9fe1-2350-4266-51982f09d3a9@suse.com> Message-ID: Date: Fri, 24 Sep 2021 11:52:14 +0200 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.14.0 In-Reply-To: <957f067b-9fe1-2350-4266-51982f09d3a9@suse.com> Content-Language: en-US Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: FR3P281CA0023.DEUP281.PROD.OUTLOOK.COM (2603:10a6:d10:1c::7) To VI1PR04MB5600.eurprd04.prod.outlook.com (2603:10a6:803:e7::16) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: a89f903f-cb29-40e6-b50f-08d97f40fd59 X-MS-TrafficTypeDiagnostic: VI1PR0401MB2446: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:9508; 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charset="utf-8" No separate feature flags exist which would control availability of these; the only restriction is HATS (establishing the maximum number of page table levels in general), and even that has a lower bound of 4. Thus we can unconditionally announce 2M, 1G, and 512G mappings. (Via non-default page sizes the implementation in principle permits arbitrary size mappings, but these require multiple identical leaf PTEs to be written, which isn't all that different from having to write multiple consecutive PTEs with increasing frame numbers. IMO that's therefore beneficial only on hardware where suitable TLBs exist; I'm unaware of such hardware.) Signed-off-by: Jan Beulich --- I'm not fully sure about allowing 512G mappings: The scheduling-for- freeing of intermediate page tables can take quite a while when replacing a tree of 4k mappings by a single 512G one. Plus (or otoh) there's no present code path via which 512G chunks of memory could be allocated (and hence mapped) anyway. --- a/xen/drivers/passthrough/amd/iommu_map.c +++ b/xen/drivers/passthrough/amd/iommu_map.c @@ -32,12 +32,13 @@ static unsigned int pfn_to_pde_idx(unsig } =20 static union amd_iommu_pte clear_iommu_pte_present(unsigned long l1_mfn, - unsigned long dfn) + unsigned long dfn, + unsigned int level) { union amd_iommu_pte *table, *pte, old; =20 table =3D map_domain_page(_mfn(l1_mfn)); - pte =3D &table[pfn_to_pde_idx(dfn, 1)]; + pte =3D &table[pfn_to_pde_idx(dfn, level)]; old =3D *pte; =20 write_atomic(&pte->raw, 0); @@ -288,10 +289,31 @@ static int iommu_pde_from_dfn(struct dom return 0; } =20 +static void queue_free_pt(struct domain *d, mfn_t mfn, unsigned int next_l= evel) +{ + if ( next_level > 1 ) + { + union amd_iommu_pte *pt =3D map_domain_page(mfn); + unsigned int i; + + for ( i =3D 0; i < PTE_PER_TABLE_SIZE; ++i ) + if ( pt[i].pr && pt[i].next_level ) + { + ASSERT(pt[i].next_level < next_level); + queue_free_pt(d, _mfn(pt[i].mfn), pt[i].next_level); + } + + unmap_domain_page(pt); + } + + iommu_queue_free_pgtable(d, mfn_to_page(mfn)); +} + int amd_iommu_map_page(struct domain *d, dfn_t dfn, mfn_t mfn, unsigned int flags, unsigned int *flush_flags) { struct domain_iommu *hd =3D dom_iommu(d); + unsigned int level =3D (IOMMUF_order(flags) / PTE_PER_TABLE_SHIFT) + 1; int rc; unsigned long pt_mfn =3D 0; union amd_iommu_pte old; @@ -320,7 +342,7 @@ int amd_iommu_map_page(struct domain *d, return rc; } =20 - if ( iommu_pde_from_dfn(d, dfn_x(dfn), 1, &pt_mfn, flush_flags, true) = || + if ( iommu_pde_from_dfn(d, dfn_x(dfn), level, &pt_mfn, flush_flags, tr= ue) || !pt_mfn ) { spin_unlock(&hd->arch.mapping_lock); @@ -330,8 +352,8 @@ int amd_iommu_map_page(struct domain *d, return -EFAULT; } =20 - /* Install 4k mapping */ - old =3D set_iommu_pte_present(pt_mfn, dfn_x(dfn), mfn_x(mfn), 1, + /* Install mapping */ + old =3D set_iommu_pte_present(pt_mfn, dfn_x(dfn), mfn_x(mfn), level, (flags & IOMMUF_writable), (flags & IOMMUF_readable)); =20 @@ -339,8 +361,13 @@ int amd_iommu_map_page(struct domain *d, =20 *flush_flags |=3D IOMMU_FLUSHF_added; if ( old.pr ) + { *flush_flags |=3D IOMMU_FLUSHF_modified; =20 + if ( level > 1 && old.next_level ) + queue_free_pt(d, _mfn(old.mfn), old.next_level); + } + return 0; } =20 @@ -349,6 +376,7 @@ int amd_iommu_unmap_page(struct domain * { unsigned long pt_mfn =3D 0; struct domain_iommu *hd =3D dom_iommu(d); + unsigned int level =3D (order / PTE_PER_TABLE_SHIFT) + 1; union amd_iommu_pte old =3D {}; =20 spin_lock(&hd->arch.mapping_lock); @@ -359,7 +387,7 @@ int amd_iommu_unmap_page(struct domain * return 0; } =20 - if ( iommu_pde_from_dfn(d, dfn_x(dfn), 1, &pt_mfn, flush_flags, false)= ) + if ( iommu_pde_from_dfn(d, dfn_x(dfn), level, &pt_mfn, flush_flags, fa= lse) ) { spin_unlock(&hd->arch.mapping_lock); AMD_IOMMU_DEBUG("Invalid IO pagetable entry dfn =3D %"PRI_dfn"\n", @@ -371,14 +399,19 @@ int amd_iommu_unmap_page(struct domain * if ( pt_mfn ) { /* Mark PTE as 'page not present'. */ - old =3D clear_iommu_pte_present(pt_mfn, dfn_x(dfn)); + old =3D clear_iommu_pte_present(pt_mfn, dfn_x(dfn), level); } =20 spin_unlock(&hd->arch.mapping_lock); =20 if ( old.pr ) + { *flush_flags |=3D IOMMU_FLUSHF_modified; =20 + if ( level > 1 && old.next_level ) + queue_free_pt(d, _mfn(old.mfn), old.next_level); + } + return 0; } =20 --- a/xen/drivers/passthrough/amd/pci_amd_iommu.c +++ b/xen/drivers/passthrough/amd/pci_amd_iommu.c @@ -630,7 +630,7 @@ static void amd_dump_page_tables(struct } =20 static const struct iommu_ops __initconstrel _iommu_ops =3D { - .page_sizes =3D PAGE_SIZE_4K, + .page_sizes =3D PAGE_SIZE_4K | PAGE_SIZE_2M | PAGE_SIZE_1G | PAGE_SIZE= _512G, .init =3D amd_iommu_domain_init, .hwdom_init =3D amd_iommu_hwdom_init, .quarantine_init =3D amd_iommu_quarantine_init, --- a/xen/include/xen/page-defs.h +++ b/xen/include/xen/page-defs.h @@ -21,4 +21,19 @@ #define PAGE_MASK_64K PAGE_MASK_GRAN(64K) #define PAGE_ALIGN_64K(addr) PAGE_ALIGN_GRAN(64K, addr) =20 +#define PAGE_SHIFT_2M 21 +#define PAGE_SIZE_2M PAGE_SIZE_GRAN(2M) +#define PAGE_MASK_2M PAGE_MASK_GRAN(2M) +#define PAGE_ALIGN_2M(addr) PAGE_ALIGN_GRAN(2M, addr) + +#define PAGE_SHIFT_1G 30 +#define PAGE_SIZE_1G PAGE_SIZE_GRAN(1G) +#define PAGE_MASK_1G PAGE_MASK_GRAN(1G) +#define PAGE_ALIGN_1G(addr) PAGE_ALIGN_GRAN(1G, addr) + +#define PAGE_SHIFT_512G 39 +#define PAGE_SIZE_512G PAGE_SIZE_GRAN(512G) +#define PAGE_MASK_512G PAGE_MASK_GRAN(512G) +#define PAGE_ALIGN_512G(addr) PAGE_ALIGN_GRAN(512G, addr) + #endif /* __XEN_PAGE_DEFS_H__ */ From nobody Fri Nov 29 16:38:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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charset="utf-8" ... depending on feature availability (and absence of quirks). Also make the page table dumping function aware of superpages. Signed-off-by: Jan Beulich --- a/xen/drivers/passthrough/vtd/iommu.c +++ b/xen/drivers/passthrough/vtd/iommu.c @@ -743,18 +743,37 @@ static int __must_check iommu_flush_iotl return iommu_flush_iotlb(d, INVALID_DFN, 0, 0); } =20 +static void queue_free_pt(struct domain *d, mfn_t mfn, unsigned int next_l= evel) +{ + if ( next_level > 1 ) + { + struct dma_pte *pt =3D map_domain_page(mfn); + unsigned int i; + + for ( i =3D 0; i < PTE_NUM; ++i ) + if ( dma_pte_present(pt[i]) && !dma_pte_superpage(pt[i]) ) + queue_free_pt(d, maddr_to_mfn(dma_pte_addr(pt[i])), + next_level - 1); + + unmap_domain_page(pt); + } + + iommu_queue_free_pgtable(d, mfn_to_page(mfn)); +} + /* clear one page's page table */ static int dma_pte_clear_one(struct domain *domain, daddr_t addr, unsigned int order, unsigned int *flush_flags) { struct domain_iommu *hd =3D dom_iommu(domain); - struct dma_pte *page =3D NULL, *pte =3D NULL; + struct dma_pte *page =3D NULL, *pte =3D NULL, old; u64 pg_maddr; + unsigned int level =3D (order / LEVEL_STRIDE) + 1; =20 spin_lock(&hd->arch.mapping_lock); - /* get last level pte */ - pg_maddr =3D addr_to_dma_page_maddr(domain, addr, 1, flush_flags, fals= e); + /* get target level pte */ + pg_maddr =3D addr_to_dma_page_maddr(domain, addr, level, flush_flags, = false); if ( pg_maddr < PAGE_SIZE ) { spin_unlock(&hd->arch.mapping_lock); @@ -762,7 +781,7 @@ static int dma_pte_clear_one(struct doma } =20 page =3D (struct dma_pte *)map_vtd_domain_page(pg_maddr); - pte =3D page + address_level_offset(addr, 1); + pte =3D &page[address_level_offset(addr, level)]; =20 if ( !dma_pte_present(*pte) ) { @@ -771,14 +790,19 @@ static int dma_pte_clear_one(struct doma return 0; } =20 + old =3D *pte; dma_clear_pte(*pte); - *flush_flags |=3D IOMMU_FLUSHF_modified; =20 spin_unlock(&hd->arch.mapping_lock); iommu_sync_cache(pte, sizeof(struct dma_pte)); =20 unmap_vtd_domain_page(page); =20 + *flush_flags |=3D IOMMU_FLUSHF_modified; + + if ( level > 1 && !dma_pte_superpage(old) ) + queue_free_pt(domain, maddr_to_mfn(dma_pte_addr(old)), level - 1); + return 0; } =20 @@ -1868,6 +1892,7 @@ static int __must_check intel_iommu_map_ struct domain_iommu *hd =3D dom_iommu(d); struct dma_pte *page, *pte, old, new =3D {}; u64 pg_maddr; + unsigned int level =3D (IOMMUF_order(flags) / LEVEL_STRIDE) + 1; int rc =3D 0; =20 /* Do nothing if VT-d shares EPT page table */ @@ -1892,7 +1917,7 @@ static int __must_check intel_iommu_map_ return 0; } =20 - pg_maddr =3D addr_to_dma_page_maddr(d, dfn_to_daddr(dfn), 1, flush_fla= gs, + pg_maddr =3D addr_to_dma_page_maddr(d, dfn_to_daddr(dfn), level, flush= _flags, true); if ( pg_maddr < PAGE_SIZE ) { @@ -1901,13 +1926,15 @@ static int __must_check intel_iommu_map_ } =20 page =3D (struct dma_pte *)map_vtd_domain_page(pg_maddr); - pte =3D &page[dfn_x(dfn) & LEVEL_MASK]; + pte =3D &page[address_level_offset(dfn_to_daddr(dfn), level)]; old =3D *pte; =20 dma_set_pte_addr(new, mfn_to_maddr(mfn)); dma_set_pte_prot(new, ((flags & IOMMUF_readable) ? DMA_PTE_READ : 0) | ((flags & IOMMUF_writable) ? DMA_PTE_WRITE : 0)); + if ( IOMMUF_order(flags) ) + dma_set_pte_superpage(new); =20 /* Set the SNP on leaf page table if Snoop Control available */ if ( iommu_snoop ) @@ -1928,8 +1955,13 @@ static int __must_check intel_iommu_map_ =20 *flush_flags |=3D IOMMU_FLUSHF_added; if ( dma_pte_present(old) ) + { *flush_flags |=3D IOMMU_FLUSHF_modified; =20 + if ( level > 1 && !dma_pte_superpage(old) ) + queue_free_pt(d, maddr_to_mfn(dma_pte_addr(old)), level - 1); + } + return rc; } =20 @@ -2286,6 +2318,7 @@ static int __init vtd_setup(void) { struct acpi_drhd_unit *drhd; struct vtd_iommu *iommu; + unsigned int large_sizes =3D PAGE_SIZE_2M | PAGE_SIZE_1G; int ret; bool reg_inval_supported =3D true; =20 @@ -2328,6 +2361,11 @@ static int __init vtd_setup(void) cap_sps_2mb(iommu->cap) ? ", 2MB" : "", cap_sps_1gb(iommu->cap) ? ", 1GB" : ""); =20 + if ( !cap_sps_2mb(iommu->cap) ) + large_sizes &=3D ~PAGE_SIZE_2M; + if ( !cap_sps_1gb(iommu->cap) ) + large_sizes &=3D ~PAGE_SIZE_1G; + #ifndef iommu_snoop if ( iommu_snoop && !ecap_snp_ctl(iommu->ecap) ) iommu_snoop =3D false; @@ -2399,6 +2437,9 @@ static int __init vtd_setup(void) if ( ret ) goto error; =20 + ASSERT(iommu_ops.page_sizes & PAGE_SIZE_4K); + iommu_ops.page_sizes |=3D large_sizes; + register_keyhandler('V', vtd_dump_iommu_info, "dump iommu info", 1); =20 return 0; @@ -2712,7 +2753,7 @@ static void vtd_dump_page_table_level(pa continue; =20 address =3D gpa + offset_level_address(i, level); - if ( next_level >=3D 1 )=20 + if ( next_level && !dma_pte_superpage(*pte) ) vtd_dump_page_table_level(dma_pte_addr(*pte), next_level, address, indent + 1); else From nobody Fri Nov 29 16:38:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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charset="utf-8" Having a separate flush-all hook has always been puzzling me some. We will want to be able to force a full flush via accumulated flush flags from the map/unmap functions. Introduce a respective new flag and fold all flush handling to use the single remaining hook. Note that because of the respective comments in SMMU and IPMMU-VMSA code, I've folded the two prior hook functions into one. For SMMU-v3, which lacks a comment towards incapable hardware, I've left both functions in place on the assumption that selective and full flushes will eventually want separating. Signed-off-by: Jan Beulich Acked-by: Julien Grall Reviewed-by: Oleksandr Tyshchenko Reviewed-by: Rahul Singh --- TBD: What we really are going to need is for the map/unmap functions to specify that a wider region needs flushing than just the one covered by the present set of (un)maps. This may still be less than a full flush, but at least as a first step it seemed better to me to keep things simple and go the flush-all route. --- v2: New. --- a/xen/drivers/passthrough/amd/iommu.h +++ b/xen/drivers/passthrough/amd/iommu.h @@ -242,7 +242,6 @@ int amd_iommu_get_reserved_device_memory int __must_check amd_iommu_flush_iotlb_pages(struct domain *d, dfn_t dfn, unsigned long page_count, unsigned int flush_flags); -int __must_check amd_iommu_flush_iotlb_all(struct domain *d); void amd_iommu_print_entries(const struct amd_iommu *iommu, unsigned int d= ev_id, dfn_t dfn); =20 --- a/xen/drivers/passthrough/amd/iommu_map.c +++ b/xen/drivers/passthrough/amd/iommu_map.c @@ -475,15 +475,18 @@ int amd_iommu_flush_iotlb_pages(struct d { unsigned long dfn_l =3D dfn_x(dfn); =20 - ASSERT(page_count && !dfn_eq(dfn, INVALID_DFN)); - ASSERT(flush_flags); + if ( !(flush_flags & IOMMU_FLUSHF_all) ) + { + ASSERT(page_count && !dfn_eq(dfn, INVALID_DFN)); + ASSERT(flush_flags); + } =20 /* Unless a PTE was modified, no flush is required */ if ( !(flush_flags & IOMMU_FLUSHF_modified) ) return 0; =20 - /* If the range wraps then just flush everything */ - if ( dfn_l + page_count < dfn_l ) + /* If so requested or if the range wraps then just flush everything. */ + if ( (flush_flags & IOMMU_FLUSHF_all) || dfn_l + page_count < dfn_l ) { amd_iommu_flush_all_pages(d); return 0; @@ -508,13 +511,6 @@ int amd_iommu_flush_iotlb_pages(struct d =20 return 0; } - -int amd_iommu_flush_iotlb_all(struct domain *d) -{ - amd_iommu_flush_all_pages(d); - - return 0; -} =20 int amd_iommu_reserve_domain_unity_map(struct domain *d, const struct ivrs_unity_map *map, --- a/xen/drivers/passthrough/amd/pci_amd_iommu.c +++ b/xen/drivers/passthrough/amd/pci_amd_iommu.c @@ -642,7 +642,6 @@ static const struct iommu_ops __initcons .map_page =3D amd_iommu_map_page, .unmap_page =3D amd_iommu_unmap_page, .iotlb_flush =3D amd_iommu_flush_iotlb_pages, - .iotlb_flush_all =3D amd_iommu_flush_iotlb_all, .reassign_device =3D reassign_device, .get_device_group_id =3D amd_iommu_group_id, .enable_x2apic =3D iov_enable_xt, --- a/xen/drivers/passthrough/arm/ipmmu-vmsa.c +++ b/xen/drivers/passthrough/arm/ipmmu-vmsa.c @@ -930,13 +930,19 @@ out: } =20 /* Xen IOMMU ops */ -static int __must_check ipmmu_iotlb_flush_all(struct domain *d) +static int __must_check ipmmu_iotlb_flush(struct domain *d, dfn_t dfn, + unsigned long page_count, + unsigned int flush_flags) { struct ipmmu_vmsa_xen_domain *xen_domain =3D dom_iommu(d)->arch.priv; =20 + ASSERT(flush_flags); + if ( !xen_domain || !xen_domain->root_domain ) return 0; =20 + /* The hardware doesn't support selective TLB flush. */ + spin_lock(&xen_domain->lock); ipmmu_tlb_invalidate(xen_domain->root_domain); spin_unlock(&xen_domain->lock); @@ -944,16 +950,6 @@ static int __must_check ipmmu_iotlb_flus return 0; } =20 -static int __must_check ipmmu_iotlb_flush(struct domain *d, dfn_t dfn, - unsigned long page_count, - unsigned int flush_flags) -{ - ASSERT(flush_flags); - - /* The hardware doesn't support selective TLB flush. */ - return ipmmu_iotlb_flush_all(d); -} - static struct ipmmu_vmsa_domain *ipmmu_get_cache_domain(struct domain *d, struct device *dev) { @@ -1303,7 +1299,6 @@ static const struct iommu_ops ipmmu_iomm .hwdom_init =3D ipmmu_iommu_hwdom_init, .teardown =3D ipmmu_iommu_domain_teardown, .iotlb_flush =3D ipmmu_iotlb_flush, - .iotlb_flush_all =3D ipmmu_iotlb_flush_all, .assign_device =3D ipmmu_assign_device, .reassign_device =3D ipmmu_reassign_device, .map_page =3D arm_iommu_map_page, --- a/xen/drivers/passthrough/arm/smmu.c +++ b/xen/drivers/passthrough/arm/smmu.c @@ -2649,11 +2649,17 @@ static int force_stage =3D 2; */ static u32 platform_features =3D ARM_SMMU_FEAT_COHERENT_WALK; =20 -static int __must_check arm_smmu_iotlb_flush_all(struct domain *d) +static int __must_check arm_smmu_iotlb_flush(struct domain *d, dfn_t dfn, + unsigned long page_count, + unsigned int flush_flags) { struct arm_smmu_xen_domain *smmu_domain =3D dom_iommu(d)->arch.priv; struct iommu_domain *cfg; =20 + ASSERT(flush_flags); + + /* ARM SMMU v1 doesn't have flush by VMA and VMID */ + spin_lock(&smmu_domain->lock); list_for_each_entry(cfg, &smmu_domain->contexts, list) { /* @@ -2670,16 +2676,6 @@ static int __must_check arm_smmu_iotlb_f return 0; } =20 -static int __must_check arm_smmu_iotlb_flush(struct domain *d, dfn_t dfn, - unsigned long page_count, - unsigned int flush_flags) -{ - ASSERT(flush_flags); - - /* ARM SMMU v1 doesn't have flush by VMA and VMID */ - return arm_smmu_iotlb_flush_all(d); -} - static struct iommu_domain *arm_smmu_get_domain(struct domain *d, struct device *dev) { @@ -2879,7 +2875,6 @@ static const struct iommu_ops arm_smmu_i .add_device =3D arm_smmu_dt_add_device_generic, .teardown =3D arm_smmu_iommu_domain_teardown, .iotlb_flush =3D arm_smmu_iotlb_flush, - .iotlb_flush_all =3D arm_smmu_iotlb_flush_all, .assign_device =3D arm_smmu_assign_dev, .reassign_device =3D arm_smmu_reassign_dev, .map_page =3D arm_iommu_map_page, --- a/xen/drivers/passthrough/arm/smmu-v3.c +++ b/xen/drivers/passthrough/arm/smmu-v3.c @@ -3431,7 +3431,6 @@ static const struct iommu_ops arm_smmu_i .hwdom_init =3D arm_smmu_iommu_hwdom_init, .teardown =3D arm_smmu_iommu_xen_domain_teardown, .iotlb_flush =3D arm_smmu_iotlb_flush, - .iotlb_flush_all =3D arm_smmu_iotlb_flush_all, .assign_device =3D arm_smmu_assign_dev, .reassign_device =3D arm_smmu_reassign_dev, .map_page =3D arm_iommu_map_page, --- a/xen/drivers/passthrough/iommu.c +++ b/xen/drivers/passthrough/iommu.c @@ -463,15 +463,12 @@ int iommu_iotlb_flush_all(struct domain const struct domain_iommu *hd =3D dom_iommu(d); int rc; =20 - if ( !is_iommu_enabled(d) || !hd->platform_ops->iotlb_flush_all || + if ( !is_iommu_enabled(d) || !hd->platform_ops->iotlb_flush || !flush_flags ) return 0; =20 - /* - * The operation does a full flush so we don't need to pass the - * flush_flags in. - */ - rc =3D iommu_call(hd->platform_ops, iotlb_flush_all, d); + rc =3D iommu_call(hd->platform_ops, iotlb_flush, d, INVALID_DFN, 0, + flush_flags | IOMMU_FLUSHF_all); if ( unlikely(rc) ) { if ( !d->is_shutting_down && printk_ratelimit() ) --- a/xen/drivers/passthrough/vtd/iommu.c +++ b/xen/drivers/passthrough/vtd/iommu.c @@ -731,18 +731,21 @@ static int __must_check iommu_flush_iotl unsigned long page_count, unsigned int flush_flags) { - ASSERT(page_count && !dfn_eq(dfn, INVALID_DFN)); - ASSERT(flush_flags); + if ( flush_flags & IOMMU_FLUSHF_all ) + { + dfn =3D INVALID_DFN; + page_count =3D 0; + } + else + { + ASSERT(page_count && !dfn_eq(dfn, INVALID_DFN)); + ASSERT(flush_flags); + } =20 return iommu_flush_iotlb(d, dfn, flush_flags & IOMMU_FLUSHF_modified, page_count); } =20 -static int __must_check iommu_flush_iotlb_all(struct domain *d) -{ - return iommu_flush_iotlb(d, INVALID_DFN, 0, 0); -} - static void queue_free_pt(struct domain *d, mfn_t mfn, unsigned int next_l= evel) { if ( next_level > 1 ) @@ -2841,7 +2844,7 @@ static int __init intel_iommu_quarantine spin_unlock(&hd->arch.mapping_lock); =20 if ( !rc ) - rc =3D iommu_flush_iotlb_all(d); + rc =3D iommu_flush_iotlb(d, INVALID_DFN, 0, 0); =20 /* Pages may be leaked in failure case */ return rc; @@ -2874,7 +2877,6 @@ static struct iommu_ops __initdata vtd_o .resume =3D vtd_resume, .crash_shutdown =3D vtd_crash_shutdown, .iotlb_flush =3D iommu_flush_iotlb_pages, - .iotlb_flush_all =3D iommu_flush_iotlb_all, .get_reserved_device_memory =3D intel_iommu_get_reserved_device_memory, .dump_page_tables =3D vtd_dump_page_tables, }; --- a/xen/include/xen/iommu.h +++ b/xen/include/xen/iommu.h @@ -147,9 +147,11 @@ enum { _IOMMU_FLUSHF_added, _IOMMU_FLUSHF_modified, + _IOMMU_FLUSHF_all, }; #define IOMMU_FLUSHF_added (1u << _IOMMU_FLUSHF_added) #define IOMMU_FLUSHF_modified (1u << _IOMMU_FLUSHF_modified) +#define IOMMU_FLUSHF_all (1u << _IOMMU_FLUSHF_all) =20 int __must_check iommu_map(struct domain *d, dfn_t dfn, mfn_t mfn, unsigned long page_count, unsigned int flags, @@ -282,7 +284,6 @@ struct iommu_ops { int __must_check (*iotlb_flush)(struct domain *d, dfn_t dfn, unsigned long page_count, unsigned int flush_flags); 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charset="utf-8" Page table are used for two purposes after allocation: They either start out all empty, or they get filled to replace a superpage. Subsequently, to replace all empty or fully contiguous page tables, contiguous sub- regions will be recorded within individual page tables. Install the initial set of markers immediately after allocation. Make sure to retain these markers when further populating a page table in preparation for it to replace a superpage. The markers are simply 4-bit fields holding the order value of contiguous entries. To demonstrate this, if a page table had just 16 entries, this would be the initial (fully contiguous) set of markers: index 0 1 2 3 4 5 6 7 8 9 A B C D E F marker 4 0 1 0 2 0 1 0 3 0 1 0 2 0 1 0 "Contiguous" here means not only present entries with successively increasing MFNs, each one suitably aligned for its slot, but also a respective number of all non-present entries. Signed-off-by: Jan Beulich --- An alternative to the ASSERT()s added to set_iommu_ptes_present() would be to make the function less general-purpose; it's used in a single place only after all (i.e. it might as well be folded into its only caller). --- v2: New. --- a/xen/drivers/passthrough/amd/iommu-defs.h +++ b/xen/drivers/passthrough/amd/iommu-defs.h @@ -445,6 +445,8 @@ union amd_iommu_x2apic_control { #define IOMMU_PAGE_TABLE_U32_PER_ENTRY (IOMMU_PAGE_TABLE_ENTRY_SIZE / 4) #define IOMMU_PAGE_TABLE_ALIGNMENT 4096 =20 +#define IOMMU_PTE_CONTIG_MASK 0x1e /* The ign0 field below. */ + union amd_iommu_pte { uint64_t raw; struct { --- a/xen/drivers/passthrough/amd/iommu_map.c +++ b/xen/drivers/passthrough/amd/iommu_map.c @@ -116,7 +116,19 @@ static void set_iommu_ptes_present(unsig =20 while ( nr_ptes-- ) { - set_iommu_pde_present(pde, next_mfn, 0, iw, ir); + ASSERT(!pde->next_level); + ASSERT(!pde->u); + + if ( pde > table ) + ASSERT(pde->ign0 =3D=3D find_first_set_bit(pde - table)); + else + ASSERT(pde->ign0 =3D=3D PAGE_SHIFT - 3); + + pde->iw =3D iw; + pde->ir =3D ir; + pde->fc =3D true; /* See set_iommu_pde_present(). */ + pde->mfn =3D next_mfn; + pde->pr =3D true; =20 ++pde; next_mfn +=3D page_sz; @@ -232,7 +244,7 @@ static int iommu_pde_from_dfn(struct dom mfn =3D next_table_mfn; =20 /* allocate lower level page table */ - table =3D iommu_alloc_pgtable(d); + table =3D iommu_alloc_pgtable(d, IOMMU_PTE_CONTIG_MASK); if ( table =3D=3D NULL ) { AMD_IOMMU_DEBUG("Cannot allocate I/O page table\n"); @@ -262,7 +274,7 @@ static int iommu_pde_from_dfn(struct dom =20 if ( next_table_mfn =3D=3D 0 ) { - table =3D iommu_alloc_pgtable(d); + table =3D iommu_alloc_pgtable(d, IOMMU_PTE_CONTIG_MASK); if ( table =3D=3D NULL ) { AMD_IOMMU_DEBUG("Cannot allocate I/O page table\n"); @@ -648,7 +660,7 @@ int __init amd_iommu_quarantine_init(str =20 spin_lock(&hd->arch.mapping_lock); =20 - hd->arch.amd.root_table =3D iommu_alloc_pgtable(d); + hd->arch.amd.root_table =3D iommu_alloc_pgtable(d, 0); if ( !hd->arch.amd.root_table ) goto out; =20 @@ -663,7 +675,7 @@ int __init amd_iommu_quarantine_init(str * page table pages, and the resulting allocations are always * zeroed. */ - pg =3D iommu_alloc_pgtable(d); + pg =3D iommu_alloc_pgtable(d, 0); if ( !pg ) break; =20 --- a/xen/drivers/passthrough/amd/pci_amd_iommu.c +++ b/xen/drivers/passthrough/amd/pci_amd_iommu.c @@ -238,7 +238,7 @@ int amd_iommu_alloc_root(struct domain * =20 if ( unlikely(!hd->arch.amd.root_table) ) { - hd->arch.amd.root_table =3D iommu_alloc_pgtable(d); + hd->arch.amd.root_table =3D iommu_alloc_pgtable(d, 0); if ( !hd->arch.amd.root_table ) return -ENOMEM; } --- a/xen/drivers/passthrough/vtd/iommu.c +++ b/xen/drivers/passthrough/vtd/iommu.c @@ -297,7 +297,7 @@ static uint64_t addr_to_dma_page_maddr(s goto out; =20 pte_maddr =3D level; - if ( !(pg =3D iommu_alloc_pgtable(domain)) ) + if ( !(pg =3D iommu_alloc_pgtable(domain, 0)) ) goto out; =20 hd->arch.vtd.pgd_maddr =3D page_to_maddr(pg); @@ -339,7 +339,7 @@ static uint64_t addr_to_dma_page_maddr(s } =20 pte_maddr =3D level - 1; - pg =3D iommu_alloc_pgtable(domain); + pg =3D iommu_alloc_pgtable(domain, DMA_PTE_CONTIG_MASK); if ( !pg ) break; =20 @@ -351,12 +351,13 @@ static uint64_t addr_to_dma_page_maddr(s struct dma_pte *split =3D map_vtd_domain_page(pte_maddr); unsigned long inc =3D 1UL << level_to_offset_bits(level - = 1); =20 - split[0].val =3D pte->val; + split[0].val |=3D pte->val & ~DMA_PTE_CONTIG_MASK; if ( inc =3D=3D PAGE_SIZE ) split[0].val &=3D ~DMA_PTE_SP; =20 for ( offset =3D 1; offset < PTE_NUM; ++offset ) - split[offset].val =3D split[offset - 1].val + inc; + split[offset].val |=3D + (split[offset - 1].val & ~DMA_PTE_CONTIG_MASK) + i= nc; =20 iommu_sync_cache(split, PAGE_SIZE); unmap_vtd_domain_page(split); @@ -1943,7 +1944,7 @@ static int __must_check intel_iommu_map_ if ( iommu_snoop ) dma_set_pte_snp(new); =20 - if ( old.val =3D=3D new.val ) + if ( !((old.val ^ new.val) & ~DMA_PTE_CONTIG_MASK) ) { spin_unlock(&hd->arch.mapping_lock); unmap_vtd_domain_page(page); @@ -2798,7 +2799,7 @@ static int __init intel_iommu_quarantine goto out; } =20 - pg =3D iommu_alloc_pgtable(d); + pg =3D iommu_alloc_pgtable(d, 0); =20 rc =3D -ENOMEM; if ( !pg ) @@ -2817,7 +2818,7 @@ static int __init intel_iommu_quarantine * page table pages, and the resulting allocations are always * zeroed. */ - pg =3D iommu_alloc_pgtable(d); + pg =3D iommu_alloc_pgtable(d, 0); =20 if ( !pg ) goto out; --- a/xen/drivers/passthrough/vtd/iommu.h +++ b/xen/drivers/passthrough/vtd/iommu.h @@ -265,6 +265,7 @@ struct dma_pte { #define DMA_PTE_PROT (DMA_PTE_READ | DMA_PTE_WRITE) #define DMA_PTE_SP (1 << 7) #define DMA_PTE_SNP (1 << 11) +#define DMA_PTE_CONTIG_MASK (0xfull << PADDR_BITS) #define dma_clear_pte(p) do {(p).val =3D 0;} while(0) #define dma_set_pte_readable(p) do {(p).val |=3D DMA_PTE_READ;} while(0) #define dma_set_pte_writable(p) do {(p).val |=3D DMA_PTE_WRITE;} while(0) @@ -278,7 +279,7 @@ struct dma_pte { #define dma_pte_write(p) (dma_pte_prot(p) & DMA_PTE_WRITE) #define dma_pte_addr(p) ((p).val & PADDR_MASK & PAGE_MASK_4K) #define dma_set_pte_addr(p, addr) do {\ - (p).val |=3D ((addr) & PAGE_MASK_4K); } while (0) + (p).val |=3D ((addr) & PADDR_MASK & PAGE_MASK_4K); } while (0) #define dma_pte_present(p) (((p).val & DMA_PTE_PROT) !=3D 0) #define dma_pte_superpage(p) (((p).val & DMA_PTE_SP) !=3D 0) =20 --- a/xen/drivers/passthrough/x86/iommu.c +++ b/xen/drivers/passthrough/x86/iommu.c @@ -433,12 +433,12 @@ int iommu_free_pgtables(struct domain *d return 0; } =20 -struct page_info *iommu_alloc_pgtable(struct domain *d) +struct page_info *iommu_alloc_pgtable(struct domain *d, uint64_t contig_ma= sk) { struct domain_iommu *hd =3D dom_iommu(d); unsigned int memflags =3D 0; struct page_info *pg; - void *p; + uint64_t *p; =20 #ifdef CONFIG_NUMA if ( hd->node !=3D NUMA_NO_NODE ) @@ -450,7 +450,28 @@ struct page_info *iommu_alloc_pgtable(st return NULL; =20 p =3D __map_domain_page(pg); - clear_page(p); + + if ( contig_mask ) + { + unsigned int i, shift =3D find_first_set_bit(contig_mask); + + ASSERT(((PAGE_SHIFT - 3) & (contig_mask >> shift)) =3D=3D PAGE_SHI= FT - 3); + + p[0] =3D (PAGE_SHIFT - 3ull) << shift; + p[1] =3D 0; + p[2] =3D 1ull << shift; + p[3] =3D 0; + + for ( i =3D 4; i < PAGE_SIZE / 8; i +=3D 4 ) + { + p[i + 0] =3D (find_first_set_bit(i) + 0ull) << shift; + p[i + 1] =3D 0; + p[i + 2] =3D 1ull << shift; + p[i + 3] =3D 0; + } + } + else + clear_page(p); =20 if ( hd->platform_ops->sync_cache ) iommu_vcall(hd->platform_ops, sync_cache, p, PAGE_SIZE); --- a/xen/include/asm-x86/iommu.h +++ b/xen/include/asm-x86/iommu.h @@ -142,7 +142,8 @@ int pi_update_irte(const struct pi_desc }) =20 int __must_check iommu_free_pgtables(struct domain *d); -struct page_info *__must_check iommu_alloc_pgtable(struct domain *d); +struct page_info *__must_check iommu_alloc_pgtable(struct domain *d, + uint64_t contig_mask); void iommu_queue_free_pgtable(struct domain *d, struct page_info *pg); =20 #endif /* !__ARCH_X86_IOMMU_H__ */ From nobody Fri Nov 29 16:38:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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charset="utf-8" This is a re-usable helper (kind of a template) which gets introduced without users so that the individual subsequent patches introducing such users can get committed independently of one another. See the comment at the top of the new file. To demonstrate the effect, if a page table had just 16 entries, this would be the set of markers for a page table with fully contiguous mappings: index 0 1 2 3 4 5 6 7 8 9 A B C D E F marker 4 0 1 0 2 0 1 0 3 0 1 0 2 0 1 0 "Contiguous" here means not only present entries with successively increasing MFNs, each one suitably aligned for its slot, but also a respective number of all non-present entries. Signed-off-by: Jan Beulich --- v2: New. --- /dev/null +++ b/xen/include/asm-x86/contig-marker.h @@ -0,0 +1,105 @@ +#ifndef __ASM_X86_CONTIG_MARKER_H +#define __ASM_X86_CONTIG_MARKER_H + +/* + * Short of having function templates in C, the function defined below is + * intended to be used by multiple parties interested in recording the + * degree of contiguity in mappings by a single page table. + * + * Scheme: Every entry records the order of contiguous successive entries, + * up to the maximum order covered by that entry (which is the number of + * clear low bits in its index, with entry 0 being the exception using + * the base-2 logarithm of the number of entries in a single page table). + * While a few entries need touching upon update, knowing whether the + * table is fully contiguous (and can hence be replaced by a higher level + * leaf entry) is then possible by simply looking at entry 0's marker. + * + * Prereqs: + * - CONTIG_MASK needs to be #define-d, to a value having at least 4 + * contiguous bits (ignored by hardware), before including this file, + * - page tables to be passed here need to be initialized with correct + * markers. + */ + +#include +#include +#include + +/* This is the same for all anticipated users, so doesn't need passing in.= */ +#define CONTIG_LEVEL_SHIFT 9 +#define CONTIG_NR (1 << CONTIG_LEVEL_SHIFT) + +#define GET_MARKER(e) MASK_EXTR(e, CONTIG_MASK) +#define SET_MARKER(e, m) \ + ((void)(e =3D ((e) & ~CONTIG_MASK) | MASK_INSR(m, CONTIG_MASK))) + +enum PTE_kind { + PTE_kind_null, + PTE_kind_leaf, + PTE_kind_table, +}; + +static bool update_contig_markers(uint64_t *pt, unsigned int idx, + unsigned int level, enum PTE_kind kind) +{ + unsigned int b, i =3D idx; + unsigned int shift =3D (level - 1) * CONTIG_LEVEL_SHIFT + PAGE_SHIFT; + + ASSERT(idx < CONTIG_NR); + ASSERT(!(pt[idx] & CONTIG_MASK)); + + /* Step 1: Reduce markers in lower numbered entries. */ + while ( i ) + { + b =3D find_first_set_bit(i); + i &=3D ~(1U << b); + if ( GET_MARKER(pt[i]) > b ) + SET_MARKER(pt[i], b); + } + + /* An intermediate table is never contiguous with anything. */ + if ( kind =3D=3D PTE_kind_table ) + return false; + + /* + * Present entries need in sync index and address to be a candidate + * for being contiguous: What we're after is whether ultimately the + * intermediate table can be replaced by a superpage. + */ + if ( kind !=3D PTE_kind_null && + idx !=3D ((pt[idx] >> shift) & (CONTIG_NR - 1)) ) + return false; + + /* Step 2: Check higher numbered entries for contiguity. */ + for ( b =3D 0; b < CONTIG_LEVEL_SHIFT && !(idx & (1U << b)); ++b ) + { + i =3D idx | (1U << b); + if ( (kind =3D=3D PTE_kind_leaf + ? ((pt[i] ^ pt[idx]) & ~CONTIG_MASK) !=3D (1ULL << (b + shif= t)) + : pt[i] & ~CONTIG_MASK) || + GET_MARKER(pt[i]) !=3D b ) + break; + } + + /* Step 3: Update markers in this and lower numbered entries. */ + for ( ; SET_MARKER(pt[idx], b), b < CONTIG_LEVEL_SHIFT; ++b ) + { + i =3D idx ^ (1U << b); + if ( (kind =3D=3D PTE_kind_leaf + ? ((pt[i] ^ pt[idx]) & ~CONTIG_MASK) !=3D (1ULL << (b + shif= t)) + : pt[i] & ~CONTIG_MASK) || + GET_MARKER(pt[i]) !=3D b ) + break; + idx &=3D ~(1U << b); + } + + return b =3D=3D CONTIG_LEVEL_SHIFT; +} + +#undef SET_MARKER +#undef GET_MARKER +#undef CONTIG_NR +#undef CONTIG_LEVEL_SHIFT +#undef CONTIG_MASK + +#endif /* __ASM_X86_CONTIG_MARKER_H */ From nobody Fri Nov 29 16:38:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; arc=pass (i=1 dmarc=pass fromdomain=suse.com); dmarc=pass(p=quarantine dis=none) header.from=suse.com ARC-Seal: i=2; a=rsa-sha256; t=1632477386; cv=pass; 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charset="utf-8" When a page table ends up with no present entries left, it can be replaced by a non-present entry at the next higher level. The page table itself can then be scheduled for freeing. Note that while its output isn't used there yet, update_contig_markers() right away needs to be called in all places where entries get updated, not just the one where entries get cleared. Signed-off-by: Jan Beulich --- v2: New. --- a/xen/drivers/passthrough/amd/iommu_map.c +++ b/xen/drivers/passthrough/amd/iommu_map.c @@ -21,6 +21,9 @@ =20 #include "iommu.h" =20 +#define CONTIG_MASK IOMMU_PTE_CONTIG_MASK +#include + /* Given pfn and page table level, return pde index */ static unsigned int pfn_to_pde_idx(unsigned long pfn, unsigned int level) { @@ -33,16 +36,20 @@ static unsigned int pfn_to_pde_idx(unsig =20 static union amd_iommu_pte clear_iommu_pte_present(unsigned long l1_mfn, unsigned long dfn, - unsigned int level) + unsigned int level, + bool *free) { union amd_iommu_pte *table, *pte, old; + unsigned int idx =3D pfn_to_pde_idx(dfn, level); =20 table =3D map_domain_page(_mfn(l1_mfn)); - pte =3D &table[pfn_to_pde_idx(dfn, level)]; + pte =3D &table[idx]; old =3D *pte; =20 write_atomic(&pte->raw, 0); =20 + *free =3D update_contig_markers(&table->raw, idx, level, PTE_kind_null= ); + unmap_domain_page(table); =20 return old; @@ -85,7 +92,11 @@ static union amd_iommu_pte set_iommu_pte if ( !old.pr || old.next_level || old.mfn !=3D next_mfn || old.iw !=3D iw || old.ir !=3D ir ) + { set_iommu_pde_present(pde, next_mfn, 0, iw, ir); + update_contig_markers(&table->raw, pfn_to_pde_idx(dfn, level), lev= el, + PTE_kind_leaf); + } else old.pr =3D false; /* signal "no change" to the caller */ =20 @@ -259,6 +270,9 @@ static int iommu_pde_from_dfn(struct dom smp_wmb(); set_iommu_pde_present(pde, next_table_mfn, next_level, true, true); + update_contig_markers(&next_table_vaddr->raw, + pfn_to_pde_idx(dfn, level), + level, PTE_kind_table); =20 *flush_flags |=3D IOMMU_FLUSHF_modified; } @@ -284,6 +298,9 @@ static int iommu_pde_from_dfn(struct dom next_table_mfn =3D mfn_x(page_to_mfn(table)); set_iommu_pde_present(pde, next_table_mfn, next_level, tru= e, true); + update_contig_markers(&next_table_vaddr->raw, + pfn_to_pde_idx(dfn, level), + level, PTE_kind_table); } else /* should never reach here */ { @@ -410,8 +427,25 @@ int amd_iommu_unmap_page(struct domain * =20 if ( pt_mfn ) { + bool free; + unsigned int pt_lvl =3D level; + /* Mark PTE as 'page not present'. */ - old =3D clear_iommu_pte_present(pt_mfn, dfn_x(dfn), level); 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charset="utf-8" When a page table ends up with no present entries left, it can be replaced by a non-present entry at the next higher level. The page table itself can then be scheduled for freeing. Note that while its output isn't used there yet, update_contig_markers() right away needs to be called in all places where entries get updated, not just the one where entries get cleared. Signed-off-by: Jan Beulich --- v2: New. --- a/xen/drivers/passthrough/vtd/iommu.c +++ b/xen/drivers/passthrough/vtd/iommu.c @@ -42,6 +42,9 @@ #include "vtd.h" #include "../ats.h" =20 +#define CONTIG_MASK DMA_PTE_CONTIG_MASK +#include + /* dom_io is used as a sentinel for quarantined devices */ #define QUARANTINE_SKIP(d) ((d) =3D=3D dom_io && !dom_iommu(d)->arch.vtd.p= gd_maddr) =20 @@ -368,6 +371,9 @@ static uint64_t addr_to_dma_page_maddr(s =20 write_atomic(&pte->val, new_pte.val); iommu_sync_cache(pte, sizeof(struct dma_pte)); + update_contig_markers(&parent->val, + address_level_offset(addr, level), + level, PTE_kind_table); } =20 if ( --level =3D=3D target ) @@ -773,7 +779,7 @@ static int dma_pte_clear_one(struct doma struct domain_iommu *hd =3D dom_iommu(domain); struct dma_pte *page =3D NULL, *pte =3D NULL, old; u64 pg_maddr; - unsigned int level =3D (order / LEVEL_STRIDE) + 1; + unsigned int level =3D (order / LEVEL_STRIDE) + 1, pt_lvl =3D level; =20 spin_lock(&hd->arch.mapping_lock); /* get target level pte */ @@ -796,9 +802,31 @@ static int dma_pte_clear_one(struct doma =20 old =3D *pte; dma_clear_pte(*pte); + iommu_sync_cache(pte, sizeof(*pte)); + + while ( update_contig_markers(&page->val, + address_level_offset(addr, pt_lvl), + pt_lvl, PTE_kind_null) && + ++pt_lvl < agaw_to_level(hd->arch.vtd.agaw) ) + { + struct page_info *pg =3D maddr_to_page(pg_maddr); + + unmap_vtd_domain_page(page); + + pg_maddr =3D addr_to_dma_page_maddr(domain, addr, pt_lvl, flush_fl= ags, + false); + BUG_ON(pg_maddr < PAGE_SIZE); + + page =3D map_vtd_domain_page(pg_maddr); + pte =3D &page[address_level_offset(addr, pt_lvl)]; + dma_clear_pte(*pte); + iommu_sync_cache(pte, sizeof(*pte)); + + *flush_flags |=3D IOMMU_FLUSHF_all; + iommu_queue_free_pgtable(domain, pg); + } =20 spin_unlock(&hd->arch.mapping_lock); - iommu_sync_cache(pte, sizeof(struct dma_pte)); =20 unmap_vtd_domain_page(page); =20 @@ -1952,8 +1980,11 @@ static int __must_check intel_iommu_map_ } =20 *pte =3D new; - iommu_sync_cache(pte, sizeof(struct dma_pte)); + update_contig_markers(&page->val, + address_level_offset(dfn_to_daddr(dfn), level), + level, PTE_kind_leaf); + spin_unlock(&hd->arch.mapping_lock); unmap_vtd_domain_page(page); =20