From nobody Fri Dec 19 02:51:20 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1607619650; cv=none; d=zohomail.com; s=zohoarc; b=llvXWayZ6WxFBJIcdPqLwH9KNULMKnkbYORi+3LS73Y1Kxj+mdfQNPBfOBa+9AhVzOcCj17kSwGm21iZx6VEHoM4Ghx1f3aDIXDNXZtBeI+nIGf03DDCV5lfwc7pk9/+PIljxMz9LStR3ZKvzeUud/+hA4LXYsEK5nRePA/8oCw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607619650; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=d0fNg7qu7wF1RCSXSh/6wZmaxxf3qMHYpBN9Lfl4VvE=; b=kx0ZkyhE5yinAw7wfnUC899URWUawv7gHMIDJauLSn/SOtrML45nsr5UPtv29lreZS3RFb2Nvkfrn14dqW5VNgVzXXFSXBUTa1Nz+NGzh9iepweyMkq5xwRCPiVVvepR4fNJni9070Y8w8h9vp9//jwsZr3roAgQC7GRFT/gmRY= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1607619650486775.1242330306783; Thu, 10 Dec 2020 09:00:50 -0800 (PST) Received: from list by lists.xenproject.org with outflank-mailman.49597.87727 (Exim 4.92) (envelope-from ) id 1knPIu-0007I7-D9; Thu, 10 Dec 2020 17:00:32 +0000 Received: by outflank-mailman (output) from mailman id 49597.87727; Thu, 10 Dec 2020 17:00:32 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1knPIu-0007I0-8e; Thu, 10 Dec 2020 17:00:32 +0000 Received: by outflank-mailman (input) for mailman id 49597; Thu, 10 Dec 2020 17:00:31 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1knPIt-0007Hm-HE for xen-devel@lists.xenproject.org; Thu, 10 Dec 2020 17:00:31 +0000 Received: from foss.arm.com (unknown [217.140.110.172]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTP id 6e9a53fb-61bf-445c-a320-c28acf59f846; Thu, 10 Dec 2020 17:00:29 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5216130E; Thu, 10 Dec 2020 09:00:29 -0800 (PST) Received: from scm-wfh-server-rahsin01.stack04.eu02.mi.arm.com (unknown [10.58.246.76]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 6CC753F66B; Thu, 10 Dec 2020 09:00:28 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 6e9a53fb-61bf-445c-a320-c28acf59f846 From: Rahul Singh To: xen-devel@lists.xenproject.org Cc: bertrand.marquis@arm.com, rahul.singh@arm.com, Stefano Stabellini , Julien Grall , Volodymyr Babchuk Subject: [PATCH v3 6/8] xen/arm: Remove Linux specific code that is not usable in XEN Date: Thu, 10 Dec 2020 16:57:04 +0000 Message-Id: <91b9845a03068d92aeaaa86fa67d4d06b2824652.1607617848.git.rahul.singh@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Remove code that is related to below functionality : 1. struct io_pgtable_ops 2. struct io_pgtable_cfg 3. struct iommu_flush_ops, 4. struct iommu_ops 5. module_param_named, MODULE_PARM_DESC, module_platform_driver, MODULE_* 6. IOMMU domain-types 7. arm_smmu_set_bus_ops 8. iommu_device_sysfs_add, iommu_device_register, iommu_device_set_fwnode Signed-off-by: Rahul Singh Reviewed-by: Bertrand Marquis Reviewed-by: Stefano Stabellini --- Changes in v3: - Commit message is updated to add more detail what is removed in this patch. - remove instances of io_pgtable_cfg. - Added back ARM_SMMU_FEAT_COHERENCY feature. --- xen/drivers/passthrough/arm/smmu-v3.c | 475 ++------------------------ 1 file changed, 21 insertions(+), 454 deletions(-) diff --git a/xen/drivers/passthrough/arm/smmu-v3.c b/xen/drivers/passthroug= h/arm/smmu-v3.c index 0f16c63c49..2966015e5d 100644 --- a/xen/drivers/passthrough/arm/smmu-v3.c +++ b/xen/drivers/passthrough/arm/smmu-v3.c @@ -394,13 +394,7 @@ #define ARM_SMMU_CMDQ_SYNC_TIMEOUT_US 1000000 /* 1s! */ #define ARM_SMMU_CMDQ_SYNC_SPIN_COUNT 10 =20 -#define MSI_IOVA_BASE 0x8000000 -#define MSI_IOVA_LENGTH 0x100000 - static bool disable_bypass =3D 1; -module_param_named(disable_bypass, disable_bypass, bool, S_IRUGO); -MODULE_PARM_DESC(disable_bypass, - "Disable bypass streams such that incoming transactions from devices that= are not attached to an iommu domain will report an abort back to the devic= e and will not be allowed to pass through the SMMU."); =20 enum pri_resp { PRI_RESP_DENY =3D 0, @@ -552,6 +546,19 @@ struct arm_smmu_strtab_cfg { u32 strtab_base_cfg; }; =20 +struct arm_lpae_s2_cfg { + u64 vttbr; + struct { + u32 ps:3; + u32 tg:2; + u32 sh:2; + u32 orgn:2; + u32 irgn:2; + u32 sl:2; + u32 tsz:6; + } vtcr; +}; + /* An SMMUv3 instance */ struct arm_smmu_device { struct device *dev; @@ -633,7 +640,6 @@ struct arm_smmu_domain { struct arm_smmu_device *smmu; struct mutex init_mutex; /* Protects smmu pointer */ =20 - struct io_pgtable_ops *pgtbl_ops; bool non_strict; atomic_t nr_ats_masters; =20 @@ -1493,7 +1499,6 @@ static int arm_smmu_atc_inv_domain(struct arm_smmu_do= main *smmu_domain, return ret ? -ETIMEDOUT : 0; } =20 -/* IO_PGTABLE API */ static void arm_smmu_tlb_inv_context(void *cookie) { struct arm_smmu_domain *smmu_domain =3D cookie; @@ -1514,86 +1519,10 @@ static void arm_smmu_tlb_inv_context(void *cookie) arm_smmu_cmdq_issue_sync(smmu); } =20 -static void arm_smmu_tlb_inv_range_nosync(unsigned long iova, size_t size, - size_t granule, bool leaf, void *cookie) -{ - struct arm_smmu_domain *smmu_domain =3D cookie; - struct arm_smmu_device *smmu =3D smmu_domain->smmu; - struct arm_smmu_cmdq_ent cmd =3D { - .tlbi =3D { - .leaf =3D leaf, - .addr =3D iova, - }, - }; - - if (!size) - return; - - cmd.opcode =3D CMDQ_OP_TLBI_S2_IPA; - cmd.tlbi.vmid =3D smmu_domain->s2_cfg.vmid; - - do { - arm_smmu_cmdq_issue_cmd(smmu, &cmd); - cmd.tlbi.addr +=3D granule; - } while (size -=3D granule); -} - -static void arm_smmu_tlb_inv_page_nosync(struct iommu_iotlb_gather *gather, - unsigned long iova, size_t granule, - void *cookie) -{ - arm_smmu_tlb_inv_range_nosync(iova, granule, granule, true, cookie); -} - -static void arm_smmu_tlb_inv_walk(unsigned long iova, size_t size, - size_t granule, void *cookie) -{ - struct arm_smmu_domain *smmu_domain =3D cookie; - struct arm_smmu_device *smmu =3D smmu_domain->smmu; - - arm_smmu_tlb_inv_range_nosync(iova, size, granule, false, cookie); - arm_smmu_cmdq_issue_sync(smmu); -} - -static void arm_smmu_tlb_inv_leaf(unsigned long iova, size_t size, - size_t granule, void *cookie) -{ - struct arm_smmu_domain *smmu_domain =3D cookie; - struct arm_smmu_device *smmu =3D smmu_domain->smmu; - - arm_smmu_tlb_inv_range_nosync(iova, size, granule, true, cookie); - arm_smmu_cmdq_issue_sync(smmu); -} - -static const struct iommu_flush_ops arm_smmu_flush_ops =3D { - .tlb_flush_all =3D arm_smmu_tlb_inv_context, - .tlb_flush_walk =3D arm_smmu_tlb_inv_walk, - .tlb_flush_leaf =3D arm_smmu_tlb_inv_leaf, - .tlb_add_page =3D arm_smmu_tlb_inv_page_nosync, -}; - -/* IOMMU API */ -static bool arm_smmu_capable(enum iommu_cap cap) -{ - switch (cap) { - case IOMMU_CAP_CACHE_COHERENCY: - return true; - case IOMMU_CAP_NOEXEC: - return true; - default: - return false; - } -} - -static struct iommu_domain *arm_smmu_domain_alloc(unsigned type) +static struct iommu_domain *arm_smmu_domain_alloc(void) { struct arm_smmu_domain *smmu_domain; =20 - if (type !=3D IOMMU_DOMAIN_UNMANAGED && - type !=3D IOMMU_DOMAIN_DMA && - type !=3D IOMMU_DOMAIN_IDENTITY) - return NULL; - /* * Allocate the domain and initialise some of its data structures. * We can't really do anything meaningful until we've added a @@ -1603,12 +1532,6 @@ static struct iommu_domain *arm_smmu_domain_alloc(un= signed type) if (!smmu_domain) return NULL; =20 - if (type =3D=3D IOMMU_DOMAIN_DMA && - iommu_get_dma_cookie(&smmu_domain->domain)) { - kfree(smmu_domain); - return NULL; - } - mutex_init(&smmu_domain->init_mutex); INIT_LIST_HEAD(&smmu_domain->devices); spin_lock_init(&smmu_domain->devices_lock); @@ -1640,9 +1563,6 @@ static void arm_smmu_domain_free(struct iommu_domain = *domain) struct arm_smmu_device *smmu =3D smmu_domain->smmu; struct arm_smmu_s2_cfg *cfg =3D &smmu_domain->s2_cfg; =20 - iommu_put_dma_cookie(domain); - free_io_pgtable_ops(smmu_domain->pgtbl_ops); - if (cfg->vmid) arm_smmu_bitmap_free(smmu->vmid_map, cfg->vmid); =20 @@ -1651,21 +1571,20 @@ static void arm_smmu_domain_free(struct iommu_domai= n *domain) =20 =20 static int arm_smmu_domain_finalise_s2(struct arm_smmu_domain *smmu_domain, - struct arm_smmu_master *master, - struct io_pgtable_cfg *pgtbl_cfg) + struct arm_smmu_master *master) { int vmid; + struct arm_lpae_s2_cfg arm_lpae_s2_cfg; struct arm_smmu_device *smmu =3D smmu_domain->smmu; struct arm_smmu_s2_cfg *cfg =3D &smmu_domain->s2_cfg; - typeof(&pgtbl_cfg->arm_lpae_s2_cfg.vtcr) vtcr; + typeof(&arm_lpae_s2_cfg.vtcr) vtcr =3D &arm_lpae_s2_cfg.vtcr; =20 vmid =3D arm_smmu_bitmap_alloc(smmu->vmid_map, smmu->vmid_bits); if (vmid < 0) return vmid; =20 - vtcr =3D &pgtbl_cfg->arm_lpae_s2_cfg.vtcr; cfg->vmid =3D (u16)vmid; - cfg->vttbr =3D pgtbl_cfg->arm_lpae_s2_cfg.vttbr; + cfg->vttbr =3D arm_lpae_s2_cfg.vttbr; cfg->vtcr =3D FIELD_PREP(STRTAB_STE_2_VTCR_S2T0SZ, vtcr->tsz) | FIELD_PREP(STRTAB_STE_2_VTCR_S2SL0, vtcr->sl) | FIELD_PREP(STRTAB_STE_2_VTCR_S2IR0, vtcr->irgn) | @@ -1680,49 +1599,15 @@ static int arm_smmu_domain_finalise(struct iommu_do= main *domain, struct arm_smmu_master *master) { int ret; - unsigned long ias, oas; - enum io_pgtable_fmt fmt; - struct io_pgtable_cfg pgtbl_cfg; - struct io_pgtable_ops *pgtbl_ops; struct arm_smmu_domain *smmu_domain =3D to_smmu_domain(domain); - struct arm_smmu_device *smmu =3D smmu_domain->smmu; - - if (domain->type =3D=3D IOMMU_DOMAIN_IDENTITY) { - smmu_domain->stage =3D ARM_SMMU_DOMAIN_BYPASS; - return 0; - } =20 /* Restrict the stage to what we can actually support */ smmu_domain->stage =3D ARM_SMMU_DOMAIN_S2; =20 - - pgtbl_cfg =3D (struct io_pgtable_cfg) { - .pgsize_bitmap =3D smmu->pgsize_bitmap, - .ias =3D ias, - .oas =3D oas, - .coherent_walk =3D smmu->features & ARM_SMMU_FEAT_COHERENCY, - .tlb =3D &arm_smmu_flush_ops, - .iommu_dev =3D smmu->dev, - }; - - if (smmu_domain->non_strict) - pgtbl_cfg.quirks |=3D IO_PGTABLE_QUIRK_NON_STRICT; - - pgtbl_ops =3D alloc_io_pgtable_ops(fmt, &pgtbl_cfg, smmu_domain); - if (!pgtbl_ops) - return -ENOMEM; - - domain->pgsize_bitmap =3D pgtbl_cfg.pgsize_bitmap; - domain->geometry.aperture_end =3D (1UL << pgtbl_cfg.ias) - 1; - domain->geometry.force_aperture =3D true; - - ret =3D arm_smmu_domain_finalise_s2(smmu_domain, master, &pgtbl_cfg); - if (ret < 0) { - free_io_pgtable_ops(pgtbl_ops); + ret =3D arm_smmu_domain_finalise_s2(smmu_domain, master); + if (ret < 0) return ret; - } =20 - smmu_domain->pgtbl_ops =3D pgtbl_ops; return 0; } =20 @@ -1939,76 +1824,6 @@ out_unlock: return ret; } =20 -static int arm_smmu_map(struct iommu_domain *domain, unsigned long iova, - phys_addr_t paddr, size_t size, int prot, gfp_t gfp) -{ - struct io_pgtable_ops *ops =3D to_smmu_domain(domain)->pgtbl_ops; - - if (!ops) - return -ENODEV; - - return ops->map(ops, iova, paddr, size, prot); -} - -static size_t arm_smmu_unmap(struct iommu_domain *domain, unsigned long io= va, - size_t size, struct iommu_iotlb_gather *gather) -{ - int ret; - struct arm_smmu_domain *smmu_domain =3D to_smmu_domain(domain); - struct io_pgtable_ops *ops =3D smmu_domain->pgtbl_ops; - - if (!ops) - return 0; - - ret =3D ops->unmap(ops, iova, size, gather); - if (ret && arm_smmu_atc_inv_domain(smmu_domain, 0, iova, size)) - return 0; - - return ret; -} - -static void arm_smmu_flush_iotlb_all(struct iommu_domain *domain) -{ - struct arm_smmu_domain *smmu_domain =3D to_smmu_domain(domain); - - if (smmu_domain->smmu) - arm_smmu_tlb_inv_context(smmu_domain); -} - -static void arm_smmu_iotlb_sync(struct iommu_domain *domain, - struct iommu_iotlb_gather *gather) -{ - struct arm_smmu_device *smmu =3D to_smmu_domain(domain)->smmu; - - if (smmu) - arm_smmu_cmdq_issue_sync(smmu); -} - -static phys_addr_t -arm_smmu_iova_to_phys(struct iommu_domain *domain, dma_addr_t iova) -{ - struct io_pgtable_ops *ops =3D to_smmu_domain(domain)->pgtbl_ops; - - if (domain->type =3D=3D IOMMU_DOMAIN_IDENTITY) - return iova; - - if (!ops) - return 0; - - return ops->iova_to_phys(ops, iova); -} - -static struct platform_driver arm_smmu_driver; - -static -struct arm_smmu_device *arm_smmu_get_by_fwnode(struct fwnode_handle *fwnod= e) -{ - struct device *dev =3D driver_find_device_by_fwnode(&arm_smmu_driver.driv= er, - fwnode); - put_device(dev); - return dev ? dev_get_drvdata(dev) : NULL; -} - static bool arm_smmu_sid_in_range(struct arm_smmu_device *smmu, u32 sid) { unsigned long limit =3D smmu->strtab_cfg.num_l1_ents; @@ -2019,8 +1834,6 @@ static bool arm_smmu_sid_in_range(struct arm_smmu_dev= ice *smmu, u32 sid) return sid < limit; } =20 -static struct iommu_ops arm_smmu_ops; - static struct iommu_device *arm_smmu_probe_device(struct device *dev) { int i, ret; @@ -2028,16 +1841,12 @@ static struct iommu_device *arm_smmu_probe_device(s= truct device *dev) struct arm_smmu_master *master; struct iommu_fwspec *fwspec =3D dev_iommu_fwspec_get(dev); =20 - if (!fwspec || fwspec->ops !=3D &arm_smmu_ops) + if (!fwspec) return ERR_PTR(-ENODEV); =20 if (WARN_ON_ONCE(dev_iommu_priv_get(dev))) return ERR_PTR(-EBUSY); =20 - smmu =3D arm_smmu_get_by_fwnode(fwspec->iommu_fwnode); - if (!smmu) - return ERR_PTR(-ENODEV); - master =3D kzalloc(sizeof(*master), GFP_KERNEL); if (!master) return ERR_PTR(-ENOMEM); @@ -2083,153 +1892,11 @@ err_free_master: return ERR_PTR(ret); } =20 -static void arm_smmu_release_device(struct device *dev) -{ - struct iommu_fwspec *fwspec =3D dev_iommu_fwspec_get(dev); - struct arm_smmu_master *master; - - if (!fwspec || fwspec->ops !=3D &arm_smmu_ops) - return; - - master =3D dev_iommu_priv_get(dev); - arm_smmu_detach_dev(master); - arm_smmu_disable_pasid(master); - kfree(master); - iommu_fwspec_free(dev); -} - -static struct iommu_group *arm_smmu_device_group(struct device *dev) -{ - struct iommu_group *group; - - /* - * We don't support devices sharing stream IDs other than PCI RID - * aliases, since the necessary ID-to-device lookup becomes rather - * impractical given a potential sparse 32-bit stream ID space. - */ - if (dev_is_pci(dev)) - group =3D pci_device_group(dev); - else - group =3D generic_device_group(dev); - - return group; -} - -static int arm_smmu_domain_get_attr(struct iommu_domain *domain, - enum iommu_attr attr, void *data) -{ - struct arm_smmu_domain *smmu_domain =3D to_smmu_domain(domain); - - switch (domain->type) { - case IOMMU_DOMAIN_UNMANAGED: - switch (attr) { - case DOMAIN_ATTR_NESTING: - *(int *)data =3D (smmu_domain->stage =3D=3D ARM_SMMU_DOMAIN_NESTED); - return 0; - default: - return -ENODEV; - } - break; - case IOMMU_DOMAIN_DMA: - switch (attr) { - case DOMAIN_ATTR_DMA_USE_FLUSH_QUEUE: - *(int *)data =3D smmu_domain->non_strict; - return 0; - default: - return -ENODEV; - } - break; - default: - return -EINVAL; - } -} - -static int arm_smmu_domain_set_attr(struct iommu_domain *domain, - enum iommu_attr attr, void *data) -{ - int ret =3D 0; - struct arm_smmu_domain *smmu_domain =3D to_smmu_domain(domain); - - mutex_lock(&smmu_domain->init_mutex); - - switch (domain->type) { - case IOMMU_DOMAIN_UNMANAGED: - switch (attr) { - case DOMAIN_ATTR_NESTING: - if (smmu_domain->smmu) { - ret =3D -EPERM; - goto out_unlock; - } - - if (*(int *)data) - smmu_domain->stage =3D ARM_SMMU_DOMAIN_NESTED; - else - smmu_domain->stage =3D ARM_SMMU_DOMAIN_S1; - break; - default: - ret =3D -ENODEV; - } - break; - case IOMMU_DOMAIN_DMA: - switch(attr) { - case DOMAIN_ATTR_DMA_USE_FLUSH_QUEUE: - smmu_domain->non_strict =3D *(int *)data; - break; - default: - ret =3D -ENODEV; - } - break; - default: - ret =3D -EINVAL; - } - -out_unlock: - mutex_unlock(&smmu_domain->init_mutex); - return ret; -} - static int arm_smmu_of_xlate(struct device *dev, struct of_phandle_args *a= rgs) { return iommu_fwspec_add_ids(dev, args->args, 1); } =20 -static void arm_smmu_get_resv_regions(struct device *dev, - struct list_head *head) -{ - struct iommu_resv_region *region; - int prot =3D IOMMU_WRITE | IOMMU_NOEXEC | IOMMU_MMIO; - - region =3D iommu_alloc_resv_region(MSI_IOVA_BASE, MSI_IOVA_LENGTH, - prot, IOMMU_RESV_SW_MSI); - if (!region) - return; - - list_add_tail(®ion->list, head); - - iommu_dma_get_resv_regions(dev, head); -} - -static struct iommu_ops arm_smmu_ops =3D { - .capable =3D arm_smmu_capable, - .domain_alloc =3D arm_smmu_domain_alloc, - .domain_free =3D arm_smmu_domain_free, - .attach_dev =3D arm_smmu_attach_dev, - .map =3D arm_smmu_map, - .unmap =3D arm_smmu_unmap, - .flush_iotlb_all =3D arm_smmu_flush_iotlb_all, - .iotlb_sync =3D arm_smmu_iotlb_sync, - .iova_to_phys =3D arm_smmu_iova_to_phys, - .probe_device =3D arm_smmu_probe_device, - .release_device =3D arm_smmu_release_device, - .device_group =3D arm_smmu_device_group, - .domain_get_attr =3D arm_smmu_domain_get_attr, - .domain_set_attr =3D arm_smmu_domain_set_attr, - .of_xlate =3D arm_smmu_of_xlate, - .get_resv_regions =3D arm_smmu_get_resv_regions, - .put_resv_regions =3D generic_iommu_put_resv_regions, - .pgsize_bitmap =3D -1UL, /* Restricted during device attach */ -}; - /* Probing and initialisation functions */ static int arm_smmu_init_one_queue(struct arm_smmu_device *smmu, struct arm_smmu_queue *q, @@ -2929,16 +2596,6 @@ static int arm_smmu_device_hw_probe(struct arm_smmu_= device *smmu) smmu->oas =3D 48; } =20 - if (arm_smmu_ops.pgsize_bitmap =3D=3D -1UL) - arm_smmu_ops.pgsize_bitmap =3D smmu->pgsize_bitmap; - else - arm_smmu_ops.pgsize_bitmap |=3D smmu->pgsize_bitmap; - - /* Set the DMA mask for our table walker */ - if (dma_set_mask_and_coherent(smmu->dev, DMA_BIT_MASK(smmu->oas))) - dev_warn(smmu->dev, - "failed to set DMA mask for table walker\n"); - smmu->ias =3D max(smmu->ias, smmu->oas); =20 dev_info(smmu->dev, "ias %lu-bit, oas %lu-bit (features 0x%08x)\n", @@ -3018,43 +2675,6 @@ static unsigned long arm_smmu_resource_size(struct a= rm_smmu_device *smmu) return SZ_128K; } =20 -static int arm_smmu_set_bus_ops(struct iommu_ops *ops) -{ - int err; - -#ifdef CONFIG_PCI - if (pci_bus_type.iommu_ops !=3D ops) { - err =3D bus_set_iommu(&pci_bus_type, ops); - if (err) - return err; - } -#endif -#ifdef CONFIG_ARM_AMBA - if (amba_bustype.iommu_ops !=3D ops) { - err =3D bus_set_iommu(&amba_bustype, ops); - if (err) - goto err_reset_pci_ops; - } -#endif - if (platform_bus_type.iommu_ops !=3D ops) { - err =3D bus_set_iommu(&platform_bus_type, ops); - if (err) - goto err_reset_amba_ops; - } - - return 0; - -err_reset_amba_ops: -#ifdef CONFIG_ARM_AMBA - bus_set_iommu(&amba_bustype, NULL); -#endif -err_reset_pci_ops: __maybe_unused; -#ifdef CONFIG_PCI - bus_set_iommu(&pci_bus_type, NULL); -#endif - return err; -} - static void __iomem *arm_smmu_ioremap(struct device *dev, resource_size_t = start, resource_size_t size) { @@ -3147,68 +2767,15 @@ static int arm_smmu_device_probe(struct platform_de= vice *pdev) if (ret) return ret; =20 - /* Record our private device structure */ - platform_set_drvdata(pdev, smmu); - /* Reset the device */ ret =3D arm_smmu_device_reset(smmu, bypass); if (ret) return ret; =20 - /* And we're up. Go go go! */ - ret =3D iommu_device_sysfs_add(&smmu->iommu, dev, NULL, - "smmu3.%pa", &ioaddr); - if (ret) - return ret; - - iommu_device_set_ops(&smmu->iommu, &arm_smmu_ops); - iommu_device_set_fwnode(&smmu->iommu, dev->fwnode); - - ret =3D iommu_device_register(&smmu->iommu); - if (ret) { - dev_err(dev, "Failed to register iommu\n"); - return ret; - } - - return arm_smmu_set_bus_ops(&arm_smmu_ops); -} - -static int arm_smmu_device_remove(struct platform_device *pdev) -{ - struct arm_smmu_device *smmu =3D platform_get_drvdata(pdev); - - arm_smmu_set_bus_ops(NULL); - iommu_device_unregister(&smmu->iommu); - iommu_device_sysfs_remove(&smmu->iommu); - arm_smmu_device_disable(smmu); - return 0; } =20 -static void arm_smmu_device_shutdown(struct platform_device *pdev) -{ - arm_smmu_device_remove(pdev); -} - static const struct of_device_id arm_smmu_of_match[] =3D { { .compatible =3D "arm,smmu-v3", }, { }, }; -MODULE_DEVICE_TABLE(of, arm_smmu_of_match); - -static struct platform_driver arm_smmu_driver =3D { - .driver =3D { - .name =3D "arm-smmu-v3", - .of_match_table =3D arm_smmu_of_match, - .suppress_bind_attrs =3D true, - }, - .probe =3D arm_smmu_device_probe, - .remove =3D arm_smmu_device_remove, - .shutdown =3D arm_smmu_device_shutdown, -}; -module_platform_driver(arm_smmu_driver); - -MODULE_DESCRIPTION("IOMMU API for ARM architected SMMUv3 implementations"); -MODULE_AUTHOR("Will Deacon "); -MODULE_ALIAS("platform:arm-smmu-v3"); -MODULE_LICENSE("GPL v2"); --=20 2.17.1