From nobody Mon Feb 9 21:39:56 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1608223776; cv=none; d=zohomail.com; s=zohoarc; b=KUZ2pnKmWW1IIxpM6k2tTKsPf0vQRRUrq2V3aSitHMftEc3uElSYWjh6tsZoi8y4CPjqP5F1AhDvqs9DBaTMUIqhQHGMkyOmOk/GFDwufl2OoRjpsjtsHhuv0UoT/UDS+otCFvlC82qlHTJF/CJLEoFeVYONWS/LFcJbyK+C7Yo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1608223776; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=i8RxqJjKGWFtFvOIyor21oh2DMSr8ty1z2SK646VqCQ=; b=L0eKJjj2om+f0wNNR4aNWGrLjWyaLW/cENxoQHlqCX/6P0L67zGYb2RT0g0zO3IsjebD8HKQ2F2nXS9cohs5jQ/Zx/Olsaerc9TOuISloWVIIx4ezVkI0yC6e9/RZxoPV6SUPy7MIu+q67uHf10A9ss2cSOcnIiTC7YxNHP5Eo4= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1608223776827179.69890260397756; Thu, 17 Dec 2020 08:49:36 -0800 (PST) Received: from list by lists.xenproject.org with outflank-mailman.55982.97694 (Exim 4.92) (envelope-from ) id 1kpvQO-0004M8-8s; Thu, 17 Dec 2020 15:42:40 +0000 Received: by outflank-mailman (output) from mailman id 55982.97694; Thu, 17 Dec 2020 15:42:40 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1kpvQN-0004Lw-WB; Thu, 17 Dec 2020 15:42:40 +0000 Received: by outflank-mailman (input) for mailman id 55982; Thu, 17 Dec 2020 15:42:39 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1kpvQM-0004GE-VT for xen-devel@lists.xenproject.org; Thu, 17 Dec 2020 15:42:39 +0000 Received: from foss.arm.com (unknown [217.140.110.172]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTP id 03bed0a0-1b34-4d46-a2ea-fdd55279b29f; Thu, 17 Dec 2020 15:42:34 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 11B19101E; Thu, 17 Dec 2020 07:42:34 -0800 (PST) Received: from e109506-lin.cambridge.arm.com (e109506-lin.cambridge.arm.com [10.1.199.1]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 5014A3F66B; Thu, 17 Dec 2020 07:42:33 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 03bed0a0-1b34-4d46-a2ea-fdd55279b29f From: Bertrand Marquis To: xen-devel@lists.xenproject.org Cc: Stefano Stabellini , Julien Grall , Volodymyr Babchuk Subject: [PATCH v4 3/8] xen/arm: Add arm64 ID registers definitions Date: Thu, 17 Dec 2020 15:38:03 +0000 Message-Id: <905822b31f5494bf20e1e2a0a56f935db0550aef.1608214355.git.bertrand.marquis@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add coprocessor registers definitions for all ID registers trapped through the TID3 bit of HSR. Those are the one that will be emulated in Xen to only publish to guests the features that are supported by Xen and that are accessible to guests. Signed-off-by: Bertrand Marquis Reviewed-by: Stefano Stabellini --- Changes in V2: Rebase Changes in V3: Add case definition for reserved registers. Changes in V4: Remove case definition for reserved registers and move it to the code directly. --- xen/include/asm-arm/arm64/hsr.h | 37 +++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/xen/include/asm-arm/arm64/hsr.h b/xen/include/asm-arm/arm64/hs= r.h index ca931dd2fe..e691d41c17 100644 --- a/xen/include/asm-arm/arm64/hsr.h +++ b/xen/include/asm-arm/arm64/hsr.h @@ -110,6 +110,43 @@ #define HSR_SYSREG_CNTP_CTL_EL0 HSR_SYSREG(3,3,c14,c2,1) #define HSR_SYSREG_CNTP_CVAL_EL0 HSR_SYSREG(3,3,c14,c2,2) =20 +/* Those registers are used when HCR_EL2.TID3 is set */ +#define HSR_SYSREG_ID_PFR0_EL1 HSR_SYSREG(3,0,c0,c1,0) +#define HSR_SYSREG_ID_PFR1_EL1 HSR_SYSREG(3,0,c0,c1,1) +#define HSR_SYSREG_ID_PFR2_EL1 HSR_SYSREG(3,0,c0,c3,4) +#define HSR_SYSREG_ID_DFR0_EL1 HSR_SYSREG(3,0,c0,c1,2) +#define HSR_SYSREG_ID_DFR1_EL1 HSR_SYSREG(3,0,c0,c3,5) +#define HSR_SYSREG_ID_AFR0_EL1 HSR_SYSREG(3,0,c0,c1,3) +#define HSR_SYSREG_ID_MMFR0_EL1 HSR_SYSREG(3,0,c0,c1,4) +#define HSR_SYSREG_ID_MMFR1_EL1 HSR_SYSREG(3,0,c0,c1,5) +#define HSR_SYSREG_ID_MMFR2_EL1 HSR_SYSREG(3,0,c0,c1,6) +#define HSR_SYSREG_ID_MMFR3_EL1 HSR_SYSREG(3,0,c0,c1,7) +#define HSR_SYSREG_ID_MMFR4_EL1 HSR_SYSREG(3,0,c0,c2,6) +#define HSR_SYSREG_ID_MMFR5_EL1 HSR_SYSREG(3,0,c0,c3,6) +#define HSR_SYSREG_ID_ISAR0_EL1 HSR_SYSREG(3,0,c0,c2,0) +#define HSR_SYSREG_ID_ISAR1_EL1 HSR_SYSREG(3,0,c0,c2,1) +#define HSR_SYSREG_ID_ISAR2_EL1 HSR_SYSREG(3,0,c0,c2,2) +#define HSR_SYSREG_ID_ISAR3_EL1 HSR_SYSREG(3,0,c0,c2,3) +#define HSR_SYSREG_ID_ISAR4_EL1 HSR_SYSREG(3,0,c0,c2,4) +#define HSR_SYSREG_ID_ISAR5_EL1 HSR_SYSREG(3,0,c0,c2,5) +#define HSR_SYSREG_ID_ISAR6_EL1 HSR_SYSREG(3,0,c0,c2,7) +#define HSR_SYSREG_MVFR0_EL1 HSR_SYSREG(3,0,c0,c3,0) +#define HSR_SYSREG_MVFR1_EL1 HSR_SYSREG(3,0,c0,c3,1) +#define HSR_SYSREG_MVFR2_EL1 HSR_SYSREG(3,0,c0,c3,2) + +#define HSR_SYSREG_ID_AA64PFR0_EL1 HSR_SYSREG(3,0,c0,c4,0) +#define HSR_SYSREG_ID_AA64PFR1_EL1 HSR_SYSREG(3,0,c0,c4,1) +#define HSR_SYSREG_ID_AA64DFR0_EL1 HSR_SYSREG(3,0,c0,c5,0) +#define HSR_SYSREG_ID_AA64DFR1_EL1 HSR_SYSREG(3,0,c0,c5,1) +#define HSR_SYSREG_ID_AA64ISAR0_EL1 HSR_SYSREG(3,0,c0,c6,0) +#define HSR_SYSREG_ID_AA64ISAR1_EL1 HSR_SYSREG(3,0,c0,c6,1) +#define HSR_SYSREG_ID_AA64MMFR0_EL1 HSR_SYSREG(3,0,c0,c7,0) +#define HSR_SYSREG_ID_AA64MMFR1_EL1 HSR_SYSREG(3,0,c0,c7,1) +#define HSR_SYSREG_ID_AA64MMFR2_EL1 HSR_SYSREG(3,0,c0,c7,2) +#define HSR_SYSREG_ID_AA64AFR0_EL1 HSR_SYSREG(3,0,c0,c5,4) +#define HSR_SYSREG_ID_AA64AFR1_EL1 HSR_SYSREG(3,0,c0,c5,5) +#define HSR_SYSREG_ID_AA64ZFR0_EL1 HSR_SYSREG(3,0,c0,c4,4) + #endif /* __ASM_ARM_ARM64_HSR_H */ =20 /* --=20 2.17.1