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Mon, 14 Jul 2025 09:02:18 -0700 (PDT) Message-ID: <8c4df1bc-4fdc-4e96-ae67-ea23870d2725@suse.com> Date: Mon, 14 Jul 2025 18:02:10 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird From: Jan Beulich Subject: [PATCH v2] x86emul: adjust BSF/BSR/LZCNT/TZCNT behavior as to EFLAGS To: "xen-devel@lists.xenproject.org" Cc: Andrew Cooper , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= Content-Language: en-US Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @suse.com) X-ZM-MESSAGEID: 1752508959616116600 Content-Type: text/plain; charset="utf-8" SDM revision 087 points out that apparently as of quite some time ago on Intel hardware BSF and BSR may alter all arithmetic flags, not just ZF. Because of the inconsistency (and because documentation doesn't look to be quite right about PF), best we can do is simply take the flag values from what the processor produces, just like we do for various other arithmetic insns. (Note also that AMD and Intel have always been disagreeing on arithmetic flags other than ZF.) To be both safe (against further anomalies) and consistent, extend this to {L,T}ZCNT as well. (Emulating the two insns correctly even when underlying hardware doesn't support it was perhaps nice, but yielded guest-observable inconsistencies.) Signed-off-by: Jan Beulich Reviewed-by: Andrew Cooper --- v2: Use emulate_2op_SrcV_srcmem() also for {L,T}ZCNT. --- a/xen/arch/x86/x86_emulate/x86_emulate.c +++ b/xen/arch/x86/x86_emulate/x86_emulate.c @@ -5270,62 +5270,26 @@ x86_emulate( break; =20 case X86EMUL_OPC(0x0f, 0xbc): /* bsf or tzcnt */ - { - bool zf; - - asm ( "bsf %2,%0" ASM_FLAG_OUT(, "; setz %1") - : "=3Dr" (dst.val), ASM_FLAG_OUT("=3D@ccz", "=3Dqm") (zf) - : "rm" (src.val) ); - _regs.eflags &=3D ~X86_EFLAGS_ZF; - if ( (vex.pfx =3D=3D vex_f3) && vcpu_has_bmi1() ) - { - _regs.eflags &=3D ~X86_EFLAGS_CF; - if ( zf ) - { - _regs.eflags |=3D X86_EFLAGS_CF; - dst.val =3D op_bytes * 8; - } - else if ( !dst.val ) - _regs.eflags |=3D X86_EFLAGS_ZF; - } - else if ( zf ) + if ( vex.pfx =3D=3D vex_f3 ) + emulate_2op_SrcV_srcmem("rep; bsf", src, dst, _regs.eflags); + else { - _regs.eflags |=3D X86_EFLAGS_ZF; - dst.type =3D OP_NONE; + emulate_2op_SrcV_srcmem("bsf", src, dst, _regs.eflags); + if ( _regs.eflags & X86_EFLAGS_ZF ) + dst.type =3D OP_NONE; } break; - } =20 case X86EMUL_OPC(0x0f, 0xbd): /* bsr or lzcnt */ - { - bool zf; - - asm ( "bsr %2,%0" ASM_FLAG_OUT(, "; setz %1") - : "=3Dr" (dst.val), ASM_FLAG_OUT("=3D@ccz", "=3Dqm") (zf) - : "rm" (src.val) ); - _regs.eflags &=3D ~X86_EFLAGS_ZF; - if ( (vex.pfx =3D=3D vex_f3) && vcpu_has_lzcnt() ) - { - _regs.eflags &=3D ~X86_EFLAGS_CF; - if ( zf ) - { - _regs.eflags |=3D X86_EFLAGS_CF; - dst.val =3D op_bytes * 8; - } - else - { - dst.val =3D op_bytes * 8 - 1 - dst.val; - if ( !dst.val ) - _regs.eflags |=3D X86_EFLAGS_ZF; - } - } - else if ( zf ) + if ( vex.pfx =3D=3D vex_f3 ) + emulate_2op_SrcV_srcmem("rep; bsr", src, dst, _regs.eflags); + else { - _regs.eflags |=3D X86_EFLAGS_ZF; - dst.type =3D OP_NONE; + emulate_2op_SrcV_srcmem("bsr", src, dst, _regs.eflags); + if ( _regs.eflags & X86_EFLAGS_ZF ) + dst.type =3D OP_NONE; } break; - } =20 case X86EMUL_OPC(0x0f, 0xbe): /* movsx rm8,r{16,32,64} */ /* Recompute DstReg as we may have decoded AH/BH/CH/DH. */