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Wed, 17 Sep 2025 14:55:58 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Alistair Francis , Bob Eshleman , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH v4 06/18] xen/riscv: introduce pte_{set,get}_mfn() Date: Wed, 17 Sep 2025 23:55:26 +0200 Message-ID: <88bac831f9d1dddd1186179f8fa6fbb44a07dd35.1758145428.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1758146185513116600 Content-Type: text/plain; charset="utf-8" Introduce helpers pte_{set,get}_mfn() to simplify setting and getting of mfn. Also, introduce PTE_PPN_MASK and add BUILD_BUG_ON() to be sure that PTE_PPN_MASK remains the same for all MMU modes except Sv32. Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich --- Changes in V4: - Nothing changed. Only Rebase. --- Changes in V3: - Add Acked-by: Jan Beulich . --- Changes in V2: - Patch "[PATCH v1 4/6] xen/riscv: define pt_t and pt_walk_t structures" w= as renamed to xen/riscv: introduce pte_{set,get}_mfn() as after dropping of bitfields for PTE structure, this patch introduce only pte_{set,get}_mfn= (). - As pt_t and pt_walk_t were dropped, update implementation of pte_{set,get}_mfn() to use bit operations and shifts instead of bitfield= s. - Introduce PTE_PPN_MASK to be able to use MASK_INSR for setting/getting P= PN. - Add BUILD_BUG_ON(RV_STAGE1_MODE > SATP_MODE_SV57) to be sure that when new MMU mode will be added, someone checks that PPN is still bits 53:10. --- xen/arch/riscv/include/asm/page.h | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/xen/arch/riscv/include/asm/page.h b/xen/arch/riscv/include/asm= /page.h index ddcc4da0a3..66cb192316 100644 --- a/xen/arch/riscv/include/asm/page.h +++ b/xen/arch/riscv/include/asm/page.h @@ -112,6 +112,30 @@ typedef struct { #endif } pte_t; =20 +#if RV_STAGE1_MODE !=3D SATP_MODE_SV32 +#define PTE_PPN_MASK _UL(0x3FFFFFFFFFFC00) +#else +#define PTE_PPN_MASK _U(0xFFFFFC00) +#endif + +static inline void pte_set_mfn(pte_t *p, mfn_t mfn) +{ + /* + * At the moment spec provides Sv32 - Sv57. + * If one day new MMU mode will be added it will be needed + * to check that PPN mask still continue to cover bits 53:10. + */ + BUILD_BUG_ON(RV_STAGE1_MODE > SATP_MODE_SV57); + + p->pte &=3D ~PTE_PPN_MASK; + p->pte |=3D MASK_INSR(mfn_x(mfn), PTE_PPN_MASK); +} + +static inline mfn_t pte_get_mfn(pte_t p) +{ + return _mfn(MASK_EXTR(p.pte, PTE_PPN_MASK)); +} + static inline bool pte_is_valid(pte_t p) { return p.pte & PTE_VALID; --=20 2.51.0