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Wed, 05 Jun 2024 09:55:07 -0700 (PDT) From: milandjokic1995@gmail.com To: xen-devel@lists.xenproject.org Cc: milan.djokic@rt-rk.com, Nikola Jelic , Alistair Francis , Bob Eshleman , Connor Davis , Andrew Cooper , George Dunlap , Jan Beulich , Julien Grall , Stefano Stabellini , Wei Liu Subject: [PATCH] xen/riscv: PE/COFF image header for RISC-V target Date: Wed, 5 Jun 2024 18:54:43 +0200 Message-Id: <87b5e458498bbff2e54ac011a50ff1f9555c3613.1717354932.git.milan.djokic@rt-rk.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1717626207258100001 Content-Type: text/plain; charset="utf-8" From: Nikola Jelic Extended RISC-V xen image with PE/COFF headers, in order to support xen boot from popular bootloaders like U-boot. Image header is optionally included (with CONFIG_RISCV_EFI) so both plain ELF and image with PE/COFF header can now be generated as build = artifacts. Tested on both QEMU and StarFive VisionFive 2 with OpenSBI->U-Boot->xen->do= m0 boot chain. Signed-off-by: Nikola Jelic --- xen/arch/riscv/Kconfig | 9 +++++ xen/arch/riscv/include/asm/image.h | 62 ++++++++++++++++++++++++++++++ xen/arch/riscv/riscv64/head.S | 33 +++++++++++++++- 3 files changed, 103 insertions(+), 1 deletion(-) create mode 100644 xen/arch/riscv/include/asm/image.h diff --git a/xen/arch/riscv/Kconfig b/xen/arch/riscv/Kconfig index f382b36f6c..59bf5aa2a6 100644 --- a/xen/arch/riscv/Kconfig +++ b/xen/arch/riscv/Kconfig @@ -9,6 +9,15 @@ config ARCH_DEFCONFIG string default "arch/riscv/configs/tiny64_defconfig" =20 +config RISCV_EFI + bool "UEFI boot service support" + depends on RISCV_64 + default n + help + This option provides support for boot services through + UEFI firmware. A UEFI stub is provided to allow Xen to + be booted as an EFI application. + menu "Architecture Features" =20 source "arch/Kconfig" diff --git a/xen/arch/riscv/include/asm/image.h b/xen/arch/riscv/include/as= m/image.h new file mode 100644 index 0000000000..b379246290 --- /dev/null +++ b/xen/arch/riscv/include/asm/image.h @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + + +#ifndef _ASM_RISCV_IMAGE_H +#define _ASM_RISCV_IMAGE_H + +#define RISCV_IMAGE_MAGIC "RISCV\0\0\0" +#define RISCV_IMAGE_MAGIC2 "RSC\x05" + +#define RISCV_IMAGE_FLAG_BE_SHIFT 0 +#define RISCV_IMAGE_FLAG_BE_MASK 0x1 + +#define RISCV_IMAGE_FLAG_LE 0 +#define RISCV_IMAGE_FLAG_BE 1 + +#ifdef CONFIG_CPU_BIG_ENDIAN +#error conversion of header fields to LE not yet implemented +#else +#define __HEAD_FLAG_BE RISCV_IMAGE_FLAG_LE +#endif + +#define __HEAD_FLAG(field) (__HEAD_FLAG_##field << \ + RISCV_IMAGE_FLAG_##field##_SHIFT) + +#define __HEAD_FLAGS (__HEAD_FLAG(BE)) + +#define RISCV_HEADER_VERSION_MAJOR 0 +#define RISCV_HEADER_VERSION_MINOR 2 + +#define RISCV_HEADER_VERSION (RISCV_HEADER_VERSION_MAJOR << 16 | \ + RISCV_HEADER_VERSION_MINOR) + +#ifndef __ASSEMBLY__ +/* + * struct riscv_image_header - riscv xen image header + * + * @code0: Executable code + * @code1: Executable code + * @text_offset: Image load offset + * @image_size: Effective Image size + * @reserved: reserved + * @reserved: reserved + * @reserved: reserved + * @magic: Magic number + * @reserved: reserved + * @reserved: reserved (will be used for PE COFF offset) + */ + +struct riscv_image_header { + u32 code0; + u32 code1; + u64 text_offset; + u64 image_size; + u64 res1; + u64 res2; + u64 res3; + u64 magic; + u32 res4; + u32 res5; +}; +#endif /* __ASSEMBLY__ */ +#endif /* __ASM_IMAGE_H */ diff --git a/xen/arch/riscv/riscv64/head.S b/xen/arch/riscv/riscv64/head.S index 3261e9fce8..0edd35b20f 100644 --- a/xen/arch/riscv/riscv64/head.S +++ b/xen/arch/riscv/riscv64/head.S @@ -1,14 +1,40 @@ #include #include +#include =20 .section .text.header, "ax", %progbits =20 /* * OpenSBI pass to start(): * a0 -> hart_id ( bootcpu_id ) - * a1 -> dtb_base=20 + * a1 -> dtb_base */ FUNC(start) +#ifdef CONFIG_RISCV_EFI + j xen_start + + /* ----------- Header -------------- */ + .word 0 + .balign 8 +#if __riscv_xlen =3D=3D 64 + /* Image load offset(2MB) from start of RAM */ + .dword 0x200000 +#else + /* Image load offset(4MB) from start of RAM */ + .dword 0x400000 +#endif + /* Effective size of xen image */ + .dword _end - _start + .dword __HEAD_FLAGS + .word RISCV_HEADER_VERSION + .word 0 + .dword 0 + .ascii RISCV_IMAGE_MAGIC + .balign 4 + .ascii RISCV_IMAGE_MAGIC2 + +FUNC(xen_start) +#endif /* Mask all interrupts */ csrw CSR_SIE, zero =20 @@ -60,6 +86,11 @@ FUNC(start) mv a1, s1 =20 tail start_xen + +#ifdef CONFIG_RISCV_EFI +END(xen_start) +#endif + END(start) =20 .section .text, "ax", %progbits --=20 2.25.1