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[109.243.67.101]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-485359bf807sm119619845e9.2.2026.03.10.10.09.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Mar 2026 10:09:25 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: e4b15c46-1ca3-11f1-9ccf-f158ae23cfc8 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1773162566; x=1773767366; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wy9UOUys3UP8UGf9H+CdlAJHj+mjN4CkBQ2c+J9DOhU=; b=eNkH5XxLel6q25erVdnuA/b+IoXyWg4q/2/UpEnkdLsPiMKy/4uu2H4blxnTOeL43u mvi9c5fS6pjKKLKoe0XSZOP2XkWZajy6qsALKX6kRK239LJgbNrv2B1iPwCOHdE7ublF ERA6JBJlI9lDkC5G3LpJwJkopK1TSvZlV52/HKToY9qbB9hoKHnK1uM1vc20MS8iMLo6 5C/wve2g6jX4zePoPLBfUafAjkobFF8FRsB4ALCyqDA+VvmhIfx50V+hrw+eprrVcIhq 1zZ6wQOWPwSWMqDsTFOZN4fLNkC6oztnWRPWpKX8OZ8hX1T0GLI4Y8UJa6GKT+28Oc/S L0Sg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1773162566; x=1773767366; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=wy9UOUys3UP8UGf9H+CdlAJHj+mjN4CkBQ2c+J9DOhU=; b=rP8cj9b6+erkrcpdNfhnebUHne8iCqDDYTPebTNEgXIr6ux/5Rp4i3MuLhax1VvblO VNqB1pYEGX35DSyGaIaZYswv+X7Est5Gvq31fSxzx8Z2I70MDDlG9vs3Mg2QalCiPfgV SLSLyVsVkVaG+i1DUaqG6DN2dnIlIxprpLxaSSr3MJwRfql/n38eCBq59LEPvHmcZZr4 2PWIwfDXi0QhjQjxovTSgAAuY5Z7Nqa4mkyWYDd8zWx2jlTI+yyuWuhd1RxyGjcXiqPx ae1kNGDUuP4DOUsU8O+lHtMNs7iwhWXCH6gK/+MHcaU4J4mw+yJHg/+1v7XEvA6kYj+d tG8g== X-Gm-Message-State: AOJu0YwImh8gYk4S0YGZUZflFVnvkN+QrS+dIp71TiOG9Yx/u8GHiw+Z QfI7M5WJbHt/9YqM/4AFAPuR70t2/TTL6wQmYtBLEI6/diQCzTQFMzTpUs+dRqLd X-Gm-Gg: ATEYQzw+hsVIW+JvFrgEPa5FNJbhVxpwf2mJyqWdudyAArZjP/Kj0lFee4OPv61EX6E MjHmx4znsP/aTt8ipilMoPHMW3nbhFxTNEaNguLdVeQAS4DruLv6yE0hlFu54sALeyvRKns0r5C 4qpKfoC0u5JrNH94skM6yEccPHLC3ehV+ybPX4hZ1mcBA2MZOW/b85L9eRpyq0X1xAo1VRCIoc8 JJ9O/VFEc97tdRSWslN+B3/VSicV/7yJtcUN7UNzlgsntRVe/RieElmG9zvqUzZg8ibLcKHi/LK dd4LkFxhhviS4Dp96NEDFiMfIUsTkfmwvraln2nH8QchyUz5YWB8O1xXyT+yq9gMMRrOpUR7xmr F9sPkLqYkBDhGSLlh0mjPpca6Lr4vcE6yht5RMXMQ9sEcSoBqfwItUeYs1BF3VN+sglHHVNLjEb TNWk2ZeY11fpiBjaRMwPZLggi/ojPz8SHpgpjlZpRqaR+i3gvVPNaLta90smBxT/KqIQ== X-Received: by 2002:a05:600c:3b89:b0:485:3f1c:d8a4 with SMTP id 5b1f17b1804b1-4853f1cda4cmr106634755e9.9.1773162566012; Tue, 10 Mar 2026 10:09:26 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Romain Caritey , Oleksii Kurochko , Alistair Francis , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH v1 14/27] xen/riscv: introduce per-vCPU IMSIC state Date: Tue, 10 Mar 2026 18:08:47 +0100 Message-ID: <8196fa8f000e384af697a44cb3d50ece966e82a7.1773157782.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1773163065090154100 Content-Type: text/plain; charset="utf-8" Each vCPU interacting with the IMSIC requires state to track the associated guest interrupt file and its backing context. Introduce a per-vCPU structure to hold IMSIC-related state, including the guest interrupt file identifier and the CPU providing the backing VS-file. Access to the guest file identifier is protected by a lock. Initialize this structure during vCPU setup and store it in arch_vcpu. The initial state marks the VS-file as software-backed until it becomes associated with a physical CPU. Add helpers to retrieve and update the guest interrupt file identifier. Signed-off-by: Oleksii Kurochko --- xen/arch/riscv/imsic.c | 42 +++++++++++++++++++++++++++++ xen/arch/riscv/include/asm/domain.h | 2 ++ xen/arch/riscv/include/asm/imsic.h | 17 ++++++++++++ 3 files changed, 61 insertions(+) diff --git a/xen/arch/riscv/imsic.c b/xen/arch/riscv/imsic.c index 0956b187705f..bbadbdf352a1 100644 --- a/xen/arch/riscv/imsic.c +++ b/xen/arch/riscv/imsic.c @@ -59,6 +59,29 @@ do { \ csr_clear(CSR_SIREG, v); \ } while (0) =20 +unsigned int vcpu_guest_file_id(const struct vcpu *v) +{ + struct imsic_state *imsic_state =3D v->arch.imsic_state; + unsigned long flags; + unsigned int vsfile_id; + + read_lock_irqsave(&imsic_state->vsfile_lock, flags); + vsfile_id =3D imsic_state->guest_file_id; + read_unlock_irqrestore(&imsic_state->vsfile_lock, flags); + + return vsfile_id; +} + +void imsic_set_guest_file_id(const struct vcpu *v, unsigned int guest_file= _id) +{ + struct imsic_state *imsic_state =3D v->arch.imsic_state; + unsigned long flags; + + write_lock_irqsave(&imsic_state->vsfile_lock, flags); + imsic_state->guest_file_id =3D guest_file_id; + write_unlock_irqrestore(&imsic_state->vsfile_lock, flags); +} + void __init imsic_ids_local_delivery(bool enable) { if ( enable ) @@ -315,6 +338,25 @@ static int imsic_parse_node(const struct dt_device_nod= e *node, return 0; } =20 +int __init vcpu_imsic_init(struct vcpu *v) +{ + struct imsic_state *imsic_state; + + /* Allocate IMSIC context */ + imsic_state =3D xvzalloc(struct imsic_state); + if ( !imsic_state ) + return -ENOMEM; + + v->arch.imsic_state =3D imsic_state; + + /* Setup IMSIC context */ + rwlock_init(&imsic_state->vsfile_lock); + + imsic_state->guest_file_id =3D imsic_state->vsfile_pcpu =3D NR_CPUS; + + return 0; +} + /* * Initialize the imsic_cfg structure based on the IMSIC DT node. * diff --git a/xen/arch/riscv/include/asm/domain.h b/xen/arch/riscv/include/a= sm/domain.h index 506365f199c7..bdb1ffd748c9 100644 --- a/xen/arch/riscv/include/asm/domain.h +++ b/xen/arch/riscv/include/asm/domain.h @@ -52,6 +52,8 @@ struct arch_vcpu { =20 struct vtimer vtimer; =20 + struct imsic_state *imsic_state; + register_t hcounteren; register_t hedeleg; register_t hideleg; diff --git a/xen/arch/riscv/include/asm/imsic.h b/xen/arch/riscv/include/as= m/imsic.h index a63d56fbd5d9..13a563dce066 100644 --- a/xen/arch/riscv/include/asm/imsic.h +++ b/xen/arch/riscv/include/asm/imsic.h @@ -11,6 +11,7 @@ #ifndef ASM_RISCV_IMSIC_H #define ASM_RISCV_IMSIC_H =20 +#include #include #include #include @@ -64,8 +65,20 @@ struct imsic_config { spinlock_t lock; }; =20 +struct imsic_state { + /* IMSIC VS-file */ + rwlock_t vsfile_lock; + unsigned int guest_file_id; + /* + * (vsfile_pcpu >=3D 0) =3D> h/w IMSIC VS-file + * (vsfile_pcpu =3D=3D NR_CPUS) =3D> s/w IMSIC SW-file + */ + unsigned long vsfile_pcpu; +}; + struct dt_device_node; struct kernel_info; +struct vcpu; =20 int imsic_init(const struct dt_device_node *node); =20 @@ -78,4 +91,8 @@ void imsic_ids_local_delivery(bool enable); =20 int imsic_make_dt_node(const struct kernel_info *kinfo); =20 +int vcpu_imsic_init(struct vcpu *v); +unsigned int vcpu_guest_file_id(const struct vcpu *v); +void imsic_set_guest_file_id(const struct vcpu *v, unsigned int guest_file= _id); + #endif /* ASM_RISCV_IMSIC_H */ --=20 2.53.0