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charset="utf-8" While already the case for PVH, there's no reason to treat PV differently here, though of course the addresses get taken from another source in this case. Except that, to match CPU side mappings, by default we permit r/o ones. This then also means we now deal consistently with IO-APICs whose MMIO is or is not covered by E820 reserved regions. Signed-off-by: Jan Beulich Reviewed-by: Roger Pau Monn=C3=A9 --- v5: Extend to also cover e.g. HPET, which in turn means explicitly excluding PCI MMCFG ranges. [integrated] v1: Integrate into series. [standalone] v2: Keep IOMMU mappings in sync with CPU ones. --- a/xen/drivers/passthrough/x86/iommu.c +++ b/xen/drivers/passthrough/x86/iommu.c @@ -13,6 +13,7 @@ */ =20 #include +#include #include #include #include @@ -275,12 +276,12 @@ void iommu_identity_map_teardown(struct } } =20 -static bool __hwdom_init hwdom_iommu_map(const struct domain *d, - unsigned long pfn, - unsigned long max_pfn) +static unsigned int __hwdom_init hwdom_iommu_map(const struct domain *d, + unsigned long pfn, + unsigned long max_pfn) { mfn_t mfn =3D _mfn(pfn); - unsigned int i, type; + unsigned int i, type, perms =3D IOMMUF_readable | IOMMUF_writable; =20 /* * Set up 1:1 mapping for dom0. Default to include only conventional R= AM @@ -289,44 +290,75 @@ static bool __hwdom_init hwdom_iommu_map * that fall in unusable ranges for PV Dom0. */ if ( (pfn > max_pfn && !mfn_valid(mfn)) || xen_in_range(pfn) ) - return false; + return 0; =20 switch ( type =3D page_get_ram_type(mfn) ) { case RAM_TYPE_UNUSABLE: - return false; + return 0; =20 case RAM_TYPE_CONVENTIONAL: if ( iommu_hwdom_strict ) - return false; + return 0; break; =20 default: if ( type & RAM_TYPE_RESERVED ) { if ( !iommu_hwdom_inclusive && !iommu_hwdom_reserved ) - return false; + perms =3D 0; } - else if ( is_hvm_domain(d) || !iommu_hwdom_inclusive || pfn > max_= pfn ) - return false; + else if ( is_hvm_domain(d) ) + return 0; + else if ( !iommu_hwdom_inclusive || pfn > max_pfn ) + perms =3D 0; } =20 /* Check that it doesn't overlap with the Interrupt Address Range. */ if ( pfn >=3D 0xfee00 && pfn <=3D 0xfeeff ) - return false; + return 0; /* ... or the IO-APIC */ - for ( i =3D 0; has_vioapic(d) && i < d->arch.hvm.nr_vioapics; i++ ) - if ( pfn =3D=3D PFN_DOWN(domain_vioapic(d, i)->base_address) ) - return false; + if ( has_vioapic(d) ) + { + for ( i =3D 0; i < d->arch.hvm.nr_vioapics; i++ ) + if ( pfn =3D=3D PFN_DOWN(domain_vioapic(d, i)->base_address) ) + return 0; + } + else if ( is_pv_domain(d) ) + { + /* + * Be consistent with CPU mappings: Dom0 is permitted to establish= r/o + * ones there (also for e.g. HPET in certain cases), so it should = also + * have such established for IOMMUs. + */ + if ( iomem_access_permitted(d, pfn, pfn) && + rangeset_contains_singleton(mmio_ro_ranges, pfn) ) + perms =3D IOMMUF_readable; + } /* * ... or the PCIe MCFG regions. * TODO: runtime added MMCFG regions are not checked to make sure they * don't overlap with already mapped regions, thus preventing trapping. */ if ( has_vpci(d) && vpci_is_mmcfg_address(d, pfn_to_paddr(pfn)) ) - return false; + return 0; + else if ( is_pv_domain(d) ) + { + /* + * Don't extend consistency with CPU mappings to PCI MMCFG regions. + * These shouldn't be accessed via DMA by devices. + */ + const struct acpi_mcfg_allocation *cfg =3D pci_mmcfg_config; + + for ( i =3D 0; i < pci_mmcfg_config_num; ++i, ++cfg ) + if ( pfn >=3D PFN_DOWN(cfg->address) + PCI_BDF(cfg->start_bus_= number, + 0, 0) && + pfn <=3D PFN_DOWN(cfg->address) + PCI_BDF(cfg->end_bus_nu= mber, + ~0, ~0)) + return 0; + } =20 - return true; + return perms; } =20 void __hwdom_init arch_iommu_hwdom_init(struct domain *d) @@ -368,15 +400,19 @@ void __hwdom_init arch_iommu_hwdom_init( for ( ; i < top; i++ ) { unsigned long pfn =3D pdx_to_pfn(i); + unsigned int perms =3D hwdom_iommu_map(d, pfn, max_pfn); int rc; =20 - if ( !hwdom_iommu_map(d, pfn, max_pfn) ) + if ( !perms ) rc =3D 0; else if ( paging_mode_translate(d) ) - rc =3D p2m_add_identity_entry(d, pfn, p2m_access_rw, 0); + rc =3D p2m_add_identity_entry(d, pfn, + perms & IOMMUF_writable ? p2m_acce= ss_rw + : p2m_acce= ss_r, + 0); else rc =3D iommu_map(d, _dfn(pfn), _mfn(pfn), 1ul << PAGE_ORDER_4K, - IOMMUF_readable | IOMMUF_writable, &flush_flags= ); + perms, &flush_flags); =20 if ( rc ) printk(XENLOG_WARNING "%pd: identity %smapping of %lx failed: = %d\n", From nobody Sat May 18 08:14:11 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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charset="utf-8" For large page mappings to be easily usable (i.e. in particular without un-shattering of smaller page mappings) and for mapping operations to then also be more efficient, pass batches of Dom0 memory to iommu_map(). In dom0_construct_pv() and its helpers (covering strict mode) this additionally requires establishing the type of those pages (albeit with zero type references). The earlier establishing of PGT_writable_page | PGT_validated requires the existing places where this gets done (through get_page_and_type()) to be updated: For pages which actually have a mapping, the type refcount needs to be 1. There is actually a related bug that gets fixed here as a side effect: Typically the last L1 table would get marked as such only after get_page_and_type(..., PGT_writable_page). While this is fine as far as refcounting goes, the page did remain mapped in the IOMMU in this case (when "iommu=3Ddom0-strict"). Signed-off-by: Jan Beulich Acked-by: Roger Pau Monn=C3=A9 --- Subsequently p2m_add_identity_entry() may want to also gain an order parameter, for arch_iommu_hwdom_init() to use. While this only affects non-RAM regions, systems typically have 2-16Mb of reserved space immediately below 4Gb, which hence could be mapped more efficiently. Eventually we may want to overhaul this logic to use a rangeset based approach instead, punching holes into originally uniformly large-page- mapped regions. Doing so right here would first and foremost be yet more of a change. The installing of zero-ref writable types has in fact shown (observed while putting together the change) that despite the intention by the XSA-288 changes (affecting DomU-s only) for Dom0 a number of sufficiently ordinary pages (at the very least initrd and P2M ones as well as pages that are part of the initial allocation but not part of the initial mapping) still have been starting out as PGT_none, meaning that they would have gained IOMMU mappings only the first time these pages would get mapped writably. Consequently an open question is whether iommu_memory_setup() should set the pages to PGT_writable_page independent of need_iommu_pt_sync(). I didn't think I need to address the bug mentioned in the description in a separate (prereq) patch, but if others disagree I could certainly break out that part (needing to first use iommu_legacy_unmap() then). Note that 4k P2M pages don't get (pre-)mapped in setup_pv_physmap(): They'll end up mapped via the later get_page_and_type(). As to the way these refs get installed: I've chosen to avoid the more expensive {get,put}_page_and_type(), favoring to put in place the intended type directly. I guess I could be convinced to avoid this bypassing of the actual logic; I merely think it's unnecessarily expensive. Note also that strictly speaking the iommu_iotlb_flush_all() here (as well as the pre-existing one in arch_iommu_hwdom_init()) shouldn't be needed: Actual hooking up (AMD) or enabling of translation (VT-d) occurs only afterwards anyway, so nothing can have made it into TLBs just yet. --- v3: Fold iommu_map() into (the now renamed) iommu_memory_setup(). Move iommu_unmap() into mark_pv_pt_pages_rdonly(). Adjust (split) log message in arch_iommu_hwdom_init(). --- a/xen/arch/x86/pv/dom0_build.c +++ b/xen/arch/x86/pv/dom0_build.c @@ -46,7 +46,8 @@ void __init dom0_update_physmap(bool com static __init void mark_pv_pt_pages_rdonly(struct domain *d, l4_pgentry_t *l4start, unsigned long vpt_start, - unsigned long nr_pt_pages) + unsigned long nr_pt_pages, + unsigned int *flush_flags) { unsigned long count; struct page_info *page; @@ -71,6 +72,14 @@ static __init void mark_pv_pt_pages_rdon ASSERT((page->u.inuse.type_info & PGT_type_mask) <=3D PGT_root_pag= e_table); ASSERT(!(page->u.inuse.type_info & ~(PGT_type_mask | PGT_pae_xen_l= 2))); =20 + /* + * Page table pages need to be removed from the IOMMU again in case + * iommu_memory_setup() ended up mapping them. + */ + if ( need_iommu_pt_sync(d) && + iommu_unmap(d, _dfn(mfn_x(page_to_mfn(page))), 1, flush_flags= ) ) + BUG(); + /* Read-only mapping + PGC_allocated + page-table page. */ page->count_info =3D PGC_allocated | 3; page->u.inuse.type_info |=3D PGT_validated | 1; @@ -107,11 +116,43 @@ static __init void mark_pv_pt_pages_rdon unmap_domain_page(pl3e); } =20 +static void __init iommu_memory_setup(struct domain *d, const char *what, + struct page_info *page, unsigned lon= g nr, + unsigned int *flush_flags) +{ + int rc; + mfn_t mfn =3D page_to_mfn(page); + + if ( !need_iommu_pt_sync(d) ) + return; + + rc =3D iommu_map(d, _dfn(mfn_x(mfn)), mfn, nr, + IOMMUF_readable | IOMMUF_writable, flush_flags); + if ( rc ) + { + printk(XENLOG_ERR "pre-mapping %s MFN [%lx,%lx) into IOMMU failed:= %d\n", + what, mfn_x(mfn), mfn_x(mfn) + nr, rc); + return; + } + + /* + * For successfully established IOMMU mappings the type of the page(s) + * needs to match (for _get_page_type() to unmap upon type change). Set + * the page(s) to writable with no type ref. + */ + for ( ; nr--; ++page ) + { + ASSERT(!page->u.inuse.type_info); + page->u.inuse.type_info =3D PGT_writable_page | PGT_validated; + } +} + static __init void setup_pv_physmap(struct domain *d, unsigned long pgtbl_= pfn, unsigned long v_start, unsigned long v= _end, unsigned long vphysmap_start, unsigned long vphysmap_end, - unsigned long nr_pages) + unsigned long nr_pages, + unsigned int *flush_flags) { struct page_info *page =3D NULL; l4_pgentry_t *pl4e, *l4start =3D map_domain_page(_mfn(pgtbl_pfn)); @@ -177,6 +218,10 @@ static __init void setup_pv_physmap(stru L3_PAGETABLE_SHIFT - PAGE_SHI= FT, MEMF_no_scrub)) !=3D NULL ) { + iommu_memory_setup(d, "P2M 1G", page, + SUPERPAGE_PAGES * SUPERPAGE_PAGES, + flush_flags); + *pl3e =3D l3e_from_page(page, L1_PROT|_PAGE_DIRTY|_PAGE_PS= E); vphysmap_start +=3D 1UL << L3_PAGETABLE_SHIFT; continue; @@ -203,6 +248,9 @@ static __init void setup_pv_physmap(stru L2_PAGETABLE_SHIFT - PAGE_SHI= FT, MEMF_no_scrub)) !=3D NULL ) { + iommu_memory_setup(d, "P2M 2M", page, SUPERPAGE_PAGES, + flush_flags); + *pl2e =3D l2e_from_page(page, L1_PROT|_PAGE_DIRTY|_PAGE_PS= E); vphysmap_start +=3D 1UL << L2_PAGETABLE_SHIFT; continue; @@ -311,6 +359,7 @@ int __init dom0_construct_pv(struct doma unsigned long initrd_pfn =3D -1, initrd_mfn =3D 0; unsigned long count; struct page_info *page =3D NULL; + unsigned int flush_flags =3D 0; start_info_t *si; struct vcpu *v =3D d->vcpu[0]; void *image_base =3D bootstrap_map(image); @@ -573,6 +622,9 @@ int __init dom0_construct_pv(struct doma BUG(); } initrd->mod_end =3D 0; + + iommu_memory_setup(d, "initrd", mfn_to_page(_mfn(initrd_mfn)), + PFN_UP(initrd_len), &flush_flags); } =20 printk("PHYSICAL MEMORY ARRANGEMENT:\n" @@ -606,6 +658,13 @@ int __init dom0_construct_pv(struct doma =20 process_pending_softirqs(); =20 + /* + * Map the full range here and then punch holes for page tables + * alongside marking them as such in mark_pv_pt_pages_rdonly(). + */ + iommu_memory_setup(d, "init-alloc", mfn_to_page(_mfn(alloc_spfn)), + alloc_epfn - alloc_spfn, &flush_flags); + mpt_alloc =3D (vpt_start - v_start) + pfn_to_paddr(alloc_spfn); if ( vinitrd_start ) mpt_alloc -=3D PAGE_ALIGN(initrd_len); @@ -690,7 +749,8 @@ int __init dom0_construct_pv(struct doma l1tab++; =20 page =3D mfn_to_page(_mfn(mfn)); - if ( !page->u.inuse.type_info && + if ( (!page->u.inuse.type_info || + page->u.inuse.type_info =3D=3D (PGT_writable_page | PGT_vali= dated)) && !get_page_and_type(page, d, PGT_writable_page) ) BUG(); } @@ -719,7 +779,7 @@ int __init dom0_construct_pv(struct doma } =20 /* Pages that are part of page tables must be read only. */ - mark_pv_pt_pages_rdonly(d, l4start, vpt_start, nr_pt_pages); + mark_pv_pt_pages_rdonly(d, l4start, vpt_start, nr_pt_pages, &flush_fla= gs); =20 /* Mask all upcalls... */ for ( i =3D 0; i < XEN_LEGACY_MAX_VCPUS; i++ ) @@ -794,7 +854,7 @@ int __init dom0_construct_pv(struct doma { pfn =3D pagetable_get_pfn(v->arch.guest_table); setup_pv_physmap(d, pfn, v_start, v_end, vphysmap_start, vphysmap_= end, - nr_pages); + nr_pages, &flush_flags); } =20 /* Write the phys->machine and machine->phys table entries. */ @@ -825,7 +885,9 @@ int __init dom0_construct_pv(struct doma if ( get_gpfn_from_mfn(mfn) >=3D count ) { BUG_ON(compat); - if ( !page->u.inuse.type_info && + if ( (!page->u.inuse.type_info || + page->u.inuse.type_info =3D=3D (PGT_writable_page | + PGT_validated)) && !get_page_and_type(page, d, PGT_writable_page) ) BUG(); =20 @@ -841,8 +903,12 @@ int __init dom0_construct_pv(struct doma #endif while ( pfn < nr_pages ) { - if ( (page =3D alloc_chunk(d, nr_pages - domain_tot_pages(d))) =3D= =3D NULL ) + count =3D domain_tot_pages(d); + if ( (page =3D alloc_chunk(d, nr_pages - count)) =3D=3D NULL ) panic("Not enough RAM for DOM0 reservation\n"); + + iommu_memory_setup(d, "chunk", page, domain_tot_pages(d) - count, + &flush_flags); while ( pfn < domain_tot_pages(d) ) { mfn =3D mfn_x(page_to_mfn(page)); @@ -857,6 +923,10 @@ int __init dom0_construct_pv(struct doma } } =20 + /* Use while() to avoid compiler warning. */ + while ( iommu_iotlb_flush_all(d, flush_flags) ) + break; + if ( initrd_len !=3D 0 ) { si->mod_start =3D vinitrd_start ?: initrd_pfn; --- a/xen/drivers/passthrough/x86/iommu.c +++ b/xen/drivers/passthrough/x86/iommu.c @@ -363,8 +363,8 @@ static unsigned int __hwdom_init hwdom_i =20 void __hwdom_init arch_iommu_hwdom_init(struct domain *d) { - unsigned long i, top, max_pfn; - unsigned int flush_flags =3D 0; + unsigned long i, top, max_pfn, start, count; + unsigned int flush_flags =3D 0, start_perms =3D 0; =20 BUG_ON(!is_hardware_domain(d)); =20 @@ -395,9 +395,9 @@ void __hwdom_init arch_iommu_hwdom_init( * First Mb will get mapped in one go by pvh_populate_p2m(). Avoid * setting up potentially conflicting mappings here. */ - i =3D paging_mode_translate(d) ? PFN_DOWN(MB(1)) : 0; + start =3D paging_mode_translate(d) ? PFN_DOWN(MB(1)) : 0; =20 - for ( ; i < top; i++ ) + for ( i =3D start, count =3D 0; i < top; ) { unsigned long pfn =3D pdx_to_pfn(i); unsigned int perms =3D hwdom_iommu_map(d, pfn, max_pfn); @@ -406,20 +406,41 @@ void __hwdom_init arch_iommu_hwdom_init( if ( !perms ) rc =3D 0; else if ( paging_mode_translate(d) ) + { rc =3D p2m_add_identity_entry(d, pfn, perms & IOMMUF_writable ? p2m_acce= ss_rw : p2m_acce= ss_r, 0); + if ( rc ) + printk(XENLOG_WARNING + "%pd: identity mapping of %lx failed: %d\n", + d, pfn, rc); + } + else if ( pfn !=3D start + count || perms !=3D start_perms ) + { + commit: + rc =3D iommu_map(d, _dfn(start), _mfn(start), count, start_per= ms, + &flush_flags); + if ( rc ) + printk(XENLOG_WARNING + "%pd: IOMMU identity mapping of [%lx,%lx) failed: %= d\n", + d, pfn, pfn + count, rc); + SWAP(start, pfn); + start_perms =3D perms; + count =3D 1; + } else - rc =3D iommu_map(d, _dfn(pfn), _mfn(pfn), 1ul << PAGE_ORDER_4K, - perms, &flush_flags); + { + ++count; + rc =3D 0; + } =20 - if ( rc ) - printk(XENLOG_WARNING "%pd: identity %smapping of %lx failed: = %d\n", - d, !paging_mode_translate(d) ? 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charset="utf-8" For vendor specific code to support superpages we need to be able to deal with a superpage mapping replacing an intermediate page table (or hierarchy thereof). Consequently an iommu_alloc_pgtable() counterpart is needed to free individual page tables while a domain is still alive. Since the freeing needs to be deferred until after a suitable IOTLB flush was performed, released page tables get queued for processing by a tasklet. Signed-off-by: Jan Beulich --- I was considering whether to use a softirq-tasklet instead. This would have the benefit of avoiding extra scheduling operations, but come with the risk of the freeing happening prematurely because of a process_pending_softirqs() somewhere. --- v5: Fix CPU_UP_PREPARE for BIGMEM. Schedule tasklet in CPU_DOWN_FAILED when list is not empty. Skip all processing in CPU_DEAD when list is empty. v4: Change type of iommu_queue_free_pgtable()'s 1st parameter. Re-base. v3: Call process_pending_softirqs() from free_queued_pgtables(). --- a/xen/arch/x86/include/asm/iommu.h +++ b/xen/arch/x86/include/asm/iommu.h @@ -147,6 +147,7 @@ void iommu_free_domid(domid_t domid, uns int __must_check iommu_free_pgtables(struct domain *d); struct domain_iommu; struct page_info *__must_check iommu_alloc_pgtable(struct domain_iommu *hd= ); +void iommu_queue_free_pgtable(struct domain_iommu *hd, struct page_info *p= g); =20 #endif /* !__ARCH_X86_IOMMU_H__ */ /* --- a/xen/drivers/passthrough/x86/iommu.c +++ b/xen/drivers/passthrough/x86/iommu.c @@ -12,6 +12,7 @@ * this program; If not, see . */ =20 +#include #include #include #include @@ -566,6 +567,98 @@ struct page_info *iommu_alloc_pgtable(st return pg; } =20 +/* + * Intermediate page tables which get replaced by large pages may only be + * freed after a suitable IOTLB flush. Hence such pages get queued on a + * per-CPU list, with a per-CPU tasklet processing the list on the assumpt= ion + * that the necessary IOTLB flush will have occurred by the time tasklets = get + * to run. (List and tasklet being per-CPU has the benefit of accesses not + * requiring any locking.) + */ +static DEFINE_PER_CPU(struct page_list_head, free_pgt_list); +static DEFINE_PER_CPU(struct tasklet, free_pgt_tasklet); + +static void free_queued_pgtables(void *arg) +{ + struct page_list_head *list =3D arg; + struct page_info *pg; + unsigned int done =3D 0; + + while ( (pg =3D page_list_remove_head(list)) ) + { + free_domheap_page(pg); + + /* Granularity of checking somewhat arbitrary. */ + if ( !(++done & 0x1ff) ) + process_pending_softirqs(); + } +} + +void iommu_queue_free_pgtable(struct domain_iommu *hd, struct page_info *p= g) +{ + unsigned int cpu =3D smp_processor_id(); + + spin_lock(&hd->arch.pgtables.lock); + page_list_del(pg, &hd->arch.pgtables.list); + spin_unlock(&hd->arch.pgtables.lock); + + page_list_add_tail(pg, &per_cpu(free_pgt_list, cpu)); + + tasklet_schedule(&per_cpu(free_pgt_tasklet, cpu)); +} + +static int cf_check cpu_callback( + struct notifier_block *nfb, unsigned long action, void *hcpu) +{ + unsigned int cpu =3D (unsigned long)hcpu; + struct page_list_head *list =3D &per_cpu(free_pgt_list, cpu); + struct tasklet *tasklet =3D &per_cpu(free_pgt_tasklet, cpu); + + switch ( action ) + { + case CPU_DOWN_PREPARE: + tasklet_kill(tasklet); + break; + + case CPU_DEAD: + if ( !page_list_empty(list) ) + { + page_list_splice(list, &this_cpu(free_pgt_list)); + INIT_PAGE_LIST_HEAD(list); + tasklet_schedule(&this_cpu(free_pgt_tasklet)); + } + break; + + case CPU_UP_PREPARE: + INIT_PAGE_LIST_HEAD(list); + fallthrough; + case CPU_DOWN_FAILED: + tasklet_init(tasklet, free_queued_pgtables, list); + if ( !page_list_empty(list) ) + tasklet_schedule(tasklet); + break; + } + + return NOTIFY_DONE; +} + +static struct notifier_block cpu_nfb =3D { + .notifier_call =3D cpu_callback, +}; + +static int __init cf_check bsp_init(void) +{ + if ( iommu_enabled ) + { + cpu_callback(&cpu_nfb, CPU_UP_PREPARE, + (void *)(unsigned long)smp_processor_id()); + register_cpu_notifier(&cpu_nfb); + } + + return 0; +} +presmp_initcall(bsp_init); + bool arch_iommu_use_permitted(const struct domain *d) { /* From nobody Sat May 18 08:14:11 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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charset="utf-8" No separate feature flags exist which would control availability of these; the only restriction is HATS (establishing the maximum number of page table levels in general), and even that has a lower bound of 4. Thus we can unconditionally announce 2M and 1G mappings. (Via non- default page sizes the implementation in principle permits arbitrary size mappings, but these require multiple identical leaf PTEs to be written, which isn't all that different from having to write multiple consecutive PTEs with increasing frame numbers. IMO that's therefore beneficial only on hardware where suitable TLBs exist; I'm unaware of such hardware.) Note that in principle 512G and 256T mappings could also be supported right away, but the freeing of page tables (to be introduced in subsequent patches) when replacing a sufficiently populated tree with a single huge page would need suitable preemption, which will require extra work. Signed-off-by: Jan Beulich Reviewed-by: Roger Pau Monn=C3=A9 --- v5: Drop PAGE_SIZE_512G. In amd_iommu_{,un}map_page() assert page order is supported. v4: Change type of queue_free_pt()'s 1st parameter. Re-base. v3: Rename queue_free_pt()'s last parameter. Replace "level > 1" checks where possible. --- a/xen/drivers/passthrough/amd/iommu_map.c +++ b/xen/drivers/passthrough/amd/iommu_map.c @@ -32,12 +32,13 @@ static unsigned int pfn_to_pde_idx(unsig } =20 static union amd_iommu_pte clear_iommu_pte_present(unsigned long l1_mfn, - unsigned long dfn) + unsigned long dfn, + unsigned int level) { union amd_iommu_pte *table, *pte, old; =20 table =3D map_domain_page(_mfn(l1_mfn)); - pte =3D &table[pfn_to_pde_idx(dfn, 1)]; + pte =3D &table[pfn_to_pde_idx(dfn, level)]; old =3D *pte; =20 write_atomic(&pte->raw, 0); @@ -351,15 +352,39 @@ static int iommu_pde_from_dfn(struct dom return 0; } =20 +static void queue_free_pt(struct domain_iommu *hd, mfn_t mfn, unsigned int= level) +{ + if ( level > 1 ) + { + union amd_iommu_pte *pt =3D map_domain_page(mfn); + unsigned int i; + + for ( i =3D 0; i < PTE_PER_TABLE_SIZE; ++i ) + if ( pt[i].pr && pt[i].next_level ) + { + ASSERT(pt[i].next_level < level); + queue_free_pt(hd, _mfn(pt[i].mfn), pt[i].next_level); + } + + unmap_domain_page(pt); + } + + iommu_queue_free_pgtable(hd, mfn_to_page(mfn)); +} + int cf_check amd_iommu_map_page( struct domain *d, dfn_t dfn, mfn_t mfn, unsigned int flags, unsigned int *flush_flags) { struct domain_iommu *hd =3D dom_iommu(d); + unsigned int level =3D (IOMMUF_order(flags) / PTE_PER_TABLE_SHIFT) + 1; int rc; unsigned long pt_mfn =3D 0; union amd_iommu_pte old; =20 + ASSERT((hd->platform_ops->page_sizes >> IOMMUF_order(flags)) & + PAGE_SIZE_4K); + spin_lock(&hd->arch.mapping_lock); =20 /* @@ -384,7 +409,7 @@ int cf_check amd_iommu_map_page( return rc; } =20 - if ( iommu_pde_from_dfn(d, dfn_x(dfn), 1, &pt_mfn, flush_flags, true) = || + if ( iommu_pde_from_dfn(d, dfn_x(dfn), level, &pt_mfn, flush_flags, tr= ue) || !pt_mfn ) { spin_unlock(&hd->arch.mapping_lock); @@ -394,8 +419,8 @@ int cf_check amd_iommu_map_page( return -EFAULT; } =20 - /* Install 4k mapping */ - old =3D set_iommu_pte_present(pt_mfn, dfn_x(dfn), mfn_x(mfn), 1, + /* Install mapping */ + old =3D set_iommu_pte_present(pt_mfn, dfn_x(dfn), mfn_x(mfn), level, (flags & IOMMUF_writable), (flags & IOMMUF_readable)); =20 @@ -403,8 +428,13 @@ int cf_check amd_iommu_map_page( =20 *flush_flags |=3D IOMMU_FLUSHF_added; if ( old.pr ) + { *flush_flags |=3D IOMMU_FLUSHF_modified; =20 + if ( IOMMUF_order(flags) && old.next_level ) + queue_free_pt(hd, _mfn(old.mfn), old.next_level); + } + return 0; } =20 @@ -413,8 +443,15 @@ int cf_check amd_iommu_unmap_page( { unsigned long pt_mfn =3D 0; struct domain_iommu *hd =3D dom_iommu(d); + unsigned int level =3D (order / PTE_PER_TABLE_SHIFT) + 1; union amd_iommu_pte old =3D {}; =20 + /* + * While really we could unmap at any granularity, for now we assume u= nmaps + * are issued by common code only at the same granularity as maps. + */ + ASSERT((hd->platform_ops->page_sizes >> order) & PAGE_SIZE_4K); + spin_lock(&hd->arch.mapping_lock); =20 if ( !hd->arch.amd.root_table ) @@ -423,7 +460,7 @@ int cf_check amd_iommu_unmap_page( return 0; } =20 - if ( iommu_pde_from_dfn(d, dfn_x(dfn), 1, &pt_mfn, flush_flags, false)= ) + if ( iommu_pde_from_dfn(d, dfn_x(dfn), level, &pt_mfn, flush_flags, fa= lse) ) { spin_unlock(&hd->arch.mapping_lock); AMD_IOMMU_ERROR("invalid IO pagetable entry dfn =3D %"PRI_dfn"\n", @@ -435,14 +472,19 @@ int cf_check amd_iommu_unmap_page( if ( pt_mfn ) { /* Mark PTE as 'page not present'. */ - old =3D clear_iommu_pte_present(pt_mfn, dfn_x(dfn)); + old =3D clear_iommu_pte_present(pt_mfn, dfn_x(dfn), level); } =20 spin_unlock(&hd->arch.mapping_lock); =20 if ( old.pr ) + { *flush_flags |=3D IOMMU_FLUSHF_modified; =20 + if ( order && old.next_level ) + queue_free_pt(hd, _mfn(old.mfn), old.next_level); + } + return 0; } =20 --- a/xen/drivers/passthrough/amd/pci_amd_iommu.c +++ b/xen/drivers/passthrough/amd/pci_amd_iommu.c @@ -747,7 +747,7 @@ static void cf_check amd_dump_page_table } =20 static const struct iommu_ops __initconst_cf_clobber _iommu_ops =3D { - .page_sizes =3D PAGE_SIZE_4K, + .page_sizes =3D PAGE_SIZE_4K | PAGE_SIZE_2M | PAGE_SIZE_1G, .init =3D amd_iommu_domain_init, .hwdom_init =3D amd_iommu_hwdom_init, .quarantine_init =3D amd_iommu_quarantine_init, --- a/xen/include/xen/page-defs.h +++ b/xen/include/xen/page-defs.h @@ -21,4 +21,14 @@ #define PAGE_MASK_64K PAGE_MASK_GRAN(64K) #define PAGE_ALIGN_64K(addr) PAGE_ALIGN_GRAN(64K, addr) =20 +#define PAGE_SHIFT_2M 21 +#define PAGE_SIZE_2M PAGE_SIZE_GRAN(2M) +#define PAGE_MASK_2M PAGE_MASK_GRAN(2M) +#define PAGE_ALIGN_2M(addr) PAGE_ALIGN_GRAN(2M, addr) + +#define PAGE_SHIFT_1G 30 +#define PAGE_SIZE_1G PAGE_SIZE_GRAN(1G) +#define PAGE_MASK_1G PAGE_MASK_GRAN(1G) +#define PAGE_ALIGN_1G(addr) PAGE_ALIGN_GRAN(1G, addr) + #endif /* __XEN_PAGE_DEFS_H__ */ From nobody Sat May 18 08:14:11 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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charset="utf-8" ... depending on feature availability (and absence of quirks). Also make the page table dumping function aware of superpages. Signed-off-by: Jan Beulich Reviewed-by: Kevin Tian Reviewed-by: Roger Pau Monn=C3=A9 --- v5: In intel_iommu_{,un}map_page() assert page order is supported. v4: Change type of queue_free_pt()'s 1st parameter. Re-base. v3: Rename queue_free_pt()'s last parameter. Replace "level > 1" checks where possible. Tighten assertion. --- a/xen/drivers/passthrough/vtd/iommu.c +++ b/xen/drivers/passthrough/vtd/iommu.c @@ -784,18 +784,37 @@ static int __must_check cf_check iommu_f return iommu_flush_iotlb(d, INVALID_DFN, 0, 0); } =20 +static void queue_free_pt(struct domain_iommu *hd, mfn_t mfn, unsigned int= level) +{ + if ( level > 1 ) + { + struct dma_pte *pt =3D map_domain_page(mfn); + unsigned int i; + + for ( i =3D 0; i < PTE_NUM; ++i ) + if ( dma_pte_present(pt[i]) && !dma_pte_superpage(pt[i]) ) + queue_free_pt(hd, maddr_to_mfn(dma_pte_addr(pt[i])), + level - 1); + + unmap_domain_page(pt); + } + + iommu_queue_free_pgtable(hd, mfn_to_page(mfn)); +} + /* clear one page's page table */ static int dma_pte_clear_one(struct domain *domain, daddr_t addr, unsigned int order, unsigned int *flush_flags) { struct domain_iommu *hd =3D dom_iommu(domain); - struct dma_pte *page =3D NULL, *pte =3D NULL; + struct dma_pte *page =3D NULL, *pte =3D NULL, old; u64 pg_maddr; + unsigned int level =3D (order / LEVEL_STRIDE) + 1; =20 spin_lock(&hd->arch.mapping_lock); - /* get last level pte */ - pg_maddr =3D addr_to_dma_page_maddr(domain, addr, 1, flush_flags, fals= e); + /* get target level pte */ + pg_maddr =3D addr_to_dma_page_maddr(domain, addr, level, flush_flags, = false); if ( pg_maddr < PAGE_SIZE ) { spin_unlock(&hd->arch.mapping_lock); @@ -803,7 +822,7 @@ static int dma_pte_clear_one(struct doma } =20 page =3D (struct dma_pte *)map_vtd_domain_page(pg_maddr); - pte =3D page + address_level_offset(addr, 1); + pte =3D &page[address_level_offset(addr, level)]; =20 if ( !dma_pte_present(*pte) ) { @@ -812,14 +831,20 @@ static int dma_pte_clear_one(struct doma return 0; } =20 + old =3D *pte; dma_clear_pte(*pte); - *flush_flags |=3D IOMMU_FLUSHF_modified; =20 spin_unlock(&hd->arch.mapping_lock); iommu_sync_cache(pte, sizeof(struct dma_pte)); =20 unmap_vtd_domain_page(page); =20 + *flush_flags |=3D IOMMU_FLUSHF_modified; + + if ( order && !dma_pte_superpage(old) ) + queue_free_pt(hd, maddr_to_mfn(dma_pte_addr(old)), + order / LEVEL_STRIDE); + return 0; } =20 @@ -2097,8 +2122,12 @@ static int __must_check cf_check intel_i struct domain_iommu *hd =3D dom_iommu(d); struct dma_pte *page, *pte, old, new =3D {}; u64 pg_maddr; + unsigned int level =3D (IOMMUF_order(flags) / LEVEL_STRIDE) + 1; int rc =3D 0; =20 + ASSERT((hd->platform_ops->page_sizes >> IOMMUF_order(flags)) & + PAGE_SIZE_4K); + /* Do nothing if VT-d shares EPT page table */ if ( iommu_use_hap_pt(d) ) return 0; @@ -2121,7 +2150,7 @@ static int __must_check cf_check intel_i return 0; } =20 - pg_maddr =3D addr_to_dma_page_maddr(d, dfn_to_daddr(dfn), 1, flush_fla= gs, + pg_maddr =3D addr_to_dma_page_maddr(d, dfn_to_daddr(dfn), level, flush= _flags, true); if ( pg_maddr < PAGE_SIZE ) { @@ -2130,13 +2159,15 @@ static int __must_check cf_check intel_i } =20 page =3D (struct dma_pte *)map_vtd_domain_page(pg_maddr); - pte =3D &page[dfn_x(dfn) & LEVEL_MASK]; + pte =3D &page[address_level_offset(dfn_to_daddr(dfn), level)]; old =3D *pte; =20 dma_set_pte_addr(new, mfn_to_maddr(mfn)); dma_set_pte_prot(new, ((flags & IOMMUF_readable) ? DMA_PTE_READ : 0) | ((flags & IOMMUF_writable) ? DMA_PTE_WRITE : 0)); + if ( IOMMUF_order(flags) ) + dma_set_pte_superpage(new); =20 /* Set the SNP on leaf page table if Snoop Control available */ if ( iommu_snoop ) @@ -2157,14 +2188,26 @@ static int __must_check cf_check intel_i =20 *flush_flags |=3D IOMMU_FLUSHF_added; if ( dma_pte_present(old) ) + { *flush_flags |=3D IOMMU_FLUSHF_modified; =20 + if ( IOMMUF_order(flags) && !dma_pte_superpage(old) ) + queue_free_pt(hd, maddr_to_mfn(dma_pte_addr(old)), + IOMMUF_order(flags) / LEVEL_STRIDE); + } + return rc; } =20 static int __must_check cf_check intel_iommu_unmap_page( struct domain *d, dfn_t dfn, unsigned int order, unsigned int *flush_f= lags) { + /* + * While really we could unmap at any granularity, for now we assume u= nmaps + * are issued by common code only at the same granularity as maps. + */ + ASSERT((dom_iommu(d)->platform_ops->page_sizes >> order) & PAGE_SIZE_4= K); + /* Do nothing if VT-d shares EPT page table */ if ( iommu_use_hap_pt(d) ) return 0; @@ -2519,6 +2562,7 @@ static int __init cf_check vtd_setup(voi { struct acpi_drhd_unit *drhd; struct vtd_iommu *iommu; + unsigned int large_sizes =3D PAGE_SIZE_2M | PAGE_SIZE_1G; int ret; bool reg_inval_supported =3D true; =20 @@ -2561,6 +2605,11 @@ static int __init cf_check vtd_setup(voi cap_sps_2mb(iommu->cap) ? ", 2MB" : "", cap_sps_1gb(iommu->cap) ? ", 1GB" : ""); =20 + if ( !cap_sps_2mb(iommu->cap) ) + large_sizes &=3D ~PAGE_SIZE_2M; + if ( !cap_sps_1gb(iommu->cap) ) + large_sizes &=3D ~PAGE_SIZE_1G; + #ifndef iommu_snoop if ( iommu_snoop && !ecap_snp_ctl(iommu->ecap) ) iommu_snoop =3D false; @@ -2632,6 +2681,9 @@ static int __init cf_check vtd_setup(voi if ( ret ) goto error; =20 + ASSERT(iommu_ops.page_sizes =3D=3D PAGE_SIZE_4K); + iommu_ops.page_sizes |=3D large_sizes; + register_keyhandler('V', vtd_dump_iommu_info, "dump iommu info", 1); =20 return 0; @@ -2964,7 +3016,7 @@ static void vtd_dump_page_table_level(pa continue; =20 address =3D gpa + offset_level_address(i, level); - if ( next_level >=3D 1 )=20 + if ( next_level && !dma_pte_superpage(*pte) ) vtd_dump_page_table_level(dma_pte_addr(*pte), next_level, address, indent + 1); else From nobody Sat May 18 08:14:11 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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charset="utf-8" Having a separate flush-all hook has always been puzzling me some. We will want to be able to force a full flush via accumulated flush flags from the map/unmap functions. Introduce a respective new flag and fold all flush handling to use the single remaining hook. Note that because of the respective comments in SMMU and IPMMU-VMSA code, I've folded the two prior hook functions into one. For SMMU-v3, which lacks a comment towards incapable hardware, I've left both functions in place on the assumption that selective and full flushes will eventually want separating. Signed-off-by: Jan Beulich Reviewed-by: Roger Pau Monn=C3=A9 Reviewed-by: Oleksandr Tyshchenko # IPMMU-V= MSA, SMMU-V2 Reviewed-by: Rahul Singh # SMMUv3 Acked-by: Julien Grall # Arm Reviewed-by: Kevin Tian --- TBD: What we really are going to need is for the map/unmap functions to specify that a wider region needs flushing than just the one covered by the present set of (un)maps. This may still be less than a full flush, but at least as a first step it seemed better to me to keep things simple and go the flush-all route. --- v4: Re-base. v3: Re-base over changes earlier in the series. v2: New. --- a/xen/drivers/passthrough/amd/iommu.h +++ b/xen/drivers/passthrough/amd/iommu.h @@ -258,7 +258,6 @@ int cf_check amd_iommu_get_reserved_devi int __must_check cf_check amd_iommu_flush_iotlb_pages( struct domain *d, dfn_t dfn, unsigned long page_count, unsigned int flush_flags); -int __must_check cf_check amd_iommu_flush_iotlb_all(struct domain *d); void amd_iommu_print_entries(const struct amd_iommu *iommu, unsigned int d= ev_id, dfn_t dfn); =20 --- a/xen/drivers/passthrough/amd/iommu_map.c +++ b/xen/drivers/passthrough/amd/iommu_map.c @@ -548,15 +548,18 @@ int cf_check amd_iommu_flush_iotlb_pages { unsigned long dfn_l =3D dfn_x(dfn); =20 - ASSERT(page_count && !dfn_eq(dfn, INVALID_DFN)); - ASSERT(flush_flags); + if ( !(flush_flags & IOMMU_FLUSHF_all) ) + { + ASSERT(page_count && !dfn_eq(dfn, INVALID_DFN)); + ASSERT(flush_flags); + } =20 /* Unless a PTE was modified, no flush is required */ if ( !(flush_flags & IOMMU_FLUSHF_modified) ) return 0; =20 - /* If the range wraps then just flush everything */ - if ( dfn_l + page_count < dfn_l ) + /* If so requested or if the range wraps then just flush everything. */ + if ( (flush_flags & IOMMU_FLUSHF_all) || dfn_l + page_count < dfn_l ) { amd_iommu_flush_all_pages(d); return 0; @@ -581,13 +584,6 @@ int cf_check amd_iommu_flush_iotlb_pages =20 return 0; } - -int cf_check amd_iommu_flush_iotlb_all(struct domain *d) -{ - amd_iommu_flush_all_pages(d); - - return 0; -} =20 int amd_iommu_reserve_domain_unity_map(struct domain *d, const struct ivrs_unity_map *map, --- a/xen/drivers/passthrough/amd/pci_amd_iommu.c +++ b/xen/drivers/passthrough/amd/pci_amd_iommu.c @@ -759,7 +759,6 @@ static const struct iommu_ops __initcons .map_page =3D amd_iommu_map_page, .unmap_page =3D amd_iommu_unmap_page, .iotlb_flush =3D amd_iommu_flush_iotlb_pages, - .iotlb_flush_all =3D amd_iommu_flush_iotlb_all, .reassign_device =3D reassign_device, .get_device_group_id =3D amd_iommu_group_id, .enable_x2apic =3D iov_enable_xt, --- a/xen/drivers/passthrough/arm/ipmmu-vmsa.c +++ b/xen/drivers/passthrough/arm/ipmmu-vmsa.c @@ -1000,13 +1000,19 @@ out: } =20 /* Xen IOMMU ops */ -static int __must_check ipmmu_iotlb_flush_all(struct domain *d) +static int __must_check ipmmu_iotlb_flush(struct domain *d, dfn_t dfn, + unsigned long page_count, + unsigned int flush_flags) { struct ipmmu_vmsa_xen_domain *xen_domain =3D dom_iommu(d)->arch.priv; =20 + ASSERT(flush_flags); + if ( !xen_domain || !xen_domain->root_domain ) return 0; =20 + /* The hardware doesn't support selective TLB flush. */ + spin_lock(&xen_domain->lock); ipmmu_tlb_invalidate(xen_domain->root_domain); spin_unlock(&xen_domain->lock); @@ -1014,16 +1020,6 @@ static int __must_check ipmmu_iotlb_flus return 0; } =20 -static int __must_check ipmmu_iotlb_flush(struct domain *d, dfn_t dfn, - unsigned long page_count, - unsigned int flush_flags) -{ - ASSERT(flush_flags); - - /* The hardware doesn't support selective TLB flush. */ - return ipmmu_iotlb_flush_all(d); -} - static struct ipmmu_vmsa_domain *ipmmu_get_cache_domain(struct domain *d, struct device *dev) { @@ -1360,7 +1356,6 @@ static const struct iommu_ops ipmmu_iomm .hwdom_init =3D arch_iommu_hwdom_init, .teardown =3D ipmmu_iommu_domain_teardown, .iotlb_flush =3D ipmmu_iotlb_flush, - .iotlb_flush_all =3D ipmmu_iotlb_flush_all, .assign_device =3D ipmmu_assign_device, .reassign_device =3D ipmmu_reassign_device, .map_page =3D arm_iommu_map_page, --- a/xen/drivers/passthrough/arm/smmu.c +++ b/xen/drivers/passthrough/arm/smmu.c @@ -2648,11 +2648,17 @@ static int force_stage =3D 2; */ static u32 platform_features =3D ARM_SMMU_FEAT_COHERENT_WALK; =20 -static int __must_check arm_smmu_iotlb_flush_all(struct domain *d) +static int __must_check arm_smmu_iotlb_flush(struct domain *d, dfn_t dfn, + unsigned long page_count, + unsigned int flush_flags) { struct arm_smmu_xen_domain *smmu_domain =3D dom_iommu(d)->arch.priv; struct iommu_domain *cfg; =20 + ASSERT(flush_flags); + + /* ARM SMMU v1 doesn't have flush by VMA and VMID */ + spin_lock(&smmu_domain->lock); list_for_each_entry(cfg, &smmu_domain->contexts, list) { /* @@ -2669,16 +2675,6 @@ static int __must_check arm_smmu_iotlb_f return 0; } =20 -static int __must_check arm_smmu_iotlb_flush(struct domain *d, dfn_t dfn, - unsigned long page_count, - unsigned int flush_flags) -{ - ASSERT(flush_flags); - - /* ARM SMMU v1 doesn't have flush by VMA and VMID */ - return arm_smmu_iotlb_flush_all(d); -} - static struct iommu_domain *arm_smmu_get_domain(struct domain *d, struct device *dev) { @@ -2863,7 +2859,6 @@ static const struct iommu_ops arm_smmu_i .add_device =3D arm_smmu_dt_add_device_generic, .teardown =3D arm_smmu_iommu_domain_teardown, .iotlb_flush =3D arm_smmu_iotlb_flush, - .iotlb_flush_all =3D arm_smmu_iotlb_flush_all, .assign_device =3D arm_smmu_assign_dev, .reassign_device =3D arm_smmu_reassign_dev, .map_page =3D arm_iommu_map_page, --- a/xen/drivers/passthrough/arm/smmu-v3.c +++ b/xen/drivers/passthrough/arm/smmu-v3.c @@ -3416,7 +3416,6 @@ static const struct iommu_ops arm_smmu_i .hwdom_init =3D arch_iommu_hwdom_init, .teardown =3D arm_smmu_iommu_xen_domain_teardown, .iotlb_flush =3D arm_smmu_iotlb_flush, - .iotlb_flush_all =3D arm_smmu_iotlb_flush_all, .assign_device =3D arm_smmu_assign_dev, .reassign_device =3D arm_smmu_reassign_dev, .map_page =3D arm_iommu_map_page, --- a/xen/drivers/passthrough/iommu.c +++ b/xen/drivers/passthrough/iommu.c @@ -478,15 +478,12 @@ int iommu_iotlb_flush_all(struct domain const struct domain_iommu *hd =3D dom_iommu(d); int rc; =20 - if ( !is_iommu_enabled(d) || !hd->platform_ops->iotlb_flush_all || + if ( !is_iommu_enabled(d) || !hd->platform_ops->iotlb_flush || !flush_flags ) return 0; =20 - /* - * The operation does a full flush so we don't need to pass the - * flush_flags in. - */ - rc =3D iommu_call(hd->platform_ops, iotlb_flush_all, d); + rc =3D iommu_call(hd->platform_ops, iotlb_flush, d, INVALID_DFN, 0, + flush_flags | IOMMU_FLUSHF_all); if ( unlikely(rc) ) { if ( !d->is_shutting_down && printk_ratelimit() ) --- a/xen/drivers/passthrough/vtd/iommu.c +++ b/xen/drivers/passthrough/vtd/iommu.c @@ -772,18 +772,21 @@ static int __must_check cf_check iommu_f struct domain *d, dfn_t dfn, unsigned long page_count, unsigned int flush_flags) { - ASSERT(page_count && !dfn_eq(dfn, INVALID_DFN)); - ASSERT(flush_flags); + if ( flush_flags & IOMMU_FLUSHF_all ) + { + dfn =3D INVALID_DFN; + page_count =3D 0; + } + else + { + ASSERT(page_count && !dfn_eq(dfn, INVALID_DFN)); + ASSERT(flush_flags); + } =20 return iommu_flush_iotlb(d, dfn, flush_flags & IOMMU_FLUSHF_modified, page_count); } =20 -static int __must_check cf_check iommu_flush_iotlb_all(struct domain *d) -{ - return iommu_flush_iotlb(d, INVALID_DFN, 0, 0); -} - static void queue_free_pt(struct domain_iommu *hd, mfn_t mfn, unsigned int= level) { if ( level > 1 ) @@ -3197,7 +3200,6 @@ static const struct iommu_ops __initcons .resume =3D vtd_resume, .crash_shutdown =3D vtd_crash_shutdown, .iotlb_flush =3D iommu_flush_iotlb_pages, - .iotlb_flush_all =3D iommu_flush_iotlb_all, .get_reserved_device_memory =3D intel_iommu_get_reserved_device_memory, .dump_page_tables =3D vtd_dump_page_tables, }; --- a/xen/include/xen/iommu.h +++ b/xen/include/xen/iommu.h @@ -147,9 +147,11 @@ enum { _IOMMU_FLUSHF_added, _IOMMU_FLUSHF_modified, + _IOMMU_FLUSHF_all, }; #define IOMMU_FLUSHF_added (1u << _IOMMU_FLUSHF_added) #define IOMMU_FLUSHF_modified (1u << _IOMMU_FLUSHF_modified) +#define IOMMU_FLUSHF_all (1u << _IOMMU_FLUSHF_all) =20 int __must_check iommu_map(struct domain *d, dfn_t dfn, mfn_t mfn, unsigned long page_count, unsigned int flags, @@ -281,7 +283,6 @@ struct iommu_ops { int __must_check (*iotlb_flush)(struct domain *d, dfn_t dfn, unsigned long page_count, unsigned int flush_flags); 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charset="utf-8" This is a re-usable helper (kind of a template) which gets introduced without users so that the individual subsequent patches introducing such users can get committed independently of one another. See the comment at the top of the new file. To demonstrate the effect, if a page table had just 16 entries, this would be the set of markers for a page table with fully contiguous mappings: index 0 1 2 3 4 5 6 7 8 9 A B C D E F marker 4 0 1 0 2 0 1 0 3 0 1 0 2 0 1 0 "Contiguous" here means not only present entries with successively increasing MFNs, each one suitably aligned for its slot, but also a respective number of all non-present entries. Signed-off-by: Jan Beulich Reviewed-by: Roger Pau Monn=C3=A9 --- @Roger: I've retained your R-b, but I was on the edge of dropping it. --- v5: Bail early from step 1 if possible. Arrange for consumers who are just after CONTIG_{LEVEL_SHIFT,NR}. Extend comment. v3: Rename function and header. Introduce IS_CONTIG(). v2: New. --- /dev/null +++ b/xen/arch/x86/include/asm/pt-contig-markers.h @@ -0,0 +1,110 @@ +#ifndef __ASM_X86_PT_CONTIG_MARKERS_H +#define __ASM_X86_PT_CONTIG_MARKERS_H + +/* + * Short of having function templates in C, the function defined below is + * intended to be used by multiple parties interested in recording the + * degree of contiguity in mappings by a single page table. + * + * Scheme: Every entry records the order of contiguous successive entries, + * up to the maximum order covered by that entry (which is the number of + * clear low bits in its index, with entry 0 being the exception using + * the base-2 logarithm of the number of entries in a single page table). + * While a few entries need touching upon update, knowing whether the + * table is fully contiguous (and can hence be replaced by a higher level + * leaf entry) is then possible by simply looking at entry 0's marker. + * + * Prereqs: + * - CONTIG_MASK needs to be #define-d, to a value having at least 4 + * contiguous bits (ignored by hardware), before including this file (or + * else only CONTIG_LEVEL_SHIFT and CONTIG_NR will become available), + * - page tables to be passed to the helper need to be initialized with + * correct markers, + * - not-present entries need to be entirely clear except for the marker. + */ + +/* This is the same for all anticipated users, so doesn't need passing in.= */ +#define CONTIG_LEVEL_SHIFT 9 +#define CONTIG_NR (1 << CONTIG_LEVEL_SHIFT) + +#ifdef CONTIG_MASK + +#include +#include +#include + +#define GET_MARKER(e) MASK_EXTR(e, CONTIG_MASK) +#define SET_MARKER(e, m) \ + ((void)((e) =3D ((e) & ~CONTIG_MASK) | MASK_INSR(m, CONTIG_MASK))) + +#define IS_CONTIG(kind, pt, i, idx, shift, b) \ + ((kind) =3D=3D PTE_kind_leaf \ + ? (((pt)[i] ^ (pt)[idx]) & ~CONTIG_MASK) =3D=3D (1ULL << ((b) + (shif= t))) \ + : !((pt)[i] & ~CONTIG_MASK)) + +enum PTE_kind { + PTE_kind_null, + PTE_kind_leaf, + PTE_kind_table, +}; + +static bool pt_update_contig_markers(uint64_t *pt, unsigned int idx, + unsigned int level, enum PTE_kind kin= d) +{ + unsigned int b, i =3D idx; + unsigned int shift =3D (level - 1) * CONTIG_LEVEL_SHIFT + PAGE_SHIFT; + + ASSERT(idx < CONTIG_NR); + ASSERT(!(pt[idx] & CONTIG_MASK)); + + /* Step 1: Reduce markers in lower numbered entries. */ + while ( i ) + { + b =3D find_first_set_bit(i); + i &=3D ~(1U << b); + if ( GET_MARKER(pt[i]) <=3D b ) + break; + SET_MARKER(pt[i], b); + } + + /* An intermediate table is never contiguous with anything. */ + if ( kind =3D=3D PTE_kind_table ) + return false; + + /* + * Present entries need in-sync index and address to be a candidate + * for being contiguous: What we're after is whether ultimately the + * intermediate table can be replaced by a superpage. + */ + if ( kind !=3D PTE_kind_null && + idx !=3D ((pt[idx] >> shift) & (CONTIG_NR - 1)) ) + return false; + + /* Step 2: Check higher numbered entries for contiguity. */ + for ( b =3D 0; b < CONTIG_LEVEL_SHIFT && !(idx & (1U << b)); ++b ) + { + i =3D idx | (1U << b); + if ( !IS_CONTIG(kind, pt, i, idx, shift, b) || GET_MARKER(pt[i]) != =3D b ) + break; + } + + /* Step 3: Update markers in this and lower numbered entries. */ + for ( ; SET_MARKER(pt[idx], b), b < CONTIG_LEVEL_SHIFT; ++b ) + { + i =3D idx ^ (1U << b); + if ( !IS_CONTIG(kind, pt, i, idx, shift, b) || GET_MARKER(pt[i]) != =3D b ) + break; + idx &=3D ~(1U << b); + } + + return b =3D=3D CONTIG_LEVEL_SHIFT; +} + +#undef IS_CONTIG +#undef SET_MARKER +#undef GET_MARKER +#undef CONTIG_MASK + +#endif /* CONTIG_MASK */ + +#endif /* __ASM_X86_PT_CONTIG_MARKERS_H */ From nobody Sat May 18 08:14:11 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; 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charset="utf-8" Page tables are used for two purposes after allocation: They either start out all empty, or they are filled to replace a superpage. Subsequently, to replace all empty or fully contiguous page tables, contiguous sub-regions will be recorded within individual page tables. Install the initial set of markers immediately after allocation. Make sure to retain these markers when further populating a page table in preparation for it to replace a superpage. The markers are simply 4-bit fields holding the order value of contiguous entries. To demonstrate this, if a page table had just 16 entries, this would be the initial (fully contiguous) set of markers: index 0 1 2 3 4 5 6 7 8 9 A B C D E F marker 4 0 1 0 2 0 1 0 3 0 1 0 2 0 1 0 "Contiguous" here means not only present entries with successively increasing MFNs, each one suitably aligned for its slot, and identical attributes, but also a respective number of all non-present (zero except for the markers) entries. Signed-off-by: Jan Beulich Reviewed-by: Kevin Tian Reviewed-by: Roger Pau Monn=C3=A9 --- An alternative to the ASSERT()s added to set_iommu_ptes_present() would be to make the function less general-purpose; it's used in a single place only after all (i.e. it might as well be folded into its only caller). While in VT-d's comment ahead of struct dma_pte I'm adjusting the description of the high bits, I'd like to note that the description of some of the lower bits isn't correct either. Yet I don't think adjusting that belongs here. --- v5: Assert next_mfn is suitably aligned in set_iommu_ptes_present(). Use CONTIG_LEVEL_SHIFT in favor of PAGE_SHIFT-3. v4: Add another comment referring to pt-contig-markers.h. Re-base. v3: Add comments. Re-base. v2: New. --- a/xen/arch/x86/include/asm/iommu.h +++ b/xen/arch/x86/include/asm/iommu.h @@ -146,7 +146,8 @@ void iommu_free_domid(domid_t domid, uns =20 int __must_check iommu_free_pgtables(struct domain *d); struct domain_iommu; -struct page_info *__must_check iommu_alloc_pgtable(struct domain_iommu *hd= ); +struct page_info *__must_check iommu_alloc_pgtable(struct domain_iommu *hd, + uint64_t contig_mask); void iommu_queue_free_pgtable(struct domain_iommu *hd, struct page_info *p= g); =20 #endif /* !__ARCH_X86_IOMMU_H__ */ --- a/xen/drivers/passthrough/amd/iommu-defs.h +++ b/xen/drivers/passthrough/amd/iommu-defs.h @@ -446,11 +446,13 @@ union amd_iommu_x2apic_control { #define IOMMU_PAGE_TABLE_U32_PER_ENTRY (IOMMU_PAGE_TABLE_ENTRY_SIZE / 4) #define IOMMU_PAGE_TABLE_ALIGNMENT 4096 =20 +#define IOMMU_PTE_CONTIG_MASK 0x1e /* The ign0 field below. */ + union amd_iommu_pte { uint64_t raw; struct { bool pr:1; - unsigned int ign0:4; + unsigned int ign0:4; /* Covered by IOMMU_PTE_CONTIG_MASK. */ bool a:1; bool d:1; unsigned int ign1:2; --- a/xen/drivers/passthrough/amd/iommu_map.c +++ b/xen/drivers/passthrough/amd/iommu_map.c @@ -21,6 +21,8 @@ =20 #include "iommu.h" =20 +#include + /* Given pfn and page table level, return pde index */ static unsigned int pfn_to_pde_idx(unsigned long pfn, unsigned int level) { @@ -113,9 +115,23 @@ static void set_iommu_ptes_present(unsig return; } =20 + ASSERT(!(next_mfn & (page_sz - 1))); + while ( nr_ptes-- ) { - set_iommu_pde_present(pde, next_mfn, 0, iw, ir); + ASSERT(!pde->next_level); + ASSERT(!pde->u); + + if ( pde > table ) + ASSERT(pde->ign0 =3D=3D find_first_set_bit(pde - table)); + else + ASSERT(pde->ign0 =3D=3D CONTIG_LEVEL_SHIFT); + + pde->iw =3D iw; + pde->ir =3D ir; + pde->fc =3D true; /* See set_iommu_pde_present(). */ + pde->mfn =3D next_mfn; + pde->pr =3D true; =20 ++pde; next_mfn +=3D page_sz; @@ -295,7 +311,7 @@ static int iommu_pde_from_dfn(struct dom mfn =3D next_table_mfn; =20 /* allocate lower level page table */ - table =3D iommu_alloc_pgtable(hd); + table =3D iommu_alloc_pgtable(hd, IOMMU_PTE_CONTIG_MASK); if ( table =3D=3D NULL ) { AMD_IOMMU_ERROR("cannot allocate I/O page table\n"); @@ -325,7 +341,7 @@ static int iommu_pde_from_dfn(struct dom =20 if ( next_table_mfn =3D=3D 0 ) { - table =3D iommu_alloc_pgtable(hd); + table =3D iommu_alloc_pgtable(hd, IOMMU_PTE_CONTIG_MASK); if ( table =3D=3D NULL ) { AMD_IOMMU_ERROR("cannot allocate I/O page table\n"); @@ -726,7 +742,7 @@ static int fill_qpt(union amd_iommu_pte * page table pages, and the resulting allocations are alw= ays * zeroed. */ - pgs[level] =3D iommu_alloc_pgtable(hd); + pgs[level] =3D iommu_alloc_pgtable(hd, 0); if ( !pgs[level] ) { rc =3D -ENOMEM; @@ -784,7 +800,7 @@ int cf_check amd_iommu_quarantine_init(s return 0; } =20 - pdev->arch.amd.root_table =3D iommu_alloc_pgtable(hd); + pdev->arch.amd.root_table =3D iommu_alloc_pgtable(hd, 0); if ( !pdev->arch.amd.root_table ) return -ENOMEM; =20 --- a/xen/drivers/passthrough/amd/pci_amd_iommu.c +++ b/xen/drivers/passthrough/amd/pci_amd_iommu.c @@ -342,7 +342,7 @@ int amd_iommu_alloc_root(struct domain * =20 if ( unlikely(!hd->arch.amd.root_table) && d !=3D dom_io ) { - hd->arch.amd.root_table =3D iommu_alloc_pgtable(hd); + hd->arch.amd.root_table =3D iommu_alloc_pgtable(hd, 0); if ( !hd->arch.amd.root_table ) return -ENOMEM; } --- a/xen/drivers/passthrough/vtd/iommu.c +++ b/xen/drivers/passthrough/vtd/iommu.c @@ -334,7 +334,7 @@ static uint64_t addr_to_dma_page_maddr(s goto out; =20 pte_maddr =3D level; - if ( !(pg =3D iommu_alloc_pgtable(hd)) ) + if ( !(pg =3D iommu_alloc_pgtable(hd, 0)) ) goto out; =20 hd->arch.vtd.pgd_maddr =3D page_to_maddr(pg); @@ -376,7 +376,7 @@ static uint64_t addr_to_dma_page_maddr(s } =20 pte_maddr =3D level - 1; - pg =3D iommu_alloc_pgtable(hd); + pg =3D iommu_alloc_pgtable(hd, DMA_PTE_CONTIG_MASK); if ( !pg ) break; =20 @@ -388,12 +388,13 @@ static uint64_t addr_to_dma_page_maddr(s struct dma_pte *split =3D map_vtd_domain_page(pte_maddr); unsigned long inc =3D 1UL << level_to_offset_bits(level - = 1); =20 - split[0].val =3D pte->val; + split[0].val |=3D pte->val & ~DMA_PTE_CONTIG_MASK; if ( inc =3D=3D PAGE_SIZE ) split[0].val &=3D ~DMA_PTE_SP; =20 for ( offset =3D 1; offset < PTE_NUM; ++offset ) - split[offset].val =3D split[offset - 1].val + inc; + split[offset].val |=3D + (split[offset - 1].val & ~DMA_PTE_CONTIG_MASK) + i= nc; =20 iommu_sync_cache(split, PAGE_SIZE); unmap_vtd_domain_page(split); @@ -2176,7 +2177,7 @@ static int __must_check cf_check intel_i if ( iommu_snoop ) dma_set_pte_snp(new); =20 - if ( old.val =3D=3D new.val ) + if ( !((old.val ^ new.val) & ~DMA_PTE_CONTIG_MASK) ) { spin_unlock(&hd->arch.mapping_lock); unmap_vtd_domain_page(page); @@ -3064,7 +3065,7 @@ static int fill_qpt(struct dma_pte *this * page table pages, and the resulting allocations are alw= ays * zeroed. */ - pgs[level] =3D iommu_alloc_pgtable(hd); + pgs[level] =3D iommu_alloc_pgtable(hd, 0); if ( !pgs[level] ) { rc =3D -ENOMEM; @@ -3121,7 +3122,7 @@ static int cf_check intel_iommu_quaranti if ( !drhd ) return -ENODEV; =20 - pg =3D iommu_alloc_pgtable(hd); + pg =3D iommu_alloc_pgtable(hd, 0); if ( !pg ) return -ENOMEM; =20 --- a/xen/drivers/passthrough/vtd/iommu.h +++ b/xen/drivers/passthrough/vtd/iommu.h @@ -253,7 +253,10 @@ struct context_entry { * 2-6: reserved * 7: super page * 8-11: available - * 12-63: Host physcial address + * 12-51: Host physcial address + * 52-61: available (52-55 used for DMA_PTE_CONTIG_MASK) + * 62: reserved + * 63: available */ struct dma_pte { u64 val; @@ -263,6 +266,7 @@ struct dma_pte { #define DMA_PTE_PROT (DMA_PTE_READ | DMA_PTE_WRITE) #define DMA_PTE_SP (1 << 7) #define DMA_PTE_SNP (1 << 11) +#define DMA_PTE_CONTIG_MASK (0xfull << PADDR_BITS) #define dma_clear_pte(p) do {(p).val =3D 0;} while(0) #define dma_set_pte_readable(p) do {(p).val |=3D DMA_PTE_READ;} while(0) #define dma_set_pte_writable(p) do {(p).val |=3D DMA_PTE_WRITE;} while(0) @@ -276,7 +280,7 @@ struct dma_pte { #define dma_pte_write(p) (dma_pte_prot(p) & DMA_PTE_WRITE) #define dma_pte_addr(p) ((p).val & PADDR_MASK & PAGE_MASK_4K) #define dma_set_pte_addr(p, addr) do {\ - (p).val |=3D ((addr) & PAGE_MASK_4K); } while (0) + (p).val |=3D ((addr) & PADDR_MASK & PAGE_MASK_4K); } while (0) #define dma_pte_present(p) (((p).val & DMA_PTE_PROT) !=3D 0) #define dma_pte_superpage(p) (((p).val & DMA_PTE_SP) !=3D 0) =20 --- a/xen/drivers/passthrough/x86/iommu.c +++ b/xen/drivers/passthrough/x86/iommu.c @@ -26,6 +26,7 @@ #include #include #include +#include #include =20 const struct iommu_init_ops *__initdata iommu_init_ops; @@ -538,11 +539,12 @@ int iommu_free_pgtables(struct domain *d return 0; } =20 -struct page_info *iommu_alloc_pgtable(struct domain_iommu *hd) +struct page_info *iommu_alloc_pgtable(struct domain_iommu *hd, + uint64_t contig_mask) { unsigned int memflags =3D 0; struct page_info *pg; - void *p; + uint64_t *p; =20 #ifdef CONFIG_NUMA if ( hd->node !=3D NUMA_NO_NODE ) @@ -554,7 +556,29 @@ struct page_info *iommu_alloc_pgtable(st return NULL; =20 p =3D __map_domain_page(pg); - clear_page(p); + + if ( contig_mask ) + { + /* See pt-contig-markers.h for a description of the marker scheme.= */ + unsigned int i, shift =3D find_first_set_bit(contig_mask); + + ASSERT((CONTIG_LEVEL_SHIFT & (contig_mask >> shift)) =3D=3D CONTIG= _LEVEL_SHIFT); + + p[0] =3D (CONTIG_LEVEL_SHIFT + 0ull) << shift; + p[1] =3D 0; + p[2] =3D 1ull << shift; + p[3] =3D 0; + + for ( i =3D 4; i < PAGE_SIZE / 8; i +=3D 4 ) + { + p[i + 0] =3D (find_first_set_bit(i) + 0ull) << shift; + p[i + 1] =3D 0; + p[i + 2] =3D 1ull << shift; + p[i + 3] =3D 0; + } + } + else + clear_page(p); =20 iommu_sync_cache(p, PAGE_SIZE); From nobody Sat May 18 08:14:11 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; arc=fail (BodyHash is different from the expected one); dmarc=pass(p=quarantine dis=none) header.from=suse.com Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1653650349589346.535523999744; Fri, 27 May 2022 04:19:09 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.337992.562727 (Exim 4.92) (envelope-from ) id 1nuXzW-0003QQ-3v; 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charset="utf-8" When a page table ends up with no present entries left, it can be replaced by a non-present entry at the next higher level. The page table itself can then be scheduled for freeing. Note that while its output isn't used there yet, pt_update_contig_markers() right away needs to be called in all places where entries get updated, not just the one where entries get cleared. Signed-off-by: Jan Beulich Reviewed-by: Roger Pau Monn=C3=A9 --- v5: Re-base over changes earlier in the series. v4: Re-base over changes earlier in the series. v3: Re-base over changes earlier in the series. v2: New. --- a/xen/drivers/passthrough/amd/iommu_map.c +++ b/xen/drivers/passthrough/amd/iommu_map.c @@ -21,6 +21,7 @@ =20 #include "iommu.h" =20 +#define CONTIG_MASK IOMMU_PTE_CONTIG_MASK #include =20 /* Given pfn and page table level, return pde index */ @@ -35,16 +36,20 @@ static unsigned int pfn_to_pde_idx(unsig =20 static union amd_iommu_pte clear_iommu_pte_present(unsigned long l1_mfn, unsigned long dfn, - unsigned int level) + unsigned int level, + bool *free) { union amd_iommu_pte *table, *pte, old; + unsigned int idx =3D pfn_to_pde_idx(dfn, level); =20 table =3D map_domain_page(_mfn(l1_mfn)); - pte =3D &table[pfn_to_pde_idx(dfn, level)]; + pte =3D &table[idx]; old =3D *pte; =20 write_atomic(&pte->raw, 0); =20 + *free =3D pt_update_contig_markers(&table->raw, idx, level, PTE_kind_n= ull); + unmap_domain_page(table); =20 return old; @@ -87,7 +92,11 @@ static union amd_iommu_pte set_iommu_pte if ( !old.pr || old.next_level || old.mfn !=3D next_mfn || old.iw !=3D iw || old.ir !=3D ir ) + { set_iommu_pde_present(pde, next_mfn, 0, iw, ir); + pt_update_contig_markers(&table->raw, pfn_to_pde_idx(dfn, level), + level, PTE_kind_leaf); + } else old.pr =3D false; /* signal "no change" to the caller */ =20 @@ -326,6 +335,9 @@ static int iommu_pde_from_dfn(struct dom smp_wmb(); set_iommu_pde_present(pde, next_table_mfn, next_level, true, true); + pt_update_contig_markers(&next_table_vaddr->raw, + pfn_to_pde_idx(dfn, level), + level, PTE_kind_table); =20 *flush_flags |=3D IOMMU_FLUSHF_modified; } @@ -351,6 +363,9 @@ static int iommu_pde_from_dfn(struct dom next_table_mfn =3D mfn_x(page_to_mfn(table)); set_iommu_pde_present(pde, next_table_mfn, next_level, tru= e, true); + pt_update_contig_markers(&next_table_vaddr->raw, + pfn_to_pde_idx(dfn, level), + level, PTE_kind_table); } else /* should never reach here */ { @@ -487,8 +502,24 @@ int cf_check amd_iommu_unmap_page( =20 if ( pt_mfn ) { + bool free; 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charset="utf-8" When a page table ends up with no present entries left, it can be replaced by a non-present entry at the next higher level. The page table itself can then be scheduled for freeing. Note that while its output isn't used there yet, pt_update_contig_markers() right away needs to be called in all places where entries get updated, not just the one where entries get cleared. Note further that while pt_update_contig_markers() updates perhaps several PTEs within the table, since these are changes to "avail" bits only I do not think that cache flushing would be needed afterwards. Such cache flushing (of entire pages, unless adding yet more logic to me more selective) would be quite noticable performance-wise (very prominent during Dom0 boot). Also note that cache sync-ing is likely more strict than necessary. This is both to be on the safe side as well as to maintain the pattern of all updates of (potentially) live tables being accompanied by a flush (if so needed). Signed-off-by: Jan Beulich Reviewed-by: Kevin Tian Reviewed-by: Roger Pau Monn=C3=A9 --- v4: Re-base over changes earlier in the series. v3: Properly bound loop. Re-base over changes earlier in the series. v2: New. --- The hang during boot on my Latitude E6410 (see the respective code comment) was pretty close after iommu_enable_translation(). No errors, no watchdog would kick in, just sometimes the first few pixel lines of the next log message's (XEN) prefix would have made it out to the screen (and there's no serial there). It's been a lot of experimenting until I figured the workaround (which I consider ugly, but halfway acceptable). I've been trying hard to make sure the workaround wouldn't be masking a real issue, yet I'm still wary of it possibly doing so ... My best guess at this point is that on these old IOMMUs the ignored bits 52...61 aren't really ignored for present entries, but also aren't "reserved" enough to trigger faults. This guess is from having tried to set other bits in this range (unconditionally, and with the workaround here in place), which yielded the same behavior. --- a/xen/drivers/passthrough/vtd/iommu.c +++ b/xen/drivers/passthrough/vtd/iommu.c @@ -43,6 +43,9 @@ #include "vtd.h" #include "../ats.h" =20 +#define CONTIG_MASK DMA_PTE_CONTIG_MASK +#include + /* dom_io is used as a sentinel for quarantined devices */ #define QUARANTINE_SKIP(d, pgd_maddr) ((d) =3D=3D dom_io && !(pgd_maddr)) #define DEVICE_DOMID(d, pdev) ((d) !=3D dom_io ? (d)->domain_id \ @@ -405,6 +408,9 @@ static uint64_t addr_to_dma_page_maddr(s =20 write_atomic(&pte->val, new_pte.val); iommu_sync_cache(pte, sizeof(struct dma_pte)); + pt_update_contig_markers(&parent->val, + address_level_offset(addr, level), + level, PTE_kind_table); } =20 if ( --level =3D=3D target ) @@ -837,9 +843,31 @@ static int dma_pte_clear_one(struct doma =20 old =3D *pte; dma_clear_pte(*pte); + iommu_sync_cache(pte, sizeof(*pte)); + + while ( pt_update_contig_markers(&page->val, + address_level_offset(addr, level), + level, PTE_kind_null) && + ++level < min_pt_levels ) + { + struct page_info *pg =3D maddr_to_page(pg_maddr); + + unmap_vtd_domain_page(page); + + pg_maddr =3D addr_to_dma_page_maddr(domain, addr, level, flush_fla= gs, + false); + BUG_ON(pg_maddr < PAGE_SIZE); + + page =3D map_vtd_domain_page(pg_maddr); + pte =3D &page[address_level_offset(addr, level)]; + dma_clear_pte(*pte); + iommu_sync_cache(pte, sizeof(*pte)); + + *flush_flags |=3D IOMMU_FLUSHF_all; + iommu_queue_free_pgtable(hd, pg); + } =20 spin_unlock(&hd->arch.mapping_lock); - iommu_sync_cache(pte, sizeof(struct dma_pte)); =20 unmap_vtd_domain_page(page); =20 @@ -2185,8 +2213,21 @@ static int __must_check cf_check intel_i } =20 *pte =3D new; - iommu_sync_cache(pte, sizeof(struct dma_pte)); + + /* + * While the (ab)use of PTE_kind_table here allows to save some work in + * the function, the main motivation for it is that it avoids a so far + * unexplained hang during boot (while preparing Dom0) on a Westmere + * based laptop. + */ + pt_update_contig_markers(&page->val, + address_level_offset(dfn_to_daddr(dfn), level= ), + level, + (hd->platform_ops->page_sizes & + (1UL << level_to_offset_bits(level + 1)) + ? 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charset="utf-8" When a page table ends up with all contiguous entries (including all identical attributes), it can be replaced by a superpage entry at the next higher level. The page table itself can then be scheduled for freeing. Signed-off-by: Jan Beulich Reviewed-by: Roger Pau Monn=C3=A9 --- Unlike the freeing of all-empty page tables, this causes quite a bit of back and forth for PV domains, due to their mapping/unmapping of pages when they get converted to/from being page tables. It may therefore be worth considering to delay re-coalescing a little, to avoid doing so when the superpage would otherwise get split again pretty soon. But I think this would better be the subject of a separate change anyway. Of course this could also be helped by more "aware" kernel side behavior: They could avoid immediately mapping freed page tables writable again, in anticipation of re-using that same page for another page table elsewhere. --- v4: Re-base over changes earlier in the series. v3: New. --- a/xen/drivers/passthrough/amd/iommu_map.c +++ b/xen/drivers/passthrough/amd/iommu_map.c @@ -81,7 +81,8 @@ static union amd_iommu_pte set_iommu_pte unsigned long dfn, unsigned long next_mfn, unsigned int level, - bool iw, bool ir) + bool iw, bool ir, + bool *contig) { union amd_iommu_pte *table, *pde, old; =20 @@ -94,11 +95,15 @@ static union amd_iommu_pte set_iommu_pte old.iw !=3D iw || old.ir !=3D ir ) { set_iommu_pde_present(pde, next_mfn, 0, iw, ir); - pt_update_contig_markers(&table->raw, pfn_to_pde_idx(dfn, level), - level, PTE_kind_leaf); + *contig =3D pt_update_contig_markers(&table->raw, + pfn_to_pde_idx(dfn, level), + level, PTE_kind_leaf); } else + { old.pr =3D false; /* signal "no change" to the caller */ + *contig =3D false; + } =20 unmap_domain_page(table); =20 @@ -409,6 +414,7 @@ int cf_check amd_iommu_map_page( { struct domain_iommu *hd =3D dom_iommu(d); unsigned int level =3D (IOMMUF_order(flags) / PTE_PER_TABLE_SHIFT) + 1; + bool contig; int rc; unsigned long pt_mfn =3D 0; union amd_iommu_pte old; @@ -452,8 +458,26 @@ int cf_check amd_iommu_map_page( =20 /* Install mapping */ old =3D set_iommu_pte_present(pt_mfn, dfn_x(dfn), mfn_x(mfn), level, - (flags & IOMMUF_writable), - (flags & IOMMUF_readable)); + flags & IOMMUF_writable, + flags & IOMMUF_readable, &contig); + + while ( unlikely(contig) && ++level < hd->arch.amd.paging_mode ) + { + struct page_info *pg =3D mfn_to_page(_mfn(pt_mfn)); + unsigned long next_mfn; + + if ( iommu_pde_from_dfn(d, dfn_x(dfn), level, &pt_mfn, flush_flags, + false) ) + BUG(); + BUG_ON(!pt_mfn); + + next_mfn =3D mfn_x(mfn) & (~0UL << (PTE_PER_TABLE_SHIFT * (level -= 1))); + set_iommu_pte_present(pt_mfn, dfn_x(dfn), next_mfn, level, + flags & IOMMUF_writable, + flags & IOMMUF_readable, &contig); + *flush_flags |=3D IOMMU_FLUSHF_modified | IOMMU_FLUSHF_all; + iommu_queue_free_pgtable(hd, pg); + } =20 spin_unlock(&hd->arch.mapping_lock); =20 From nobody Sat May 18 08:14:11 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; arc=pass (i=1 dmarc=pass fromdomain=suse.com); dmarc=pass(p=quarantine dis=none) header.from=suse.com ARC-Seal: i=2; a=rsa-sha256; t=1653650528; cv=pass; d=zohomail.com; s=zohoarc; b=bjCbwWrWlpD2upk7SSPyg4NXX1AyHLKY8Xp34X9A6lRKoDHitgUORI1+U3WXPqXJSINO1939PzatqVHg5Q9/PNEMuRjA9bh8dn1bV3PFgO5cPQjuYc9FblGmqaptdjFx2FOqCUXLry7Q5veeKQZUaBItHJAN5Qhw/cjHBBVFhek= ARC-Message-Signature: i=2; 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charset="utf-8" When a page table ends up with all contiguous entries (including all identical attributes), it can be replaced by a superpage entry at the next higher level. The page table itself can then be scheduled for freeing. The adjustment to LEVEL_MASK is merely to avoid leaving a latent trap for whenever we (and obviously hardware) start supporting 512G mappings. Note that cache sync-ing is likely more strict than necessary. This is both to be on the safe side as well as to maintain the pattern of all updates of (potentially) live tables being accompanied by a flush (if so needed). Signed-off-by: Jan Beulich Reviewed-by: Kevin Tian Reviewed-by: Roger Pau Monn=C3=A9 --- Unlike the freeing of all-empty page tables, this causes quite a bit of back and forth for PV domains, due to their mapping/unmapping of pages when they get converted to/from being page tables. It may therefore be worth considering to delay re-coalescing a little, to avoid doing so when the superpage would otherwise get split again pretty soon. But I think this would better be the subject of a separate change anyway. Of course this could also be helped by more "aware" kernel side behavior: They could avoid immediately mapping freed page tables writable again, in anticipation of re-using that same page for another page table elsewhere. --- v4: Re-base over changes earlier in the series. v3: New. --- a/xen/drivers/passthrough/vtd/iommu.c +++ b/xen/drivers/passthrough/vtd/iommu.c @@ -2219,14 +2219,35 @@ static int __must_check cf_check intel_i * While the (ab)use of PTE_kind_table here allows to save some work in * the function, the main motivation for it is that it avoids a so far * unexplained hang during boot (while preparing Dom0) on a Westmere - * based laptop. + * based laptop. This also has the intended effect of terminating the + * loop when super pages aren't supported anymore at the next level. */ - pt_update_contig_markers(&page->val, - address_level_offset(dfn_to_daddr(dfn), level= ), - level, - (hd->platform_ops->page_sizes & - (1UL << level_to_offset_bits(level + 1)) - ? PTE_kind_leaf : PTE_kind_table)); + while ( pt_update_contig_markers(&page->val, + address_level_offset(dfn_to_daddr(dfn= ), level), + level, + (hd->platform_ops->page_sizes & + (1UL << level_to_offset_bits(level += 1)) + ? PTE_kind_leaf : PTE_kind_table)) ) + { + struct page_info *pg =3D maddr_to_page(pg_maddr); + + unmap_vtd_domain_page(page); + + new.val &=3D ~(LEVEL_MASK << level_to_offset_bits(level)); + dma_set_pte_superpage(new); + + pg_maddr =3D addr_to_dma_page_maddr(d, dfn_to_daddr(dfn), ++level, + flush_flags, false); + BUG_ON(pg_maddr < PAGE_SIZE); + + page =3D map_vtd_domain_page(pg_maddr); + pte =3D &page[address_level_offset(dfn_to_daddr(dfn), level)]; + *pte =3D new; + iommu_sync_cache(pte, sizeof(*pte)); + + *flush_flags |=3D IOMMU_FLUSHF_modified | IOMMU_FLUSHF_all; + iommu_queue_free_pgtable(hd, pg); + } =20 spin_unlock(&hd->arch.mapping_lock); unmap_vtd_domain_page(page); --- a/xen/drivers/passthrough/vtd/iommu.h +++ b/xen/drivers/passthrough/vtd/iommu.h @@ -232,7 +232,7 @@ struct context_entry { =20 /* page table handling */ #define LEVEL_STRIDE (9) -#define LEVEL_MASK ((1 << LEVEL_STRIDE) - 1) +#define LEVEL_MASK (PTE_NUM - 1UL) #define PTE_NUM (1 << LEVEL_STRIDE) #define level_to_agaw(val) ((val) - 2) #define agaw_to_level(val) ((val) + 2) From nobody Sat May 18 08:14:11 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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charset="utf-8" Signed-off-by: Jan Beulich Reviewed-by: Kevin tian Reviewed-by: Roger Pau Monn=C3=A9 --- v3: New. --- a/xen/arch/x86/include/asm/perfc_defn.h +++ b/xen/arch/x86/include/asm/perfc_defn.h @@ -125,4 +125,7 @@ PERFCOUNTER(realmode_exits, "vmexit =20 PERFCOUNTER(pauseloop_exits, "vmexits from Pause-Loop Detection") =20 +PERFCOUNTER(iommu_pt_shatters, "IOMMU page table shatters") +PERFCOUNTER(iommu_pt_coalesces, "IOMMU page table coalesces") + /*#endif*/ /* __XEN_PERFC_DEFN_H__ */ --- a/xen/drivers/passthrough/amd/iommu_map.c +++ b/xen/drivers/passthrough/amd/iommu_map.c @@ -345,6 +345,8 @@ static int iommu_pde_from_dfn(struct dom level, PTE_kind_table); =20 *flush_flags |=3D IOMMU_FLUSHF_modified; + + perfc_incr(iommu_pt_shatters); } =20 /* Install lower level page table for non-present entries */ @@ -477,6 +479,7 @@ int cf_check amd_iommu_map_page( flags & IOMMUF_readable, &contig); *flush_flags |=3D IOMMU_FLUSHF_modified | IOMMU_FLUSHF_all; iommu_queue_free_pgtable(hd, pg); + perfc_incr(iommu_pt_coalesces); } =20 spin_unlock(&hd->arch.mapping_lock); @@ -543,6 +546,7 @@ int cf_check amd_iommu_unmap_page( clear_iommu_pte_present(pt_mfn, dfn_x(dfn), level, &free); *flush_flags |=3D IOMMU_FLUSHF_all; iommu_queue_free_pgtable(hd, pg); + perfc_incr(iommu_pt_coalesces); } } =20 --- a/xen/drivers/passthrough/vtd/iommu.c +++ b/xen/drivers/passthrough/vtd/iommu.c @@ -404,6 +404,8 @@ static uint64_t addr_to_dma_page_maddr(s =20 if ( flush_flags ) *flush_flags |=3D IOMMU_FLUSHF_modified; + + perfc_incr(iommu_pt_shatters); } =20 write_atomic(&pte->val, new_pte.val); @@ -865,6 +867,7 @@ static int dma_pte_clear_one(struct doma =20 *flush_flags |=3D IOMMU_FLUSHF_all; iommu_queue_free_pgtable(hd, pg); + perfc_incr(iommu_pt_coalesces); } =20 spin_unlock(&hd->arch.mapping_lock); @@ -2247,6 +2250,7 @@ static int __must_check cf_check intel_i =20 *flush_flags |=3D IOMMU_FLUSHF_modified | IOMMU_FLUSHF_all; iommu_queue_free_pgtable(hd, pg); + perfc_incr(iommu_pt_coalesces); } =20 spin_unlock(&hd->arch.mapping_lock); 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charset="utf-8" With iommu_flush_iotlb_all() gone, iommu_flush_iotlb_pages() is merely a wrapper around the not otherwise called iommu_flush_iotlb(). Fold both functions. No functional change intended. Signed-off-by: Jan Beulich Reviewed-by: Kevin Tian Reviewed-by: Roger Pau Monn=C3=A9 --- v4: New. --- a/xen/drivers/passthrough/vtd/iommu.c +++ b/xen/drivers/passthrough/vtd/iommu.c @@ -728,9 +728,9 @@ static int __must_check iommu_flush_all( return rc; } =20 -static int __must_check iommu_flush_iotlb(struct domain *d, dfn_t dfn, - bool_t dma_old_pte_present, - unsigned long page_count) +static int __must_check cf_check iommu_flush_iotlb(struct domain *d, dfn_t= dfn, + unsigned long page_coun= t, + unsigned int flush_flag= s) { struct domain_iommu *hd =3D dom_iommu(d); struct acpi_drhd_unit *drhd; @@ -739,6 +739,17 @@ static int __must_check iommu_flush_iotl int iommu_domid; int ret =3D 0; =20 + if ( flush_flags & IOMMU_FLUSHF_all ) + { + dfn =3D INVALID_DFN; + page_count =3D 0; + } + else + { + ASSERT(page_count && !dfn_eq(dfn, INVALID_DFN)); + ASSERT(flush_flags); + } + /* * No need pcideves_lock here because we have flush * when assign/deassign device @@ -765,7 +776,7 @@ static int __must_check iommu_flush_iotl rc =3D iommu_flush_iotlb_psi(iommu, iommu_domid, dfn_to_daddr(dfn), get_order_from_pages(page_count), - !dma_old_pte_present, + !(flush_flags & IOMMU_FLUSHF_modifi= ed), flush_dev_iotlb); =20 if ( rc > 0 ) @@ -777,25 +788,6 @@ static int __must_check iommu_flush_iotl return ret; } =20 -static int __must_check cf_check iommu_flush_iotlb_pages( - struct domain *d, dfn_t dfn, unsigned long page_count, - unsigned int flush_flags) -{ - if ( flush_flags & IOMMU_FLUSHF_all ) - { - dfn =3D INVALID_DFN; - page_count =3D 0; - } - else - { - ASSERT(page_count && !dfn_eq(dfn, INVALID_DFN)); - ASSERT(flush_flags); - } - - return iommu_flush_iotlb(d, dfn, flush_flags & IOMMU_FLUSHF_modified, - page_count); -} - static void queue_free_pt(struct domain_iommu *hd, mfn_t mfn, unsigned int= level) { if ( level > 1 ) @@ -3266,7 +3258,7 @@ static const struct iommu_ops __initcons .suspend =3D vtd_suspend, .resume =3D vtd_resume, .crash_shutdown =3D vtd_crash_shutdown, - .iotlb_flush =3D iommu_flush_iotlb_pages, + .iotlb_flush =3D iommu_flush_iotlb, .get_reserved_device_memory =3D intel_iommu_get_reserved_device_memory, .dump_page_tables =3D vtd_dump_page_tables, }; From nobody Sat May 18 08:14:11 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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charset="utf-8" This way intel_iommu_unmap_page() ends up quite a bit more similar to intel_iommu_map_page(). No functional change intended. Signed-off-by: Jan Beulich Reviewed-by: Kevin Tian Reviewed-by: Roger Pau Monn=C3=A9 --- v5: Re-base of changes earlier in the series. v4: New. --- a/xen/drivers/passthrough/vtd/iommu.c +++ b/xen/drivers/passthrough/vtd/iommu.c @@ -806,75 +806,6 @@ static void queue_free_pt(struct domain_ iommu_queue_free_pgtable(hd, mfn_to_page(mfn)); } =20 -/* clear one page's page table */ -static int dma_pte_clear_one(struct domain *domain, daddr_t addr, - unsigned int order, - unsigned int *flush_flags) -{ - struct domain_iommu *hd =3D dom_iommu(domain); - struct dma_pte *page =3D NULL, *pte =3D NULL, old; - u64 pg_maddr; - unsigned int level =3D (order / LEVEL_STRIDE) + 1; - - spin_lock(&hd->arch.mapping_lock); - /* get target level pte */ - pg_maddr =3D addr_to_dma_page_maddr(domain, addr, level, flush_flags, = false); - if ( pg_maddr < PAGE_SIZE ) - { - spin_unlock(&hd->arch.mapping_lock); - return pg_maddr ? -ENOMEM : 0; - } - - page =3D (struct dma_pte *)map_vtd_domain_page(pg_maddr); - pte =3D &page[address_level_offset(addr, level)]; - - if ( !dma_pte_present(*pte) ) - { - spin_unlock(&hd->arch.mapping_lock); - unmap_vtd_domain_page(page); - return 0; - } - - old =3D *pte; - dma_clear_pte(*pte); - iommu_sync_cache(pte, sizeof(*pte)); - - while ( pt_update_contig_markers(&page->val, - address_level_offset(addr, level), - level, PTE_kind_null) && - ++level < min_pt_levels ) - { - struct page_info *pg =3D maddr_to_page(pg_maddr); - - unmap_vtd_domain_page(page); - - pg_maddr =3D addr_to_dma_page_maddr(domain, addr, level, flush_fla= gs, - false); - BUG_ON(pg_maddr < PAGE_SIZE); - - page =3D map_vtd_domain_page(pg_maddr); - pte =3D &page[address_level_offset(addr, level)]; - dma_clear_pte(*pte); - iommu_sync_cache(pte, sizeof(*pte)); - - *flush_flags |=3D IOMMU_FLUSHF_all; - iommu_queue_free_pgtable(hd, pg); - perfc_incr(iommu_pt_coalesces); - } - - spin_unlock(&hd->arch.mapping_lock); - - unmap_vtd_domain_page(page); - - *flush_flags |=3D IOMMU_FLUSHF_modified; - - if ( order && !dma_pte_superpage(old) ) - queue_free_pt(hd, maddr_to_mfn(dma_pte_addr(old)), - order / LEVEL_STRIDE); - - return 0; -} - static int iommu_set_root_entry(struct vtd_iommu *iommu) { u32 sts; @@ -2264,11 +2195,17 @@ static int __must_check cf_check intel_i static int __must_check cf_check intel_iommu_unmap_page( struct domain *d, dfn_t dfn, unsigned int order, unsigned int *flush_f= lags) { + struct domain_iommu *hd =3D dom_iommu(d); + daddr_t addr =3D dfn_to_daddr(dfn); + struct dma_pte *page =3D NULL, *pte =3D NULL, old; + uint64_t pg_maddr; + unsigned int level =3D (order / LEVEL_STRIDE) + 1; + /* * While really we could unmap at any granularity, for now we assume u= nmaps * are issued by common code only at the same granularity as maps. */ - ASSERT((dom_iommu(d)->platform_ops->page_sizes >> order) & PAGE_SIZE_4= K); + ASSERT((hd->platform_ops->page_sizes >> order) & PAGE_SIZE_4K); =20 /* Do nothing if VT-d shares EPT page table */ if ( iommu_use_hap_pt(d) ) @@ -2278,7 +2215,62 @@ static int __must_check cf_check intel_i if ( iommu_hwdom_passthrough && is_hardware_domain(d) ) return 0; =20 - return dma_pte_clear_one(d, dfn_to_daddr(dfn), order, flush_flags); + spin_lock(&hd->arch.mapping_lock); + /* get target level pte */ + pg_maddr =3D addr_to_dma_page_maddr(d, addr, level, flush_flags, false= ); + if ( pg_maddr < PAGE_SIZE ) + { + spin_unlock(&hd->arch.mapping_lock); + return pg_maddr ? -ENOMEM : 0; + } + + page =3D map_vtd_domain_page(pg_maddr); + pte =3D &page[address_level_offset(addr, level)]; + + if ( !dma_pte_present(*pte) ) + { + spin_unlock(&hd->arch.mapping_lock); + unmap_vtd_domain_page(page); + return 0; + } + + old =3D *pte; + dma_clear_pte(*pte); + iommu_sync_cache(pte, sizeof(*pte)); + + while ( pt_update_contig_markers(&page->val, + address_level_offset(addr, level), + level, PTE_kind_null) && + ++level < min_pt_levels ) + { + struct page_info *pg =3D maddr_to_page(pg_maddr); + + unmap_vtd_domain_page(page); + + pg_maddr =3D addr_to_dma_page_maddr(d, addr, level, flush_flags, f= alse); + BUG_ON(pg_maddr < PAGE_SIZE); + + page =3D map_vtd_domain_page(pg_maddr); + pte =3D &page[address_level_offset(addr, level)]; + dma_clear_pte(*pte); + iommu_sync_cache(pte, sizeof(*pte)); + + *flush_flags |=3D IOMMU_FLUSHF_all; + iommu_queue_free_pgtable(hd, pg); + perfc_incr(iommu_pt_coalesces); + } + + spin_unlock(&hd->arch.mapping_lock); + + unmap_vtd_domain_page(page); + + *flush_flags |=3D IOMMU_FLUSHF_modified; + + if ( order && !dma_pte_superpage(old) ) + queue_free_pt(hd, maddr_to_mfn(dma_pte_addr(old)), + order / LEVEL_STRIDE); + + return 0; } =20 static int cf_check intel_iommu_lookup_page(