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[37.24.206.209]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a93c2945f2esm519701466b.117.2024.09.30.04.57.57 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 30 Sep 2024 04:57:57 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 3c41286c-7f23-11ef-a0ba-8be0dac302b0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=google; t=1727697478; x=1728302278; darn=lists.xenproject.org; h=content-transfer-encoding:in-reply-to:autocrypt:content-language :references:cc:to:from:subject:user-agent:mime-version:date :message-id:from:to:cc:subject:date:message-id:reply-to; bh=IwGX/SkbzLq4zJqJalyoWTF+TyvScc7TAFVMyq5kwXg=; b=gKybBAt1GwN4RUcd7hpuWgKOhgLTTCOLGGEtHpGCP9ahc6CeL/aqSSBvz8DUlsrkDJ eriH+CG14LZGjkCw5aiyRrbH9nJ8lfeQmsjD07rXcWaPDK7QfC6t9Uz1Gt4o4I+hl+lD 6Ft4qpE0Qx7EqqIA3mxsO75tOYsEldOj9NkrwRAj10NtlyrLGkOEDXuLIlh4f2rkcCxk KbZmt1bTgCPPcfWHnh56ATYv0/q3vNVk7KQWgS5RDoAfuBnJYhfhvl/dlW3Q/aX0UAEH hIIdNLKP/ZBBO1SBWlAYyaY6jRl8doqkm40ZKMDbo7QmV4d7fuE3onk73pdF8kZ21TaZ ErxQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1727697478; x=1728302278; h=content-transfer-encoding:in-reply-to:autocrypt:content-language :references:cc:to:from:subject:user-agent:mime-version:date :message-id:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=IwGX/SkbzLq4zJqJalyoWTF+TyvScc7TAFVMyq5kwXg=; b=xOU/KS/nMwhtTNQycHa1kevM08ayyHtHVhnFVBVUZblQK1ISH4Z5LrNbY9Vf+rCFil 8lLVobW9L4ffUehCiAkvsrdX/PPsI9StIwyk3VI3a+heYpBaUFMvDp/HHdsnnna1/6ll hNAR/nG6nEefVCm8PeS99vh/Ql27jf/P8+IUrb/NkLNT9k0Wmt4gqQYNJC1leB+vIqrW SCnVNdxcLguO8xszBfTZkNgRgKSHqEE7n0OC7LLRT5QxeYs+gcQX2OQ4lD9dKti96mjq pCJKadaw/+y3Rf++JWDcDW2FjNbjabJAyLqVxYeyAN+GqjpaAHGedzKU5/2ZqrzKOe+s H6Mw== X-Gm-Message-State: AOJu0Yz69GnsGRnEPyU9VAdf3SZF1hlSECaRL1A8rSay7eR4PCEZYjDQ Cwf8INF458BhYv7vIUexpFHuLbc7Uh4Gh83v3ovPy6qSMW7Vul98+bmzb3reKWOhg39F0ehTdng = X-Google-Smtp-Source: AGHT+IFLuerBbh6NdD+AmEvpPMlz1l2JojqYKRPb2jM+uS7+oCECo8D2UA7aNLMmFTJLo7o0B+7dCg== X-Received: by 2002:a17:907:3203:b0:a86:851e:3a2b with SMTP id a640c23a62f3a-a93c49299e7mr1247644966b.29.1727697477453; Mon, 30 Sep 2024 04:57:57 -0700 (PDT) Message-ID: <7c186e8f-1902-4688-a29a-d59cf5c84709@suse.com> Date: Mon, 30 Sep 2024 13:57:56 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH v6 1/5] x86emul: support LKGS From: Jan Beulich To: "xen-devel@lists.xenproject.org" Cc: Andrew Cooper , Wei Liu , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= References: <88b00dbf-b095-4ce2-9365-2a195ca0d65c@suse.com> Content-Language: en-US Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <88b00dbf-b095-4ce2-9365-2a195ca0d65c@suse.com> Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @suse.com) X-ZM-MESSAGEID: 1727697506442116600 Content-Type: text/plain; charset="utf-8" Provide support for this insn, which is a prereq to FRED. CPUID-wise introduce both its, FRED's, and the NMI_SRC bit at this occasion, thus allowing to also express the dependency right away. While adding a testcase, also add a SWAPGS one. In order to not affect the behavior of pre-existing tests, install write_{segment,msr} hooks only transiently. Signed-off-by: Jan Beulich --- Instead of ->read_segment() we could of course also use ->read_msr() to fetch the original GS base. I don't think I can see a clear advantage of either approach; the way it's done it matches how we handle SWAPGS. For PV save_segments() would need adjustment, but the insn being restricted to ring 0 means PV guests can't use it anyway (unless we wanted to emulate it as another privileged insn). --- v6: Use MSR constants in test harness. S->s in cpufeatureset.h. Add NMI_SRC feature bits. Re-base. v5: Re-base. v3: Add dependency on LM. Re-base. v2: Use X86_EXC_*. Add comments. --- a/tools/tests/x86_emulator/predicates.c +++ b/tools/tests/x86_emulator/predicates.c @@ -326,6 +326,7 @@ static const struct { { { 0x00, 0x18 }, { 2, 2 }, T, R }, /* ltr */ { { 0x00, 0x20 }, { 2, 2 }, T, R }, /* verr */ { { 0x00, 0x28 }, { 2, 2 }, T, R }, /* verw */ + { { 0x00, 0x30 }, { 0, 2 }, T, R, pfx_f2 }, /* lkgs */ { { 0x01, 0x00 }, { 2, 2 }, F, W }, /* sgdt */ { { 0x01, 0x08 }, { 2, 2 }, F, W }, /* sidt */ { { 0x01, 0x10 }, { 2, 2 }, F, R }, /* lgdt */ --- a/tools/tests/x86_emulator/test_x86_emulator.c +++ b/tools/tests/x86_emulator/test_x86_emulator.c @@ -672,6 +672,10 @@ static int blk( return x86_emul_blk((void *)offset, p_data, bytes, eflags, state, ctxt= ); } =20 +#ifdef __x86_64__ +static unsigned long gs_base, gs_base_shadow; +#endif + static int read_segment( enum x86_segment seg, struct segment_register *reg, @@ -681,8 +685,30 @@ static int read_segment( return X86EMUL_UNHANDLEABLE; memset(reg, 0, sizeof(*reg)); reg->p =3D 1; + +#ifdef __x86_64__ + if ( seg =3D=3D x86_seg_gs ) + reg->base =3D gs_base; +#endif + + return X86EMUL_OKAY; +} + +#ifdef __x86_64__ +static int write_segment( + enum x86_segment seg, + const struct segment_register *reg, + struct x86_emulate_ctxt *ctxt) +{ + if ( !is_x86_user_segment(seg) ) + return X86EMUL_UNHANDLEABLE; + + if ( seg =3D=3D x86_seg_gs ) + gs_base =3D reg->base; + return X86EMUL_OKAY; } +#endif =20 static int read_msr( unsigned int reg, @@ -695,6 +721,20 @@ static int read_msr( *val =3D ctxt->addr_size > 32 ? EFER_LME | EFER_LMA : 0; return X86EMUL_OKAY; =20 +#ifdef __x86_64__ + case MSR_GS_BASE: + if ( ctxt->addr_size < 64 ) + break; + *val =3D gs_base; + return X86EMUL_OKAY; + + case MSR_SHADOW_GS_BASE: + if ( ctxt->addr_size < 64 ) + break; + *val =3D gs_base_shadow; + return X86EMUL_OKAY; +#endif + case MSR_TSC_AUX: #define TSC_AUX_VALUE 0xCACACACA *val =3D TSC_AUX_VALUE; @@ -704,6 +744,31 @@ static int read_msr( return X86EMUL_UNHANDLEABLE; } =20 +#ifdef __x86_64__ +static int write_msr( + unsigned int reg, + uint64_t val, + struct x86_emulate_ctxt *ctxt) +{ + switch ( reg ) + { + case MSR_GS_BASE: + if ( ctxt->addr_size < 64 || !is_canonical_address(val) ) + break; + gs_base =3D val; + return X86EMUL_OKAY; + + case MSR_SHADOW_GS_BASE: + if ( ctxt->addr_size < 64 || !is_canonical_address(val) ) + break; + gs_base_shadow =3D val; + return X86EMUL_OKAY; + } + + return X86EMUL_UNHANDLEABLE; +} +#endif + #define INVPCID_ADDR 0x12345678 #define INVPCID_PCID 0x123 =20 @@ -1338,6 +1403,41 @@ int main(int argc, char **argv) printf("%u bytes read - ", bytes_read); goto fail; } + printf("okay\n"); + + emulops.write_segment =3D write_segment; + emulops.write_msr =3D write_msr; + + printf("%-40s", "Testing swapgs..."); + instr[0] =3D 0x0f; instr[1] =3D 0x01; instr[2] =3D 0xf8; + regs.eip =3D (unsigned long)&instr[0]; + gs_base =3D 0xffffeeeecccc8888UL; + gs_base_shadow =3D 0x0000111122224444UL; + rc =3D x86_emulate(&ctxt, &emulops); + if ( (rc !=3D X86EMUL_OKAY) || + (regs.eip !=3D (unsigned long)&instr[3]) || + (gs_base !=3D 0x0000111122224444UL) || + (gs_base_shadow !=3D 0xffffeeeecccc8888UL) ) + goto fail; + printf("okay\n"); + + printf("%-40s", "Testing lkgs 2(%rdx)..."); + instr[0] =3D 0xf2; instr[1] =3D 0x0f; instr[2] =3D 0x00; instr[3] =3D = 0x72; instr[4] =3D 0x02; + regs.eip =3D (unsigned long)&instr[0]; + regs.edx =3D (unsigned long)res; + res[0] =3D 0x00004444; + res[1] =3D 0x8888cccc; + i =3D cpu_policy.extd.nscb; cpu_policy.extd.nscb =3D true; /* for AMD = */ + rc =3D x86_emulate(&ctxt, &emulops); + if ( (rc !=3D X86EMUL_OKAY) || + (regs.eip !=3D (unsigned long)&instr[5]) || + (gs_base !=3D 0x0000111122224444UL) || + gs_base_shadow ) + goto fail; + + cpu_policy.extd.nscb =3D i; + emulops.write_segment =3D NULL; + emulops.write_msr =3D NULL; #endif printf("okay\n"); =20 --- a/tools/tests/x86_emulator/x86-emulate.c +++ b/tools/tests/x86_emulator/x86-emulate.c @@ -85,6 +85,7 @@ bool emul_test_init(void) cpu_policy.feat.invpcid =3D true; cpu_policy.feat.adx =3D true; cpu_policy.feat.rdpid =3D true; + cpu_policy.feat.lkgs =3D true; cpu_policy.feat.wrmsrns =3D true; cpu_policy.extd.clzero =3D true; =20 --- a/xen/arch/x86/x86_emulate/decode.c +++ b/xen/arch/x86/x86_emulate/decode.c @@ -744,8 +744,12 @@ decode_twobyte(struct x86_emulate_state case 0: s->desc |=3D DstMem | SrcImplicit | Mov; break; + case 6: + if ( !(s->modrm_reg & 1) && mode_64bit() ) + { case 2: case 4: - s->desc |=3D SrcMem16; + s->desc |=3D SrcMem16; + } break; } break; --- a/xen/arch/x86/x86_emulate/private.h +++ b/xen/arch/x86/x86_emulate/private.h @@ -594,6 +594,7 @@ amd_like(const struct x86_emulate_ctxt * #define vcpu_has_avx_vnni() (ctxt->cpuid->feat.avx_vnni) #define vcpu_has_avx512_bf16() (ctxt->cpuid->feat.avx512_bf16) #define vcpu_has_cmpccxadd() (ctxt->cpuid->feat.cmpccxadd) +#define vcpu_has_lkgs() (ctxt->cpuid->feat.lkgs) #define vcpu_has_wrmsrns() (ctxt->cpuid->feat.wrmsrns) #define vcpu_has_avx_ifma() (ctxt->cpuid->feat.avx_ifma) #define vcpu_has_avx_vnni_int8() (ctxt->cpuid->feat.avx_vnni_int8) --- a/xen/arch/x86/x86_emulate/x86_emulate.c +++ b/xen/arch/x86/x86_emulate/x86_emulate.c @@ -2871,8 +2871,35 @@ x86_emulate( break; } break; - default: - generate_exception_if(true, X86_EXC_UD); + case 6: /* lkgs */ + generate_exception_if((modrm_reg & 1) || vex.pfx !=3D vex_f2, + X86_EXC_UD); + generate_exception_if(!mode_64bit() || !mode_ring0(), X86_EXC_= UD); + vcpu_must_have(lkgs); + fail_if(!ops->read_segment || !ops->read_msr || + !ops->write_segment || !ops->write_msr); + if ( (rc =3D ops->read_msr(MSR_SHADOW_GS_BASE, &msr_val, + ctxt)) !=3D X86EMUL_OKAY || + (rc =3D ops->read_segment(x86_seg_gs, &sreg, + ctxt)) !=3D X86EMUL_OKAY ) + goto done; + dst.orig_val =3D sreg.base; /* Preserve full GS Base. */ + if ( (rc =3D protmode_load_seg(x86_seg_gs, src.val, false, &sr= eg, + ctxt, ops)) !=3D X86EMUL_OKAY || + /* Write (32-bit) base into SHADOW_GS. */ + (rc =3D ops->write_msr(MSR_SHADOW_GS_BASE, sreg.base, + ctxt)) !=3D X86EMUL_OKAY ) + goto done; + sreg.base =3D dst.orig_val; /* Reinstate full GS Base. */ + if ( (rc =3D ops->write_segment(x86_seg_gs, &sreg, + ctxt)) !=3D X86EMUL_OKAY ) + { + /* Best effort unwind (i.e. no real error checking). */ + if ( ops->write_msr(MSR_SHADOW_GS_BASE, msr_val, + ctxt) =3D=3D X86EMUL_EXCEPTION ) + x86_emul_reset_event(ctxt); + goto done; + } break; } break; --- a/xen/include/public/arch-x86/cpufeatureset.h +++ b/xen/include/public/arch-x86/cpufeatureset.h @@ -307,7 +307,10 @@ XEN_CPUFEATURE(CMPCCXADD, 10*32+ 7) / XEN_CPUFEATURE(FZRM, 10*32+10) /*A Fast Zero-length REP MOVSB */ XEN_CPUFEATURE(FSRS, 10*32+11) /*A Fast Short REP STOSB */ XEN_CPUFEATURE(FSRCS, 10*32+12) /*A Fast Short REP CMPSB/SCASB */ +XEN_CPUFEATURE(FRED, 10*32+17) /* Flexible Return and Event Deli= very */ +XEN_CPUFEATURE(LKGS, 10*32+18) /*s Load Kernel GS Base */ XEN_CPUFEATURE(WRMSRNS, 10*32+19) /*S WRMSR Non-Serialising */ +XEN_CPUFEATURE(NMI_SRC, 10*32+20) /* NMI-source reporting */ XEN_CPUFEATURE(AMX_FP16, 10*32+21) /* AMX FP16 instruction */ XEN_CPUFEATURE(AVX_IFMA, 10*32+23) /*A AVX-IFMA Instructions */ =20 --- a/xen/tools/gen-cpuid.py +++ b/xen/tools/gen-cpuid.py @@ -274,7 +274,8 @@ def crunch_numbers(state): # superpages, PCID and PKU are only available in 4 level paging. # NO_LMSL indicates the absense of Long Mode Segment Limits, which # have been dropped in hardware. - LM: [CX16, PCID, LAHF_LM, PAGE1GB, PKU, NO_LMSL, AMX_TILE, CMPCCXA= DD], + LM: [CX16, PCID, LAHF_LM, PAGE1GB, PKU, NO_LMSL, AMX_TILE, CMPCCXA= DD, + LKGS], =20 # AMD K6-2+ and K6-III processors shipped with 3DNow+, beyond the # standard 3DNow in the earlier K6 processors. @@ -343,6 +344,9 @@ def crunch_numbers(state): # computational instructions. All further AMX features are built = on top # of AMX-TILE. AMX_TILE: [AMX_BF16, AMX_INT8, AMX_FP16, AMX_COMPLEX], + + # FRED builds on the LKGS instruction. + LKGS: [FRED], } =20 deep_features =3D tuple(sorted(deps.keys()))