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Wed, 04 Jun 2025 02:48:01 -0700 (PDT) Message-ID: <78b3ddeb-4317-4d54-ad52-9eb03bdf7942@suse.com> Date: Wed, 4 Jun 2025 11:48:00 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird From: Jan Beulich Subject: [PATCH v2] x86/HVM: restrict use of pinned cache attributes as well as associated flushing To: "xen-devel@lists.xenproject.org" Cc: Andrew Cooper , Wei Liu , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= Content-Language: en-US Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @suse.com) X-ZM-MESSAGEID: 1749030507785116600 Content-Type: text/plain; charset="utf-8" We don't permit use of uncachable memory types elsewhere unless a domain meets certain criteria. Enforce this also during registration of pinned cache attribute ranges. Furthermore restrict cache flushing to just uncachable range registration. While there, also (mainly be calling memory_type_changed()) - take CPU self-snoop as well as IOMMU snoop into account (albeit the latter still is a global property rather than a per-domain one), - avoid flushes when the domain isn't running yet (which ought to be the common case). Reported-by: Andrew Cooper Signed-off-by: Jan Beulich --- At the expense of yet larger a diff it would be possible to get away without any "goto", by moving the whole "new entry" handling into the switch(). Personally I'd prefer that, but the larger diff may be unwelcome. I have to admit that I can't spot what part of epte_get_entry_emt() the comment refers to that is being deleted. The function does use hvm_get_mem_pinned_cacheattr(), yes, but there's nothing there that talks about cache flushes (and their avoiding) in any way. Is it really sensible to add/remove ranges once the guest is already running? (If it is, limiting the scope of the flush would be nice, but would require knowing dirtyness for the domain wrt the caches, which currently we don't track.) This is kind of amending XSA-428. --- v2: Use memory_type_changed() and conditionalize call to p2m_memory_type_changed(). --- a/xen/arch/x86/hvm/mtrr.c +++ b/xen/arch/x86/hvm/mtrr.c @@ -582,6 +582,7 @@ int hvm_set_mem_pinned_cacheattr(struct { struct hvm_mem_pinned_cacheattr_range *range, *newr; unsigned int nr =3D 0; + bool flush =3D false; int rc =3D 1; =20 if ( !is_hvm_domain(d) ) @@ -605,31 +606,35 @@ int hvm_set_mem_pinned_cacheattr(struct =20 type =3D range->type; call_rcu(&range->rcu, free_pinned_cacheattr_entry); - p2m_memory_type_changed(d); switch ( type ) { - case X86_MT_UCM: + case X86_MT_WB: + case X86_MT_WP: + case X86_MT_WT: /* - * For EPT we can also avoid the flush in this case; - * see epte_get_entry_emt(). + * Flush since we don't know what the cachability is g= oing + * to be. */ - if ( hap_enabled(d) && cpu_has_vmx ) - case X86_MT_UC: - break; - /* fall through */ - default: - flush_all(FLUSH_CACHE); + if ( is_iommu_enabled(d) || cache_flush_permitted(d) ) + flush =3D true; break; } - return 0; + rc =3D 0; + goto finish; } domain_unlock(d); return -ENOENT; =20 case X86_MT_UCM: case X86_MT_UC: - case X86_MT_WB: case X86_MT_WC: + /* Flush since we don't know what the cachability was. */ + if ( !is_iommu_enabled(d) && !cache_flush_permitted(d) ) + return -EPERM; + flush =3D true; + break; + + case X86_MT_WB: case X86_MT_WP: case X86_MT_WT: break; @@ -682,9 +687,11 @@ int hvm_set_mem_pinned_cacheattr(struct =20 xfree(newr); =20 - p2m_memory_type_changed(d); - if ( type !=3D X86_MT_WB ) - flush_all(FLUSH_CACHE); + finish: + if ( flush ) + memory_type_changed(d); + else if ( d->vcpu && d->vcpu[0] ) + p2m_memory_type_changed(d); =20 return rc; }