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mx.microsoft.com 1; spf=pass smtp.mailfrom=suse.com; dmarc=pass action=none header.from=suse.com; dkim=pass header.d=suse.com; arc=none Authentication-Results: xen.org; dkim=none (message not signed) header.d=none;xen.org; dmarc=none action=none header.from=suse.com; Subject: [PATCH v2 09/18] AMD/IOMMU: drop stray TLB flush From: Jan Beulich To: "xen-devel@lists.xenproject.org" Cc: Andrew Cooper , Paul Durrant References: <957f067b-9fe1-2350-4266-51982f09d3a9@suse.com> Message-ID: <6d825fc7-d600-6759-5bc2-ab8b17e4033b@suse.com> Date: Fri, 24 Sep 2021 11:48:57 +0200 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.14.0 In-Reply-To: <957f067b-9fe1-2350-4266-51982f09d3a9@suse.com> Content-Language: en-US Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: FR3P281CA0015.DEUP281.PROD.OUTLOOK.COM (2603:10a6:d10:1d::13) To VI1PR04MB5600.eurprd04.prod.outlook.com (2603:10a6:803:e7::16) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 699ce415-eff7-45cd-7d45-08d97f408877 X-MS-TrafficTypeDiagnostic: VI1PR04MB4383: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:7219; 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charset="utf-8" I think this flush was overlooked when flushing was moved out of the core (un)mapping functions. The flush the caller is required to invoke anyway will satisfy the needs resulting from the splitting of a superpage. Signed-off-by: Jan Beulich Reviewed-by: Roger Pau Monn=C3=A9 --- a/xen/drivers/passthrough/amd/iommu_map.c +++ b/xen/drivers/passthrough/amd/iommu_map.c @@ -179,7 +179,7 @@ void __init iommu_dte_add_device_entry(s */ static int iommu_pde_from_dfn(struct domain *d, unsigned long dfn, unsigned int target, unsigned long *pt_mfn, - bool map) + unsigned int *flush_flags, bool map) { union amd_iommu_pte *pde, *next_table_vaddr; unsigned long next_table_mfn; @@ -237,7 +237,7 @@ static int iommu_pde_from_dfn(struct dom set_iommu_pde_present(pde, next_table_mfn, next_level, true, true); =20 - amd_iommu_flush_all_pages(d); + *flush_flags |=3D IOMMU_FLUSHF_modified; } =20 /* Install lower level page table for non-present entries */ @@ -309,7 +309,8 @@ int amd_iommu_map_page(struct domain *d, return rc; } =20 - if ( iommu_pde_from_dfn(d, dfn_x(dfn), 1, &pt_mfn, true) || !pt_mfn ) + if ( iommu_pde_from_dfn(d, dfn_x(dfn), 1, &pt_mfn, flush_flags, true) = || + !pt_mfn ) { spin_unlock(&hd->arch.mapping_lock); AMD_IOMMU_DEBUG("Invalid IO pagetable entry dfn =3D %"PRI_dfn"\n", @@ -342,7 +343,7 @@ int amd_iommu_unmap_page(struct domain * return 0; } =20 - if ( iommu_pde_from_dfn(d, dfn_x(dfn), 1, &pt_mfn, false) ) + if ( iommu_pde_from_dfn(d, dfn_x(dfn), 1, &pt_mfn, flush_flags, false)= ) { spin_unlock(&hd->arch.mapping_lock); AMD_IOMMU_DEBUG("Invalid IO pagetable entry dfn =3D %"PRI_dfn"\n",