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charset="utf-8" In order to be able to insert/remove super-pages we need to allow callers of the walking function to specify at which point to stop the walk. For intel_iommu_lookup_page() integrate the last level access into the main walking function. dma_pte_clear_one() gets only partly adjusted for now: Error handling and order parameter get put in place, but the order parameter remains ignored (just like intel_iommu_map_page()'s order part of the flags). Signed-off-by: Jan Beulich --- I have to admit that I don't understand why domain_pgd_maddr() wants to populate all page table levels for DFN 0. I was actually wondering whether it wouldn't make sense to integrate dma_pte_clear_one() into its only caller intel_iommu_unmap_page(), for better symmetry with intel_iommu_map_page(). --- v2: Fix build. --- a/xen/drivers/passthrough/vtd/iommu.c +++ b/xen/drivers/passthrough/vtd/iommu.c @@ -264,63 +264,116 @@ static u64 bus_to_context_maddr(struct v return maddr; } =20 -static u64 addr_to_dma_page_maddr(struct domain *domain, u64 addr, int all= oc) +/* + * This function walks (and if requested allocates) page tables to the + * designated target level. It returns + * - 0 when a non-present entry was encountered and no allocation was + * requested, + * - a small positive value (the level, i.e. below PAGE_SIZE) upon allocat= ion + * failure, + * - for target > 0 the address of the page table holding the leaf PTE for + * the requested address, + * - for target =3D=3D 0 the full PTE. + */ +static uint64_t addr_to_dma_page_maddr(struct domain *domain, daddr_t addr, + unsigned int target, + unsigned int *flush_flags, bool all= oc) { struct domain_iommu *hd =3D dom_iommu(domain); int addr_width =3D agaw_to_width(hd->arch.vtd.agaw); struct dma_pte *parent, *pte =3D NULL; - int level =3D agaw_to_level(hd->arch.vtd.agaw); - int offset; + unsigned int level =3D agaw_to_level(hd->arch.vtd.agaw), offset; u64 pte_maddr =3D 0; =20 addr &=3D (((u64)1) << addr_width) - 1; ASSERT(spin_is_locked(&hd->arch.mapping_lock)); + ASSERT(target || !alloc); + if ( !hd->arch.vtd.pgd_maddr ) { struct page_info *pg; =20 - if ( !alloc || !(pg =3D iommu_alloc_pgtable(domain)) ) + if ( !alloc ) + goto out; + + pte_maddr =3D level; + if ( !(pg =3D iommu_alloc_pgtable(domain)) ) goto out; =20 hd->arch.vtd.pgd_maddr =3D page_to_maddr(pg); } =20 - parent =3D (struct dma_pte *)map_vtd_domain_page(hd->arch.vtd.pgd_madd= r); - while ( level > 1 ) + pte_maddr =3D hd->arch.vtd.pgd_maddr; + parent =3D map_vtd_domain_page(pte_maddr); + while ( level > target ) { offset =3D address_level_offset(addr, level); pte =3D &parent[offset]; =20 pte_maddr =3D dma_pte_addr(*pte); - if ( !pte_maddr ) + if ( !dma_pte_present(*pte) || (level > 1 && dma_pte_superpage(*pt= e)) ) { struct page_info *pg; + /* + * Higher level tables always set r/w, last level page table + * controls read/write. + */ + struct dma_pte new_pte =3D { DMA_PTE_PROT }; =20 if ( !alloc ) - break; + { + pte_maddr =3D 0; + if ( !dma_pte_present(*pte) ) + break; + + /* + * When the leaf entry was requested, pass back the full P= TE, + * with the address adjusted to account for the residual of + * the walk. + */ + pte_maddr =3D pte->val + + (addr & ((1UL << level_to_offset_bits(level)) - 1) & + PAGE_MASK); + if ( !target ) + break; + } =20 + pte_maddr =3D level - 1; pg =3D iommu_alloc_pgtable(domain); if ( !pg ) break; =20 pte_maddr =3D page_to_maddr(pg); - dma_set_pte_addr(*pte, pte_maddr); + dma_set_pte_addr(new_pte, pte_maddr); =20 - /* - * high level table always sets r/w, last level - * page table control read/write - */ - dma_set_pte_readable(*pte); - dma_set_pte_writable(*pte); + if ( dma_pte_present(*pte) ) + { + struct dma_pte *split =3D map_vtd_domain_page(pte_maddr); + unsigned long inc =3D 1UL << level_to_offset_bits(level - = 1); + + split[0].val =3D pte->val; + if ( inc =3D=3D PAGE_SIZE ) + split[0].val &=3D ~DMA_PTE_SP; + + for ( offset =3D 1; offset < PTE_NUM; ++offset ) + split[offset].val =3D split[offset - 1].val + inc; + + iommu_sync_cache(split, PAGE_SIZE); + unmap_vtd_domain_page(split); + + if ( flush_flags ) + *flush_flags |=3D IOMMU_FLUSHF_modified; + } + + write_atomic(&pte->val, new_pte.val); iommu_sync_cache(pte, sizeof(struct dma_pte)); } =20 - if ( level =3D=3D 2 ) + if ( --level =3D=3D target ) break; =20 unmap_vtd_domain_page(parent); parent =3D map_vtd_domain_page(pte_maddr); - level--; } =20 unmap_vtd_domain_page(parent); @@ -346,7 +399,7 @@ static uint64_t domain_pgd_maddr(struct if ( !hd->arch.vtd.pgd_maddr ) { /* Ensure we have pagetables allocated down to leaf PTE. */ - addr_to_dma_page_maddr(d, 0, 1); + addr_to_dma_page_maddr(d, 0, 1, NULL, true); =20 if ( !hd->arch.vtd.pgd_maddr ) return 0; @@ -691,8 +744,9 @@ static int __must_check iommu_flush_iotl } =20 /* clear one page's page table */ -static void dma_pte_clear_one(struct domain *domain, uint64_t addr, - unsigned int *flush_flags) +static int dma_pte_clear_one(struct domain *domain, daddr_t addr, + unsigned int order, + unsigned int *flush_flags) { struct domain_iommu *hd =3D dom_iommu(domain); struct dma_pte *page =3D NULL, *pte =3D NULL; @@ -700,11 +754,11 @@ static void dma_pte_clear_one(struct dom =20 spin_lock(&hd->arch.mapping_lock); /* get last level pte */ - pg_maddr =3D addr_to_dma_page_maddr(domain, addr, 0); - if ( pg_maddr =3D=3D 0 ) + pg_maddr =3D addr_to_dma_page_maddr(domain, addr, 1, flush_flags, fals= e); + if ( pg_maddr < PAGE_SIZE ) { spin_unlock(&hd->arch.mapping_lock); - return; + return pg_maddr ? -ENOMEM : 0; } =20 page =3D (struct dma_pte *)map_vtd_domain_page(pg_maddr); @@ -714,7 +768,7 @@ static void dma_pte_clear_one(struct dom { spin_unlock(&hd->arch.mapping_lock); unmap_vtd_domain_page(page); - return; + return 0; } =20 dma_clear_pte(*pte); @@ -724,6 +778,8 @@ static void dma_pte_clear_one(struct dom iommu_sync_cache(pte, sizeof(struct dma_pte)); =20 unmap_vtd_domain_page(page); + + return 0; } =20 static int iommu_set_root_entry(struct vtd_iommu *iommu) @@ -1836,8 +1892,9 @@ static int __must_check intel_iommu_map_ return 0; } =20 - pg_maddr =3D addr_to_dma_page_maddr(d, dfn_to_daddr(dfn), 1); - if ( !pg_maddr ) + pg_maddr =3D addr_to_dma_page_maddr(d, dfn_to_daddr(dfn), 1, flush_fla= gs, + true); + if ( pg_maddr < PAGE_SIZE ) { spin_unlock(&hd->arch.mapping_lock); return -ENOMEM; @@ -1887,17 +1944,14 @@ static int __must_check intel_iommu_unma if ( iommu_hwdom_passthrough && is_hardware_domain(d) ) return 0; =20 - dma_pte_clear_one(d, dfn_to_daddr(dfn), flush_flags); - - return 0; + return dma_pte_clear_one(d, dfn_to_daddr(dfn), 0, flush_flags); } =20 static int intel_iommu_lookup_page(struct domain *d, dfn_t dfn, mfn_t *mfn, unsigned int *flags) { struct domain_iommu *hd =3D dom_iommu(d); - struct dma_pte *page, val; - u64 pg_maddr; + uint64_t val; =20 /* * If VT-d shares EPT page table or if the domain is the hardware @@ -1909,25 +1963,16 @@ static int intel_iommu_lookup_page(struc =20 spin_lock(&hd->arch.mapping_lock); =20 - pg_maddr =3D addr_to_dma_page_maddr(d, dfn_to_daddr(dfn), 0); - if ( !pg_maddr ) - { - spin_unlock(&hd->arch.mapping_lock); - return -ENOENT; - } - - page =3D map_vtd_domain_page(pg_maddr); - val =3D page[dfn_x(dfn) & LEVEL_MASK]; + val =3D addr_to_dma_page_maddr(d, dfn_to_daddr(dfn), 0, NULL, false); =20 - unmap_vtd_domain_page(page); spin_unlock(&hd->arch.mapping_lock); =20 - if ( !dma_pte_present(val) ) + if ( val < PAGE_SIZE ) return -ENOENT; =20 - *mfn =3D maddr_to_mfn(dma_pte_addr(val)); - *flags =3D dma_pte_read(val) ? IOMMUF_readable : 0; - *flags |=3D dma_pte_write(val) ? IOMMUF_writable : 0; + *mfn =3D maddr_to_mfn(val); + *flags =3D val & DMA_PTE_READ ? IOMMUF_readable : 0; + *flags |=3D val & DMA_PTE_WRITE ? IOMMUF_writable : 0; =20 return 0; }