From nobody Sat Nov 30 10:53:36 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1611154591; cv=none; d=zohomail.com; s=zohoarc; b=k3oVLSRXokDjvQVgjy7Ayy6RMV24RQZ1W6HqIYRVwT/DWkdisOEnyfJ4ElBv64f0qmF/XsHP8SA9IGPvNEPIKSNZDYTk/X/mPCUwOeFlUjG4/k2lg51Y4H9wFJ2IAQF7jBAsgL3CCLowvHFq+Yyr07KWicIb/0/tsSIQ4b8kNuI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1611154591; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=LpQOoJV7e4B5GZ7GCcFCf9O6KD4LU4VZjg1dqXkM488=; b=FkzNYkA7C3zsx+5f11pJU/ixgb4dwn1Ms3NtYav8osfaHNm0C77WZrj1TR2wLXbpaqpi8t1S6bRM7buKdFH9o3iGdfIgPJCfjyF0CdjA/LiOGcYKRqkyvgQrbx+4E8twsLL6qF93gZV/MYM7hrYEBu5wa/tCRFWRexGWDj+RRyA= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1611154591358527.5972812095863; Wed, 20 Jan 2021 06:56:31 -0800 (PST) Received: from list by lists.xenproject.org with outflank-mailman.71489.128074 (Exim 4.92) (envelope-from ) id 1l2EuB-00019Z-Iz; Wed, 20 Jan 2021 14:56:19 +0000 Received: by outflank-mailman (output) from mailman id 71489.128074; Wed, 20 Jan 2021 14:56:19 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1l2EuB-00019S-FU; Wed, 20 Jan 2021 14:56:19 +0000 Received: by outflank-mailman (input) for mailman id 71489; Wed, 20 Jan 2021 14:56:18 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1l2EuA-00016G-Gk for xen-devel@lists.xenproject.org; Wed, 20 Jan 2021 14:56:18 +0000 Received: from foss.arm.com (unknown [217.140.110.172]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTP id dbea5636-9c2d-4901-88e2-8a61b688f87b; Wed, 20 Jan 2021 14:56:14 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C7FB6101E; Wed, 20 Jan 2021 06:56:13 -0800 (PST) Received: from scm-wfh-server-rahsin01.stack04.eu02.mi.arm.com (unknown [10.58.246.76]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id E4D4E3F68F; Wed, 20 Jan 2021 06:56:12 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: dbea5636-9c2d-4901-88e2-8a61b688f87b From: Rahul Singh To: xen-devel@lists.xenproject.org Cc: bertrand.marquis@arm.com, rahul.singh@arm.com, Stefano Stabellini , Julien Grall , Volodymyr Babchuk Subject: [PATCH v5 03/10] xen/arm: smmuv3: Revert patch related to XArray Date: Wed, 20 Jan 2021 14:52:37 +0000 Message-Id: <62949812e62e41505e3ddb645cb979d56659db41.1611153615.git.rahul.singh@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" XArray is not implemented in XEN revert the patch that introduce the XArray code in SMMUv3 driver. XArray is added in preparation for sharing some ASIDs with the CPU, As XEN support only Stage-2 translation, ASID is used for Stage-1 translation there is no consequences of reverting this patch for XEN. Once XArray is implemented in XEN this patch can be added in XEN if XEN supports Stage-1 translation. Reverted the commit 0299a1a81ca056e79c1a7fb751f936ec0d5c7afe Signed-off-by: Rahul Singh Acked-by: Stefano Stabellini --- Changes since v2: - Added consequences of reverting this patch in commit message Changes since v3: No changes Changes since v4: No changes --- --- xen/drivers/passthrough/arm/smmu-v3.c | 27 +++++++++------------------ 1 file changed, 9 insertions(+), 18 deletions(-) diff --git a/xen/drivers/passthrough/arm/smmu-v3.c b/xen/drivers/passthroug= h/arm/smmu-v3.c index 8b7747ed38..7b29ead48c 100644 --- a/xen/drivers/passthrough/arm/smmu-v3.c +++ b/xen/drivers/passthrough/arm/smmu-v3.c @@ -625,6 +625,7 @@ struct arm_smmu_device { =20 #define ARM_SMMU_MAX_ASIDS (1 << 16) unsigned int asid_bits; + DECLARE_BITMAP(asid_map, ARM_SMMU_MAX_ASIDS); =20 #define ARM_SMMU_MAX_VMIDS (1 << 16) unsigned int vmid_bits; @@ -690,8 +691,6 @@ struct arm_smmu_option_prop { const char *prop; }; =20 -static DEFINE_XARRAY_ALLOC1(asid_xa); - static struct arm_smmu_option_prop arm_smmu_options[] =3D { { ARM_SMMU_OPT_SKIP_PREFETCH, "hisilicon,broken-prefetch-cmd" }, { ARM_SMMU_OPT_PAGE0_REGS_ONLY, "cavium,cn9900-broken-page1-regspace"}, @@ -1346,14 +1345,6 @@ static void arm_smmu_free_cd_tables(struct arm_smmu_= domain *smmu_domain) cdcfg->cdtab =3D NULL; } =20 -static void arm_smmu_free_asid(struct arm_smmu_ctx_desc *cd) -{ - if (!cd->asid) - return; - - xa_erase(&asid_xa, cd->asid); -} - /* Stream table manipulation functions */ static void arm_smmu_write_strtab_l1_desc(__le64 *dst, struct arm_smmu_strtab_l1_desc = *desc) @@ -1988,9 +1979,10 @@ static void arm_smmu_domain_free(struct iommu_domain= *domain) if (smmu_domain->stage =3D=3D ARM_SMMU_DOMAIN_S1) { struct arm_smmu_s1_cfg *cfg =3D &smmu_domain->s1_cfg; =20 - if (cfg->cdcfg.cdtab) + if (cfg->cdcfg.cdtab) { arm_smmu_free_cd_tables(smmu_domain); - arm_smmu_free_asid(&cfg->cd); + arm_smmu_bitmap_free(smmu->asid_map, cfg->cd.asid); + } } else { struct arm_smmu_s2_cfg *cfg =3D &smmu_domain->s2_cfg; if (cfg->vmid) @@ -2005,15 +1997,14 @@ static int arm_smmu_domain_finalise_s1(struct arm_s= mmu_domain *smmu_domain, struct io_pgtable_cfg *pgtbl_cfg) { int ret; - u32 asid; + int asid; struct arm_smmu_device *smmu =3D smmu_domain->smmu; struct arm_smmu_s1_cfg *cfg =3D &smmu_domain->s1_cfg; typeof(&pgtbl_cfg->arm_lpae_s1_cfg.tcr) tcr =3D &pgtbl_cfg->arm_lpae_s1_c= fg.tcr; =20 - ret =3D xa_alloc(&asid_xa, &asid, &cfg->cd, - XA_LIMIT(1, (1 << smmu->asid_bits) - 1), GFP_KERNEL); - if (ret) - return ret; + asid =3D arm_smmu_bitmap_alloc(smmu->asid_map, smmu->asid_bits); + if (asid < 0) + return asid; =20 cfg->s1cdmax =3D master->ssid_bits; =20 @@ -2046,7 +2037,7 @@ static int arm_smmu_domain_finalise_s1(struct arm_smm= u_domain *smmu_domain, out_free_cd_tables: arm_smmu_free_cd_tables(smmu_domain); out_free_asid: - arm_smmu_free_asid(&cfg->cd); + arm_smmu_bitmap_free(smmu->asid_map, asid); return ret; } =20 --=20 2.17.1