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[109.243.67.101]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-485359bf807sm119619845e9.2.2026.03.10.10.09.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Mar 2026 10:09:32 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: e916d655-1ca3-11f1-b164-2bf370ae4941 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1773162573; x=1773767373; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=vggNX4iy/s3rYe31fA6JCPRN0nqiyw41a2u9JUGJC2M=; b=A2A7GGJ0CAL4ikMnK2xD81wYIzdXp39h5Zq/4vsUGRd5AAbzcp2wfPNKv4aCeFr04B C4IbuMfaJg+/kwf7iFC7ERmKa2lyb/rL60QRuKtcY+M5bQ0kRLhYbvE82t5yai5yh3rf /avseKkvQXMffFCmcBc/FeMTFbjpP9WW61twM2zGhRBwzJVbBl9DaB5SHGLr+XVJ2J26 uGpNrwjofjMFzPFKjfSnCPe278/WhkG0LOvCONnmF5/7++mAxzgQu/CrYLHjzobcuMXp xeJacLC+YzLuSdchQgjCPfOWsDtUDr0prU6K+szRuJKjE4jxzn0q3asWrKyvDMvK5Tzy HQYg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1773162573; x=1773767373; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=vggNX4iy/s3rYe31fA6JCPRN0nqiyw41a2u9JUGJC2M=; b=Ig6dVDQ+LcTI/hW/gNALG5n4zaBY5wgNasgTTkJ4IEcQLvm+1Wq8658V+Q84j7rO14 eXVqsgEVi4uWTXQO68mFpKgebN3sHw+E4sFBiYbyngX6A7x4xC2n8bXfMCYvsuDVqN21 sdCoDBrqOmzzb6Vg/Rpii8HVBfOq4W560EjSnPvAS+nrarQ1LTapvErbtHJm387d43JX Jzx+0HwnfNIJ/fRIBwBa5D7sQGaXmj4eTdEsBsuhPuDH1mUt9efG6fG0xabWX5YbgenC tIuKWGqPoBykdjwjASKL7Df5f8v/Lq5dnWG89zK3Ix2jkzVekOXHdgAT5PTs6RPeGDql CIzA== X-Gm-Message-State: AOJu0YxHYzbxq5VrgemTmpLf7h5FhkmIfrK8Fi9ObWdSLz2wOJuE5pHv FFdfmOHZFv0QrMiXQwwGs51QLEOF+ev2K3HAH9iK6BiHqV+3CRgK9FlwB9lZOYo1 X-Gm-Gg: ATEYQzxt0YRSDIoNzbT7YtZ4xE66nEdsGPuZf1CMrlnU2egtqfIJaukap7FwDAhJVMG Bv3IAXfyZTAorslb5BBZgUumzuIqXiSoI7tYB++k1faqAVA+vsyqKYwGGz3ne2QlTncm8WpleKS rOtAewu+pwtW6TnTBYz6GYH9DDeZAu3B8wapYPhB59y7CrPR6R8EczrceWT3CAuzZyStowGC+5m DiKGicdCJuU/SXmH3aFf23LhCYlN+ca2ecqI8n8BA3vzcwm7GMp6PIFCqDs7j1MZTEEom/4nZNE 9P/EnKbLGT7MyHlDbxye5MhdoFzSjdvQsJj4+YhfpX1Y4Ef95C33LJdgmCDVVAjRlVTi0hiNC3x HWIOKZB0mzZ7jfAqBFcZpIHtDx2Y6yRHNU4EYIYqDi2j61xrRJC/cGY3LT0xFCOHKp6mRiLwZMg 5fu30+Oej0zHO7+t75TBUU2+4yRdP9lfxIcpNHL1GqYp6J/O8Fnf/gN+dWy0z1hylL5g== X-Received: by 2002:a05:600c:a08b:b0:485:42ba:fc8 with SMTP id 5b1f17b1804b1-48542ba105dmr58826615e9.4.1773162573184; Tue, 10 Mar 2026 10:09:33 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Romain Caritey , Oleksii Kurochko , Alistair Francis , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH v1 20/27] xen/riscv: emulate guest reads from virtual APLIC MMIO Date: Tue, 10 Mar 2026 18:08:53 +0100 Message-ID: <626d0874c2c7ec858725860bc3857691f0f829ad.1773157782.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1773163081535158500 Guests may read back APLIC registers to inspect interrupt state and routing configuration. When virtualising APLIC, Xen must intercept these MMIO reads and present a consistent, restricted view of the virtual interrupt controller state. Note that at the moment only MSI mode is supported. Introduce vaplic_emulate_load() to handle guest loads from virtual APLIC registers. Readback is filtered through the domain=E2=80=99s authoris= ed interrupt bitmap so that guests can observe state only for interrupts they are permitted to control. Registers defined by the AIA specification to read as zero are handled accordingly, while other registers return masked values derived from the underlying virtual APLIC state. Unsupported accesses are treated as fatal, as they indicate a emulation error. Co-developed-by: Romain Caritey Signed-off-by: Oleksii Kurochko --- xen/arch/riscv/include/asm/intc.h | 4 ++ xen/arch/riscv/vaplic.c | 69 +++++++++++++++++++++++++++++++ 2 files changed, 73 insertions(+) diff --git a/xen/arch/riscv/include/asm/intc.h b/xen/arch/riscv/include/asm= /intc.h index 92a74eede4a0..45d41e191e30 100644 --- a/xen/arch/riscv/include/asm/intc.h +++ b/xen/arch/riscv/include/asm/intc.h @@ -56,6 +56,10 @@ struct vintc_ops { /* Initialize some vINTC-related stuff for a vCPU */ int (*vcpu_init)(struct vcpu *vcpu); =20 + /* Emulate load to virtual interrupt controller MMIOs */ + int (*emulate_load)(const struct vcpu *vcpu, unsigned long addr, + uint32_t *out); + /* Emulate store to virtual interrupt controller MMIOs */ int (*emulate_store)(const struct vcpu *vcpu, unsigned long addr, uint32_t in); diff --git a/xen/arch/riscv/vaplic.c b/xen/arch/riscv/vaplic.c index 5540b4884179..293729ad0ad4 100644 --- a/xen/arch/riscv/vaplic.c +++ b/xen/arch/riscv/vaplic.c @@ -137,6 +137,74 @@ int vaplic_map_device_irqs_to_domain(struct domain *d, return 0; } =20 +static int vaplic_emulate_load(const struct vcpu *vcpu, + const unsigned long addr, uint32_t *out) +{ + const struct vaplic *vaplic =3D to_vaplic(vcpu->domain->arch.vintc); + struct aplic_priv *priv =3D vaplic->base.info->private; + const unsigned long offset =3D addr & APLIC_REG_OFFSET_MASK; + const uint32_t *auth_irq_bmp =3D vcpu->domain->arch.vintc->private; + bool auth_bit; + + switch ( offset ) + { + case APLIC_DOMAINCFG: + *out =3D vaplic->regs.domaincfg; + break; + + case APLIC_SETIPNUM: + case APLIC_SETIPNUM_LE: + case APLIC_CLRIPNUM: + case APLIC_SETIENUM: + /* + * Based on the RISC-V AIA sepc a read of these registers + * always returns zero + */ + *out =3D 0; + break; + + case APLIC_SETIP_BASE ... APLIC_SETIP_LAST: + auth_bit =3D auth_irq_bmp[regval_to_irqn(offset - APLIC_SETIP_BASE= )]; + *out =3D APLIC_REG_GET(priv->regs, addr - priv->paddr_start) & aut= h_bit; + break; + + case APLIC_CLRIP_BASE ... APLIC_CLRIP_LAST: + auth_bit =3D auth_irq_bmp[regval_to_irqn(offset - APLIC_CLRIP_BASE= )]; + *out =3D APLIC_REG_GET(priv->regs, addr - priv->paddr_start) & aut= h_bit; + break; + + case APLIC_SETIE_BASE ... APLIC_SETIE_LAST: + auth_bit =3D auth_irq_bmp[regval_to_irqn(offset - APLIC_CLRIP_BASE= )]; + *out =3D APLIC_REG_GET(priv->regs, addr - priv->paddr_start) & aut= h_bit; + break; + + case APLIC_CLRIE_BASE ... APLIC_CLRIE_LAST: + auth_bit =3D auth_irq_bmp[regval_to_irqn(offset - APLIC_CLRIE_BASE= )]; + *out =3D APLIC_REG_GET(priv->regs, addr - priv->paddr_start) & aut= h_bit; + break; + + case APLIC_TARGET_BASE ... APLIC_TARGET_LAST: + /* + * As target registers start for 1: + * 0x3000 genmsi + * 0x3004 target[1] + * 0x3008 target[2] + * ... + * 0x3FFC target[1023] + * It is necessary to calculate an interrupt number by substracting + * of APLIC_GENMSI instead of APLIC_TARGET_BASE. + */ + auth_bit =3D auth_irq_bmp[regval_to_irqn(offset - APLIC_GENMSI)]; + *out =3D APLIC_REG_GET(priv->regs, addr - priv->paddr_start) & aut= h_bit; + break; + + default: + panic("%s: unsupported register offset: %#lx", __func__, offset); + } + + return 0; +} + static void vaplic_dm_update_target(const unsigned long hart_id, uint32_t = *iprio) { *iprio &=3D APLIC_TARGET_IPRIO_MASK; @@ -327,6 +395,7 @@ static const struct vintc_ops vaplic_ops =3D { .map_device_irqs_to_domain =3D vaplic_map_device_irqs_to_domain, .is_access =3D vaplic_is_access, .emulate_store =3D vaplic_emulate_store, + .emulate_load =3D vaplic_emulate_load, }; =20 static struct vintc * __init vaplic_alloc(void) --=20 2.53.0