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charset="utf-8" Provide support for this insn, which is a prereq to FRED. CPUID-wise introduce both its and FRED's bit at this occasion, thus allowing to also express the dependency right away. While adding a testcase, also add a SWAPGS one. In order to not affect the behavior of pre-existing tests, install write_{segment,msr} hooks only transiently. Signed-off-by: Jan Beulich --- Since I was asked to post this work, I've rebased it ahead of most other emulator work I have pending, _except_ "x86emul: a few small steps towards disintegration". Instead of ->read_segment() we could of course also use ->read_msr() to fetch the original GS base. I don't think I can see a clear advantage of either approach; the way it's done it matches how we handle SWAPGS. For PV save_segments() would need adjustment, but the insn being restricted to ring 0 means PV guests can't use it anyway (unless we wanted to emulate it as another privileged insn). --- a/tools/libs/light/libxl_cpuid.c +++ b/tools/libs/light/libxl_cpuid.c @@ -235,6 +235,8 @@ int libxl_cpuid_parse_config(libxl_cpuid {"fzrm", 0x00000007, 1, CPUID_REG_EAX, 10, 1}, {"fsrs", 0x00000007, 1, CPUID_REG_EAX, 11, 1}, {"fsrcs", 0x00000007, 1, CPUID_REG_EAX, 12, 1}, + {"fred", 0x00000007, 1, CPUID_REG_EAX, 17, 1}, + {"lkgs", 0x00000007, 1, CPUID_REG_EAX, 18, 1}, {"wrmsrns", 0x00000007, 1, CPUID_REG_EAX, 19, 1}, =20 {"cet-sss", 0x00000007, 1, CPUID_REG_EDX, 18, 1}, --- a/tools/misc/xen-cpuid.c +++ b/tools/misc/xen-cpuid.c @@ -190,7 +190,8 @@ static const char *const str_7a1[32] =3D [10] =3D "fzrm", [11] =3D "fsrs", [12] =3D "fsrcs", =20 - /* 18 */ [19] =3D "wrmsrns", + /* 16 */ [17] =3D "fred", + [18] =3D "lkgs", [19] =3D "wrmsrns", }; =20 static const char *const str_e21a[32] =3D --- a/tools/tests/x86_emulator/predicates.c +++ b/tools/tests/x86_emulator/predicates.c @@ -326,6 +326,7 @@ static const struct { { { 0x00, 0x18 }, { 2, 2 }, T, R }, /* ltr */ { { 0x00, 0x20 }, { 2, 2 }, T, R }, /* verr */ { { 0x00, 0x28 }, { 2, 2 }, T, R }, /* verw */ + { { 0x00, 0x30 }, { 0, 2 }, T, R, pfx_f2 }, /* lkgs */ { { 0x01, 0x00 }, { 2, 2 }, F, W }, /* sgdt */ { { 0x01, 0x08 }, { 2, 2 }, F, W }, /* sidt */ { { 0x01, 0x10 }, { 2, 2 }, F, R }, /* lgdt */ --- a/tools/tests/x86_emulator/test_x86_emulator.c +++ b/tools/tests/x86_emulator/test_x86_emulator.c @@ -666,6 +666,10 @@ static int blk( return x86_emul_blk((void *)offset, p_data, bytes, eflags, state, ctxt= ); } =20 +#ifdef __x86_64__ +static unsigned long gs_base, gs_base_shadow; +#endif + static int read_segment( enum x86_segment seg, struct segment_register *reg, @@ -675,8 +679,30 @@ static int read_segment( return X86EMUL_UNHANDLEABLE; memset(reg, 0, sizeof(*reg)); reg->p =3D 1; + +#ifdef __x86_64__ + if ( seg =3D=3D x86_seg_gs ) + reg->base =3D gs_base; +#endif + + return X86EMUL_OKAY; +} + +#ifdef __x86_64__ +static int write_segment( + enum x86_segment seg, + const struct segment_register *reg, + struct x86_emulate_ctxt *ctxt) +{ + if ( !is_x86_user_segment(seg) ) + return X86EMUL_UNHANDLEABLE; + + if ( seg =3D=3D x86_seg_gs ) + gs_base =3D reg->base; + return X86EMUL_OKAY; } +#endif =20 static int read_msr( unsigned int reg, @@ -689,6 +715,20 @@ static int read_msr( *val =3D ctxt->addr_size > 32 ? 0x500 /* LME|LMA */ : 0; return X86EMUL_OKAY; =20 +#ifdef __x86_64__ + case 0xc0000101: /* GS_BASE */ + if ( ctxt->addr_size < 64 ) + break; + *val =3D gs_base; + return X86EMUL_OKAY; + + case 0xc0000102: /* SHADOW_GS_BASE */ + if ( ctxt->addr_size < 64 ) + break; + *val =3D gs_base_shadow; + return X86EMUL_OKAY; +#endif + case 0xc0000103: /* TSC_AUX */ #define TSC_AUX_VALUE 0xCACACACA *val =3D TSC_AUX_VALUE; @@ -698,6 +738,31 @@ static int read_msr( return X86EMUL_UNHANDLEABLE; } =20 +#ifdef __x86_64__ +static int write_msr( + unsigned int reg, + uint64_t val, + struct x86_emulate_ctxt *ctxt) +{ + switch ( reg ) + { + case 0xc0000101: /* GS_BASE */ + if ( ctxt->addr_size < 64 || !is_canonical_address(val) ) + break; + gs_base =3D val; + return X86EMUL_OKAY; + + case 0xc0000102: /* SHADOW_GS_BASE */ + if ( ctxt->addr_size < 64 || !is_canonical_address(val) ) + break; + gs_base_shadow =3D val; + return X86EMUL_OKAY; + } + + return X86EMUL_UNHANDLEABLE; +} +#endif + #define INVPCID_ADDR 0x12345678 #define INVPCID_PCID 0x123 =20 @@ -1331,6 +1396,41 @@ int main(int argc, char **argv) printf("%u bytes read - ", bytes_read); goto fail; } + printf("okay\n"); + + emulops.write_segment =3D write_segment; + emulops.write_msr =3D write_msr; + + printf("%-40s", "Testing swapgs..."); + instr[0] =3D 0x0f; instr[1] =3D 0x01; instr[2] =3D 0xf8; + regs.eip =3D (unsigned long)&instr[0]; + gs_base =3D 0xffffeeeecccc8888UL; + gs_base_shadow =3D 0x0000111122224444UL; + rc =3D x86_emulate(&ctxt, &emulops); + if ( (rc !=3D X86EMUL_OKAY) || + (regs.eip !=3D (unsigned long)&instr[3]) || + (gs_base !=3D 0x0000111122224444UL) || + (gs_base_shadow !=3D 0xffffeeeecccc8888UL) ) + goto fail; + printf("okay\n"); + + printf("%-40s", "Testing lkgs 2(%rdx)..."); + instr[0] =3D 0xf2; instr[1] =3D 0x0f; instr[2] =3D 0x00; instr[3] =3D = 0x72; instr[4] =3D 0x02; + regs.eip =3D (unsigned long)&instr[0]; + regs.edx =3D (unsigned long)res; + res[0] =3D 0x00004444; + res[1] =3D 0x8888cccc; + i =3D cp.extd.nscb; cp.extd.nscb =3D true; /* for AMD */ + rc =3D x86_emulate(&ctxt, &emulops); + if ( (rc !=3D X86EMUL_OKAY) || + (regs.eip !=3D (unsigned long)&instr[5]) || + (gs_base !=3D 0x0000111122224444UL) || + gs_base_shadow ) + goto fail; + + cp.extd.nscb =3D i; + emulops.write_segment =3D NULL; + emulops.write_msr =3D NULL; #endif printf("okay\n"); =20 --- a/tools/tests/x86_emulator/x86-emulate.c +++ b/tools/tests/x86_emulator/x86-emulate.c @@ -86,6 +86,7 @@ bool emul_test_init(void) cp.feat.adx =3D true; cp.feat.avx512pf =3D cp.feat.avx512f; cp.feat.rdpid =3D true; + cp.feat.lkgs =3D true; cp.extd.clzero =3D true; =20 if ( cpu_has_xsave ) --- a/xen/arch/x86/x86_emulate/decode.c +++ b/xen/arch/x86/x86_emulate/decode.c @@ -744,8 +744,12 @@ decode_twobyte(struct x86_emulate_state case 0: s->desc |=3D DstMem | SrcImplicit | Mov; break; + case 6: + if ( !(s->modrm_reg & 1) && mode_64bit() ) + { case 2: case 4: - s->desc |=3D SrcMem16; + s->desc |=3D SrcMem16; + } break; } break; --- a/xen/arch/x86/x86_emulate/private.h +++ b/xen/arch/x86/x86_emulate/private.h @@ -593,6 +593,7 @@ amd_like(const struct x86_emulate_ctxt * #define vcpu_has_tsxldtrk() (ctxt->cpuid->feat.tsxldtrk) #define vcpu_has_avx_vnni() (ctxt->cpuid->feat.avx_vnni) #define vcpu_has_avx512_bf16() (ctxt->cpuid->feat.avx512_bf16) +#define vcpu_has_lkgs() (ctxt->cpuid->feat.lkgs) =20 #define vcpu_must_have(feat) \ generate_exception_if(!vcpu_has_##feat(), X86_EXC_UD) --- a/xen/arch/x86/x86_emulate/x86_emulate.c +++ b/xen/arch/x86/x86_emulate/x86_emulate.c @@ -2890,8 +2890,31 @@ x86_emulate( break; } break; - default: - generate_exception_if(true, EXC_UD); + case 6: /* lkgs */ + generate_exception_if((modrm_reg & 1) || vex.pfx !=3D vex_f2, = EXC_UD); + generate_exception_if(!mode_64bit() || !mode_ring0(), EXC_UD); + vcpu_must_have(lkgs); + fail_if(!ops->read_segment || !ops->read_msr || + !ops->write_segment || !ops->write_msr); + if ( (rc =3D ops->read_msr(MSR_SHADOW_GS_BASE, &msr_val, + ctxt)) !=3D X86EMUL_OKAY || + (rc =3D ops->read_segment(x86_seg_gs, &sreg, + ctxt)) !=3D X86EMUL_OKAY ) + goto done; + dst.orig_val =3D sreg.base; + if ( (rc =3D protmode_load_seg(x86_seg_gs, src.val, false, &sr= eg, + ctxt, ops)) !=3D X86EMUL_OKAY || + (rc =3D ops->write_msr(MSR_SHADOW_GS_BASE, sreg.base, + ctxt)) !=3D X86EMUL_OKAY ) + goto done; + sreg.base =3D dst.orig_val; + if ( (rc =3D ops->write_segment(x86_seg_gs, &sreg, + ctxt)) !=3D X86EMUL_OKAY ) + { + /* Best effort unwind (i.e. no error checking). */ + ops->write_msr(MSR_SHADOW_GS_BASE, msr_val, ctxt); + goto done; + } break; } break; --- a/xen/include/public/arch-x86/cpufeatureset.h +++ b/xen/include/public/arch-x86/cpufeatureset.h @@ -281,6 +281,8 @@ XEN_CPUFEATURE(AVX512_BF16, 10*32+ 5) / XEN_CPUFEATURE(FZRM, 10*32+10) /*A Fast Zero-length REP MOVSB */ XEN_CPUFEATURE(FSRS, 10*32+11) /*A Fast Short REP STOSB */ XEN_CPUFEATURE(FSRCS, 10*32+12) /*A Fast Short REP CMPSB/SCASB */ +XEN_CPUFEATURE(FRED, 10*32+17) /* Flexible Return and Event Deli= very */ +XEN_CPUFEATURE(LKGS, 10*32+18) /*S Load Kernel GS Base */ XEN_CPUFEATURE(WRMSRNS, 10*32+19) /* WRMSR Non-Serialising */ =20 /* AMD-defined CPU features, CPUID level 0x80000021.eax, word 11 */ --- a/xen/tools/gen-cpuid.py +++ b/xen/tools/gen-cpuid.py @@ -295,6 +295,9 @@ def crunch_numbers(state): =20 # In principle the TSXLDTRK insns could also be considered indepen= dent. RTM: [TSXLDTRK], + + # FRED builds on the LKGS instruction. + LKGS: [FRED], } =20 deep_features =3D tuple(sorted(deps.keys()))