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Wed, 26 Jun 2024 09:28:46 -0700 (PDT) From: Alejandro Vallejo To: Xen-devel Cc: Alejandro Vallejo , Jan Beulich , Andrew Cooper , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Anthony PERARD Subject: [PATCH v4 07/10] xen/lib: Add topology generator for x86 Date: Wed, 26 Jun 2024 17:28:34 +0100 Message-Id: <5ab2cb62745bca462ab3768ea1eb826d2b6e2c76.1719416329.git.alejandro.vallejo@cloud.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @cloud.com) X-ZM-MESSAGEID: 1719419347005100001 Content-Type: text/plain; charset="utf-8" Add a helper to populate topology leaves in the cpu policy from threads/core and cores/package counts. It's unit-tested in test-cpu-policy.= c, but it's not connected to the rest of the code yet. Adds the ASSERT() macro to xen/lib/x86/private.h, as it was missing. Signed-off-by: Alejandro Vallejo --- v4: * v1->v2 introduced a bug. lppp must be MIN(0xff, threads_per_pkg). * Add missing MIN() when setting p->extd.nc (should've been done in v2) --- tools/tests/cpu-policy/test-cpu-policy.c | 133 +++++++++++++++++++++++ xen/include/xen/lib/x86/cpu-policy.h | 16 +++ xen/lib/x86/policy.c | 88 +++++++++++++++ xen/lib/x86/private.h | 4 + 4 files changed, 241 insertions(+) diff --git a/tools/tests/cpu-policy/test-cpu-policy.c b/tools/tests/cpu-pol= icy/test-cpu-policy.c index 301df2c00285..849d7cebaa7c 100644 --- a/tools/tests/cpu-policy/test-cpu-policy.c +++ b/tools/tests/cpu-policy/test-cpu-policy.c @@ -650,6 +650,137 @@ static void test_is_compatible_failure(void) } } =20 +static void test_topo_from_parts(void) +{ + static const struct test { + unsigned int threads_per_core; + unsigned int cores_per_pkg; + struct cpu_policy policy; + } tests[] =3D { + { + .threads_per_core =3D 3, .cores_per_pkg =3D 1, + .policy =3D { + .x86_vendor =3D X86_VENDOR_AMD, + .topo.subleaf =3D { + { .nr_logical =3D 3, .level =3D 0, .type =3D 1, .id_sh= ift =3D 2, }, + { .nr_logical =3D 1, .level =3D 1, .type =3D 2, .id_sh= ift =3D 2, }, + }, + }, + }, + { + .threads_per_core =3D 1, .cores_per_pkg =3D 3, + .policy =3D { + .x86_vendor =3D X86_VENDOR_AMD, + .topo.subleaf =3D { + { .nr_logical =3D 1, .level =3D 0, .type =3D 1, .id_sh= ift =3D 0, }, + { .nr_logical =3D 3, .level =3D 1, .type =3D 2, .id_sh= ift =3D 2, }, + }, + }, + }, + { + .threads_per_core =3D 7, .cores_per_pkg =3D 5, + .policy =3D { + .x86_vendor =3D X86_VENDOR_AMD, + .topo.subleaf =3D { + { .nr_logical =3D 7, .level =3D 0, .type =3D 1, .id_sh= ift =3D 3, }, + { .nr_logical =3D 5, .level =3D 1, .type =3D 2, .id_sh= ift =3D 6, }, + }, + }, + }, + { + .threads_per_core =3D 2, .cores_per_pkg =3D 128, + .policy =3D { + .x86_vendor =3D X86_VENDOR_AMD, + .topo.subleaf =3D { + { .nr_logical =3D 2, .level =3D 0, .type =3D 1, .id_sh= ift =3D 1, }, + { .nr_logical =3D 128, .level =3D 1, .type =3D 2, + .id_shift =3D 8, }, + }, + }, + }, + { + .threads_per_core =3D 3, .cores_per_pkg =3D 1, + .policy =3D { + .x86_vendor =3D X86_VENDOR_INTEL, + .topo.subleaf =3D { + { .nr_logical =3D 3, .level =3D 0, .type =3D 1, .id_sh= ift =3D 2, }, + { .nr_logical =3D 3, .level =3D 1, .type =3D 2, .id_sh= ift =3D 2, }, + }, + }, + }, + { + .threads_per_core =3D 1, .cores_per_pkg =3D 3, + .policy =3D { + .x86_vendor =3D X86_VENDOR_INTEL, + .topo.subleaf =3D { + { .nr_logical =3D 1, .level =3D 0, .type =3D 1, .id_sh= ift =3D 0, }, + { .nr_logical =3D 3, .level =3D 1, .type =3D 2, .id_sh= ift =3D 2, }, + }, + }, + }, + { + .threads_per_core =3D 7, .cores_per_pkg =3D 5, + .policy =3D { + .x86_vendor =3D X86_VENDOR_INTEL, + .topo.subleaf =3D { + { .nr_logical =3D 7, .level =3D 0, .type =3D 1, .id_sh= ift =3D 3, }, + { .nr_logical =3D 35, .level =3D 1, .type =3D 2, .id_s= hift =3D 6, }, + }, + }, + }, + { + .threads_per_core =3D 2, .cores_per_pkg =3D 128, + .policy =3D { + .x86_vendor =3D X86_VENDOR_INTEL, + .topo.subleaf =3D { + { .nr_logical =3D 2, .level =3D 0, .type =3D 1, .id_sh= ift =3D 1, }, + { .nr_logical =3D 256, .level =3D 1, .type =3D 2, + .id_shift =3D 8, }, + }, + }, + }, + }; + + printf("Testing topology synthesis from parts:\n"); + + for ( size_t i =3D 0; i < ARRAY_SIZE(tests); ++i ) + { + const struct test *t =3D &tests[i]; + struct cpu_policy actual =3D { .x86_vendor =3D t->policy.x86_vendo= r }; + int rc =3D x86_topo_from_parts(&actual, t->threads_per_core, + t->cores_per_pkg); + + if ( rc || memcmp(&actual.topo, &t->policy.topo, sizeof(actual.top= o)) ) + { +#define TOPO(n, f) t->policy.topo.subleaf[(n)].f, actual.topo.subleaf[(n)= ].f + fail("FAIL[%d] - '%s %u t/c, %u c/p'\n", + rc, + x86_cpuid_vendor_to_str(t->policy.x86_vendor), + t->threads_per_core, t->cores_per_pkg); + printf(" subleaf=3D%u expected_n=3D%u actual_n=3D%u\n" + " expected_lvl=3D%u actual_lvl=3D%u\n" + " expected_type=3D%u actual_type=3D%u\n" + " expected_shift=3D%u actual_shift=3D%u\n", + 0, + TOPO(0, nr_logical), + TOPO(0, level), + TOPO(0, type), + TOPO(0, id_shift)); + + printf(" subleaf=3D%u expected_n=3D%u actual_n=3D%u\n" + " expected_lvl=3D%u actual_lvl=3D%u\n" + " expected_type=3D%u actual_type=3D%u\n" + " expected_shift=3D%u actual_shift=3D%u\n", + 1, + TOPO(1, nr_logical), + TOPO(1, level), + TOPO(1, type), + TOPO(1, id_shift)); +#undef TOPO + } + } +} + int main(int argc, char **argv) { printf("CPU Policy unit tests\n"); @@ -667,6 +798,8 @@ int main(int argc, char **argv) test_is_compatible_success(); test_is_compatible_failure(); =20 + test_topo_from_parts(); + if ( nr_failures ) printf("Done: %u failures\n", nr_failures); else diff --git a/xen/include/xen/lib/x86/cpu-policy.h b/xen/include/xen/lib/x86= /cpu-policy.h index d26012c6da78..79fdf9045a1b 100644 --- a/xen/include/xen/lib/x86/cpu-policy.h +++ b/xen/include/xen/lib/x86/cpu-policy.h @@ -542,6 +542,22 @@ int x86_cpu_policies_are_compatible(const struct cpu_p= olicy *host, const struct cpu_policy *guest, struct cpu_policy_errors *err); =20 +/** + * Synthesise topology information in `p` given high-level constraints + * + * Topology is given in various fields accross several leaves, some of + * which are vendor-specific. This function uses the policy itself to + * derive such leaves from threads/core and cores/package. + * + * @param p CPU policy of the domain. + * @param threads_per_core threads/core. Doesn't need to be a power of = 2. + * @param cores_per_package cores/package. Doesn't need to be a power of= 2. + * @return 0 on success; -errno on failure + */ +int x86_topo_from_parts(struct cpu_policy *p, + unsigned int threads_per_core, + unsigned int cores_per_pkg); + #endif /* !XEN_LIB_X86_POLICIES_H */ =20 /* diff --git a/xen/lib/x86/policy.c b/xen/lib/x86/policy.c index f033d22785be..72b67b44a893 100644 --- a/xen/lib/x86/policy.c +++ b/xen/lib/x86/policy.c @@ -2,6 +2,94 @@ =20 #include =20 +static unsigned int order(unsigned int n) +{ + ASSERT(n); /* clz(0) is UB */ + + return 8 * sizeof(n) - __builtin_clz(n); +} + +int x86_topo_from_parts(struct cpu_policy *p, + unsigned int threads_per_core, + unsigned int cores_per_pkg) +{ + unsigned int threads_per_pkg =3D threads_per_core * cores_per_pkg; + unsigned int apic_id_size; + + if ( !p || !threads_per_core || !cores_per_pkg ) + return -EINVAL; + + p->basic.max_leaf =3D MAX(0xb, p->basic.max_leaf); + + memset(p->topo.raw, 0, sizeof(p->topo.raw)); + + /* thread level */ + p->topo.subleaf[0].nr_logical =3D threads_per_core; + p->topo.subleaf[0].id_shift =3D 0; + p->topo.subleaf[0].level =3D 0; + p->topo.subleaf[0].type =3D 1; + if ( threads_per_core > 1 ) + p->topo.subleaf[0].id_shift =3D order(threads_per_core - 1); + + /* core level */ + p->topo.subleaf[1].nr_logical =3D cores_per_pkg; + if ( p->x86_vendor =3D=3D X86_VENDOR_INTEL ) + p->topo.subleaf[1].nr_logical =3D threads_per_pkg; + p->topo.subleaf[1].id_shift =3D p->topo.subleaf[0].id_shift; + p->topo.subleaf[1].level =3D 1; + p->topo.subleaf[1].type =3D 2; + if ( cores_per_pkg > 1 ) + p->topo.subleaf[1].id_shift +=3D order(cores_per_pkg - 1); + + apic_id_size =3D p->topo.subleaf[1].id_shift; + + /* + * Contrary to what the name might seem to imply. HTT is an enabler for + * SMP and there's no harm in setting it even with a single vCPU. + */ + p->basic.htt =3D true; + p->basic.lppp =3D MIN(0xff, threads_per_pkg); + + switch ( p->x86_vendor ) + { + case X86_VENDOR_INTEL: { + struct cpuid_cache_leaf *sl =3D p->cache.subleaf; + + for ( size_t i =3D 0; sl->type && + i < ARRAY_SIZE(p->cache.raw); i++, sl++ ) + { + sl->cores_per_package =3D cores_per_pkg - 1; + sl->threads_per_cache =3D threads_per_core - 1; + if ( sl->type =3D=3D 3 /* unified cache */ ) + sl->threads_per_cache =3D threads_per_pkg - 1; + } + break; + } + + case X86_VENDOR_AMD: + case X86_VENDOR_HYGON: + /* Expose p->basic.lppp */ + p->extd.cmp_legacy =3D true; + + /* Clip NC to the maximum value it can hold */ + p->extd.nc =3D MIN(0xff, threads_per_pkg - 1); + + /* TODO: Expose leaf e1E */ + p->extd.topoext =3D false; + + /* + * Clip APIC ID to 8 bits, as that's what high core-count machines= do. + * + * That's what AMD EPYC 9654 does with >256 CPUs. + */ + p->extd.apic_id_size =3D MIN(8, apic_id_size); + + break; + } + + return 0; +} + int x86_cpu_policies_are_compatible(const struct cpu_policy *host, const struct cpu_policy *guest, struct cpu_policy_errors *err) diff --git a/xen/lib/x86/private.h b/xen/lib/x86/private.h index 60bb82a400b7..2ec9dbee33c2 100644 --- a/xen/lib/x86/private.h +++ b/xen/lib/x86/private.h @@ -4,6 +4,7 @@ #ifdef __XEN__ =20 #include +#include #include #include #include @@ -17,6 +18,7 @@ =20 #else =20 +#include #include #include #include @@ -28,6 +30,8 @@ =20 #include =20 +#define ASSERT(x) assert(x) + static inline bool test_bit(unsigned int bit, const void *vaddr) { const char *addr =3D vaddr; --=20 2.34.1