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Wed, 18 Jun 2025 00:04:57 -0700 (PDT) Message-ID: <03d20e4f-f264-49ce-8f6e-1a8217d1da87@suse.com> Date: Wed, 18 Jun 2025 09:04:50 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH v8 1/7] x86emul: support LKGS From: Jan Beulich To: "xen-devel@lists.xenproject.org" Cc: Andrew Cooper , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= References: <585f1b0b-6768-4f9c-8f9f-bcf6e20fbfb7@suse.com> Content-Language: en-US Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <585f1b0b-6768-4f9c-8f9f-bcf6e20fbfb7@suse.com> Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @suse.com) X-ZM-MESSAGEID: 1750230316545116600 Content-Type: text/plain; charset="utf-8" Provide support for this insn, which is a prereq to FRED. CPUID-wise introduce both its, FRED's, and the NMI_SRC bit at this occasion, thus allowing to also express the dependency right away. While adding a testcase, also add a SWAPGS one. In order to not affect the behavior of pre-existing tests, install write_{segment,msr} hooks only transiently. Signed-off-by: Jan Beulich --- Instead of ->read_segment() we could of course also use ->read_msr() to fetch the original GS base. I don't think I can see a clear advantage of either approach; the way it's done it matches how we handle SWAPGS. For PV save_segments() would need adjustment, but the insn being restricted to ring 0 means PV guests can't use it anyway (unless we wanted to emulate it as another privileged insn). --- v8: Re-base. v6: Use MSR constants in test harness. S->s in cpufeatureset.h. Add NMI_SRC feature bits. Re-base. v5: Re-base. v3: Add dependency on LM. Re-base. v2: Use X86_EXC_*. Add comments. --- a/tools/tests/x86_emulator/predicates.c +++ b/tools/tests/x86_emulator/predicates.c @@ -326,6 +326,7 @@ static const struct { { { 0x00, 0x18 }, { 2, 2 }, T, R }, /* ltr */ { { 0x00, 0x20 }, { 2, 2 }, T, R }, /* verr */ { { 0x00, 0x28 }, { 2, 2 }, T, R }, /* verw */ + { { 0x00, 0x30 }, { 0, 2 }, T, R, pfx_f2 }, /* lkgs */ { { 0x01, 0x00 }, { 2, 2 }, F, W }, /* sgdt */ { { 0x01, 0x08 }, { 2, 2 }, F, W }, /* sidt */ { { 0x01, 0x10 }, { 2, 2 }, F, R }, /* lgdt */ --- a/tools/tests/x86_emulator/test_x86_emulator.c +++ b/tools/tests/x86_emulator/test_x86_emulator.c @@ -672,6 +672,10 @@ static int blk( return x86_emul_blk((void *)offset, p_data, bytes, eflags, state, ctxt= ); } =20 +#ifdef __x86_64__ +static unsigned long gs_base, gs_base_shadow; +#endif + static int read_segment( enum x86_segment seg, struct segment_register *reg, @@ -681,8 +685,30 @@ static int read_segment( return X86EMUL_UNHANDLEABLE; memset(reg, 0, sizeof(*reg)); reg->p =3D 1; + +#ifdef __x86_64__ + if ( seg =3D=3D x86_seg_gs ) + reg->base =3D gs_base; +#endif + + return X86EMUL_OKAY; +} + +#ifdef __x86_64__ +static int write_segment( + enum x86_segment seg, + const struct segment_register *reg, + struct x86_emulate_ctxt *ctxt) +{ + if ( !is_x86_user_segment(seg) ) + return X86EMUL_UNHANDLEABLE; + + if ( seg =3D=3D x86_seg_gs ) + gs_base =3D reg->base; + return X86EMUL_OKAY; } +#endif =20 static int read_msr( unsigned int reg, @@ -695,6 +721,20 @@ static int read_msr( *val =3D ctxt->addr_size > 32 ? EFER_LME | EFER_LMA : 0; return X86EMUL_OKAY; =20 +#ifdef __x86_64__ + case MSR_GS_BASE: + if ( ctxt->addr_size < 64 ) + break; + *val =3D gs_base; + return X86EMUL_OKAY; + + case MSR_SHADOW_GS_BASE: + if ( ctxt->addr_size < 64 ) + break; + *val =3D gs_base_shadow; + return X86EMUL_OKAY; +#endif + case MSR_TSC_AUX: #define TSC_AUX_VALUE 0xCACACACA *val =3D TSC_AUX_VALUE; @@ -704,6 +744,31 @@ static int read_msr( return X86EMUL_UNHANDLEABLE; } =20 +#ifdef __x86_64__ +static int write_msr( + unsigned int reg, + uint64_t val, + struct x86_emulate_ctxt *ctxt) +{ + switch ( reg ) + { + case MSR_GS_BASE: + if ( ctxt->addr_size < 64 || !is_canonical_address(val) ) + break; + gs_base =3D val; + return X86EMUL_OKAY; + + case MSR_SHADOW_GS_BASE: + if ( ctxt->addr_size < 64 || !is_canonical_address(val) ) + break; + gs_base_shadow =3D val; + return X86EMUL_OKAY; + } + + return X86EMUL_UNHANDLEABLE; +} +#endif + #define INVPCID_ADDR 0x12345678 #define INVPCID_PCID 0x123 =20 @@ -1338,6 +1403,41 @@ int main(int argc, char **argv) printf("%u bytes read - ", bytes_read); goto fail; } + printf("okay\n"); + + emulops.write_segment =3D write_segment; + emulops.write_msr =3D write_msr; + + printf("%-40s", "Testing swapgs..."); + instr[0] =3D 0x0f; instr[1] =3D 0x01; instr[2] =3D 0xf8; + regs.eip =3D (unsigned long)&instr[0]; + gs_base =3D 0xffffeeeecccc8888UL; + gs_base_shadow =3D 0x0000111122224444UL; + rc =3D x86_emulate(&ctxt, &emulops); + if ( (rc !=3D X86EMUL_OKAY) || + (regs.eip !=3D (unsigned long)&instr[3]) || + (gs_base !=3D 0x0000111122224444UL) || + (gs_base_shadow !=3D 0xffffeeeecccc8888UL) ) + goto fail; + printf("okay\n"); + + printf("%-40s", "Testing lkgs 2(%rdx)..."); + instr[0] =3D 0xf2; instr[1] =3D 0x0f; instr[2] =3D 0x00; instr[3] =3D = 0x72; instr[4] =3D 0x02; + regs.eip =3D (unsigned long)&instr[0]; + regs.edx =3D (unsigned long)res; + res[0] =3D 0x00004444; + res[1] =3D 0x8888cccc; + i =3D cpu_policy.extd.nscb; cpu_policy.extd.nscb =3D true; /* for AMD = */ + rc =3D x86_emulate(&ctxt, &emulops); + if ( (rc !=3D X86EMUL_OKAY) || + (regs.eip !=3D (unsigned long)&instr[5]) || + (gs_base !=3D 0x0000111122224444UL) || + gs_base_shadow ) + goto fail; + + cpu_policy.extd.nscb =3D i; + emulops.write_segment =3D NULL; + emulops.write_msr =3D NULL; #endif printf("okay\n"); =20 --- a/tools/tests/x86_emulator/x86-emulate.c +++ b/tools/tests/x86_emulator/x86-emulate.c @@ -85,6 +85,7 @@ bool emul_test_init(void) cpu_policy.feat.invpcid =3D true; cpu_policy.feat.adx =3D true; cpu_policy.feat.rdpid =3D true; + cpu_policy.feat.lkgs =3D true; cpu_policy.feat.wrmsrns =3D true; cpu_policy.extd.clzero =3D true; =20 --- a/xen/arch/x86/x86_emulate/decode.c +++ b/xen/arch/x86/x86_emulate/decode.c @@ -744,8 +744,12 @@ decode_twobyte(struct x86_emulate_state case 0: s->desc |=3D DstMem | SrcImplicit | Mov; break; + case 6: + if ( !(s->modrm_reg & 1) && mode_64bit() ) + { case 2: case 4: - s->desc |=3D SrcMem16; + s->desc |=3D SrcMem16; + } break; } break; --- a/xen/arch/x86/x86_emulate/private.h +++ b/xen/arch/x86/x86_emulate/private.h @@ -607,6 +607,7 @@ amd_like(const struct x86_emulate_ctxt * #define vcpu_has_avx_vnni() (ctxt->cpuid->feat.avx_vnni) #define vcpu_has_avx512_bf16() (ctxt->cpuid->feat.avx512_bf16) #define vcpu_has_cmpccxadd() (ctxt->cpuid->feat.cmpccxadd) +#define vcpu_has_lkgs() (ctxt->cpuid->feat.lkgs) #define vcpu_has_wrmsrns() (ctxt->cpuid->feat.wrmsrns) #define vcpu_has_avx_ifma() (ctxt->cpuid->feat.avx_ifma) #define vcpu_has_avx_vnni_int8() (ctxt->cpuid->feat.avx_vnni_int8) --- a/xen/arch/x86/x86_emulate/x86_emulate.c +++ b/xen/arch/x86/x86_emulate/x86_emulate.c @@ -2899,8 +2899,35 @@ x86_emulate( break; } break; - default: - generate_exception_if(true, X86_EXC_UD); + case 6: /* lkgs */ + generate_exception_if((modrm_reg & 1) || vex.pfx !=3D vex_f2, + X86_EXC_UD); + generate_exception_if(!mode_64bit() || !mode_ring0(), X86_EXC_= UD); + vcpu_must_have(lkgs); + fail_if(!ops->read_segment || !ops->read_msr || + !ops->write_segment || !ops->write_msr); + if ( (rc =3D ops->read_msr(MSR_SHADOW_GS_BASE, &msr_val, + ctxt)) !=3D X86EMUL_OKAY || + (rc =3D ops->read_segment(x86_seg_gs, &sreg, + ctxt)) !=3D X86EMUL_OKAY ) + goto done; + dst.orig_val =3D sreg.base; /* Preserve full GS Base. */ + if ( (rc =3D protmode_load_seg(x86_seg_gs, src.val, false, &sr= eg, + ctxt, ops)) !=3D X86EMUL_OKAY || + /* Write (32-bit) base into SHADOW_GS. */ + (rc =3D ops->write_msr(MSR_SHADOW_GS_BASE, sreg.base, + ctxt)) !=3D X86EMUL_OKAY ) + goto done; + sreg.base =3D dst.orig_val; /* Reinstate full GS Base. */ + if ( (rc =3D ops->write_segment(x86_seg_gs, &sreg, + ctxt)) !=3D X86EMUL_OKAY ) + { + /* Best effort unwind (i.e. no real error checking). */ + if ( ops->write_msr(MSR_SHADOW_GS_BASE, msr_val, + ctxt) =3D=3D X86EMUL_EXCEPTION ) + x86_emul_reset_event(ctxt); + goto done; + } break; } break; --- a/xen/include/public/arch-x86/cpufeatureset.h +++ b/xen/include/public/arch-x86/cpufeatureset.h @@ -310,7 +310,10 @@ XEN_CPUFEATURE(ARCH_PERF_MON, 10*32+8) / XEN_CPUFEATURE(FZRM, 10*32+10) /*A Fast Zero-length REP MOVSB */ XEN_CPUFEATURE(FSRS, 10*32+11) /*A Fast Short REP STOSB */ XEN_CPUFEATURE(FSRCS, 10*32+12) /*A Fast Short REP CMPSB/SCASB */ +XEN_CPUFEATURE(FRED, 10*32+17) /* Flexible Return and Event Deli= very */ +XEN_CPUFEATURE(LKGS, 10*32+18) /*s Load Kernel GS Base */ XEN_CPUFEATURE(WRMSRNS, 10*32+19) /*S WRMSR Non-Serialising */ +XEN_CPUFEATURE(NMI_SRC, 10*32+20) /* NMI-source reporting */ XEN_CPUFEATURE(AMX_FP16, 10*32+21) /* AMX FP16 instruction */ XEN_CPUFEATURE(AVX_IFMA, 10*32+23) /*A AVX-IFMA Instructions */ XEN_CPUFEATURE(LAM, 10*32+26) /* Linear Address Masking */ --- a/xen/tools/gen-cpuid.py +++ b/xen/tools/gen-cpuid.py @@ -274,7 +274,8 @@ def crunch_numbers(state): # superpages, PCID and PKU are only available in 4 level paging. # NO_LMSL indicates the absense of Long Mode Segment Limits, which # have been dropped in hardware. - LM: [CX16, PCID, LAHF_LM, PAGE1GB, PKU, NO_LMSL, AMX_TILE, CMPCCXA= DD], + LM: [CX16, PCID, LAHF_LM, PAGE1GB, PKU, NO_LMSL, AMX_TILE, CMPCCXA= DD, + LKGS], =20 # AMD K6-2+ and K6-III processors shipped with 3DNow+, beyond the # standard 3DNow in the earlier K6 processors. @@ -343,6 +344,9 @@ def crunch_numbers(state): # computational instructions. All further AMX features are built = on top # of AMX-TILE. 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Wed, 18 Jun 2025 00:05:27 -0700 (PDT) Message-ID: <228a62ce-dbf2-435a-9c6e-02c0dd3c9dbd@suse.com> Date: Wed, 18 Jun 2025 09:05:20 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH v8 2/7] x86emul+VMX: support {RD,WR}MSRLIST From: Jan Beulich To: "xen-devel@lists.xenproject.org" Cc: Andrew Cooper , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= References: <585f1b0b-6768-4f9c-8f9f-bcf6e20fbfb7@suse.com> Content-Language: en-US Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <585f1b0b-6768-4f9c-8f9f-bcf6e20fbfb7@suse.com> Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @suse.com) X-ZM-MESSAGEID: 1750230359380116600 Content-Type: text/plain; charset="utf-8" These are "compound" instructions to issue a series of RDMSR / WRMSR respectively. In the emulator we can therefore implement them by using the existing msr_{read,write}() hooks. The memory accesses utilize that the HVM ->read() / ->write() hooks are already linear-address (x86_seg_none) aware (by way of hvmemul_virtual_to_linear() handling this case). Preemption is being checked for in WRMSRLIST handling only, as only MSR writes are expected to possibly take long. Signed-off-by: Jan Beulich --- RFC: In vmx_vmexit_handler() handling is forwarded to the emulator blindly. Alternatively we could consult the exit qualification and process just a single MSR at a time (without involving the emulator), exiting back to the guest after every iteration. (I don't think a mix of both models makes a lot of sense.) The precise behavior of MSR_BARRIER is still not spelled out in ISE 050, so the (minimal) implementation continues to be a guess for now. Wouldn't calculate_hvm_max_policy() for MPX better behave the same way as done here, at least from an abstract perspective (assuming that AMD won't add such functionality now that Intel have deprecated it)? --- v8: Re-base. v6: Use MSR constants in test harness. Re-base. v5: Add missing vmx_init_vmcs_config() and construct_vmcs() adjustments. Avoid unnecessary uses of r(). Re-base. v3: Add dependency on LM. Limit exposure to HVM. Utilize new info from ISE 050. Re-base. v2: Use X86_EXC_*. Add preemption checking to WRMSRLIST handling. Remove the feature from "max" when the VMX counterpart isn't available. --- a/tools/tests/x86_emulator/predicates.c +++ b/tools/tests/x86_emulator/predicates.c @@ -342,6 +342,8 @@ static const struct { { { 0x01, 0xc4 }, { 2, 2 }, F, N }, /* vmxoff */ { { 0x01, 0xc5 }, { 2, 2 }, F, N }, /* pconfig */ { { 0x01, 0xc6 }, { 2, 2 }, F, N }, /* wrmsrns */ + { { 0x01, 0xc6 }, { 0, 2 }, F, W, pfx_f2 }, /* rdmsrlist */ + { { 0x01, 0xc6 }, { 0, 2 }, F, R, pfx_f3 }, /* wrmsrlist */ { { 0x01, 0xc8 }, { 2, 2 }, F, N }, /* monitor */ { { 0x01, 0xc9 }, { 2, 2 }, F, N }, /* mwait */ { { 0x01, 0xca }, { 2, 2 }, F, N }, /* clac */ --- a/tools/tests/x86_emulator/test_x86_emulator.c +++ b/tools/tests/x86_emulator/test_x86_emulator.c @@ -625,7 +625,7 @@ static int write( if ( verbose ) printf("** %s(%u, %p,, %u,)\n", __func__, seg, (void *)offset, byt= es); =20 - if ( !is_x86_user_segment(seg) ) + if ( !is_x86_user_segment(seg) && seg !=3D x86_seg_none ) return X86EMUL_UNHANDLEABLE; memcpy((void *)offset, p_data, bytes); return X86EMUL_OKAY; @@ -717,6 +717,10 @@ static int read_msr( { switch ( reg ) { + case MSR_BARRIER: + *val =3D 0; + return X86EMUL_OKAY; + case MSR_EFER: *val =3D ctxt->addr_size > 32 ? EFER_LME | EFER_LMA : 0; return X86EMUL_OKAY; @@ -1434,9 +1438,53 @@ int main(int argc, char **argv) (gs_base !=3D 0x0000111122224444UL) || gs_base_shadow ) goto fail; + printf("okay\n"); =20 cpu_policy.extd.nscb =3D i; emulops.write_segment =3D NULL; + + printf("%-40s", "Testing rdmsrlist..."); + instr[0] =3D 0xf2; instr[1] =3D 0x0f; instr[2] =3D 0x01; instr[3] =3D = 0xc6; + regs.rip =3D (unsigned long)&instr[0]; + regs.rsi =3D (unsigned long)(res + 0x80); + regs.rdi =3D (unsigned long)(res + 0x80 + 0x40 * 2); + regs.rcx =3D 0x0002000100008000UL; + gs_base_shadow =3D 0x0000222244446666UL; + memset(res + 0x80, ~0, 0x40 * 8 * 2); + res[0x80 + 0x0f * 2] =3D MSR_GS_BASE; + res[0x80 + 0x0f * 2 + 1] =3D 0; + res[0x80 + 0x20 * 2] =3D MSR_SHADOW_GS_BASE; + res[0x80 + 0x20 * 2 + 1] =3D 0; + res[0x80 + 0x31 * 2] =3D MSR_BARRIER; + res[0x80 + 0x31 * 2 + 1] =3D 0; + rc =3D x86_emulate(&ctxt, &emulops); + if ( (rc !=3D X86EMUL_OKAY) || + (regs.rip !=3D (unsigned long)&instr[4]) || + regs.rcx || + (res[0x80 + (0x40 + 0x0f) * 2] !=3D (unsigned int)gs_base) || + (res[0x80 + (0x40 + 0x0f) * 2 + 1] !=3D (gs_base >> (8 * sizeof(i= nt)))) || + (res[0x80 + (0x40 + 0x20) * 2] !=3D (unsigned int)gs_base_shadow)= || + (res[0x80 + (0x40 + 0x20) * 2 + 1] !=3D (gs_base_shadow >> (8 * s= izeof(int)))) || + res[0x80 + (0x40 + 0x31) * 2] || res[0x80 + (0x40 + 0x31) * 2 + 1= ] ) + goto fail; + printf("okay\n"); + + printf("%-40s", "Testing wrmsrlist..."); + instr[0] =3D 0xf3; instr[1] =3D 0x0f; instr[2] =3D 0x01; instr[3] =3D = 0xc6; + regs.eip =3D (unsigned long)&instr[0]; + regs.rsi -=3D 0x11 * 8; + regs.rdi -=3D 0x11 * 8; + regs.rcx =3D 0x0002000100000000UL; + res[0x80 + 0x0f * 2] =3D MSR_SHADOW_GS_BASE; + res[0x80 + 0x20 * 2] =3D MSR_GS_BASE; + rc =3D x86_emulate(&ctxt, &emulops); + if ( (rc !=3D X86EMUL_OKAY) || + (regs.rip !=3D (unsigned long)&instr[4]) || + regs.rcx || + (gs_base !=3D 0x0000222244446666UL) || + (gs_base_shadow !=3D 0x0000111122224444UL) ) + goto fail; + emulops.write_msr =3D NULL; #endif printf("okay\n"); --- a/tools/tests/x86_emulator/x86-emulate.c +++ b/tools/tests/x86_emulator/x86-emulate.c @@ -87,6 +87,7 @@ bool emul_test_init(void) cpu_policy.feat.rdpid =3D true; cpu_policy.feat.lkgs =3D true; cpu_policy.feat.wrmsrns =3D true; + cpu_policy.feat.msrlist =3D true; cpu_policy.extd.clzero =3D true; =20 if ( cpu_has_xsave ) --- a/xen/arch/x86/cpu-policy.c +++ b/xen/arch/x86/cpu-policy.c @@ -778,6 +778,9 @@ static void __init calculate_hvm_max_pol __clear_bit(X86_FEATURE_XSAVES, fs); } =20 + if ( !cpu_has_vmx_msrlist ) + __clear_bit(X86_FEATURE_MSRLIST, fs); + /* * Xen doesn't use PKS, so the guest support for it has opted to not u= se * the VMCS load/save controls for efficiency reasons. This depends on --- a/xen/arch/x86/hvm/vmx/vmcs.c +++ b/xen/arch/x86/hvm/vmx/vmcs.c @@ -354,8 +354,9 @@ static int vmx_init_vmcs_config(bool bsp =20 if ( caps.cpu_based_exec_control & CPU_BASED_ACTIVATE_TERTIARY_CONTROL= S ) { - uint64_t opt =3D (TERTIARY_EXEC_VIRT_SPEC_CTRL | - TERTIARY_EXEC_EPT_PAGING_WRITE); + uint64_t opt =3D TERTIARY_EXEC_EPT_PAGING_WRITE | + TERTIARY_EXEC_ENABLE_MSRLIST | + TERTIARY_EXEC_VIRT_SPEC_CTRL; =20 caps.tertiary_exec_control =3D adjust_vmx_controls2( "Tertiary Exec Control", 0, opt, @@ -1103,7 +1104,8 @@ static int construct_vmcs(struct vcpu *v v->arch.hvm.vmx.exec_control |=3D CPU_BASED_RDTSC_EXITING; =20 v->arch.hvm.vmx.secondary_exec_control =3D vmx_caps.secondary_exec_con= trol; - v->arch.hvm.vmx.tertiary_exec_control =3D vmx_caps.tertiary_exec_cont= rol; + v->arch.hvm.vmx.tertiary_exec_control =3D vmx_caps.tertiary_exec_cont= rol & + ~TERTIARY_EXEC_ENABLE_MSRLIST; =20 /* * Disable features which we don't want active by default: --- a/xen/arch/x86/hvm/vmx/vmx.c +++ b/xen/arch/x86/hvm/vmx/vmx.c @@ -884,6 +884,20 @@ static void cf_check vmx_cpuid_policy_ch else vmx_set_msr_intercept(v, MSR_PKRS, VMX_MSR_RW); =20 + if ( cp->feat.msrlist ) + { + vmx_clear_msr_intercept(v, MSR_BARRIER, VMX_MSR_RW); + v->arch.hvm.vmx.tertiary_exec_control |=3D TERTIARY_EXEC_ENABLE_MS= RLIST; + vmx_update_tertiary_exec_control(v); + } + else if ( v->arch.hvm.vmx.tertiary_exec_control & + TERTIARY_EXEC_ENABLE_MSRLIST ) + { + vmx_set_msr_intercept(v, MSR_BARRIER, VMX_MSR_RW); + v->arch.hvm.vmx.tertiary_exec_control &=3D ~TERTIARY_EXEC_ENABLE_M= SRLIST; + vmx_update_tertiary_exec_control(v); + } + out: vmx_vmcs_exit(v); =20 @@ -3824,6 +3838,22 @@ gp_fault: return X86EMUL_EXCEPTION; } =20 +static bool cf_check is_msrlist( + const struct x86_emulate_state *state, const struct x86_emulate_ctxt *= ctxt) +{ + + if ( ctxt->opcode =3D=3D X86EMUL_OPC(0x0f, 0x01) ) + { + unsigned int rm, reg; + int mode =3D x86_insn_modrm(state, &rm, ®); + + /* This also includes WRMSRNS; should be okay. */ + return mode =3D=3D 3 && rm =3D=3D 6 && !reg; + } + + return false; +} + static void vmx_do_extint(struct cpu_user_regs *regs) { unsigned long vector; @@ -4631,6 +4661,17 @@ void asmlinkage vmx_vmexit_handler(struc } break; =20 + case EXIT_REASON_RDMSRLIST: + case EXIT_REASON_WRMSRLIST: + if ( vmx_guest_x86_mode(v) !=3D 8 || !currd->arch.cpuid->feat.msrl= ist ) + { + ASSERT_UNREACHABLE(); + hvm_inject_hw_exception(X86_EXC_UD, X86_EVENT_NO_EC); + } + else if ( !hvm_emulate_one_insn(is_msrlist, "MSR list") ) + hvm_inject_hw_exception(X86_EXC_GP, 0); + break; + case EXIT_REASON_VMXOFF: case EXIT_REASON_VMXON: case EXIT_REASON_VMCLEAR: --- a/xen/arch/x86/include/asm/hvm/vmx/vmcs.h +++ b/xen/arch/x86/include/asm/hvm/vmx/vmcs.h @@ -262,8 +262,13 @@ void vmx_vmcs_reload(struct vcpu *v); #define TERTIARY_EXEC_EPT_PAGING_WRITE BIT(2, UL) #define TERTIARY_EXEC_GUEST_PAGING_VERIFY BIT(3, UL) #define TERTIARY_EXEC_IPI_VIRT BIT(4, UL) +#define TERTIARY_EXEC_ENABLE_MSRLIST BIT(6, UL) #define TERTIARY_EXEC_VIRT_SPEC_CTRL BIT(7, UL) =20 +#define cpu_has_vmx_msrlist \ + (IS_ENABLED(CONFIG_INTEL_VMX) && \ + (vmx_caps.tertiary_exec_control & TERTIARY_EXEC_ENABLE_MSRLIST)) + #define cpu_has_vmx_virt_spec_ctrl \ (vmx_caps.tertiary_exec_control & TERTIARY_EXEC_VIRT_SPEC_CTRL) =20 --- a/xen/arch/x86/include/asm/hvm/vmx/vmx.h +++ b/xen/arch/x86/include/asm/hvm/vmx/vmx.h @@ -201,6 +201,8 @@ static inline void pi_clear_sn(struct pi #define EXIT_REASON_XRSTORS 64 #define EXIT_REASON_BUS_LOCK 74 #define EXIT_REASON_NOTIFY 75 +#define EXIT_REASON_RDMSRLIST 78 +#define EXIT_REASON_WRMSRLIST 79 /* Remember to also update VMX_PERF_EXIT_REASON_SIZE! */ =20 /* --- a/xen/arch/x86/include/asm/msr-index.h +++ b/xen/arch/x86/include/asm/msr-index.h @@ -24,6 +24,8 @@ #define APIC_BASE_ENABLE (_AC(1, ULL) << 11) #define APIC_BASE_ADDR_MASK _AC(0x000ffffffffff000, ULL) =20 +#define MSR_BARRIER 0x0000002f + #define MSR_TEST_CTRL 0x00000033 #define TEST_CTRL_SPLITLOCK_DETECT (_AC(1, ULL) << 29) #define TEST_CTRL_SPLITLOCK_DISABLE (_AC(1, ULL) << 31) --- a/xen/arch/x86/include/asm/perfc_defn.h +++ b/xen/arch/x86/include/asm/perfc_defn.h @@ -6,7 +6,7 @@ PERFCOUNTER_ARRAY(exceptions, =20 #ifdef CONFIG_HVM =20 -#define VMX_PERF_EXIT_REASON_SIZE 76 +#define VMX_PERF_EXIT_REASON_SIZE 80 #define VMEXIT_NPF_PERFC 143 #define SVM_PERF_EXIT_REASON_SIZE (VMEXIT_NPF_PERFC + 1) PERFCOUNTER_ARRAY(vmexits, "vmexits", --- a/xen/arch/x86/msr.c +++ b/xen/arch/x86/msr.c @@ -147,6 +147,12 @@ int guest_rdmsr(struct vcpu *v, uint32_t case MSR_AMD_PPIN: goto gp_fault; =20 + case MSR_BARRIER: + if ( !cp->feat.msrlist ) + goto gp_fault; + *val =3D 0; + break; + case MSR_IA32_FEATURE_CONTROL: /* * Architecturally, availability of this MSR is enumerated by the @@ -428,6 +434,7 @@ int guest_wrmsr(struct vcpu *v, uint32_t uint64_t rsvd; =20 /* Read-only */ + case MSR_BARRIER: case MSR_IA32_PLATFORM_ID: case MSR_CORE_CAPABILITIES: case MSR_INTEL_CORE_THREAD_COUNT: --- a/xen/arch/x86/x86_emulate/0f01.c +++ b/xen/arch/x86/x86_emulate/0f01.c @@ -11,6 +11,7 @@ #include "private.h" =20 #ifdef __XEN__ +#include #include #endif =20 @@ -28,6 +29,7 @@ int x86emul_0f01(struct x86_emulate_stat switch ( s->modrm ) { unsigned long base, limit, cr0, cr0w, cr4; + unsigned int n; struct segment_register sreg; uint64_t msr_val; =20 @@ -42,6 +44,64 @@ int x86emul_0f01(struct x86_emulate_stat ((uint64_t)regs->r(dx) << 32) | regs->eax, ctxt); goto done; + + case vex_f3: /* wrmsrlist */ + vcpu_must_have(msrlist); + generate_exception_if(!mode_64bit(), X86_EXC_UD); + generate_exception_if(!mode_ring0() || (regs->esi & 7) || + (regs->edi & 7), + X86_EXC_GP, 0); + fail_if(!ops->write_msr); + while ( regs->r(cx) ) + { + n =3D __builtin_ffsl(regs->r(cx)) - 1; + if ( (rc =3D ops->read(x86_seg_none, regs->r(si) + n * 8, + &msr_val, 8, ctxt)) !=3D X86EMUL_OKAY= ) + break; + generate_exception_if(msr_val !=3D (uint32_t)msr_val, + X86_EXC_GP, 0); + base =3D msr_val; + if ( (rc =3D ops->read(x86_seg_none, regs->r(di) + n * 8, + &msr_val, 8, ctxt)) !=3D X86EMUL_OKAY= || + (rc =3D ops->write_msr(base, msr_val, ctxt)) !=3D X86= EMUL_OKAY ) + break; + regs->r(cx) &=3D ~(1UL << n); + +#ifdef __XEN__ + if ( regs->r(cx) && local_events_need_delivery() ) + { + rc =3D X86EMUL_RETRY; + break; + } +#endif + } + goto done; + + case vex_f2: /* rdmsrlist */ + vcpu_must_have(msrlist); + generate_exception_if(!mode_64bit(), X86_EXC_UD); + generate_exception_if(!mode_ring0() || (regs->esi & 7) || + (regs->edi & 7), + X86_EXC_GP, 0); + fail_if(!ops->read_msr || !ops->write); + while ( regs->r(cx) ) + { + n =3D __builtin_ffsl(regs->r(cx)) - 1; + if ( (rc =3D ops->read(x86_seg_none, regs->r(si) + n * 8, + &msr_val, 8, ctxt)) !=3D X86EMUL_OKAY= ) + break; + generate_exception_if(msr_val !=3D (uint32_t)msr_val, + X86_EXC_GP, 0); + if ( (rc =3D ops->read_msr(msr_val, &msr_val, + ctxt)) !=3D X86EMUL_OKAY || + (rc =3D ops->write(x86_seg_none, regs->r(di) + n * 8, + &msr_val, 8, ctxt)) !=3D X86EMUL_OKA= Y ) + break; + regs->r(cx) &=3D ~(1UL << n); + } + if ( rc !=3D X86EMUL_OKAY ) + ctxt->regs->r(cx) =3D regs->r(cx); + goto done; } generate_exception(X86_EXC_UD); =20 --- a/xen/arch/x86/x86_emulate/private.h +++ b/xen/arch/x86/x86_emulate/private.h @@ -610,6 +610,7 @@ amd_like(const struct x86_emulate_ctxt * #define vcpu_has_lkgs() (ctxt->cpuid->feat.lkgs) #define vcpu_has_wrmsrns() (ctxt->cpuid->feat.wrmsrns) #define vcpu_has_avx_ifma() (ctxt->cpuid->feat.avx_ifma) +#define vcpu_has_msrlist() (ctxt->cpuid->feat.msrlist) #define vcpu_has_avx_vnni_int8() (ctxt->cpuid->feat.avx_vnni_int8) #define vcpu_has_avx_ne_convert() (ctxt->cpuid->feat.avx_ne_convert) #define vcpu_has_avx_vnni_int16() (ctxt->cpuid->feat.avx_vnni_int16) --- a/xen/arch/x86/x86_emulate/util.c +++ b/xen/arch/x86/x86_emulate/util.c @@ -100,6 +100,9 @@ bool cf_check x86_insn_is_mem_access(con break; =20 case X86EMUL_OPC(0x0f, 0x01): + /* {RD,WR}MSRLIST */ + if ( mode_64bit() && s->modrm =3D=3D 0xc6 ) + return s->vex.pfx >=3D vex_f3; /* Cover CLZERO. */ return (s->modrm_rm & 7) =3D=3D 4 && (s->modrm_reg & 7) =3D=3D 7; } @@ -160,7 +163,11 @@ bool cf_check x86_insn_is_mem_write(cons case 0xff: /* Grp5 */ break; =20 - case X86EMUL_OPC(0x0f, 0x01): /* CLZERO is the odd one. */ + case X86EMUL_OPC(0x0f, 0x01): + /* RDMSRLIST */ + if ( mode_64bit() && s->modrm =3D=3D 0xc6 ) + return s->vex.pfx =3D=3D vex_f2; + /* CLZERO is another odd one. */ return (s->modrm_rm & 7) =3D=3D 4 && (s->modrm_reg & 7) =3D=3D= 7; =20 default: --- a/xen/tools/gen-cpuid.py +++ b/xen/tools/gen-cpuid.py @@ -275,7 +275,7 @@ def crunch_numbers(state): # NO_LMSL indicates the absense of Long Mode Segment Limits, which # have been dropped in hardware. LM: [CX16, PCID, LAHF_LM, PAGE1GB, PKU, NO_LMSL, AMX_TILE, CMPCCXA= DD, - LKGS], + LKGS, MSRLIST], =20 # AMD K6-2+ and K6-III processors shipped with 3DNow+, beyond the # standard 3DNow in the earlier K6 processors. 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Wed, 18 Jun 2025 00:05:51 -0700 (PDT) Message-ID: <25af4f84-8e24-4738-bf4b-79e8ead3e970@suse.com> Date: Wed, 18 Jun 2025 09:05:44 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH v8 3/7] x86emul: support USER_MSR instructions From: Jan Beulich To: "xen-devel@lists.xenproject.org" Cc: Andrew Cooper , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= References: <585f1b0b-6768-4f9c-8f9f-bcf6e20fbfb7@suse.com> Content-Language: en-US Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <585f1b0b-6768-4f9c-8f9f-bcf6e20fbfb7@suse.com> Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @suse.com) X-ZM-MESSAGEID: 1750230371143116600 Content-Type: text/plain; charset="utf-8" While UWRMSR probably isn't of much use as long as we don't support UINTR, URDMSR may well be useful to guests even without that (depending on what OSes are willing to permit access to). Since the two VEX encodings introduce a lonely opcode point in map 7, for now don't bother introducing a full 256-entry table. Signed-off-by: Jan Beulich --- The retaining of (possible) #PF from the bitmap access is "speculative" (the spec doesn't mention #PF as a possible exception; conceivably this might also need converting to #GP). I'm a little wary of the "MSRs Writeable by UWRMSR" table that the spec has, and that our code thus also enforces: As new MSRs are added to that table, we'll need piecemeal updates to that switch() statement. The forced setting of cpu_policy.feat.utmr could likely be done globally, i.e. early in main(). Limiting its scope is merely "just in case". Thoughts? --- v8: Switch to using fallthrough pseudo-keyword. Re-base. v7.1: Add MSR-specific feature checks for UWRMSR (incl the UTMR feature bit and its overriding in the test harness). v7: Add missing vcpu_must_have() and override in emul_test_init(). Use MSR constants even more. v6: Add MSR_UINTR_TIMER to header. Use MSR constants in test harness. Re-base. v5: Correct ModR/M.reg check for VEX-encoded forms. Cosmetic test harness adjustment. Re-base. v4: MSR index input regs are 64-bit (albeit only the APX spec has it this way for now). v3: New. --- a/tools/tests/x86_emulator/predicates.c +++ b/tools/tests/x86_emulator/predicates.c @@ -864,7 +864,9 @@ static const struct { { { 0xf6 }, { 2, 2 }, T, R, pfx_66 }, /* adcx */ { { 0xf6 }, { 2, 2 }, T, R, pfx_f3 }, /* adox */ { { 0xf8 }, { 2, 2 }, F, W, pfx_66 }, /* movdir64b */ + { { 0xf8, 0xc0 }, { 0, 2 }, F, N, pfx_f3 }, /* uwrmsr */ { { 0xf8 }, { 2, 2 }, F, W, pfx_f3 }, /* enqcmds */ + { { 0xf8, 0xc0 }, { 0, 2 }, F, N, pfx_f2 }, /* urdmsr */ { { 0xf8 }, { 2, 2 }, F, W, pfx_f2 }, /* enqcmd */ { { 0xf9 }, { 2, 2 }, F, W }, /* movdiri */ }; @@ -1516,6 +1518,9 @@ static const struct vex { { { 0xde }, 3, T, R, pfx_66, W0, L0 }, /* vsm3rnds2 */ { { 0xdf }, 3, T, R, pfx_66, WIG, Ln }, /* vaeskeygenassist */ { { 0xf0 }, 3, T, R, pfx_f2, Wn, L0 }, /* rorx */ +}, vex_map7[] =3D { + { { 0xf8, 0xc0 }, 6, F, N, pfx_f3, W0, L0 }, /* uwrmsr */ + { { 0xf8, 0xc0 }, 6, F, N, pfx_f2, W0, L0 }, /* urdmsr */ }; =20 static const struct { @@ -1525,6 +1530,10 @@ static const struct { { vex_0f, ARRAY_SIZE(vex_0f) }, { vex_0f38, ARRAY_SIZE(vex_0f38) }, { vex_0f3a, ARRAY_SIZE(vex_0f3a) }, + { NULL, 0 }, /* map 4 */ + { NULL, 0 }, /* map 5 */ + { NULL, 0 }, /* map 6 */ + { vex_map7, ARRAY_SIZE(vex_map7) }, }; =20 static const struct xop { @@ -2420,7 +2429,8 @@ void predicates_test(void *instr, struct =20 if ( vex[x].tbl[t].w =3D=3D WIG || (vex[x].tbl[t].w & W0) ) { - memcpy(ptr, vex[x].tbl[t].opc, vex[x].tbl[t].len); + memcpy(ptr, vex[x].tbl[t].opc, + MIN(vex[x].tbl[t].len, ARRAY_SIZE(vex->tbl->opc= ))); =20 if ( vex[x].tbl[t].l =3D=3D LIG || (vex[x].tbl[t].l & = L0) ) do_test(instr, vex[x].tbl[t].len + ((void *)ptr - = instr), @@ -2430,7 +2440,8 @@ void predicates_test(void *instr, struct if ( vex[x].tbl[t].l =3D=3D LIG || (vex[x].tbl[t].l & = L1) ) { ptr[-1] |=3D 4; - memcpy(ptr, vex[x].tbl[t].opc, vex[x].tbl[t].len); + memcpy(ptr, vex[x].tbl[t].opc, + MIN(vex[x].tbl[t].len, ARRAY_SIZE(vex->tbl-= >opc))); =20 do_test(instr, vex[x].tbl[t].len + ((void *)ptr - = instr), vex[x].tbl[t].modrm ? (void *)ptr - instr = + 1 : 0, @@ -2441,7 +2452,8 @@ void predicates_test(void *instr, struct if ( vex[x].tbl[t].w =3D=3D WIG || (vex[x].tbl[t].w & W1) ) { ptr[-1] =3D 0xf8 | vex[x].tbl[t].pfx; - memcpy(ptr, vex[x].tbl[t].opc, vex[x].tbl[t].len); + memcpy(ptr, vex[x].tbl[t].opc, + MIN(vex[x].tbl[t].len, ARRAY_SIZE(vex->tbl->opc= ))); =20 if ( vex[x].tbl[t].l =3D=3D LIG || (vex[x].tbl[t].l & = L0) ) do_test(instr, vex[x].tbl[t].len + ((void *)ptr - = instr), @@ -2451,7 +2463,8 @@ void predicates_test(void *instr, struct if ( vex[x].tbl[t].l =3D=3D LIG || (vex[x].tbl[t].l & = L1) ) { ptr[-1] |=3D 4; - memcpy(ptr, vex[x].tbl[t].opc, vex[x].tbl[t].len); + memcpy(ptr, vex[x].tbl[t].opc, + MIN(vex[x].tbl[t].len, ARRAY_SIZE(vex->tbl-= >opc))); =20 do_test(instr, vex[x].tbl[t].len + ((void *)ptr - = instr), vex[x].tbl[t].modrm ? (void *)ptr - instr = + 1 : 0, --- a/tools/tests/x86_emulator/test_x86_emulator.c +++ b/tools/tests/x86_emulator/test_x86_emulator.c @@ -674,6 +674,7 @@ static int blk( =20 #ifdef __x86_64__ static unsigned long gs_base, gs_base_shadow; +static unsigned long uintr_timer; #endif =20 static int read_segment( @@ -708,6 +709,15 @@ static int write_segment( =20 return X86EMUL_OKAY; } + +static const uint8_t __attribute__((aligned(0x1000))) umsr_bitmap[0x1000] = =3D { +#define RD(msr) [(msr) >> 3] =3D 1 << ((msr) & 7) +#define WR(msr) [0x800 + ((msr) >> 3)] =3D 1 << ((msr) & 7) + RD(MSR_IA32_APERF), + WR(MSR_UINTR_TIMER), +#undef WR +#undef RD +}; #endif =20 static int read_msr( @@ -717,10 +727,22 @@ static int read_msr( { switch ( reg ) { +#ifdef __x86_64__ + case MSR_USER_MSR_CTL: + *val =3D (unsigned long)umsr_bitmap | 1; + return X86EMUL_OKAY; +#endif + case MSR_BARRIER: *val =3D 0; return X86EMUL_OKAY; =20 + case MSR_IA32_APERF: +#define APERF_LO_VALUE 0xAEAEAEAE +#define APERF_HI_VALUE 0xEAEAEAEA + *val =3D ((uint64_t)APERF_HI_VALUE << 32) | APERF_LO_VALUE; + return X86EMUL_OKAY; + case MSR_EFER: *val =3D ctxt->addr_size > 32 ? EFER_LME | EFER_LMA : 0; return X86EMUL_OKAY; @@ -756,6 +778,12 @@ static int write_msr( { switch ( reg ) { + case MSR_UINTR_TIMER: + if ( ctxt->addr_size < 64 ) + break; + uintr_timer =3D val; + return X86EMUL_OKAY; + case MSR_GS_BASE: if ( ctxt->addr_size < 64 || !is_canonical_address(val) ) break; @@ -1484,6 +1512,68 @@ int main(int argc, char **argv) (gs_base !=3D 0x0000222244446666UL) || (gs_base_shadow !=3D 0x0000111122224444UL) ) goto fail; + printf("okay\n"); + + printf("%-40s", "Testing urdmsr %rdx,%rcx..."); + instr[0] =3D 0xf2; instr[1] =3D 0x0f; instr[2] =3D 0x38; instr[3] =3D = 0xf8; instr[4] =3D 0xd1; + regs.rip =3D (unsigned long)&instr[0]; + regs.rdx =3D MSR_IA32_APERF; + rc =3D x86_emulate(&ctxt, &emulops); + if ( (rc !=3D X86EMUL_OKAY) || + (regs.rip !=3D (unsigned long)&instr[5]) || + (regs.rcx !=3D (((uint64_t)APERF_HI_VALUE << 32) | APERF_LO_VALUE= )) ) + goto fail; + printf("okay\n"); + + printf("%-40s", "Testing urdmsr $MSR_IA32_APERF,%rdx..."); + instr[0] =3D 0xc4; instr[1] =3D 0xe7; instr[2] =3D 0x7b; instr[3] =3D = 0xf8; instr[4] =3D 0xc2; + *(uint32_t *)&instr[5] =3D MSR_IA32_APERF; + regs.rip =3D (unsigned long)&instr[0]; + rc =3D x86_emulate(&ctxt, &emulops); + if ( (rc !=3D X86EMUL_OKAY) || + (regs.rip !=3D (unsigned long)&instr[9]) || + (regs.rdx !=3D (((uint64_t)APERF_HI_VALUE << 32) | APERF_LO_VALUE= )) ) + goto fail; + printf("okay\n"); + + /* Our write_msr() knows of MSR_UINTR_TIMER. */ + i =3D cpu_policy.feat.utmr; + cpu_policy.feat.utmr =3D true; + + printf("%-40s", "Testing uwrmsr %rdi,%rsi..."); + instr[0] =3D 0xf3; instr[1] =3D 0x0f; instr[2] =3D 0x38; instr[3] =3D = 0xf8; instr[4] =3D 0xf7; + regs.rip =3D (unsigned long)&instr[0]; + regs.rsi =3D MSR_UINTR_TIMER; + regs.rdi =3D 0x0011223344556677UL; + rc =3D x86_emulate(&ctxt, &emulops); + if ( (rc !=3D X86EMUL_OKAY) || + (regs.rip !=3D (unsigned long)&instr[5]) || + (uintr_timer !=3D 0x0011223344556677UL) ) + goto fail; + printf("okay\n"); + + printf("%-40s", "Testing uwrmsr %rsi,$MSR_UINTR_TIMER..."); + instr[0] =3D 0xc4; instr[1] =3D 0xe7; instr[2] =3D 0x7a; instr[3] =3D = 0xf8; instr[4] =3D 0xc6; + *(uint32_t *)&instr[5] =3D MSR_UINTR_TIMER; + regs.rip =3D (unsigned long)&instr[0]; + regs.rsi =3D 0x8877665544332211UL; + rc =3D x86_emulate(&ctxt, &emulops); + if ( (rc !=3D X86EMUL_OKAY) || + (regs.rip !=3D (unsigned long)&instr[9]) || + (uintr_timer !=3D 0x8877665544332211UL) ) + goto fail; + printf("okay\n"); + + cpu_policy.feat.utmr =3D i; + + printf("%-40s", "Testing uwrmsr %rsi,$MSR_UARCH_MISC_CTRL..."); + *(uint32_t *)&instr[5] =3D MSR_UARCH_MISC_CTRL; + regs.rip =3D (unsigned long)&instr[0]; + regs.rsi =3D 0; + rc =3D x86_emulate(&ctxt, &emulops); + if ( (rc !=3D X86EMUL_EXCEPTION) || + (regs.rip !=3D (unsigned long)&instr[0]) ) + goto fail; =20 emulops.write_msr =3D NULL; #endif --- a/tools/tests/x86_emulator/x86-emulate.c +++ b/tools/tests/x86_emulator/x86-emulate.c @@ -88,6 +88,7 @@ bool emul_test_init(void) cpu_policy.feat.lkgs =3D true; cpu_policy.feat.wrmsrns =3D true; cpu_policy.feat.msrlist =3D true; + cpu_policy.feat.user_msr =3D true; cpu_policy.extd.clzero =3D true; =20 if ( cpu_has_xsave ) --- a/xen/arch/x86/include/asm/msr-index.h +++ b/xen/arch/x86/include/asm/msr-index.h @@ -24,6 +24,10 @@ #define APIC_BASE_ENABLE (_AC(1, ULL) << 11) #define APIC_BASE_ADDR_MASK _AC(0x000ffffffffff000, ULL) =20 +#define MSR_USER_MSR_CTL 0x0000001c +#define USER_MSR_ENABLE (_AC(1, ULL) << 0) +#define USER_MSR_ADDR_MASK 0xfffffffffffff000ULL + #define MSR_BARRIER 0x0000002f =20 #define MSR_TEST_CTRL 0x00000033 @@ -195,6 +199,8 @@ #define MCU_CONTROL_DIS_MCU_LOAD (_AC(1, ULL) << 1) #define MCU_CONTROL_EN_SMM_BYPASS (_AC(1, ULL) << 2) =20 +#define MSR_UINTR_TIMER 0x00001b00 + #define MSR_UARCH_MISC_CTRL 0x00001b01 #define UARCH_CTRL_DOITM (_AC(1, ULL) << 0) =20 --- a/xen/arch/x86/x86_emulate/decode.c +++ b/xen/arch/x86/x86_emulate/decode.c @@ -903,7 +903,7 @@ decode_0f38(struct x86_emulate_state *s, { case 0x00 ... 0xef: case 0xf2 ... 0xf5: - case 0xf7 ... 0xf8: + case 0xf7: case 0xfa ... 0xff: s->op_bytes =3D 0; /* fall through */ @@ -948,6 +948,18 @@ decode_0f38(struct x86_emulate_state *s, case X86EMUL_OPC_VEX_F2(0, 0xf7): /* shrx */ break; =20 + case 0xf8: + if ( s->modrm_mod =3D=3D 3 ) /* u{rd,wr}msr */ + { + s->desc =3D DstMem | SrcReg | Mov; + s->op_bytes =3D 8; + s->simd_size =3D simd_none; + } + else /* movdir64b / enqcmd{,s} */ + s->op_bytes =3D 0; + ctxt->opcode |=3D MASK_INSR(s->vex.pfx, X86EMUL_OPC_PFX_MASK); + break; + default: s->op_bytes =3D 0; break; @@ -1246,6 +1258,16 @@ int x86emul_decode(struct x86_emulate_st */ d =3D twobyte_table[0x38].desc; break; + + case vex_map7: + opcode |=3D MASK_INSR(7, X86EMUL_OPC_EXT_MASK); + /* + * No table lookup here for now, as there's only a= single + * opcode point (0xf8) populated in map 7. + */ + d =3D DstMem | SrcImm | ModRM | Mov; + s->op_bytes =3D 8; + break; } } else if ( s->ext < ext_8f08 + ARRAY_SIZE(xop_table) ) @@ -1602,6 +1624,7 @@ int x86emul_decode(struct x86_emulate_st s->simd_size =3D ext8f09_table[b].simd_size; break; =20 + case ext_map7: case ext_8f08: case ext_8f0a: /* @@ -1816,6 +1839,7 @@ int x86emul_decode(struct x86_emulate_st =20 case ext_map5: case ext_map6: + case ext_map7: case ext_8f09: case ext_8f0a: break; --- a/xen/arch/x86/x86_emulate/private.h +++ b/xen/arch/x86/x86_emulate/private.h @@ -202,6 +202,7 @@ enum vex_opcx { vex_0f3a, evex_map5 =3D 5, evex_map6, + vex_map7, }; =20 enum vex_pfx { @@ -258,6 +259,7 @@ struct x86_emulate_state { ext_0f3a =3D vex_0f3a, ext_map5 =3D evex_map5, ext_map6 =3D evex_map6, + ext_map7 =3D vex_map7, /* * For XOP use values such that the respective instruction field * can be used without adjustment. @@ -614,6 +616,7 @@ amd_like(const struct x86_emulate_ctxt * #define vcpu_has_avx_vnni_int8() (ctxt->cpuid->feat.avx_vnni_int8) #define vcpu_has_avx_ne_convert() (ctxt->cpuid->feat.avx_ne_convert) #define vcpu_has_avx_vnni_int16() (ctxt->cpuid->feat.avx_vnni_int16) +#define vcpu_has_user_msr() (ctxt->cpuid->feat.user_msr) =20 #define vcpu_must_have(feat) \ generate_exception_if(!vcpu_has_##feat(), X86_EXC_UD) --- a/xen/arch/x86/x86_emulate/x86_emulate.c +++ b/xen/arch/x86/x86_emulate/x86_emulate.c @@ -7075,10 +7075,73 @@ x86_emulate( state->simd_size =3D simd_none; break; =20 - case X86EMUL_OPC_F2(0x0f38, 0xf8): /* enqcmd r,m512 */ - case X86EMUL_OPC_F3(0x0f38, 0xf8): /* enqcmds r,m512 */ + case X86EMUL_OPC_F3(0x0f38, 0xf8): /* enqcmds r,m512 / uwrmsr r64,r32 = */ + case X86EMUL_OPC_F2(0x0f38, 0xf8): /* enqcmd r,m512 / urdmsr r32,r64 */ + if ( ea.type =3D=3D OP_MEM ) + goto enqcmd; + imm1 =3D src.val; + fallthrough; + case X86EMUL_OPC_VEX_F3(7, 0xf8): /* uwrmsr r64,imm32 */ + case X86EMUL_OPC_VEX_F2(7, 0xf8): /* urdmsr imm32,r64 */ + generate_exception_if(!mode_64bit() || ea.type !=3D OP_REG, X86_EX= C_UD); + generate_exception_if(vex.l || vex.w, X86_EXC_UD); + generate_exception_if(vex.opcx && ((modrm_reg & 7) || vex.reg !=3D= 0xf), + X86_EXC_UD); + vcpu_must_have(user_msr); + fail_if(!ops->read_msr); + if ( ops->read_msr(MSR_USER_MSR_CTL, &msr_val, ctxt) !=3D X86EMUL_= OKAY ) + { + x86_emul_reset_event(ctxt); + msr_val =3D 0; + } + generate_exception_if(!(msr_val & USER_MSR_ENABLE), X86_EXC_UD); + generate_exception_if(imm1 & ~0x3fff, X86_EXC_GP, 0); + + /* Check the corresponding bitmap. */ + ea.mem.off =3D msr_val & ~0xfff; + if ( vex.pfx !=3D vex_f2 ) + ea.mem.off +=3D 0x800; + ea.mem.off +=3D imm1 >> 3; + if ( (rc =3D ops->read(x86_seg_sys, ea.mem.off, &b, 1, + ctxt)) !=3D X86EMUL_OKAY ) + goto done; + generate_exception_if(!(b & (1 << (imm1 & 7))), X86_EXC_GP, 0); + + /* Carry out the actual MSR access. */ + if ( vex.pfx =3D=3D vex_f2 ) + { + /* urdmsr */ + if ( (rc =3D ops->read_msr(imm1, &msr_val, ctxt)) !=3D X86EMUL= _OKAY ) + goto done; + dst.val =3D msr_val; + ASSERT(dst.type =3D=3D OP_REG); + dst.bytes =3D 8; + } + else + { + /* uwrmsr */ + switch ( imm1 ) + { + case 0x1b00: /* UINTR_TIMER */ + generate_exception_if(!cp->feat.utmr, X86_EXC_GP, 0); + break; + + case 0x1b01: /* UARCH_MISC_CTL */ + generate_exception_if(!cp->arch_caps.doitm, X86_EXC_GP, 0); + break; + + default: + generate_exception(X86_EXC_GP, 0); + } + fail_if(!ops->write_msr); + if ( (rc =3D ops->write_msr(imm1, dst.val, ctxt)) !=3D X86EMUL= _OKAY ) + goto done; + dst.type =3D OP_NONE; + } + break; + + enqcmd: host_and_vcpu_must_have(enqcmd); - generate_exception_if(ea.type !=3D OP_MEM, X86_EXC_UD); generate_exception_if(vex.pfx !=3D vex_f2 && !mode_ring0(), X86_EX= C_GP, 0); src.val =3D truncate_ea(*dst.reg); generate_exception_if(!is_aligned(x86_seg_es, src.val, 64, ctxt, o= ps), --- a/xen/include/public/arch-x86/cpufeatureset.h +++ b/xen/include/public/arch-x86/cpufeatureset.h @@ -357,7 +357,9 @@ XEN_CPUFEATURE(AVX_VNNI_INT8, 15*32 XEN_CPUFEATURE(AVX_NE_CONVERT, 15*32+ 5) /*A AVX-NE-CONVERT Instructi= ons */ XEN_CPUFEATURE(AMX_COMPLEX, 15*32+ 8) /* AMX Complex Instructions= */ XEN_CPUFEATURE(AVX_VNNI_INT16, 15*32+10) /*A AVX-VNNI-INT16 Instructi= ons */ +XEN_CPUFEATURE(UTMR, 15*32+13) /* User Timer */ XEN_CPUFEATURE(PREFETCHI, 15*32+14) /*A PREFETCHIT{0,1} Instruct= ions */ +XEN_CPUFEATURE(USER_MSR, 15*32+15) /* U{RD,WR}MSR Instructions= */ XEN_CPUFEATURE(UIRET_UIF, 15*32+17) /* UIRET updates UIF */ XEN_CPUFEATURE(CET_SSS, 15*32+18) /* CET Supervisor Shadow St= acks safe to use */ XEN_CPUFEATURE(SLSM, 15*32+24) /* Static Lockstep Mode */ --- a/xen/tools/gen-cpuid.py +++ b/xen/tools/gen-cpuid.py @@ -275,7 +275,7 @@ def crunch_numbers(state): # NO_LMSL indicates the absense of Long Mode Segment Limits, which # have been dropped in hardware. LM: [CX16, PCID, LAHF_LM, PAGE1GB, PKU, NO_LMSL, AMX_TILE, CMPCCXA= DD, - LKGS, MSRLIST], + LKGS, MSRLIST, USER_MSR], =20 # AMD K6-2+ and K6-III processors shipped with 3DNow+, beyond the # standard 3DNow in the earlier K6 processors. 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Wed, 18 Jun 2025 00:06:20 -0700 (PDT) Message-ID: <5b0be3b6-53fb-42ab-b2d9-141f7fae1496@suse.com> Date: Wed, 18 Jun 2025 09:06:13 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH v8 4/7] x86/cpu-policy: re-arrange no-VMX logic From: Jan Beulich To: "xen-devel@lists.xenproject.org" Cc: Andrew Cooper , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= References: <585f1b0b-6768-4f9c-8f9f-bcf6e20fbfb7@suse.com> Content-Language: en-US Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <585f1b0b-6768-4f9c-8f9f-bcf6e20fbfb7@suse.com> Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @suse.com) X-ZM-MESSAGEID: 1750230397169116600 Content-Type: text/plain; charset="utf-8" Move the PKS check into an "else" for the corresponding "if()", such that further adjustments (like for USER_MSR) can easily be put there as well. Signed-off-by: Jan Beulich --- v5: Re-base. v4: New. --- a/xen/arch/x86/cpu-policy.c +++ b/xen/arch/x86/cpu-policy.c @@ -777,19 +777,20 @@ static void __init calculate_hvm_max_pol if ( !cpu_has_vmx_xsaves ) __clear_bit(X86_FEATURE_XSAVES, fs); } + else + { + /* + * Xen doesn't use PKS, so the guest support for it has opted to n= ot use + * the VMCS load/save controls for efficiency reasons. This depen= ds on + * the exact vmentry/exit behaviour, so don't expose PKS in other + * situations until someone has cross-checked the behaviour for sa= fety. + */ + __clear_bit(X86_FEATURE_PKS, fs); + } =20 if ( !cpu_has_vmx_msrlist ) __clear_bit(X86_FEATURE_MSRLIST, fs); =20 - /* - * Xen doesn't use PKS, so the guest support for it has opted to not u= se - * the VMCS load/save controls for efficiency reasons. This depends on - * the exact vmentry/exit behaviour, so don't expose PKS in other - * situations until someone has cross-checked the behaviour for safety. - */ - if ( !cpu_has_vmx ) - __clear_bit(X86_FEATURE_PKS, fs); - /*=20 * Make adjustments to possible (nested) virtualization features expos= ed * to the guest From nobody Fri Oct 31 03:42:50 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=quarantine dis=none) header.from=suse.com ARC-Seal: i=1; a=rsa-sha256; t=1750230681; cv=none; d=zohomail.com; s=zohoarc; b=bmei05CPXVUfoBqftAbT4Tdodx7PXZJQKWtkAV7XdOIOsLcAmNvNlNx+LSUC+wHseBHiWMxyNDKUHFX0va6tmUvHak8N1dZQbFhE1Nsc/6LQtofhMv9J1rATADbNF+ldBRS8il22ROBaFGft+Swi752Gwz0jdTe5dOCpAdtSBqU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1750230681; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=1+Q+rknhKt/qTaPwfO0xWIDCympY5+1iNAgBNhqS5wA=; b=KpNAES/25eeR2Wx1HJpgMcSjQWHjuVwdNxjdFgQDizAStrUs67VI4VcBT5IWlTC0ZcbELbsSdiJS7KURI7FCQrZWtzuuDxl6pRsqFCm0ctLk3C8vtJcZIIX6Of49d/z4z7rQIgH050lcZQ8OGoJkR6BFNfbzGMVFr/VREAsbZGc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=quarantine dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1750230681530674.2713457608583; Wed, 18 Jun 2025 00:11:21 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.1018882.1395758 (Exim 4.92) (envelope-from ) id 1uRmwk-0001Cj-H5; Wed, 18 Jun 2025 07:10:58 +0000 Received: by outflank-mailman (output) from mailman id 1018882.1395758; Wed, 18 Jun 2025 07:10:58 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uRmwk-0001Cc-Ct; Wed, 18 Jun 2025 07:10:58 +0000 Received: by outflank-mailman (input) for mailman id 1018882; Wed, 18 Jun 2025 07:10:57 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uRmsj-0004U2-JB for xen-devel@lists.xenproject.org; Wed, 18 Jun 2025 07:06:49 +0000 Received: from mail-wm1-x32e.google.com (mail-wm1-x32e.google.com [2a00:1450:4864:20::32e]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id ccadedfc-4c12-11f0-b894-0df219b8e170; Wed, 18 Jun 2025 09:06:47 +0200 (CEST) Received: by mail-wm1-x32e.google.com with SMTP id 5b1f17b1804b1-453398e90e9so36368465e9.1 for ; Wed, 18 Jun 2025 00:06:47 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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Wed, 18 Jun 2025 00:06:47 -0700 (PDT) Message-ID: <0557b0e8-cd02-4812-9b58-62784afafe8e@suse.com> Date: Wed, 18 Jun 2025 09:06:39 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH v8 5/7] VMX: support USER_MSR From: Jan Beulich To: "xen-devel@lists.xenproject.org" Cc: Andrew Cooper , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= References: <585f1b0b-6768-4f9c-8f9f-bcf6e20fbfb7@suse.com> Content-Language: en-US Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <585f1b0b-6768-4f9c-8f9f-bcf6e20fbfb7@suse.com> Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @suse.com) X-ZM-MESSAGEID: 1750230682921116600 Content-Type: text/plain; charset="utf-8" Hook up the new VM exit codes and handle guest accesses, context switch, and save/restore. At least for now don't allow the guest direct access to the control MSR; this may need changing if guests were to frequently access it (e.g. on their own context switch path). While there also correct a one-off in union ldt_or_tr_instr_info's comment. Signed-off-by: Jan Beulich --- Needing to change two places in hvm.c continues to be unhelpful; I recall I already did forget to also adjust hvm_load_cpu_msrs() for XFD. Considering that MSRs typically arrive in the order the table has it, couldn't we incrementally look up the incoming MSR index there, falling back to a full lookup only when the incremental lookup failed (and thus not normally re-iterating through the initial part of the array)? Said comment in union ldt_or_tr_instr_info is further odd (same for union gdt_or_idt_instr_info's) in that Instruction Information is only a 32-bit field. Hence bits 32-63 aren't undefined, but simply don't exist. RFC: The wee attempt to "deal" with nested is likely wrong, but I'm afraid I simply don't know where such enforcement would be done properly. Returning an error there is also commented out, for domain_cpu_policy_changed() returning void without "x86/xstate: re-size save area when CPUID policy changes" in place. --- v8: Re-base. v5: Introduce user_msr_gpr(). v4: New. --- a/xen/arch/x86/cpu-policy.c +++ b/xen/arch/x86/cpu-policy.c @@ -786,6 +786,12 @@ static void __init calculate_hvm_max_pol * situations until someone has cross-checked the behaviour for sa= fety. */ __clear_bit(X86_FEATURE_PKS, fs); + + /* + * Don't expose USER_MSR until it is known how (if at all) it is + * virtualized on SVM. + */ + __clear_bit(X86_FEATURE_USER_MSR, fs); } =20 if ( !cpu_has_vmx_msrlist ) --- a/xen/arch/x86/domain.c +++ b/xen/arch/x86/domain.c @@ -450,6 +450,10 @@ void domain_cpu_policy_changed(struct do } } =20 + /* Nested doesn't have the necessary processing, yet. */ + if ( nestedhvm_enabled(d) && p->feat.user_msr ) + return /* -EINVAL */; + for_each_vcpu ( d, v ) { cpu_policy_updated(v); --- a/xen/arch/x86/hvm/hvm.c +++ b/xen/arch/x86/hvm/hvm.c @@ -1383,6 +1383,7 @@ static int cf_check hvm_load_cpu_xsave_s =20 #define HVM_CPU_MSR_SIZE(cnt) offsetof(struct hvm_msr, msr[cnt]) static const uint32_t msrs_to_send[] =3D { + MSR_USER_MSR_CTL, MSR_SPEC_CTRL, MSR_INTEL_MISC_FEATURES_ENABLES, MSR_PKRS, @@ -1537,6 +1538,7 @@ static int cf_check hvm_load_cpu_msrs(st { int rc; =20 + case MSR_USER_MSR_CTL: case MSR_SPEC_CTRL: case MSR_INTEL_MISC_FEATURES_ENABLES: case MSR_PKRS: --- a/xen/arch/x86/hvm/vmx/vmx.c +++ b/xen/arch/x86/hvm/vmx/vmx.c @@ -689,13 +689,18 @@ static void cf_check vmx_vcpu_destroy(st } =20 /* - * To avoid MSR save/restore at every VM exit/entry time, we restore - * the x86_64 specific MSRs at domain switch time. Since these MSRs - * are not modified once set for para domains, we don't save them, - * but simply reset them to values set in percpu_traps_init(). + * To avoid MSR save/restore at every VM exit/entry time, we restore the + * x86_64 specific MSRs at vcpu switch time. Since these MSRs are not + * modified once set for para domains, we don't save them, but simply clear + * them or reset them to values set in percpu_traps_init(). */ -static void vmx_restore_host_msrs(void) +static void vmx_restore_host_msrs(const struct vcpu *v) { + const struct vcpu_msrs *msrs =3D v->arch.msrs; + + if ( msrs->user_msr_ctl.enable ) + wrmsrl(MSR_USER_MSR_CTL, 0); + /* No PV guests? No need to restore host SYSCALL infrastructure. */ if ( !IS_ENABLED(CONFIG_PV) ) return; @@ -749,6 +754,9 @@ static void vmx_restore_guest_msrs(struc =20 if ( cp->feat.pks ) wrpkrs(msrs->pkrs); + + if ( msrs->user_msr_ctl.enable ) + wrmsrl(MSR_USER_MSR_CTL, msrs->user_msr_ctl.raw); } =20 void vmx_update_cpu_exec_control(struct vcpu *v) @@ -1192,7 +1200,7 @@ static void cf_check vmx_ctxt_switch_fro if ( !v->arch.fully_eager_fpu ) vmx_fpu_leave(v); vmx_save_guest_msrs(v); - vmx_restore_host_msrs(); + vmx_restore_host_msrs(v); vmx_save_dr(v); =20 if ( v->domain->arch.hvm.pi_ops.flags & PI_CSW_FROM ) @@ -4172,6 +4180,14 @@ static int vmx_handle_apic_write(void) return vlapic_apicv_write(current, exit_qualification & 0xfff); } =20 +static unsigned int user_msr_gpr(void) +{ + user_msr_instr_info_t info; + + __vmread(VMX_INSTRUCTION_INFO, &info.raw); + return info.gpr; +} + static void undo_nmis_unblocked_by_iret(void) { unsigned long guest_info; @@ -4672,6 +4688,41 @@ void asmlinkage vmx_vmexit_handler(struc hvm_inject_hw_exception(X86_EXC_GP, 0); break; =20 + case EXIT_REASON_URDMSR: + { + uint64_t msr_content =3D 0; + + __vmread(EXIT_QUALIFICATION, &exit_qualification); + switch ( hvm_msr_read_intercept(exit_qualification, &msr_content) ) + { + case X86EMUL_OKAY: + *decode_gpr(regs, user_msr_gpr()) =3D msr_content; + update_guest_eip(); /* Safe: URDMSR */ + break; + + case X86EMUL_EXCEPTION: + hvm_inject_hw_exception(X86_EXC_GP, 0); + break; + } + break; + } + + case EXIT_REASON_UWRMSR: + __vmread(EXIT_QUALIFICATION, &exit_qualification); + switch ( hvm_msr_write_intercept(exit_qualification, + *decode_gpr(regs, user_msr_gpr()), + true) ) + { + case X86EMUL_OKAY: + update_guest_eip(); /* Safe: UWRMSR */ + break; + + case X86EMUL_EXCEPTION: + hvm_inject_hw_exception(X86_EXC_GP, 0); + break; + } + break; + case EXIT_REASON_VMXOFF: case EXIT_REASON_VMXON: case EXIT_REASON_VMCLEAR: --- a/xen/arch/x86/include/asm/hvm/vmx/vmx.h +++ b/xen/arch/x86/include/asm/hvm/vmx/vmx.h @@ -203,6 +203,8 @@ static inline void pi_clear_sn(struct pi #define EXIT_REASON_NOTIFY 75 #define EXIT_REASON_RDMSRLIST 78 #define EXIT_REASON_WRMSRLIST 79 +#define EXIT_REASON_URDMSR 80 +#define EXIT_REASON_UWRMSR 81 /* Remember to also update VMX_PERF_EXIT_REASON_SIZE! */ =20 /* @@ -577,8 +579,18 @@ typedef union ldt_or_tr_instr_info { base_reg_invalid :1, /* bit 27 - Base register invalid */ instr_identity :1, /* bit 28 - 0:LDT, 1:TR */ instr_write :1, /* bit 29 - 0:store, 1:load */ - :34; /* bits 31:63 - Undefined */ + :34; /* bits 30:63 - Undefined */ }; } ldt_or_tr_instr_info_t; =20 +/* VM-Exit instruction info for URDMSR and UWRMSR */ +typedef union user_msr_instr_info { + unsigned long raw; + struct { + unsigned int :3, /* Bits 0:2 - Undefined */ + gpr :4, /* Bits 3:6 - Source/Destination regi= ster */ + :25; /* bits 7:31 - Undefined */ + }; +} user_msr_instr_info_t; + #endif /* __ASM_X86_HVM_VMX_VMX_H__ */ --- a/xen/arch/x86/include/asm/msr.h +++ b/xen/arch/x86/include/asm/msr.h @@ -277,6 +277,20 @@ uint64_t msr_spec_ctrl_valid_bits(const struct vcpu_msrs { /* + * 0x0000001c - MSR_USER_MSR_CTL + * + * Value is guest chosen, and always loaded in vcpu context. + */ + union { + uint64_t raw; + struct { + bool enable:1; + unsigned int :11; + unsigned long bitmap:52; + }; + } user_msr_ctl; + + /* * 0x00000048 - MSR_SPEC_CTRL * 0xc001011f - MSR_VIRT_SPEC_CTRL (if X86_FEATURE_AMD_SSBD) * --- a/xen/arch/x86/include/asm/perfc_defn.h +++ b/xen/arch/x86/include/asm/perfc_defn.h @@ -6,7 +6,7 @@ PERFCOUNTER_ARRAY(exceptions, =20 #ifdef CONFIG_HVM =20 -#define VMX_PERF_EXIT_REASON_SIZE 80 +#define VMX_PERF_EXIT_REASON_SIZE 82 #define VMEXIT_NPF_PERFC 143 #define SVM_PERF_EXIT_REASON_SIZE (VMEXIT_NPF_PERFC + 1) PERFCOUNTER_ARRAY(vmexits, "vmexits", --- a/xen/arch/x86/msr.c +++ b/xen/arch/x86/msr.c @@ -279,6 +279,12 @@ int guest_rdmsr(struct vcpu *v, uint32_t *val =3D msrs->xss.raw; break; =20 + case MSR_USER_MSR_CTL: + if ( !cp->feat.user_msr ) + goto gp_fault; + *val =3D msrs->user_msr_ctl.raw; + break; + case 0x40000000 ... 0x400001ff: if ( is_viridian_domain(d) ) { @@ -617,6 +623,19 @@ int guest_wrmsr(struct vcpu *v, uint32_t msrs->xss.raw =3D val; break; =20 + case MSR_USER_MSR_CTL: + if ( !cp->feat.user_msr ) + goto gp_fault; + + if ( (val & ~(USER_MSR_ENABLE | USER_MSR_ADDR_MASK)) || + !is_canonical_address(val) ) + goto gp_fault; + + msrs->user_msr_ctl.raw =3D val; + if ( v =3D=3D curr ) + wrmsrl(MSR_USER_MSR_CTL, val); + break; + case 0x40000000 ... 0x400001ff: if ( is_viridian_domain(d) ) { --- a/xen/include/public/arch-x86/cpufeatureset.h +++ b/xen/include/public/arch-x86/cpufeatureset.h @@ -359,7 +359,7 @@ XEN_CPUFEATURE(AMX_COMPLEX, 15*32 XEN_CPUFEATURE(AVX_VNNI_INT16, 15*32+10) /*A AVX-VNNI-INT16 Instructi= ons */ XEN_CPUFEATURE(UTMR, 15*32+13) /* User Timer */ XEN_CPUFEATURE(PREFETCHI, 15*32+14) /*A PREFETCHIT{0,1} Instruct= ions */ -XEN_CPUFEATURE(USER_MSR, 15*32+15) /* U{RD,WR}MSR Instructions= */ +XEN_CPUFEATURE(USER_MSR, 15*32+15) /*s U{RD,WR}MSR Instructions= */ XEN_CPUFEATURE(UIRET_UIF, 15*32+17) /* UIRET updates UIF */ XEN_CPUFEATURE(CET_SSS, 15*32+18) /* CET Supervisor Shadow St= acks safe to use */ XEN_CPUFEATURE(SLSM, 15*32+24) /* Static Lockstep Mode */ From nobody Fri Oct 31 03:42:50 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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Wed, 18 Jun 2025 00:07:32 -0700 (PDT) Message-ID: <8b2b6887-a780-47d9-9ef6-bd03c644b6e6@suse.com> Date: Wed, 18 Jun 2025 09:07:25 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH v8 6/7] x86emul: support MSR_IMM instructions From: Jan Beulich To: "xen-devel@lists.xenproject.org" Cc: Andrew Cooper , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= References: <585f1b0b-6768-4f9c-8f9f-bcf6e20fbfb7@suse.com> Content-Language: en-US Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <585f1b0b-6768-4f9c-8f9f-bcf6e20fbfb7@suse.com> Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @suse.com) X-ZM-MESSAGEID: 1750230470217116600 Content-Type: text/plain; charset="utf-8" Encoding-wise these are very similar to URDMSR/UWRMSR, so existing logic is easy to extend. Signed-off-by: Jan Beulich --- RFC only for now, as the VMX part is missing: The existing intercepts can't be re-used unmodified, as those require the MSR index to be fetched from guest ECX. --- v8: Don't mark the feature 's' just yet. Re-base. v7: New. --- a/tools/tests/x86_emulator/predicates.c +++ b/tools/tests/x86_emulator/predicates.c @@ -1519,6 +1519,8 @@ static const struct vex { { { 0xdf }, 3, T, R, pfx_66, WIG, Ln }, /* vaeskeygenassist */ { { 0xf0 }, 3, T, R, pfx_f2, Wn, L0 }, /* rorx */ }, vex_map7[] =3D { + { { 0xf6, 0xc0 }, 6, F, N, pfx_f3, W0, L0 }, /* wrmsrns */ + { { 0xf6, 0xc0 }, 6, F, N, pfx_f2, W0, L0 }, /* rdmsr */ { { 0xf8, 0xc0 }, 6, F, N, pfx_f3, W0, L0 }, /* uwrmsr */ { { 0xf8, 0xc0 }, 6, F, N, pfx_f2, W0, L0 }, /* urdmsr */ }; --- a/tools/tests/x86_emulator/test_x86_emulator.c +++ b/tools/tests/x86_emulator/test_x86_emulator.c @@ -1574,6 +1574,30 @@ int main(int argc, char **argv) if ( (rc !=3D X86EMUL_EXCEPTION) || (regs.rip !=3D (unsigned long)&instr[0]) ) goto fail; + printf("okay\n"); + + printf("%-40s", "Testing rdmsr $MSR_GS_BASE,%rdx..."); + instr[0] =3D 0xc4; instr[1] =3D 0xe7; instr[2] =3D 0x7b; instr[3] =3D = 0xf6; instr[4] =3D 0xc2; + *(uint32_t *)&instr[5] =3D MSR_GS_BASE; + regs.rip =3D (unsigned long)&instr[0]; + regs.rdx =3D ~gs_base; + rc =3D x86_emulate(&ctxt, &emulops); + if ( (rc !=3D X86EMUL_OKAY) || + (regs.rip !=3D (unsigned long)&instr[9]) || + (regs.rdx !=3D gs_base) ) + goto fail; + printf("okay\n"); + + printf("%-40s", "Testing wrmsrns %rsi,$MSR_SHADOW_GS_BASE..."); + instr[0] =3D 0xc4; instr[1] =3D 0xe7; instr[2] =3D 0x7a; instr[3] =3D = 0xf6; instr[4] =3D 0xc6; + *(uint32_t *)&instr[5] =3D MSR_SHADOW_GS_BASE; + regs.rip =3D (unsigned long)&instr[0]; + regs.rsi =3D 0x665544332211UL; + rc =3D x86_emulate(&ctxt, &emulops); + if ( (rc !=3D X86EMUL_OKAY) || + (regs.rip !=3D (unsigned long)&instr[9]) || + (gs_base_shadow !=3D 0x665544332211UL) ) + goto fail; =20 emulops.write_msr =3D NULL; #endif --- a/tools/tests/x86_emulator/x86-emulate.c +++ b/tools/tests/x86_emulator/x86-emulate.c @@ -88,6 +88,7 @@ bool emul_test_init(void) cpu_policy.feat.lkgs =3D true; cpu_policy.feat.wrmsrns =3D true; cpu_policy.feat.msrlist =3D true; + cpu_policy.feat.msr_imm =3D true; cpu_policy.feat.user_msr =3D true; cpu_policy.extd.clzero =3D true; =20 --- a/xen/arch/x86/x86_emulate/decode.c +++ b/xen/arch/x86/x86_emulate/decode.c @@ -1262,8 +1262,9 @@ int x86emul_decode(struct x86_emulate_st case vex_map7: opcode |=3D MASK_INSR(7, X86EMUL_OPC_EXT_MASK); /* - * No table lookup here for now, as there's only a= single - * opcode point (0xf8) populated in map 7. + * No table lookup here for now, as there are only= two + * (very similar) opcode points (0xf6, 0xf8) popul= ated + * in map 7. */ d =3D DstMem | SrcImm | ModRM | Mov; s->op_bytes =3D 8; --- a/xen/arch/x86/x86_emulate/private.h +++ b/xen/arch/x86/x86_emulate/private.h @@ -613,6 +613,7 @@ amd_like(const struct x86_emulate_ctxt * #define vcpu_has_wrmsrns() (ctxt->cpuid->feat.wrmsrns) #define vcpu_has_avx_ifma() (ctxt->cpuid->feat.avx_ifma) #define vcpu_has_msrlist() (ctxt->cpuid->feat.msrlist) +#define vcpu_has_msr_imm() (ctxt->cpuid->feat.msr_imm) #define vcpu_has_avx_vnni_int8() (ctxt->cpuid->feat.avx_vnni_int8) #define vcpu_has_avx_ne_convert() (ctxt->cpuid->feat.avx_ne_convert) #define vcpu_has_avx_vnni_int16() (ctxt->cpuid->feat.avx_vnni_int16) --- a/xen/arch/x86/x86_emulate/x86_emulate.c +++ b/xen/arch/x86/x86_emulate/x86_emulate.c @@ -7075,6 +7075,34 @@ x86_emulate( state->simd_size =3D simd_none; break; =20 + case X86EMUL_OPC_VEX_F3(7, 0xf6): /* wrmsrns r64,imm32 */ + case X86EMUL_OPC_VEX_F2(7, 0xf6): /* rdmsr imm32,r64 */ + generate_exception_if(!mode_64bit() || ea.type !=3D OP_REG, X86_EX= C_UD); + generate_exception_if(vex.l || vex.w, X86_EXC_UD); + generate_exception_if(vex.opcx && ((modrm_reg & 7) || vex.reg !=3D= 0xf), + X86_EXC_UD); + vcpu_must_have(msr_imm); + generate_exception_if(!mode_ring0(), X86_EXC_GP, 0); + if ( vex.pfx =3D=3D vex_f2 ) + { + /* urdmsr */ + fail_if(!ops->read_msr); + if ( (rc =3D ops->read_msr(imm1, &msr_val, ctxt)) !=3D X86EMUL= _OKAY ) + goto done; + dst.val =3D msr_val; + ASSERT(dst.type =3D=3D OP_REG); + dst.bytes =3D 8; + } + else + { + /* wrmsrns */ + fail_if(!ops->write_msr); + if ( (rc =3D ops->write_msr(imm1, dst.val, ctxt)) !=3D X86EMUL= _OKAY ) + goto done; + dst.type =3D OP_NONE; + } + break; + case X86EMUL_OPC_F3(0x0f38, 0xf8): /* enqcmds r,m512 / uwrmsr r64,r32 = */ case X86EMUL_OPC_F2(0x0f38, 0xf8): /* enqcmd r,m512 / urdmsr r32,r64 */ if ( ea.type =3D=3D OP_MEM ) --- a/xen/include/public/arch-x86/cpufeatureset.h +++ b/xen/include/public/arch-x86/cpufeatureset.h @@ -351,6 +351,7 @@ XEN_CPUFEATURE(MCDT_NO, 13*32 XEN_CPUFEATURE(UC_LOCK_DIS, 13*32+ 6) /* UC-lock disable */ =20 /* Intel-defined CPU features, CPUID level 0x00000007:1.ecx, word 14 */ +XEN_CPUFEATURE(MSR_IMM, 14*32+ 5) /* RDMSR/WRMSRNS with immed= iate operand */ =20 /* Intel-defined CPU features, CPUID level 0x00000007:1.edx, word 15 */ XEN_CPUFEATURE(AVX_VNNI_INT8, 15*32+ 4) /*A AVX-VNNI-INT8 Instructio= ns */ --- a/xen/tools/gen-cpuid.py +++ b/xen/tools/gen-cpuid.py @@ -275,7 +275,7 @@ def crunch_numbers(state): # NO_LMSL indicates the absense of Long Mode Segment Limits, which # have been dropped in hardware. LM: [CX16, PCID, LAHF_LM, PAGE1GB, PKU, NO_LMSL, AMX_TILE, CMPCCXA= DD, - LKGS, MSRLIST, USER_MSR], + LKGS, MSRLIST, USER_MSR, MSR_IMM], =20 # AMD K6-2+ and K6-III processors shipped with 3DNow+, beyond the # standard 3DNow in the earlier K6 processors. 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Wed, 18 Jun 2025 00:08:21 -0700 (PDT) Message-ID: <8e5acc40-ffdd-408e-af4c-c98fe94fb798@suse.com> Date: Wed, 18 Jun 2025 09:08:14 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH v8 7/7] x86emul: support non-SIMD MOVRS From: Jan Beulich To: "xen-devel@lists.xenproject.org" Cc: Andrew Cooper , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= References: <585f1b0b-6768-4f9c-8f9f-bcf6e20fbfb7@suse.com> Content-Language: en-US Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <585f1b0b-6768-4f9c-8f9f-bcf6e20fbfb7@suse.com> Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @suse.com) X-ZM-MESSAGEID: 1750230518502116600 Content-Type: text/plain; charset="utf-8" As we ignore cachability aspects of insns, they're treated like simple MOVs. Signed-off-by: Jan Beulich --- SDE: -dmr --- v7: New. --- a/tools/tests/x86_emulator/predicates.c +++ b/tools/tests/x86_emulator/predicates.c @@ -843,6 +843,9 @@ static const struct { { { 0x80 }, { 2, 2 }, T, R, pfx_66 }, /* invept */ { { 0x81 }, { 2, 2 }, T, R, pfx_66 }, /* invvpid */ { { 0x82 }, { 2, 2 }, T, R, pfx_66 }, /* invpcid */ + { { 0x8a }, { 2, 2 }, T, R, pfx_no }, /* movrsb */ + { { 0x8b }, { 2, 2 }, T, R, pfx_no }, /* movrs{d,q} */ + { { 0x8b }, { 2, 2 }, T, R, pfx_66 }, /* movrsw */ { { 0xc8 }, { 2, 2 }, T, R, pfx_no }, /* sha1nexte */ { { 0xc9 }, { 2, 2 }, T, R, pfx_no }, /* sha1msg1 */ { { 0xca }, { 2, 2 }, T, R, pfx_no }, /* sha1msg2 */ --- a/tools/tests/x86_emulator/test_x86_emulator.c +++ b/tools/tests/x86_emulator/test_x86_emulator.c @@ -1869,6 +1869,29 @@ int main(int argc, char **argv) } else printf("skipped\n"); + + { + /* For the non-SIMD forms the emulator doesn't itself use MOVRS. */ + bool movrs =3D cpu_policy.feat.movrs; + + cpu_policy.feat.movrs =3D true; + + printf("%-40s", "Testing movrs 6(%rdi),%si..."); + instr[0] =3D 0x66; instr[1] =3D 0x0f; instr[2] =3D 0x38; + instr[3] =3D 0x8b; instr[4] =3D 0x77; instr[5] =3D 0x06; + regs.rip =3D (unsigned long)&instr[0]; + regs.rsi =3D 0x8888777766665555UL; + regs.rdi =3D (unsigned long)res; + res[1] =3D 0x88777788U; + rc =3D x86_emulate(&ctxt, &emulops); + if ( (rc !=3D X86EMUL_OKAY) || + (regs.rip !=3D (unsigned long)&instr[6]) || + (regs.rsi !=3D 0x8888777766668877UL) ) + goto fail; + printf("okay\n"); + + cpu_policy.feat.movrs =3D movrs; + } #endif /* x86-64 */ =20 printf("%-40s", "Testing shld $1,%ecx,(%edx)..."); --- a/xen/arch/x86/x86_emulate/decode.c +++ b/xen/arch/x86/x86_emulate/decode.c @@ -901,7 +901,8 @@ decode_0f38(struct x86_emulate_state *s, { switch ( ctxt->opcode & X86EMUL_OPC_MASK ) { - case 0x00 ... 0xef: + case 0x00 ... 0x89: + case 0x8c ... 0xef: case 0xf2 ... 0xf5: case 0xf7: case 0xfa ... 0xff: @@ -912,6 +913,13 @@ decode_0f38(struct x86_emulate_state *s, ctxt->opcode |=3D MASK_INSR(s->vex.pfx, X86EMUL_OPC_PFX_MASK); break; =20 + case 0x8a ... 0x8b: /* movrs */ + s->desc =3D DstReg | SrcMem | Mov; + if ( !(ctxt->opcode & 1) ) + s->desc |=3D ByteOp; + s->simd_size =3D simd_none; + break; + case X86EMUL_OPC_VEX_66(0, 0x2d): /* vmaskmovpd */ s->simd_size =3D simd_packed_fp; break; --- a/xen/arch/x86/x86_emulate/private.h +++ b/xen/arch/x86/x86_emulate/private.h @@ -613,6 +613,7 @@ amd_like(const struct x86_emulate_ctxt * #define vcpu_has_wrmsrns() (ctxt->cpuid->feat.wrmsrns) #define vcpu_has_avx_ifma() (ctxt->cpuid->feat.avx_ifma) #define vcpu_has_msrlist() (ctxt->cpuid->feat.msrlist) +#define vcpu_has_movrs() (ctxt->cpuid->feat.movrs) #define vcpu_has_msr_imm() (ctxt->cpuid->feat.msr_imm) #define vcpu_has_avx_vnni_int8() (ctxt->cpuid->feat.avx_vnni_int8) #define vcpu_has_avx_ne_convert() (ctxt->cpuid->feat.avx_ne_convert) --- a/xen/arch/x86/x86_emulate/x86_emulate.c +++ b/xen/arch/x86/x86_emulate/x86_emulate.c @@ -6374,6 +6374,16 @@ x86_emulate( fault_suppression =3D false; goto avx512f_no_sae; =20 +#endif /* !X86EMUL_NO_SIMD */ + + case X86EMUL_OPC(0x0f38, 0x8a) + ... X86EMUL_OPC(0x0f38, 0x8b): /* movrs */ + vcpu_must_have(movrs); + dst.val =3D src.val; + break; + +#ifndef X86EMUL_NO_SIMD + case X86EMUL_OPC_VEX_66(0x0f38, 0x8c): /* vpmaskmov{d,q} mem,{x,y}mm,{= x,y}mm */ case X86EMUL_OPC_VEX_66(0x0f38, 0x8e): /* vpmaskmov{d,q} {x,y}mm,{x,y}= mm,mem */ generate_exception_if(ea.type !=3D OP_MEM, X86_EXC_UD); --- a/xen/include/public/arch-x86/cpufeatureset.h +++ b/xen/include/public/arch-x86/cpufeatureset.h @@ -319,6 +319,7 @@ XEN_CPUFEATURE(AVX_IFMA, 10*32+23) / XEN_CPUFEATURE(LAM, 10*32+26) /* Linear Address Masking */ XEN_CPUFEATURE(MSRLIST, 10*32+27) /* {RD,WR}MSRLIST instructions */ XEN_CPUFEATURE(NO_INVD, 10*32+30) /* INVD instruction unusable */ +XEN_CPUFEATURE(MOVRS, 10*32+31) /*a MOV-read-shared instructions */ =20 /* AMD-defined CPU features, CPUID level 0x80000021.eax, word 11 */ XEN_CPUFEATURE(NO_NEST_BP, 11*32+ 0) /*A No Nested Data Breakpoin= ts */ --- a/xen/tools/gen-cpuid.py +++ b/xen/tools/gen-cpuid.py @@ -275,7 +275,7 @@ def crunch_numbers(state): # NO_LMSL indicates the absense of Long Mode Segment Limits, which # have been dropped in hardware. LM: [CX16, PCID, LAHF_LM, PAGE1GB, PKU, NO_LMSL, AMX_TILE, CMPCCXA= DD, - LKGS, MSRLIST, USER_MSR, MSR_IMM], + LKGS, MSRLIST, USER_MSR, MSR_IMM, MOVRS], =20 # AMD K6-2+ and K6-III processors shipped with 3DNow+, beyond the # standard 3DNow in the earlier K6 processors.