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charset="utf-8" This follows Linux commit de09cdd09fa1 ("intel_idle: stop exposing platform acronyms in sysfs"), but their main justifications (sysfs exposure and similarity with acpi-idle) don't apply to us. The field is only used in a single printk() right now, but having the platform tags there isn't useful either. Requested-by: Roger Pau Monn=C3=A9 Signed-off-by: Jan Beulich --- v2: New. --- a/xen/arch/x86/cpu/mwait-idle.c +++ b/xen/arch/x86/cpu/mwait-idle.c @@ -134,25 +134,25 @@ static const struct cpuidle_state { */ static const struct cpuidle_state nehalem_cstates[] =3D { { - .name =3D "C1-NHM", + .name =3D "C1", .flags =3D MWAIT2flg(0x00), .exit_latency =3D 3, .target_residency =3D 6, }, { - .name =3D "C1E-NHM", + .name =3D "C1E", .flags =3D MWAIT2flg(0x01), .exit_latency =3D 10, .target_residency =3D 20, }, { - .name =3D "C3-NHM", + .name =3D "C3", .flags =3D MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 20, .target_residency =3D 80, }, { - .name =3D "C6-NHM", + .name =3D "C6", .flags =3D MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 200, .target_residency =3D 800, @@ -162,31 +162,31 @@ static const struct cpuidle_state nehale =20 static const struct cpuidle_state snb_cstates[] =3D { { - .name =3D "C1-SNB", + .name =3D "C1", .flags =3D MWAIT2flg(0x00), .exit_latency =3D 2, .target_residency =3D 2, }, { - .name =3D "C1E-SNB", + .name =3D "C1E", .flags =3D MWAIT2flg(0x01), .exit_latency =3D 10, .target_residency =3D 20, }, { - .name =3D "C3-SNB", + .name =3D "C3", .flags =3D MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 80, .target_residency =3D 211, }, { - .name =3D "C6-SNB", + .name =3D "C6", .flags =3D MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 104, .target_residency =3D 345, }, { - .name =3D "C7-SNB", + .name =3D "C7", .flags =3D MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 109, .target_residency =3D 345, @@ -196,31 +196,31 @@ static const struct cpuidle_state snb_cs =20 static const struct cpuidle_state byt_cstates[] =3D { { - .name =3D "C1-BYT", + .name =3D "C1", .flags =3D MWAIT2flg(0x00), .exit_latency =3D 1, .target_residency =3D 1, }, { - .name =3D "C6N-BYT", + .name =3D "C6N", .flags =3D MWAIT2flg(0x58) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 300, .target_residency =3D 275, }, { - .name =3D "C6S-BYT", + .name =3D "C6S", .flags =3D MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 500, .target_residency =3D 560, }, { - .name =3D "C7-BYT", + .name =3D "C7", .flags =3D MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 1200, .target_residency =3D 4000, }, { - .name =3D "C7S-BYT", + .name =3D "C7S", .flags =3D MWAIT2flg(0x64) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 10000, .target_residency =3D 20000, @@ -230,31 +230,31 @@ static const struct cpuidle_state byt_cs =20 static const struct cpuidle_state cht_cstates[] =3D { { - .name =3D "C1-CHT", + .name =3D "C1", .flags =3D MWAIT2flg(0x00), .exit_latency =3D 1, .target_residency =3D 1, }, { - .name =3D "C6N-CHT", + .name =3D "C6N", .flags =3D MWAIT2flg(0x58) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 80, .target_residency =3D 275, }, { - .name =3D "C6S-CHT", + .name =3D "C6S", .flags =3D MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 200, .target_residency =3D 560, }, { - .name =3D "C7-CHT", + .name =3D "C7", .flags =3D MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 1200, .target_residency =3D 4000, }, { - .name =3D "C7S-CHT", + .name =3D "C7S", .flags =3D MWAIT2flg(0x64) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 10000, .target_residency =3D 20000, @@ -264,31 +264,31 @@ static const struct cpuidle_state cht_cs =20 static const struct cpuidle_state ivb_cstates[] =3D { { - .name =3D "C1-IVB", + .name =3D "C1", .flags =3D MWAIT2flg(0x00), .exit_latency =3D 1, .target_residency =3D 1, }, { - .name =3D "C1E-IVB", + .name =3D "C1E", .flags =3D MWAIT2flg(0x01), .exit_latency =3D 10, .target_residency =3D 20, }, { - .name =3D "C3-IVB", + .name =3D "C3", .flags =3D MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 59, .target_residency =3D 156, }, { - .name =3D "C6-IVB", + .name =3D "C6", .flags =3D MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 80, .target_residency =3D 300, }, { - .name =3D "C7-IVB", + .name =3D "C7", .flags =3D MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 87, .target_residency =3D 300, @@ -298,25 +298,25 @@ static const struct cpuidle_state ivb_cs =20 static const struct cpuidle_state ivt_cstates[] =3D { { - .name =3D "C1-IVT", + .name =3D "C1", .flags =3D MWAIT2flg(0x00), .exit_latency =3D 1, .target_residency =3D 1, }, { - .name =3D "C1E-IVT", + .name =3D "C1E", .flags =3D MWAIT2flg(0x01), .exit_latency =3D 10, .target_residency =3D 80, }, { - .name =3D "C3-IVT", + .name =3D "C3", .flags =3D MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 59, .target_residency =3D 156, }, { - .name =3D "C6-IVT", + .name =3D "C6", .flags =3D MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 82, .target_residency =3D 300, @@ -326,25 +326,25 @@ static const struct cpuidle_state ivt_cs =20 static const struct cpuidle_state ivt_cstates_4s[] =3D { { - .name =3D "C1-IVT-4S", + .name =3D "C1", .flags =3D MWAIT2flg(0x00), .exit_latency =3D 1, .target_residency =3D 1, }, { - .name =3D "C1E-IVT-4S", + .name =3D "C1E", .flags =3D MWAIT2flg(0x01), .exit_latency =3D 10, .target_residency =3D 250, }, { - .name =3D "C3-IVT-4S", + .name =3D "C3", .flags =3D MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 59, .target_residency =3D 300, }, { - .name =3D "C6-IVT-4S", + .name =3D "C6", .flags =3D MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 84, .target_residency =3D 400, @@ -354,25 +354,25 @@ static const struct cpuidle_state ivt_cs =20 static const struct cpuidle_state ivt_cstates_8s[] =3D { { - .name =3D "C1-IVT-8S", + .name =3D "C1", .flags =3D MWAIT2flg(0x00), .exit_latency =3D 1, .target_residency =3D 1, }, { - .name =3D "C1E-IVT-8S", + .name =3D "C1E", .flags =3D MWAIT2flg(0x01), .exit_latency =3D 10, .target_residency =3D 500, }, { - .name =3D "C3-IVT-8S", + .name =3D "C3", .flags =3D MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 59, .target_residency =3D 600, }, { - .name =3D "C6-IVT-8S", + .name =3D "C6", .flags =3D MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 88, .target_residency =3D 700, @@ -382,49 +382,49 @@ static const struct cpuidle_state ivt_cs =20 static const struct cpuidle_state hsw_cstates[] =3D { { - .name =3D "C1-HSW", + .name =3D "C1", .flags =3D MWAIT2flg(0x00), .exit_latency =3D 2, .target_residency =3D 2, }, { - .name =3D "C1E-HSW", + .name =3D "C1E", .flags =3D MWAIT2flg(0x01), .exit_latency =3D 10, .target_residency =3D 20, }, { - .name =3D "C3-HSW", + .name =3D "C3", .flags =3D MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 33, .target_residency =3D 100, }, { - .name =3D "C6-HSW", + .name =3D "C6", .flags =3D MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 133, .target_residency =3D 400, }, { - .name =3D "C7s-HSW", + .name =3D "C7s", .flags =3D MWAIT2flg(0x32) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 166, .target_residency =3D 500, }, { - .name =3D "C8-HSW", + .name =3D "C8", .flags =3D MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 300, .target_residency =3D 900, }, { - .name =3D "C9-HSW", + .name =3D "C9", .flags =3D MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 600, .target_residency =3D 1800, }, { - .name =3D "C10-HSW", + .name =3D "C10", .flags =3D MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 2600, .target_residency =3D 7700, @@ -434,49 +434,49 @@ static const struct cpuidle_state hsw_cs =20 static const struct cpuidle_state bdw_cstates[] =3D { { - .name =3D "C1-BDW", + .name =3D "C1", .flags =3D MWAIT2flg(0x00), .exit_latency =3D 2, .target_residency =3D 2, }, { - .name =3D "C1E-BDW", + .name =3D "C1E", .flags =3D MWAIT2flg(0x01), .exit_latency =3D 10, .target_residency =3D 20, }, { - .name =3D "C3-BDW", + .name =3D "C3", .flags =3D MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 40, .target_residency =3D 100, }, { - .name =3D "C6-BDW", + .name =3D "C6", .flags =3D MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 133, .target_residency =3D 400, }, { - .name =3D "C7s-BDW", + .name =3D "C7s", .flags =3D MWAIT2flg(0x32) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 166, .target_residency =3D 500, }, { - .name =3D "C8-BDW", + .name =3D "C8", .flags =3D MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 300, .target_residency =3D 900, }, { - .name =3D "C9-BDW", + .name =3D "C9", .flags =3D MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 600, .target_residency =3D 1800, }, { - .name =3D "C10-BDW", + .name =3D "C10", .flags =3D MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 2600, .target_residency =3D 7700, @@ -486,49 +486,49 @@ static const struct cpuidle_state bdw_cs =20 static struct cpuidle_state __read_mostly skl_cstates[] =3D { { - .name =3D "C1-SKL", + .name =3D "C1", .flags =3D MWAIT2flg(0x00), .exit_latency =3D 2, .target_residency =3D 2, }, { - .name =3D "C1E-SKL", + .name =3D "C1E", .flags =3D MWAIT2flg(0x01), .exit_latency =3D 10, .target_residency =3D 20, }, { - .name =3D "C3-SKL", + .name =3D "C3", .flags =3D MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 70, .target_residency =3D 100, }, { - .name =3D "C6-SKL", + .name =3D "C6", .flags =3D MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 85, .target_residency =3D 200, }, { - .name =3D "C7s-SKL", + .name =3D "C7s", .flags =3D MWAIT2flg(0x33) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 124, .target_residency =3D 800, }, { - .name =3D "C8-SKL", + .name =3D "C8", .flags =3D MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 200, .target_residency =3D 800, }, { - .name =3D "C9-SKL", + .name =3D "C9", .flags =3D MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 480, .target_residency =3D 5000, }, { - .name =3D "C10-SKL", + .name =3D "C10", .flags =3D MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 890, .target_residency =3D 5000, @@ -538,19 +538,19 @@ static struct cpuidle_state __read_mostl =20 static struct cpuidle_state __read_mostly skx_cstates[] =3D { { - .name =3D "C1-SKX", + .name =3D "C1", .flags =3D MWAIT2flg(0x00), .exit_latency =3D 2, .target_residency =3D 2, }, { - .name =3D "C1E-SKX", + .name =3D "C1E", .flags =3D MWAIT2flg(0x01), .exit_latency =3D 10, .target_residency =3D 20, }, { - .name =3D "C6-SKX", + .name =3D "C6", .flags =3D MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 133, .target_residency =3D 600, @@ -560,19 +560,19 @@ static struct cpuidle_state __read_mostl =20 static const struct cpuidle_state icx_cstates[] =3D { { - .name =3D "C1-ICX", + .name =3D "C1", .flags =3D MWAIT2flg(0x00), .exit_latency =3D 1, .target_residency =3D 1, }, { - .name =3D "C1E-ICX", + .name =3D "C1E", .flags =3D MWAIT2flg(0x01), .exit_latency =3D 4, .target_residency =3D 4, }, { - .name =3D "C6-ICX", + .name =3D "C6", .flags =3D MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 170, .target_residency =3D 600, @@ -582,25 +582,25 @@ static const struct cpuidle_state icx_cs =20 static const struct cpuidle_state atom_cstates[] =3D { { - .name =3D "C1E-ATM", + .name =3D "C1E", .flags =3D MWAIT2flg(0x00), .exit_latency =3D 10, .target_residency =3D 20, }, { - .name =3D "C2-ATM", + .name =3D "C2", .flags =3D MWAIT2flg(0x10), .exit_latency =3D 20, .target_residency =3D 80, }, { - .name =3D "C4-ATM", + .name =3D "C4", .flags =3D MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 100, .target_residency =3D 400, }, { - .name =3D "C6-ATM", + .name =3D "C6", .flags =3D MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 140, .target_residency =3D 560, @@ -610,31 +610,31 @@ static const struct cpuidle_state atom_c =20 static const struct cpuidle_state tangier_cstates[] =3D { { - .name =3D "C1-TNG", + .name =3D "C1", .flags =3D MWAIT2flg(0x00), .exit_latency =3D 1, .target_residency =3D 4, }, { - .name =3D "C4-TNG", + .name =3D "C4", .flags =3D MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 100, .target_residency =3D 400, }, { - .name =3D "C6-TNG", + .name =3D "C6", .flags =3D MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 140, .target_residency =3D 560, }, { - .name =3D "C7-TNG", + .name =3D "C7", .flags =3D MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 1200, .target_residency =3D 4000, }, { - .name =3D "C9-TNG", + .name =3D "C9", .flags =3D MWAIT2flg(0x64) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 10000, .target_residency =3D 20000, @@ -644,13 +644,13 @@ static const struct cpuidle_state tangie =20 static const struct cpuidle_state avn_cstates[] =3D { { - .name =3D "C1-AVN", + .name =3D "C1", .flags =3D MWAIT2flg(0x00), .exit_latency =3D 2, .target_residency =3D 2, }, { - .name =3D "C6-AVN", + .name =3D "C6", .flags =3D MWAIT2flg(0x51) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 15, .target_residency =3D 45, @@ -660,13 +660,13 @@ static const struct cpuidle_state avn_cs =20 static const struct cpuidle_state knl_cstates[] =3D { { - .name =3D "C1-KNL", + .name =3D "C1", .flags =3D MWAIT2flg(0x00), .exit_latency =3D 1, .target_residency =3D 2, }, { - .name =3D "C6-KNL", + .name =3D "C6", .flags =3D MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 120, .target_residency =3D 500, @@ -676,43 +676,43 @@ static const struct cpuidle_state knl_cs =20 static struct cpuidle_state __read_mostly bxt_cstates[] =3D { { - .name =3D "C1-BXT", + .name =3D "C1", .flags =3D MWAIT2flg(0x00), .exit_latency =3D 2, .target_residency =3D 2, }, { - .name =3D "C1E-BXT", + .name =3D "C1E", .flags =3D MWAIT2flg(0x01), .exit_latency =3D 10, .target_residency =3D 20, }, { - .name =3D "C6-BXT", + .name =3D "C6", .flags =3D MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 133, .target_residency =3D 133, }, { - .name =3D "C7s-BXT", + .name =3D "C7s", .flags =3D MWAIT2flg(0x31) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 155, .target_residency =3D 155, }, { - .name =3D "C8-BXT", + .name =3D "C8", .flags =3D MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 1000, .target_residency =3D 1000, }, { - .name =3D "C9-BXT", + .name =3D "C9", .flags =3D MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 2000, .target_residency =3D 2000, }, { - .name =3D "C10-BXT", + .name =3D "C10", .flags =3D MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 10000, .target_residency =3D 10000, @@ -722,19 +722,19 @@ static struct cpuidle_state __read_mostl =20 static const struct cpuidle_state dnv_cstates[] =3D { { - .name =3D "C1-DNV", + .name =3D "C1", .flags =3D MWAIT2flg(0x00), .exit_latency =3D 2, .target_residency =3D 2, }, { - .name =3D "C1E-DNV", + .name =3D "C1E", .flags =3D MWAIT2flg(0x01), .exit_latency =3D 10, .target_residency =3D 20, }, { - .name =3D "C6-DNV", + .name =3D "C6", .flags =3D MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 50, .target_residency =3D 500, From nobody Sun May 19 01:43:09 2024 Delivered-To: importer@patchew.org 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X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f7a17af6-1c5c-4a36-aa8b-f5be247aa4ba X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: sVJMlcdzOTwjlBuzGRK0kuM3jDVzhArcNAlftzrcDgHVTGmDj6rD6MUzhbDq2nJVIEtmTxGTTYIg79zzhNW+9A== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DBBPR04MB7643 X-ZohoMail-DKIM: pass (identity @suse.com) X-ZM-MESSAGEID: 1642687371931100001 Content-Type: text/plain; charset="utf-8" When the driver was first ported, we didn't have "bool" yet, so conversion to bool_t / 0 / 1 was necessary. Undo that conversion, easing ports of newer changes as well as tidying things up. Requested-by: Roger Pau Monn=C3=A9 Signed-off-by: Jan Beulich Acked-by: Roger Pau Monn=C3=A9 --- v2: New. --- a/xen/arch/x86/cpu/mwait-idle.c +++ b/xen/arch/x86/cpu/mwait-idle.c @@ -76,7 +76,7 @@ # define pr_debug(fmt...) #endif =20 -static __initdata bool_t opt_mwait_idle =3D 1; +static __initdata bool opt_mwait_idle =3D true; boolean_param("mwait-idle", opt_mwait_idle); =20 static unsigned int mwait_substates; @@ -93,8 +93,8 @@ struct idle_cpu { * Indicate which enable bits to clear here. */ unsigned long auto_demotion_disable_flags; - bool_t byt_auto_demotion_disable_flag; - bool_t disable_promotion_to_c1e; + bool byt_auto_demotion_disable_flag; + bool disable_promotion_to_c1e; }; =20 static const struct idle_cpu *icpu; @@ -867,7 +867,7 @@ static void c1e_promotion_disable(void * static const struct idle_cpu idle_cpu_nehalem =3D { .state_table =3D nehalem_cstates, .auto_demotion_disable_flags =3D NHM_C1_AUTO_DEMOTE | NHM_C3_AUTO_DEMOTE, - .disable_promotion_to_c1e =3D 1, + .disable_promotion_to_c1e =3D true, }; =20 static const struct idle_cpu idle_cpu_atom =3D { @@ -885,59 +885,59 @@ static const struct idle_cpu idle_cpu_li =20 static const struct idle_cpu idle_cpu_snb =3D { .state_table =3D snb_cstates, - .disable_promotion_to_c1e =3D 1, + .disable_promotion_to_c1e =3D true, }; =20 static const struct idle_cpu idle_cpu_byt =3D { .state_table =3D byt_cstates, - .disable_promotion_to_c1e =3D 1, - .byt_auto_demotion_disable_flag =3D 1, + .disable_promotion_to_c1e =3D true, + .byt_auto_demotion_disable_flag =3D true, }; =20 static const struct idle_cpu idle_cpu_cht =3D { .state_table =3D cht_cstates, - .disable_promotion_to_c1e =3D 1, - .byt_auto_demotion_disable_flag =3D 1, + .disable_promotion_to_c1e =3D true, + .byt_auto_demotion_disable_flag =3D true, }; =20 static const struct idle_cpu idle_cpu_ivb =3D { .state_table =3D ivb_cstates, - .disable_promotion_to_c1e =3D 1, + .disable_promotion_to_c1e =3D true, }; =20 static const struct idle_cpu idle_cpu_ivt =3D { .state_table =3D ivt_cstates, - .disable_promotion_to_c1e =3D 1, + .disable_promotion_to_c1e =3D true, }; =20 static const struct idle_cpu idle_cpu_hsw =3D { .state_table =3D hsw_cstates, - .disable_promotion_to_c1e =3D 1, + .disable_promotion_to_c1e =3D true, }; =20 static const struct idle_cpu idle_cpu_bdw =3D { .state_table =3D bdw_cstates, - .disable_promotion_to_c1e =3D 1, + .disable_promotion_to_c1e =3D true, }; =20 static const struct idle_cpu idle_cpu_skl =3D { .state_table =3D skl_cstates, - .disable_promotion_to_c1e =3D 1, + .disable_promotion_to_c1e =3D true, }; =20 static const struct idle_cpu idle_cpu_skx =3D { .state_table =3D skx_cstates, - .disable_promotion_to_c1e =3D 1, + .disable_promotion_to_c1e =3D true, }; =20 static const struct idle_cpu idle_cpu_icx =3D { .state_table =3D icx_cstates, - .disable_promotion_to_c1e =3D 1, + .disable_promotion_to_c1e =3D true, }; =20 static const struct idle_cpu idle_cpu_avn =3D { .state_table =3D avn_cstates, - .disable_promotion_to_c1e =3D 1, + .disable_promotion_to_c1e =3D true, }; =20 static const struct idle_cpu idle_cpu_knl =3D { @@ -946,12 +946,12 @@ static const struct idle_cpu idle_cpu_kn =20 static const struct idle_cpu idle_cpu_bxt =3D { .state_table =3D bxt_cstates, - .disable_promotion_to_c1e =3D 1, + .disable_promotion_to_c1e =3D true, }; =20 static const struct idle_cpu idle_cpu_dnv =3D { .state_table =3D dnv_cstates, - .disable_promotion_to_c1e =3D 1, + .disable_promotion_to_c1e =3D true, }; =20 #define ICPU(model, cpu) \ From nobody Sun May 19 01:43:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; arc=fail (BodyHash is different from the expected one); dmarc=pass(p=quarantine dis=none) header.from=suse.com Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1642687402916450.60295121095646; Thu, 20 Jan 2022 06:03:22 -0800 (PST) Received: from list by lists.xenproject.org with outflank-mailman.259074.446824 (Exim 4.92) (envelope-from ) id 1nAY1d-0006t4-K5; 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charset="utf-8" From: Artem Bityutskiy Add C-state table for the SnowRidge SoC which is found on Intel Jacobsville platforms. The following has been changed. 1. C1E latency changed from 10us to 15us. It was measured using the open source "wult" tool (the "nic" method, 15us is the 99.99th percentile). 2. C1E power break even changed from 20us to 25us, which may result in less C1E residency in some workloads. 3. C6 latency changed from 50us to 130us. Measured the same way as C1E. The C6 C-state is supported only by some SnowRidge revisions, so add a C-st= ate table commentary about this. On SnowRidge, C6 support is enumerated via the usual mechanism: "mwait" lea= f of the "cpuid" instruction. The 'intel_idle' driver does check this leaf, so e= ven though C6 is present in the table, the driver will only use it if the CPU d= oes support it. Signed-off-by: Artem Bityutskiy Signed-off-by: Rafael J. Wysocki [Linux commit: 9cf93f056f783f986c19f40d5304d1bcffa0fc0d] Signed-off-by: Jan Beulich Acked-by: Roger Pau Monn=C3=A9 --- a/xen/arch/x86/cpu/mwait-idle.c +++ b/xen/arch/x86/cpu/mwait-idle.c @@ -742,6 +742,32 @@ static const struct cpuidle_state dnv_cs {} }; =20 +/* + * Note, depending on HW and FW revision, SnowRidge SoC may or may not sup= port + * C6, and this is indicated in the CPUID mwait leaf. + */ +static const struct cpuidle_state snr_cstates[] =3D { + { + .name =3D "C1", + .flags =3D MWAIT2flg(0x00), + .exit_latency =3D 2, + .target_residency =3D 2, + }, + { + .name =3D "C1E", + .flags =3D MWAIT2flg(0x01), + .exit_latency =3D 15, + .target_residency =3D 25, + }, + { + .name =3D "C6", + .flags =3D MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, + .exit_latency =3D 130, + .target_residency =3D 500, + }, + {} +}; + static void mwait_idle(void) { unsigned int cpu =3D smp_processor_id(); @@ -954,6 +980,11 @@ static const struct idle_cpu idle_cpu_dn .disable_promotion_to_c1e =3D true, }; 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charset="utf-8" From: Artem Bityutskiy Enable local interrupts before requesting C1 on the last two generations of Intel Xeon platforms: Sky Lake, Cascade Lake, Cooper Lake, Ice Lake. This decreases average C1 interrupt latency by about 5-10%, as measured with the 'wult' tool. The '->enter()' function of the driver enters C-states with local interrupts disabled by executing the 'monitor' and 'mwait' pair of instructions. If an interrupt happens, the CPU exits the C-state and continues executing instructions after 'mwait'. It does not jump to the interrupt handler, because local interrupts are disabled. The cpuidle subsystem enables interrupts a bit later, after doing some housekeeping. With this patch, we enable local interrupts before requesting C1. In this case, if the CPU wakes up because of an interrupt, it will jump to the interrupt handler right away. The cpuidle housekeeping will be done after the pending interrupt(s) are handled. Enabling interrupts before entering a C-state has measurable impact for faster C-states, like C1. Deeper, but slower C-states like C6 do not really benefit from this sort of change, because their latency is a lot higher comparing to the delay added by cpuidle housekeeping. This change was also tested with cyclictest and dbench. In case of Ice Lake, the average cyclictest latency decreased by 5.1%, and the average 'dbench' throughput increased by about 0.8%. Both tests were run for 4 hours with only C1 enabled (all other idle states, including 'POLL', were disabled). CPU frequency was pinned to HFM, and uncore frequency was pinned to the maximum value. The other platforms had similar single-digit percentage improvements. It is worth noting that this patch affects 'cpuidle' statistics a tiny bit. Before this patch, C1 residency did not include the interrupt handling time, but with this patch, it will include it. This is similar to what happens in case of the 'POLL' state, which also runs with interrupts enabled. Suggested-by: Len Brown Signed-off-by: Artem Bityutskiy [Linux commit: c227233ad64c77e57db738ab0e46439db71822a3] We don't have a pointer into cpuidle_state_table[] readily available. To compensate, make use of the new flag only appearing for C1 and hence only in the first table entry. Unlike Linux we want to disable IRQs again after MWAITing, as subsequently invoked functions assume so. Signed-off-by: Jan Beulich Acked-by: Roger Pau Monn=C3=A9 --- RFC: I'm not entirely certain that we want to take this, i.e. whether we're as much worried about interrupt latency. RFC: I was going back and forth between putting the local_irq_enable() ahead of or after cpu_is_haltable(). --- v2: New. --- a/xen/arch/x86/cpu/mwait-idle.c +++ b/xen/arch/x86/cpu/mwait-idle.c @@ -108,6 +108,11 @@ static const struct cpuidle_state { =20 #define CPUIDLE_FLAG_DISABLED 0x1 /* + * Enable interrupts before entering the C-state. On some platforms and for + * some C-states, this may measurably decrease interrupt latency. + */ +#define CPUIDLE_FLAG_IRQ_ENABLE 0x8000 +/* * Set this flag for states where the HW flushes the TLB for us * and so we don't need cross-calls to keep it consistent. * If this flag is set, SW flushes the TLB, so even if the @@ -539,7 +544,7 @@ static struct cpuidle_state __read_mostl static struct cpuidle_state __read_mostly skx_cstates[] =3D { { .name =3D "C1", - .flags =3D MWAIT2flg(0x00), + .flags =3D MWAIT2flg(0x00) | CPUIDLE_FLAG_IRQ_ENABLE, .exit_latency =3D 2, .target_residency =3D 2, }, @@ -561,7 +566,7 @@ static struct cpuidle_state __read_mostl static const struct cpuidle_state icx_cstates[] =3D { { .name =3D "C1", - .flags =3D MWAIT2flg(0x00), + .flags =3D MWAIT2flg(0x00) | CPUIDLE_FLAG_IRQ_ENABLE, .exit_latency =3D 1, .target_residency =3D 1, }, @@ -776,6 +781,7 @@ static void mwait_idle(void) unsigned int next_state; u64 before, after; u32 exp =3D 0, pred =3D 0, irq_traced[4] =3D { 0 }; + bool irq_enable_early =3D false; =20 if (max_cstate > 0 && power && (next_state =3D cpuidle_current_governor->select(power)) > 0) { @@ -806,6 +812,12 @@ static void mwait_idle(void) return; } =20 + if (cx->idx =3D=3D 1 && cx->type =3D=3D ACPI_STATE_C1 && + (cpuidle_state_table[0].flags & CPUIDLE_FLAG_IRQ_ENABLE)) { + ASSERT(cx->address =3D=3D flg2MWAIT(cpuidle_state_table[0].flags)); + irq_enable_early =3D true; + } + cpufreq_dbs_timer_suspend(); =20 rcu_idle_enter(cpu); @@ -842,9 +854,15 @@ static void mwait_idle(void) =20 update_last_cx_stat(power, cx, before); =20 - if (cpu_is_haltable(cpu)) + if (cpu_is_haltable(cpu)) { + if (irq_enable_early) + local_irq_enable(); + mwait_idle_with_hints(cx->address, MWAIT_ECX_INTERRUPT_BREAK); =20 + local_irq_disable(); + } + after =3D alternative_call(cpuidle_get_tick); =20 cstate_restore_tsc(); From nobody Sun May 19 01:43:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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charset="utf-8" While we don't want to skip calling update_idle_stats(), arrange for it to not increment the overall time spent in the state we didn't really enter. Signed-off-by: Jan Beulich --- RFC: Arguably more of what follows could be moved into the if() - thoughts? --- v2: New. --- a/xen/arch/x86/cpu/mwait-idle.c +++ b/xen/arch/x86/cpu/mwait-idle.c @@ -861,9 +861,11 @@ static void mwait_idle(void) mwait_idle_with_hints(cx->address, MWAIT_ECX_INTERRUPT_BREAK); =20 local_irq_disable(); - } =20 - after =3D alternative_call(cpuidle_get_tick); + after =3D alternative_call(cpuidle_get_tick); + } + else + before =3D after =3D alternative_call(cpuidle_get_tick); =20 cstate_restore_tsc(); trace_exit_reason(irq_traced);